library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity colorgen is
  port (
    Clk         : in  std_logic;
    WE          : in  std_logic;
 --   EN          : in  std_logic;
    addr_vram   : in  std_logic_vector(3 downto 0);
    addr_mux    : in  std_logic_vector(3 downto 0);
    di          : in std_logic_vector(7 downto 0);
    do          : out std_logic_vector(5 downto 0)
    );
end colorgen;
architecture behavior of colorgen is
  
   type ram_type is array(15 downto 0) of std_logic_vector(5 downto 0);
--   signal RAM : ram_type;
constant RAM : ram_type :=
  ("000000", "100000", "000000", "000000",
   "001101", "000110", "010110", "100110",
   "001101", "001010", "011010", "101010",
   "001101", "000010", "010010", "100010");
    
begin
  process(we, addr_mux, addr_vram, di)
  begin
--    if Clk'event and Clk = '1' then
--      if en = '1' then
--         if we = '1' then
--           RAM(conv_integer(addr_vram)) <= di;
--           do <= di(5 downto 0);
--         else
          do <= RAM(conv_integer(addr_mux))(5 downto 0);                  
--        end if;
--      end if;
--    end if;
  end process;        
  
end behavior;
