
--Create Entity:
--Library=NES,Cell=shift_reg,View=entity
--Time:Wed May  5 15:18:16 2004
--By:neel

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shift_reg IS
    PORT(
        output : OUT std_logic_vector(1 DOWNTO 0);
        data1 : IN std_logic_vector(7 DOWNTO 0);
        data2 : IN std_logic_vector(7 DOWNTO 0);
        load1 : IN std_logic;
        load2 : IN std_logic;
        clk : IN std_logic
    );
END shift_reg;
architecture behavior of shift_reg is

signal shift1, shift2 : std_logic_vector(7 downto 0);
signal count8 : std_logic_vector(2 downto 0);

begin  -- imp

    process(clk, load1, load2)
      begin
        if clk = '1' and clk'event then 
          if (load1 = '1' or load2 = '1') then
            count8 <= "000";
            if load1 = '1' then
              shift1 <= data1;
            end if;
            if load2 = '1' then
              shift2 <= data2;
            end if;
          end if;
        for i in 6 to 0 loop
          shift1(i + 1) <= shift1(i);
          shift2(i + 1) <= shift2(i);
        end loop;  -- i

        end if;
      end process;

      output <= shift2(7) & shift1(7);
      
end behavior;
