library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity mem_interface is
  
  port (
    data_to_mem : in std_logic_vector(15 downto 0);
    write_to_mem : in std_logic;
    read_from_mem : in std_logic;
    chip_enable : out std_logic;
    mem_bus : inout std_logic_vector(15 downto 0);
    data_from_mem : out std_logic_vector(15 downto 0);
    upper_en : out std_logic;
    lower_en : out std_logic;
    output_en : out std_logic;
    write_en : out std_logic
  );
    
end mem_interface;

architecture behavior of mem_interface is

begin  -- behavior

  -- chip enable is active low
  chip_enable <= '0' when write_to_mem = '1' or read_from_mem = '1'
                 else '1';

  upper_en <= '0';                      -- enable upper byte
  lower_en <= '0';                      -- enable lower byte

  data_from_mem <= mem_bus when read_from_mem = '1' else
                   "XXXXXXXXXXXXXXXX";

  write_en <= not(write_to_mem);        -- write_to_mem is active high
  output_en <= not(read_from_mem);      -- read_from_mem is active high

  mem_bus <= data_to_mem when write_to_mem = '1' else
             "ZZZZZZZZZZZZZZZZ"; 
             

end behavior;
