
--Create Entity:
--Library=NES,Cell=nes_ppu_still,View=entity
--Time:Sat May  8 18:10:11 2004
--By:neel

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY nes_ppu_still IS
    PORT(
        b : OUT std_logic_vector(7 DOWNTO 0);
        g : OUT std_logic_vector(7 DOWNTO 0);
        r : OUT std_logic_vector(7 DOWNTO 0);
        v_addr : OUT std_logic_vector(13 DOWNTO 0);
        v_data : OUT std_logic_vector(7 DOWNTO 0);
        v_read : OUT std_logic;
        v_write : OUT std_logic;
        ppu_go : out std_logic;
        addr : IN std_logic_vector(15 DOWNTO 0);
        clock : IN std_logic;
        cpu_data : IN std_logic_vector(7 DOWNTO 0);
        cpu_r : IN std_logic;
        cpu_w : IN std_logic;
        rst : IN std_logic;
        v_in : IN std_logic_vector(7 DOWNTO 0)
    );
END nes_ppu_still;

--Netlist:
--Library=NES,Cell=nes_ppu_still,View=schematic
--Time:Wed May  5 16:49:38 2004
--By:neel

ARCHITECTURE schematic OF nes_ppu_still IS
    COMPONENT decoder
        PORT(
            din : IN std_logic_vector(5 DOWNTO 0);
            rout : OUT std_logic_vector(7 DOWNTO 0);
            bout : OUT std_logic_vector(7 DOWNTO 0);
            gout : OUT std_logic_vector(7 DOWNTO 0)
        );
    END COMPONENT;
    
    COMPONENT colorgen
        PORT(
            clk : IN std_logic;
            we : IN std_logic;
            addr_vram : IN std_logic_vector(3 DOWNTO 0);
            addr_mux : IN std_logic_vector(3 DOWNTO 0);
            di : IN std_logic_vector(7 DOWNTO 0);
            do : OUT std_logic_vector(5 DOWNTO 0)
        );
    END COMPONENT;
    
--     COMPONENT vram
--         PORT(
--             clk : IN std_logic;
--             addr : IN std_logic_vector(13 DOWNTO 0);
--             din : IN std_logic_vector(7 DOWNTO 0);
--             dout : OUT std_logic_vector(7 DOWNTO 0);
--             wr : IN std_logic;
--             rd : IN std_logic
--         );
--     END COMPONENT;
    
    COMPONENT shift_reg
        PORT(
            output : OUT std_logic_vector(1 DOWNTO 0);
            data1 : IN std_logic_vector(7 DOWNTO 0);
            data2 : IN std_logic_vector(7 DOWNTO 0);
            load1 : IN std_logic;
            load2 : IN std_logic;
            clk : IN std_logic
        );
    END COMPONENT;
    
    COMPONENT control
        PORT(
            cpu_in : IN std_logic_vector(7 DOWNTO 0);
            addr_in : IN std_logic_vector(15 DOWNTO 0);
            cpu_read : IN std_logic;
            cpu_write : IN std_logic;
            ppu_clock : IN std_logic;
            reset : IN std_logic;
            vram_addr : OUT std_logic_vector(13 DOWNTO 0);
            vram_data : OUT std_logic_vector(7 DOWNTO 0);
            vram_write : OUT std_logic;
            loadsr1 : OUT std_logic;
            loadsr2 : OUT std_logic;
            sr1_data : OUT std_logic_vector(7 DOWNTO 0);
            sr2_data : OUT std_logic_vector(7 DOWNTO 0);
            vram_in : IN std_logic_vector(7 DOWNTO 0);
            attrib_out : OUT std_logic_vector(1 DOWNTO 0);
            write_color : OUT std_logic;
            ppu_going : out std_logic;
            color_data : OUT std_logic_vector(7 DOWNTO 0);
            color_addr : OUT std_logic_vector(3 DOWNTO 0);
            vram_read : OUT std_logic
        );
    END COMPONENT;
    
    SIGNAL net33 : std_logic;
    SIGNAL bits : std_logic_vector(3 DOWNTO 0);
    SIGNAL net35 : std_logic_vector(0 TO 3);
    SIGNAL net50 : std_logic;
    SIGNAL net36 : std_logic_vector(0 TO 7);
    SIGNAL net34 : std_logic_vector(0 TO 7);
    SIGNAL net49 : std_logic;
    SIGNAL net48 : std_logic_vector(0 TO 7);
    SIGNAL net43 : std_logic;
    SIGNAL net20 : std_logic_vector(0 TO 5);
    SIGNAL net46 : std_logic_vector(0 TO 13);
    SIGNAL net47 : std_logic_vector(0 TO 7);
    SIGNAL net44 : std_logic;
    SIGNAL net45 : std_logic_vector(0 TO 7);
    ALIAS clock_wire : std_ulogic IS clock;
    
    
BEGIN
    
    
    \I5\ : decoder 
        PORT MAP(
            din(5 DOWNTO 0) => net20(0 TO 5),
            rout(7 DOWNTO 0) => r(7 DOWNTO 0),
            bout(7 DOWNTO 0) => b(7 DOWNTO 0),
            gout(7 DOWNTO 0) => g(7 DOWNTO 0)
        );
    
    \I4\ : colorgen 
        PORT MAP(
            clk => clock_wire,
            we => net33,
            addr_vram(3 DOWNTO 0) => net35(0 TO 3),
            addr_mux(3 DOWNTO 0) => bits(3 DOWNTO 0),
            di(7 DOWNTO 0) => net34(0 TO 7),
            do(5 DOWNTO 0) => net20(0 TO 5)
        );
    
--     \I2\ : vram 
--         PORT MAP(
--             clk => clock_wire,
--             addr(13 DOWNTO 0) => net46(0 TO 13),
--             din(7 DOWNTO 0) => net45(0 TO 7),
--             dout(7 DOWNTO 0) => net36(0 TO 7),
--             wr => net43,
--             rd => net44
--         );
    
    \I1\ : shift_reg 
        PORT MAP(
            output(1 DOWNTO 0) => bits(1 DOWNTO 0),
            data1(7 DOWNTO 0) => net48(0 TO 7),
            data2(7 DOWNTO 0) => net47(0 TO 7),
            load1 => net50,
            load2 => net49,
            clk => clock_wire
        );
    
    \I0\ : control 
        PORT MAP(
            cpu_in(7 DOWNTO 0) => cpu_data(7 DOWNTO 0),
            addr_in(15 DOWNTO 0) => addr(15 DOWNTO 0),
            cpu_read => cpu_r,
            cpu_write => cpu_w,
            ppu_clock => clock_wire,
            reset => rst,
            vram_addr(13 DOWNTO 0) => v_addr(13 downto 0), -- net46(0 TO 13),
            vram_data(7 DOWNTO 0) => v_data(7 downto 0), --net45(0 TO 7),
            vram_write => v_write, --net43,
            loadsr1 => net50,
            loadsr2 => net49,
            sr1_data(7 DOWNTO 0) => net48(0 TO 7),
            sr2_data(7 DOWNTO 0) => net47(0 TO 7),
            vram_in(7 DOWNTO 0) => v_in(7 downto 0), --net36(0 TO 7),
            attrib_out(1 DOWNTO 0) => bits(3 DOWNTO 2),
            write_color => net33,
            ppu_going => ppu_go,
            color_data(7 DOWNTO 0) => net34(0 TO 7),
            color_addr(3 DOWNTO 0) => net35(0 TO 3),
            vram_read => v_read --net44
        );
    
END schematic;
