# Basename of the chip being compiled
# Make sure $(SYSTEM).xst refers to $(SYSTEM).prj and $(SYSTEM).lso

SYSTEM = system

# VHDL source files 

VSRC = main.vhd hex2led.vhd

# Constraints file (pins and names)

CONSTRAINTS = xsb.ucf

# Directories

XILINX = /usr/cad/xilinx/ise6.2i
ISEBINDIR = $(XILINX)/bin/lin
ISEENVCMDS = LD_LIBRARY_PATH=$(ISEBINDIR) XILINX=$(XILINX) PATH=$(ISEBINDIR)
XESSBINDIR = /usr/cad/xess/bin

# Executables

XST = $(ISEENVCMDS) $(ISEBINDIR)/xst
NGDBUILD = $(ISEENVCMDS) $(ISEBINDIR)/ngdbuild
MAP = $(ISEENVCMDS) $(ISEBINDIR)/map
PAR = $(ISEENVCMDS) $(ISEBINDIR)/par
TRCE = $(ISEENVCMDS) $(ISEBINDIR)/trce
BITGEN = $(ISEENVCMDS) $(ISEBINDIR)/bitgen
XSLOAD = $(XESSBINDIR)/xsload
XESS_BOARD = XSB-300E

# Variables for simulation

SIM_SOURCEFILES = testbench.vhd $(VSRC)

ROOT_ENTITY = testbench
ROOT_ARCHITECTURE = behavioral

WORK_DIR = ./work

MAIN_INCLUDE = /usr/cad/ldv/tools.lnx86/inca/files/cdsvhdl.lib

CDSBIN = /usr/cad/ldv/tools/bin
NCVHDL = $(CDSBIN)/ncvhdl
NCELAB = $(CDSBIN)/ncelab
NCSIM = $(CDSBIN)/ncsim

NCVHDLARGS = -V93
NCSIMARGS = -gui
NCELABARGS = -ACCESS +r

# "make all" generates the .bit file for downloading to the FPGA

all: $(SYSTEM).bit

$(SYSTEM).prj : Makefile
	rm -f $(SYSTEM).prj
	for file in $(VSRC) ; do \
		echo "vhdl work $$file" >> $(SYSTEM).prj ; \
	done

# Synthesis
#
# .xst: Arguments for controlling synthesis
# .syr: Log (synthesis report)
# .ngc: Netlist file
# .ngr: Netlist file for viewer
# .lso: Library search order
# .prj: Project file (list of sources files)

$(SYSTEM).ngc $(SYSTEM).ngr $(SYSTEM).syr $(SYSTEM)_vhdl.prj : \
   $(SYSTEM).xst $(VSRC) $(SYSTEM).prj $(SYSTEM).lso 
	$(XST) -intstyle ise -ifn $(SYSTEM).xst -ofn $(SYSTEM).syr

# Add constraints to netlist information
#
# .bld : Log (build report)
# .ngd : Generic database (netlist + other information)
# .ucf : Constraints file (pins, clock timing)
# netlist.lst : List of netlists (.ngc files) read

$(SYSTEM).ngd $(SYSTEM).bld netlist.lst : $(SYSTEM).ngc $(CONSTRAINTS)
	$(NGDBUILD) -intstyle ise -p xc2s300e-pq208-6 -uc $(CONSTRAINTS) \
		$(SYSTEM).ngc $(SYSTEM).ngd

# Technology mapping (gates to LUTs)
#
# .pcf: Physical constraints file
# .ncd: Native Circuit Description (mapped netlist)
# .ngm: netlist with constraints incorporated
# .mpr: Log (map report)

$(SYSTEM)-mapped.ncd $(SYSTEM).pcf $(SYSTEM)-mapped.ngm $(SYSTEM)-mapped.mrp : \
    $(SYSTEM).ngd
	$(MAP) -intstyle ise -p xc2s300e-pq208-6 -cm area -pr b -k 4 \
	-c 100 -tx off -o $(SYSTEM)-mapped.ncd $(SYSTEM).ngd $(SYSTEM).pcf

# Place and route: Decide where the LUTs are physically, and connect wires
#
# .ncd : Placed and routed netlist
# _pad.txt : Text file describing the list of pins and their usage
# _pad.csv : Comma-separated-value file for the same
# .pad : Bar-separated file for the same
# .xpi : status

$(SYSTEM).ncd $(SYSTEM)_pad.txt $(SYSTEM)_pad.csv $(SYSTEM).xpi : \
   $(SYSTEM)-mapped.ncd $(SYSTEM).pcf
	$(PAR) -w -intstyle ise -ol 5 -xe 2 -t 1 $(SYSTEM)-mapped.ncd \
		$(SYSTEM).ncd $(SYSTEM).pcf

# Static timing analysis: verify timing constraints

$(SYSTEM).twr : $(SYSTEM).ncd $(SYSTEM).pcf
	$(TRCE)  -intstyle ise -e 3 -l 3 -xml $(SYSTEM) $(SYSTEM).ncd \
		-o $(SYSTEM).twr $(SYSTEM).pcf

# Bitstream generation
# 
# .drc: Design-rule-checking report
# .bgn: Log (bit gen)
# .bit: Bitstream to be downloaded
# .ut: options file

$(SYSTEM).bit $(SYSTEM).drc : $(SYSTEM).ncd $(SYSTEM).ut
	$(BITGEN) -intstyle ise -f $(SYSTEM).ut $(SYSTEM).ncd

# Download the bistream to the board

.PHONY : download
download : $(SYSTEM).bit
	$(XSLOAD) -fpga -b $(XESS_BOARD) $(SYSTEM).bit

clean:
	rm -f *~
	rm -f *.bgn *.bit *.bld *.drc *.ncd *.ngc *.ngd *.csv
	rm -f *.ngr *.pad *.par *.pcf *.syr *.twr *.twx *.xpi *.prj *.txt
	rm -f $(SYSTEM)-mapped.*
	rm -f netlist.lst
	rm -rf xst
	rm -rf hdl.var cds.lib $(WORK_DIR) ncvhdl.log ncelab.log \
	analyzed elaborated waves.shm ncsim.log ncsim.key .simcontrol

.PHONY : sim
sim : elaborated
	$(NCSIM) $(NCSIMARGS) $(ROOT_ENTITY)

elaborate elaborated : analyzed
	rm -f elaborated
	$(NCELAB) $(NCELABARGS) $(ROOT_ENTITY):$(ROOT_ARCHITECTURE)
	touch elaborated

analyze analyzed : hdl.var cds.lib $(WORK_DIR) $(SIM_SOURCEFILES)
	rm -f analyzed
	$(NCVHDL) $(NCVHDLARGS) $(SIM_SOURCEFILES)
	touch analyzed

hdl.var : Makefile
	echo "DEFINE WORK mywork" > hdl.var

cds.lib : Makefile
	echo "DEFINE mywork $(WORK_DIR)" > cds.lib
	echo "SOFTINCLUDE $(MAIN_INCLUDE)" >> cds.lib

$(WORK_DIR) :
	-mkdir $(WORK_DIR)

clean :
