library ieee;
use ieee.std_logic_1164.all;

-- distortion is taking the absolute value of the data.

entity distortion is
  port(clk: in STD_LOGIC;
    rst: in std_logic;
    din:in std_logic_vector(15 downto 0);
    dout:out std_logic_vector(15 downto 0));
end distortion;

architecture behavioral of distortion is
  signal temp: std_logic_vector(15 downto 0):=x"0000";
begin

  process(clk,rst)
    begin
      if rst = '1' then
          temp<=x"0000";
      elsif clk='1' and clk'event then
          if din(15)='1' then
            temp(15)<=not(din(15));
            temp(14)<=not(din(14));
            temp(13)<=not(din(13));
            temp(12)<=not(din(12));
            temp(11)<=not(din(11));
            temp(10)<=not(din(10));
            temp(9)<=not(din(9));
            temp(8)<=not(din(8));
            temp(7)<=not(din(7));
            temp(6)<=not(din(6));
            temp(5)<=not(din(5));
            temp(4)<=not(din(4));
            temp(3)<=not(din(3));
            temp(2)<=not(din(2));
            temp(1)<=not(din(1));
            temp(0)<=not(din(0));
          else
            temp(15 downto 0)<=din(15 downto 0);
          end if;
      end if;
  end process;

  dout<=temp(15 downto 0);
end behavioral;

