library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;


entity audio_clks is

port	(
      CLK : in std_logic;
      RST : in std_logic;
      
      AU_BCLK : out std_logic;
      AU_MCLK : out std_logic;
      AU_LRCK : out std_logic;

      BITCNT : out std_logic_Vector(4 downto 0)
	  );
end audio_clks;
architecture Behavioral of audio_clks is

signal clkcnt : std_logic_vector(4 downto 0);
signal audio_clk : std_logic;
signal lrck : std_logic;
signal sample_cnt : std_logic_Vector(2 downto 0);
signal bit_cnt : std_logic_vector(4 downto 0);

begin
  
process(Clk, Rst)
begin
	if Rst = '1' then 
		clkcnt <= "00000";
	elsif clk'event and clk='1' then
		clkcnt <= clkcnt + 1;                
	end if;
end process;
AU_MCLK <= clkcnt(1); -- master clock, 12.5 MHz
audio_clk <= clkcnt(4); -- this is the serial clock, 1.5625 Mhz
--AU_BCLK <= audio_clk;
AU_BCLK <= not audio_clk; -- BCLK is antiphase (as to sample in the middle
                          -- of data)

process(audio_clk, Rst)
begin
    
  if rst = '1' then
    bit_cnt <= "00000";
    lrck <= '0';
  elsif audio_clk'event and audio_clk='1' then
    bit_cnt <= bit_cnt + 1;
    lrck <= not bit_cnt(4);
  end if; 
end process;

BITCNT <= bit_cnt;
  
AU_LRCK <= lrck; --channel selection clock, 48.828 kHz

end Behavioral;
