
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 6.2 EDK_Gm.11
* DO NOT EDIT.
*
* Copyright (c) 2003 Xilinx, Inc.  All rights reserved. 
* 
* Description: Driver parameters
*
*******************************************************************/

#define STDIN_BASEADDRESS 0xFEFF0100
#define STDOUT_BASEADDRESS 0xFEFF0100

/******************************************************************/

#define XPAR_LMB_DATA_CONTROLLER_BASEADDR 0x00000000
#define XPAR_LMB_DATA_CONTROLLER_HIGHADDR 0x00001FFF
#define XPAR_LMB_INSTRUCTION_CONTROLLER_BASEADDR 0x00000000
#define XPAR_LMB_INSTRUCTION_CONTROLLER_HIGHADDR 0x00001FFF
#define XPAR_AK4565_BASEADDR 0xFEFE0000
#define XPAR_AK4565_HIGHADDR 0xFEFEFFFF

/******************************************************************/

#define XPAR_XUARTLITE_NUM_INSTANCES 1
#define XPAR_MYUART_BASEADDR 0xFEFF0100
#define XPAR_MYUART_HIGHADDR 0xFEFF01FF
#define XPAR_MYUART_DEVICE_ID 0
#define XPAR_MYUART_BAUDRATE 9600
#define XPAR_MYUART_USE_PARITY 0
#define XPAR_MYUART_ODD_PARITY 1
#define XPAR_MYUART_DATA_BITS 8

/******************************************************************/

