Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : opb_timer_1_wrapper_xst.prj

---- Target Parameters
Target Device                      : XC3S200FT256-4
Output File Name                   : ../implementation/opb_timer_1_wrapper/opb_timer_1_wrapper.ngc

---- Source Options
Top Module Name                    : opb_timer_1_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Effort                : 2
Optimization Goal                  : speed
RTL Output                         : YES
Hierarchy Separator                : /

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/common_types_pkg.vhd in Library proc_common_v1_00_b.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/tc_types_be.vhd in Library opb_timer_v1_00_b.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd in Library opb_timer_v1_00_b.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter.vhd in Library opb_timer_v1_00_b.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd in Library proc_common_v1_00_b.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd in Library opb_timer_v1_00_b.
Entity <Bus_Interface> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd in Library opb_timer_v1_00_b.
Entity <count_module> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd in Library opb_timer_v1_00_b.
Entity <timer_control> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd in Library proc_common_v1_00_b.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/tc_core.vhd in Library opb_timer_v1_00_b.
Entity <TC_Core> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd in Library opb_timer_v1_00_b.
Entity <OPB_Timer> (Architecture <IMP>) compiled.
Compiling vhdl file C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/opb_timer_1_wrapper.vhd in Library work.
Entity <opb_timer_1_wrapper> (Architecture <STRUCTURE>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd in Library proc_common_v1_00_b.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/family.vhd in Library proc_common_v1_00_b.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <opb_timer_1_wrapper> (Architecture <STRUCTURE>).
Instantiating component <opb_timer> from Library <opb_timer_v1_00_b>.
WARNING:Xst:37 - Unknown property "IP_GROUP".
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Clk> in unit <opb_timer>.
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Rst> in unit <opb_timer>.
WARNING:Xst:37 - Unknown property "SIGIS".
Entity <opb_timer_1_wrapper> analyzed. Unit <opb_timer_1_wrapper> generated.

Analyzing generic Entity <opb_timer> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_COUNT_WIDTH = 32
	C_ONE_TIMER_ONLY = 1
	C_TRIG0_ASSERT = <u>1
	C_TRIG1_ASSERT = <u>1
	C_GEN0_ASSERT = <u>1
	C_GEN1_ASSERT = <u>1
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_BASEADDR = <u>10000000001000000000000000000000
	C_HIGHADDR = <u>10000000001000000000000011111111
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Clk> in unit <opb_timer> (previous value was "10000").
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Rst> in unit <opb_timer> (previous value was "10000").
WARNING:Xst:37 - Unknown property "SIGIS".
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 273: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 283: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 293: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 293: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 293: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 293: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 302: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 309: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd line 316: Generating a Black Box for component <FDR>.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
Entity <opb_timer> analyzed. Unit <opb_timer> generated.

Analyzing generic Entity <pselect> (Architecture <imp>).
	C_AB = 24
	C_AW = 32
	C_BAR = <u>10000000001000000000000000000000
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
Entity <pselect> analyzed. Unit <pselect> generated.

Analyzing generic Entity <TC_Core> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_COUNT_WIDTH = 32
	C_ONE_TIMER_ONLY = 1
	C_OPB_DWIDTH = 32
	C_OPB_AWIDTH = 32
	C_Y = 0
	C_X = 0
	C_U_SET = "timer_control"
	C_TRIG0_ASSERT = <u>1
	C_TRIG1_ASSERT = <u>1
	C_GEN0_ASSERT = <u>1
	C_GEN1_ASSERT = <u>1
    Set user-defined property "KEEP =  TRUE" for signal <count_Down>.
WARNING:Xst:1542 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/tc_core.vhd line 271: No default binding for component: <Bus_Interface>. Generic <C_OPB_DWIDTH> is not on the component.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/tc_core.vhd line 394: Generating a Black Box for component <FDRS>.
Entity <TC_Core> analyzed. Unit <TC_Core> generated.

Analyzing generic Entity <Bus_Interface> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_COUNT_WIDTH = 32
	C_Y = 0
	C_X = 0
	C_U_SET = "timer_control"
Instantiating component <mux_onehot> from Library <proc_common_v1_00_b>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 220: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 230: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd line 238: Generating a Black Box for component <FDR>.
Entity <Bus_Interface> analyzed. Unit <Bus_Interface> generated.

Analyzing generic Entity <mux_onehot> (Architecture <imp>).
	C_DW = 32
	C_NB = 6
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd line 204: Generating a Black Box for component <MUXCY>.
Entity <mux_onehot> analyzed. Unit <mux_onehot> generated.

Analyzing generic Entity <count_module> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_COUNT_WIDTH = 32
	C_Y = 0
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd line 178: Generating a Black Box for component <FDRE>.
Entity <count_module> analyzed. Unit <count_module> generated.

Analyzing generic Entity <Counter> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_COUNT_WIDTH = 32
	C_Y = 0
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <Counter> analyzed. Unit <Counter> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 0
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 1
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit0> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 2
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit1> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 3
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit2> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 4
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit3> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 5
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit4> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 6
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit5> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 7
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit6> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 8
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit7> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 9
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit8> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 10
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit9> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 11
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit10> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 12
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit11> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 13
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit12> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 14
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit13> generated.

Analyzing generic Entity <counter_bit> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 15
	C_X = 0
	C_U_SET = "TC_Counter0"
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 179: Generating a Black Box for component <LUT4>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 190: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 197: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd line 203: Generating a Black Box for component <FDRE>.
Entity <counter_bit> analyzed. Unit <counter_bit14> generated.

Analyzing generic Entity <timer_control> (Architecture <imp>).
	C_FAMILY = "spartan3"
	C_Y = 0
	C_X = 0
	C_U_SET = "timer_control"
	C_TRIG0_ASSERT = <u>1
	C_TRIG1_ASSERT = <u>1
	C_GEN0_ASSERT = <u>1
	C_GEN1_ASSERT = <u>1
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 223: Generating a Black Box for component <FDRSE>.
WARNING:Xst:819 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 234: The following signals are missing in the process sensitivity list:
   ENT0.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 268: Generating a Black Box for component <FDRSE>.
WARNING:Xst:819 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 279: The following signals are missing in the process sensitivity list:
   ENT1.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 316: Generating a Black Box for component <FDRSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd line 326: Generating a Black Box for component <FDRSE>.
Entity <timer_control> analyzed. Unit <timer_control> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <counter_bit14>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit14> synthesized.


Synthesizing Unit <counter_bit13>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit13> synthesized.


Synthesizing Unit <counter_bit12>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit12> synthesized.


Synthesizing Unit <counter_bit11>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit11> synthesized.


Synthesizing Unit <counter_bit10>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit10> synthesized.


Synthesizing Unit <counter_bit9>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit9> synthesized.


Synthesizing Unit <counter_bit8>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit8> synthesized.


Synthesizing Unit <counter_bit7>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit7> synthesized.


Synthesizing Unit <counter_bit6>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit6> synthesized.


Synthesizing Unit <counter_bit5>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit5> synthesized.


Synthesizing Unit <counter_bit4>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit4> synthesized.


Synthesizing Unit <counter_bit3>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit3> synthesized.


Synthesizing Unit <counter_bit2>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit2> synthesized.


Synthesizing Unit <counter_bit1>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit1> synthesized.


Synthesizing Unit <counter_bit0>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit0> synthesized.


Synthesizing Unit <counter_bit>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter_bit.vhd.
Unit <counter_bit> synthesized.


Synthesizing Unit <Counter>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/counter.vhd.
    Found 1-bit xor2 for signal <carry_active_high>.
Unit <Counter> synthesized.


Synthesizing Unit <mux_onehot>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd.
WARNING:Xst:1780 - Signal <lutout<6>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<13>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<20>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<27>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<34>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<41>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<48>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<55>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<62>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<69>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<76>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<83>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<90>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<97>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<104>> is never used or assigned.
WARNING:Xst:1780 - Signal <lutout<111>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<6>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<13>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<20>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<27>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<34>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<41>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<48>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<55>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<62>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<69>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<76>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<83>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<90>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<97>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<104>> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout<111>> is never used or assigned.
WARNING:Xst:653 - Signal <one> is used but never assigned. Tied to value 1.
WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 0.
Unit <mux_onehot> synthesized.


Synthesizing Unit <timer_control>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/timer_control.vhd.
    Found 1-bit register for signal <Interrupt>.
    Found 1-bit register for signal <GenerateOut0>.
    Found 1-bit register for signal <GenerateOut1>.
    Found 1-bit register for signal <captureTrig0_d>.
    Found 1-bit register for signal <captureTrig0_d2>.
    Found 1-bit register for signal <captureTrig1_d>.
    Found 1-bit register for signal <captureTrig1_d2>.
    Found 2-bit register for signal <counter_TC_Reg>.
    Found 1-bit register for signal <generateOutPre0>.
    Found 1-bit register for signal <generateOutPre1>.
    Summary:
	inferred  11 D-type flip-flop(s).
Unit <timer_control> synthesized.


Synthesizing Unit <count_module>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/count_module.vhd.
WARNING:Xst:1780 - Signal <counter_out> is never used or assigned.
    Found 32 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  32 Multiplexer(s).
Unit <count_module> synthesized.


Synthesizing Unit <Bus_Interface>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/bus_interface.vhd.
WARNING:Xst:647 - Input <TCSR0_Reg<0:20>> is never used.
WARNING:Xst:647 - Input <TCSR1_Reg<0:20>> is never used.
WARNING:Xst:647 - Input <OPB_ABus<0:25>> is never used.
WARNING:Xst:647 - Input <OPB_ABus<30:31>> is never used.
WARNING:Xst:1780 - Signal <xferAck_FF> is never used or assigned.
WARNING:Xst:1780 - Signal <shiftReg> is never used or assigned.
WARNING:Xst:1780 - Signal <tc_xferAck_Reg> is never used or assigned.
Unit <Bus_Interface> synthesized.


Synthesizing Unit <TC_Core>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/tc_core.vhd.
WARNING:Xst:1780 - Signal <tCR2_Select> is never used or assigned.
WARNING:Xst:1780 - Signal <tCCR2_Select> is never used or assigned.
WARNING:Xst:1780 - Signal <tCSR2_Select> is never used or assigned.
WARNING:Xst:646 - Signal <counter_En<1>> is assigned but never used.
WARNING:Xst:646 - Signal <tCR1_Select> is assigned but never used.
WARNING:Xst:646 - Signal <load_Counter_Reg<1>> is assigned but never used.
WARNING:Xst:646 - Signal <captGen_Mux_Sel<1>> is assigned but never used.
WARNING:Xst:646 - Signal <load_Load_Reg<1>> is assigned but never used.
WARNING:Xst:646 - Signal <tCR0_Select> is assigned but never used.
WARNING:Xst:646 - Signal <write_Load_Reg<1>> is assigned but never used.
WARNING:Xst:646 - Signal <count_Reset<1>> is assigned but never used.
WARNING:Xst:1780 - Signal <opb_Read_Reg_CE> is never used or assigned.
WARNING:Xst:1580 - Signal <count_Down<1>> with a "keep" property is assigned but never used. Related logic will not be removed.
WARNING:Xst:1780 - Signal <tCR3_Select> is never used or assigned.
WARNING:Xst:1780 - Signal <tCCR3_Select> is never used or assigned.
Unit <TC_Core> synthesized.


Synthesizing Unit <pselect>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd.
WARNING:Xst:647 - Input <A<24:31>> is never used.
WARNING:Xst:1780 - Signal <lut_out<6>> is never used or assigned.
Unit <pselect> synthesized.


Synthesizing Unit <opb_timer>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_timer_v1_00_b/hdl/vhdl/opb_timer.vhd.
WARNING:Xst:646 - Signal <opb_seqAddr_Reg> is assigned but never used.
Unit <opb_timer> synthesized.


Synthesizing Unit <opb_timer_1_wrapper>.
    Related source file is C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/opb_timer_1_wrapper.vhd.
Unit <opb_timer_1_wrapper> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 11
 1-bit register                    : 11
# Multiplexers                     : 1
 32-bit 2-to-1 multiplexer         : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <counter_TC_Reg_1> is unconnected in block <TIMER_CONTROL_I>.

Optimizing unit <opb_timer_1_wrapper> ...

Optimizing unit <pselect> ...

Optimizing unit <timer_control> ...

Optimizing unit <mux_onehot> ...

Optimizing unit <Bus_Interface> ...

Optimizing unit <Counter> ...

Optimizing unit <count_module> ...

Optimizing unit <opb_timer> ...

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/GenerateOut1> (without init value) is constant in block <opb_timer_1_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/generateOutPre1> (without init value) is constant in block <opb_timer_1_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/counter_TC_Reg_1> (without init value) is constant in block <opb_timer_1_wrapper>.
Building and optimizing final netlist ...
WARNING:Xst:382 - Register opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_FF_I21 is equivalent to opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_FF_I21
WARNING:Xst:382 - Register opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_FF_I21 is equivalent to opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_FF_I21
WARNING:Xst:382 - Register opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_FF_I21 is equivalent to opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_FF_I21

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ../implementation/opb_timer_1_wrapper/opb_timer_1_wrapper.ngr
Top Level Output File Name         : ../implementation/opb_timer_1_wrapper/opb_timer_1_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 116

Macro Statistics :
# Registers                        : 11
#      1-bit register              : 11
# Multiplexers                     : 1
#      2-to-1 multiplexer          : 1

Cell Usage :
# BELS                             : 367
#      GND                         : 1
#      LUT2                        : 11
#      LUT2_D                      : 1
#      LUT2_L                      : 1
#      LUT3                        : 21
#      LUT3_D                      : 4
#      LUT3_L                      : 65
#      LUT4                        : 42
#      LUT4_D                      : 3
#      LUT4_L                      : 51
#      MUXCY                       : 102
#      MUXCY_L                     : 32
#      VCC                         : 1
#      XORCY                       : 32
# FlipFlops/Latches                : 245
#      FDR                         : 113
#      FDRE                        : 65
#      FDRS                        : 1
#      FDRSE                       : 66
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     226  out of   1920    11%  
 Number of Slice Flip Flops:           245  out of   3840     6%  
 Number of 4 input LUTs:               199  out of   3840     5%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
OPB_Clk                            | NONE                   | 245   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.909ns (Maximum Frequency: 126.438MHz)
   Minimum input arrival time before clock: 2.898ns
   Maximum output required time after clock: 0.720ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'OPB_Clk'
Delay:               7.909ns (Levels of Logic = 36)
  Source:            opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_FF_I31 (FF)
  Destination:       opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/CARRY_OUT_I (FF)
  Source Clock:      OPB_Clk rising
  Destination Clock: OPB_Clk rising

  Data Path: opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_FF_I31 to opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/CARRY_OUT_I
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRSE:C->Q            6   0.720   0.688  opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_FF_I31 (opb_timer_1/TC_CORE_I/tCSR0_Reg<31>)
     LUT2_D:I0->LO         1   0.551   0.100  opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/_n0441_SW0 (N109218)
     LUT4:I2->O           17   0.551   1.031  opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/_n0441 (opb_timer_1/TC_CORE_I/load_Counter_Reg<0>)
     LUT4:I2->O            1   0.551   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I31/I_ALU_LUT (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I31/count_AddSub)
     MUXCY_L:S->LO         1   0.500   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I31/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<31>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I30/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<30>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I29/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<29>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I28/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<28>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I27/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<27>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I26/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<26>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I25/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<25>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I24/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<24>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I23/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<23>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I22/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<22>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I21/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<21>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I20/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<20>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I19/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<19>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I18/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<18>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I17/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<17>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I16/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<16>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I15/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<15>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I14/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<14>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I13/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<13>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I12/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<12>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I11/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<11>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I10/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<10>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I9/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<9>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I8/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<8>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I7/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<7>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I6/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<6>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I5/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<5>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I4/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<4>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I3/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<3>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I2/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<2>)
     MUXCY_L:CI->LO        1   0.064   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I1/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<1>)
     MUXCY_L:CI->LO        1   0.303   0.240  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Counter_Bit_I0/MUXCY_I (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/alu_cy<0>)
     LUT2_L:I1->LO         1   0.551   0.000  opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/Mxor_carry_active_high_Result1 (opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/carry_active_high)
     FDRE:D                    0.203          opb_timer_1/TC_CORE_I/COUNTER_0_I/COUNTER_I/CARRY_OUT_I
    ----------------------------------------
    Total                      7.909ns (5.850ns logic, 2.059ns route)
                                       (74.0% logic, 26.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'OPB_Clk'
Offset:              2.898ns (Levels of Logic = 1)
  Source:            OPB_Rst (PAD)
  Destination:       opb_timer_1/TC_CORE_I/BUS_INTERFACE_I/READ_REG_FF_I21 (FF)
  Destination Clock: OPB_Clk rising

  Data Path: OPB_Rst to opb_timer_1/TC_CORE_I/BUS_INTERFACE_I/READ_REG_FF_I21
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT4:I1->O           32   0.551   1.321  opb_timer_1/TC_CORE_I/BUS_INTERFACE_I/opb_Read_Reg_Rst1 (opb_timer_1/TC_CORE_I/BUS_INTERFACE_I/opb_Read_Reg_Rst)
     FDR:R                     1.026          opb_timer_1/TC_CORE_I/BUS_INTERFACE_I/READ_REG_FF_I0
    ----------------------------------------
    Total                      2.898ns (1.577ns logic, 1.321ns route)
                                       (54.4% logic, 45.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'OPB_Clk'
Offset:              0.720ns (Levels of Logic = 0)
  Source:            opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/Interrupt (FF)
  Destination:       Interrupt (PAD)
  Source Clock:      OPB_Clk rising

  Data Path: opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/Interrupt to Interrupt
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              0   0.720   0.000  opb_timer_1/TC_CORE_I/TIMER_CONTROL_I/Interrupt (Interrupt)
    ----------------------------------------
    Total                      0.720ns (0.720ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 9.16 / 298.36 s | Elapsed : 9.00 / 10.00 s
 
--> 

Total memory usage is 329572 kilobytes


