Release 6.3i - xst G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> PM_SPEC -- Xilinx path component is <C:/EDK>

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : system_xst.prj

---- Target Parameters
Target Device                      : xc3s400ft256-4
Output File Name                   : ../implementation/system.ngc

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Effort                : 2
Optimization Goal                  : speed
RTL Output                         : YES
Hierarchy Separator                : /

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd in Library work.
Entity <system> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <system> (Architecture <STRUCTURE>).
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1604: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1610: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1616: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1622: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1628: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1634: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1640: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1646: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1652: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1658: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1664: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1670: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1676: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1682: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1688: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1694: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1700: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1706: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1712: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1718: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1724: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1730: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1736: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1742: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1748: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1754: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1760: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1766: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1772: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1778: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1784: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1790: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1798: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1806: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1814: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1822: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1830: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1838: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1846: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1854: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1862: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1870: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1878: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1886: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1894: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1902: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1910: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1918: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1926: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1934: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1942: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1950: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1958: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1966: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1974: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1982: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1990: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 1998: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2006: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2014: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2022: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2030: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2038: Generating a Black Box for component <IOBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2046: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2052: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2058: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2064: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2070: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2076: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2082: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2088: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2094: Generating a Black Box for component <BUFGP>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2100: Generating a Black Box for component <IBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2106: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2112: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2118: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2124: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2130: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2136: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2142: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2148: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2154: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2160: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2166: Generating a Black Box for component <OBUF>.
WARNING:Xst:766 - c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd line 2172: Generating a Black Box for component <OBUF>.
Entity <system> analyzed. Unit <system> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <system>.
    Related source file is c:/edk_user_repository/lab1/synthesis/../hdl/system.vhd.
Unit <system> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <system> ...
Loading device for application Xst from file '3s400.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ../implementation/system.ngr
Top Level Output File Name         : ../implementation/system.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 85

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 84
#      IBUF                        : 5
#      IOBUF                       : 32
#      OBUF                        : 47
# Others                           : 18
#      debug_module_wrapper        : 1
#      dlmb_cntlr_wrapper          : 1
#      dlmb_wrapper                : 1
#      ilmb_cntlr_wrapper          : 1
#      ilmb_wrapper                : 1
#      led_anodes_wrapper          : 1
#      led_cathodes_wrapper        : 1
#      leds_8bit_wrapper           : 1
#      lmb_bram_wrapper            : 1
#      mb_opb_wrapper              : 1
#      microblaze_0_wrapper        : 1
#      opb_bram_if_cntlr_1_bram_wrapper: 1
#      opb_bram_if_cntlr_1_wrapper : 1
#      opb_intc_0_wrapper          : 1
#      push_buttons_3bit_wrapper   : 1
#      rs232_wrapper               : 1
#      sram_256kx32_util_bus_split_0_wrapper: 1
#      sram_256kx32_wrapper        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400ft256-4 

 Number of bonded IOBs:                 84  out of    173    48%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 5.358ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               5.358ns (Levels of Logic = 1)
  Source:            sram_256kx32:Mem_DQ_T<27> (PAD)
  Destination:       fpga_0_SRAM_256Kx32_Mem_DQ_pin<27> (PAD)

  Data Path: sram_256kx32:Mem_DQ_T<27> to fpga_0_SRAM_256Kx32_Mem_DQ_pin<27>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    sram_256kx32_wrapper:Mem_DQ_T<27>    1   0.000   0.240  sram_256kx32 (fpga_0_SRAM_256Kx32_Mem_DQ_T<27>)
     IOBUF:T->IO               5.118          iobuf_58 (fpga_0_SRAM_256Kx32_Mem_DQ_pin<27>)
    ----------------------------------------
    Total                      5.358ns (5.118ns logic, 0.240ns route)
                                       (95.5% logic, 4.5% route)

=========================================================================
CPU : 11.63 / 12.67 s | Elapsed : 11.00 / 12.00 s
 
--> 

Total memory usage is 77432 kilobytes


