Release 6.3i - xst G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : mb_opb_wrapper_xst.prj

---- Target Parameters
Target Device                      : xc3s400ft256-4
Output File Name                   : ../implementation/mb_opb_wrapper/mb_opb_wrapper.ngc

---- Source Options
Top Module Name                    : mb_opb_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Effort                : 2
Optimization Goal                  : speed
RTL Output                         : YES
Hierarchy Separator                : /

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/dma_sg_pkg.vhd in Library opb_ipif_v1_23_a.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_a/hdl/vhdl/proc_common_pkg.vhd in Library proc_common_v1_00_a.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/dma_sg.vhd in Library opb_ipif_v1_23_a.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/dma_sg_cmp.vhd in Library opb_ipif_v1_23_a.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/ctrl_reg.vhd in Library opb_ipif_v1_23_a.
Entity <ctrl_reg> (Architecture <sim>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_a/hdl/vhdl/ld_arith_reg.vhd in Library proc_common_v1_00_a.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_a/hdl/vhdl/srl_fifo.vhd in Library proc_common_v1_00_a.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/ipif_control_wr.vhd in Library opb_ipif_v1_23_a.
Entity <ipif_control_wr> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/wrpfifo_dp_cntl.vhd in Library opb_ipif_v1_23_a.
Entity <wrpfifo_dp_cntl> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/ipif_control_rd.vhd in Library opb_ipif_v1_23_a.
Entity <ipif_control_rd> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/rdpfifo_dp_cntl.vhd in Library opb_ipif_v1_23_a.
Entity <rdpfifo_dp_cntl> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/ipif_pkg.vhd in Library opb_ipif_v1_23_a.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_a/hdl/vhdl/pselect.vhd in Library proc_common_v1_00_a.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_a/hdl/vhdl/valid_be.vhd in Library proc_common_v1_00_a.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/dma_sg_sim.vhd in Library opb_ipif_v1_23_a.
Entity <dma_sg> (Architecture <sim>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/wrpfifo_top.vhd in Library opb_ipif_v1_23_a.
Entity <wrpfifo_top> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/rdpfifo_top.vhd in Library opb_ipif_v1_23_a.
Entity <rpfifo_top> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/ipif_reset.vhd in Library opb_ipif_v1_23_a.
Entity <ipif_reset> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/ip2bus_dmux.vhd in Library opb_ipif_v1_23_a.
Entity <ip2bus_dmux> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/ip2bus_srmux.vhd in Library opb_ipif_v1_23_a.
Entity <ip2bus_srmux> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/sramdecode.vhd in Library opb_ipif_v1_23_a.
Entity <sramdecode> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/regdecode.vhd in Library opb_ipif_v1_23_a.
Entity <regdecode> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/mst_attach.vhd in Library opb_ipif_v1_23_a.
Entity <mst_attach> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/opb_arb_pkg.vhd in Library opb_arbiter_v1_02_d.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/or_muxcy.vhd in Library opb_arbiter_v1_02_d.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/master_attachment.vhd in Library opb_ipif_v1_23_a.
Entity <master_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/addr_decode.vhd in Library opb_ipif_v1_23_a.
Entity <addr_decode> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/ip2bus_srmux_blk.vhd in Library opb_ipif_v1_23_a.
Entity <ip2bus_srmux_blk> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/bus2ip_amux.vhd in Library opb_ipif_v1_23_a.
Entity <bus2ip_amux> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/ip2bus_dmux_blk.vhd in Library opb_ipif_v1_23_a.
Entity <ip2bus_dmux_blk> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/slave_attachment.vhd in Library opb_ipif_v1_23_a.
Entity <slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/reset_control.vhd in Library opb_ipif_v1_23_a.
Entity <reset_control> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/interrupt_control.vhd in Library opb_ipif_v1_23_a.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/rdfifo.vhd in Library opb_ipif_v1_23_a.
Entity <rdfifo> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/wrfifo.vhd in Library opb_ipif_v1_23_a.
Entity <wrfifo> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/dma_sg_blk.vhd in Library opb_ipif_v1_23_a.
Entity <dma_sg_blk> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/or_bits.vhd in Library opb_arbiter_v1_02_d.
Entity <or_bits> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/or_gate.vhd in Library opb_arbiter_v1_02_d.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/mux_onehot.vhd in Library opb_arbiter_v1_02_d.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/ipif.vhd in Library opb_ipif_v1_23_a.
Entity <ipif> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/onehot2encoded.vhd in Library opb_arbiter_v1_02_d.
Entity <onehot2encoded> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/priority_reg.vhd in Library opb_arbiter_v1_02_d.
Entity <priority_reg> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/watchdog_timer.vhd in Library opb_arbiter_v1_02_d.
Entity <watchdog_timer> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/control_register_logic.vhd in Library opb_arbiter_v1_02_d.
Entity <control_register_logic> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/priority_register_logic.vhd in Library opb_arbiter_v1_02_d.
Entity <priority_register_logic> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/ipif_regonly_slave.vhd in Library opb_arbiter_v1_02_d.
Entity <ipif_regonly_slave> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/arb2bus_data_mux.vhd in Library opb_arbiter_v1_02_d.
Entity <arb2bus_data_mux> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/arbitration_logic.vhd in Library opb_arbiter_v1_02_d.
Entity <arbitration_logic> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/park_lock_logic.vhd in Library opb_arbiter_v1_02_d.
Entity <park_lock_logic> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_utils_v1_00_a/hdl/vhdl/conv_funs_pkg.vhd in Library proc_utils_v1_00_a.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/opb_arbiter_core.vhd in Library opb_arbiter_v1_02_d.
Entity <opb_arbiter_core> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd in Library proc_common_v1_00_b.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/opb_arbiter.vhd in Library opb_arbiter_v1_02_d.
Entity <opb_arbiter> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_b/hdl/vhdl/opb_v20.vhd in Library opb_v20_v1_10_b.
Entity <opb_v20> (Architecture <imp>) compiled.
Compiling vhdl file C:/edk_user_repository/lab1/synthesis/../hdl/mb_opb_wrapper.vhd in Library work.
Entity <mb_opb_wrapper> (Architecture <STRUCTURE>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v1_23_a/hdl/vhdl/opb_ipif.vhd in Library opb_ipif_v1_23_a.
Entity <opb_ipif> (Architecture <implementation>) compiled.
Compiling vhdl file C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd in Library proc_common_v1_00_b.
Entity <or_muxcy> (Architecture <implementation>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <mb_opb_wrapper> (Architecture <STRUCTURE>).
Instantiating component <opb_v20> from Library <opb_v20_v1_10_b>.
Entity <mb_opb_wrapper> analyzed. Unit <mb_opb_wrapper> generated.

Analyzing generic Entity <opb_v20> (Architecture <imp>).
	C_BASEADDR = <u>11111111111111111111111111111111
	C_HIGHADDR = <u>00000000000000000000000000000000
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_NUM_MASTERS = 2
	C_NUM_SLAVES = 9
	C_USE_LUT_OR = 1
	C_EXT_RESET_HIGH = 1
	C_DYNAM_PRIORITY = 0
	C_PARK = 0
	C_PROC_INTRFCE = 0
	C_REG_GRANTS = 1
	C_DEV_BLK_ID = 0
	C_DEV_MIR_ENABLE = 0
WARNING:Xst:766 - C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_b/hdl/vhdl/opb_v20.vhd line 470: Generating a Black Box for component <SRL16>.
    Set user-defined property "INIT =  FFFF" for instance <POR_SRL_I> in unit <opb_v20>.
WARNING:Xst:766 - C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_b/hdl/vhdl/opb_v20.vhd line 484: Generating a Black Box for component <FDS>.
WARNING:Xst:821 - C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_b/hdl/vhdl/opb_v20.vhd line 538: Loop body will iterate zero times
WARNING:Xst:821 - C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_b/hdl/vhdl/opb_v20.vhd line 541: Loop body will iterate zero times
Instantiating component <opb_arbiter> from Library <opb_arbiter_v1_02_d>.
Entity <opb_v20> analyzed. Unit <opb_v20> generated.

Analyzing generic Entity <or_gate> (Architecture <imp>).
	C_OR_WIDTH = 2
	C_BUS_WIDTH = 32
	C_USE_LUT_OR = <u>1
Entity <or_gate> analyzed. Unit <or_gate> generated.

Analyzing generic Entity <or_gate> (Architecture <imp>).
	C_OR_WIDTH = 2
	C_BUS_WIDTH = 4
	C_USE_LUT_OR = <u>1
Entity <or_gate> analyzed. Unit <or_gate0> generated.

Analyzing generic Entity <or_gate> (Architecture <imp>).
	C_OR_WIDTH = 2
	C_BUS_WIDTH = 1
	C_USE_LUT_OR = <u>1
Entity <or_gate> analyzed. Unit <or_gate1> generated.

Analyzing generic Entity <or_gate> (Architecture <imp>).
	C_OR_WIDTH = 1
	C_BUS_WIDTH = 1
	C_USE_LUT_OR = <u>1
Entity <or_gate> analyzed. Unit <or_gate2> generated.

Analyzing generic Entity <or_gate> (Architecture <imp>).
	C_OR_WIDTH = 9
	C_BUS_WIDTH = 1
	C_USE_LUT_OR = <u>1
Entity <or_gate> analyzed. Unit <or_gate3> generated.

Analyzing generic Entity <or_gate> (Architecture <imp>).
	C_OR_WIDTH = 9
	C_BUS_WIDTH = 32
	C_USE_LUT_OR = <u>1
Entity <or_gate> analyzed. Unit <or_gate4> generated.

Analyzing generic Entity <opb_arbiter> (Architecture <implementation>).
	C_BASEADDR = <u>11111111111111111111111111111111
	C_HIGHADDR = <u>00000000000000000000000000000000
	C_NUM_MASTERS = 2
	C_OPB_DWIDTH = 32
	C_OPB_AWIDTH = 32
	C_DYNAM_PRIORITY = 0
	C_PARK = 0
	C_PROC_INTRFCE = 0
	C_REG_GRANTS = 1
	C_DEV_BLK_ID = 0
	C_DEV_MIR_ENABLE = 0
Entity <opb_arbiter> analyzed. Unit <opb_arbiter> generated.

Analyzing generic Entity <opb_arbiter_core> (Architecture <implementation>).
	C_BASEADDR = <u>11111111111111111111111111111111
	C_HIGHADDR = <u>00000000000000000000000000000000
	C_NUM_MASTERS = 2
	C_OPBDATA_WIDTH = 32
	C_OPBADDR_WIDTH = 32
	C_DYNAM_PRIORITY = <u>0
	C_REG_GRANTS = <u>1
	C_PARK = <u>0
	C_PROC_INTRFCE = <u>0
	C_DEV_BLK_ID = 0
	C_DEV_MIR_ENABLE = <u>0
Entity <opb_arbiter_core> analyzed. Unit <opb_arbiter_core> generated.

Analyzing Entity <watchdog_timer> (Architecture <implementation>).
Entity <watchdog_timer> analyzed. Unit <watchdog_timer> generated.

Analyzing generic Entity <control_register_logic> (Architecture <implementation>).
	C_OPBDATA_WIDTH = 32
	C_NUM_MID_BITS = 1
	C_DYNAM_PRIORITY = <u>0
	C_PARK = <u>0
	C_PROC_INTRFCE = <u>0
Entity <control_register_logic> analyzed. Unit <control_register_logic> generated.

Analyzing generic Entity <priority_register_logic> (Architecture <implementation>).
	C_NUM_MASTERS = 2
	C_OPBDATA_WIDTH = 32
	C_NUM_MID_BITS = 1
	C_DYNAM_PRIORITY = <u>0
Entity <priority_register_logic> analyzed. Unit <priority_register_logic> generated.

Analyzing generic Entity <priority_reg> (Architecture <implementation>).
	C_RESET_VALUE = <u>0
	C_NUM_MID_BITS = 1
	C_OPBDATA_WIDTH = 32
Entity <priority_reg> analyzed. Unit <priority_reg> generated.

Analyzing generic Entity <priority_reg> (Architecture <implementation>).
	C_RESET_VALUE = <u>1
	C_NUM_MID_BITS = 1
	C_OPBDATA_WIDTH = 32
Entity <priority_reg> analyzed. Unit <priority_reg5> generated.

Analyzing generic Entity <arbitration_logic> (Architecture <implementation>).
	C_NUM_MASTERS = 2
	C_NUM_MID_BITS = 1
	C_OPBDATA_WIDTH = 32
	C_DYNAM_PRIORITY = <u>0
	C_REG_GRANTS = <u>1
WARNING:Xst:766 - C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/arbitration_logic.vhd line 643: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/arbitration_logic.vhd line 643: Generating a Black Box for component <MUXCY>.
Entity <arbitration_logic> analyzed. Unit <arbitration_logic> generated.

Analyzing generic Entity <park_lock_logic> (Architecture <implementation>).
	C_NUM_MASTERS = 2
	C_NUM_MID_BITS = 1
	C_PARK = <u>0
	C_REG_GRANTS = <u>1
Entity <park_lock_logic> analyzed. Unit <park_lock_logic> generated.

Analyzing generic Entity <or_bits> (Architecture <implementation>).
	C_NUM_BITS = 2
	C_START_BIT = 0
	C_BUS_SIZE = 2
Entity <or_bits> analyzed. Unit <or_bits> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <or_bits>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/or_bits.vhd.
Unit <or_bits> synthesized.


Synthesizing Unit <priority_reg5>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/priority_reg.vhd.
WARNING:Xst:647 - Input <Bus2ip_data<0:30>> is never used.
    Found 1-bit register for signal <master_id<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <priority_reg5> synthesized.


Synthesizing Unit <priority_reg>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/priority_reg.vhd.
WARNING:Xst:647 - Input <Bus2ip_data<0:30>> is never used.
    Found 1-bit register for signal <master_id<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <priority_reg> synthesized.


Synthesizing Unit <park_lock_logic>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/park_lock_logic.vhd.
WARNING:Xst:647 - Input <Park_enable> is never used.
WARNING:Xst:647 - Input <Park_master_notlast> is never used.
WARNING:Xst:647 - Input <Park_master_id<0>> is never used.
WARNING:Xst:1780 - Signal <pend_req> is never used or assigned.
WARNING:Xst:646 - Signal <others_park> is assigned but never used.
WARNING:Xst:1780 - Signal <pend_req_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <park_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <any_request> is never used or assigned.
WARNING:Xst:646 - Signal <park_fe> is assigned but never used.
WARNING:Xst:646 - Signal <park> is assigned but never used.
    Found 2-bit register for signal <grant_last_reg>.
    Found 2-bit register for signal <mgrant_reg_i>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <park_lock_logic> synthesized.


Synthesizing Unit <arbitration_logic>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/arbitration_logic.vhd.
WARNING:Xst:1780 - Signal <engrntreg_cs> is never used or assigned.
WARNING:Xst:1780 - Signal <engrntcmb_ns> is never used or assigned.
WARNING:Xst:646 - Signal <request_lvl_n<1>> is assigned but never used.
WARNING:Xst:1780 - Signal <engrntreg_ns> is never used or assigned.
WARNING:Xst:1780 - Signal <en_grant_reg> is never used or assigned.
WARNING:Xst:1780 - Signal <engrntcmb_cs> is never used or assigned.
WARNING:Xst:1780 - Signal <any_grant> is never used or assigned.
WARNING:Xst:1780 - Signal <M_muxout<0><1>> is never used or assigned.
WARNING:Xst:1780 - Signal <M_muxout<1>> is never used or assigned.
WARNING:Xst:1780 - Signal <M_muxout<1><1>> is never used or assigned.
    Found 1-bit register for signal <arbcycle_cs<0>>.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <arbitration_logic> synthesized.


Synthesizing Unit <priority_register_logic>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/priority_register_logic.vhd.
WARNING:Xst:647 - Input <MGrant> is never used.
WARNING:Xst:653 - Signal <shift> is used but never assigned. Tied to value 00.
WARNING:Xst:646 - Signal <mgrant_n_pad> is assigned but never used.
WARNING:Xst:653 - Signal <granted_mid<0>> is used but never assigned. Tied to value 0.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 Multiplexer(s).
Unit <priority_register_logic> synthesized.


Synthesizing Unit <control_register_logic>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/control_register_logic.vhd.
WARNING:Xst:647 - Input <Clk> is never used.
WARNING:Xst:647 - Input <Rst> is never used.
WARNING:Xst:647 - Input <Bus2Ip_Data> is never used.
WARNING:Xst:647 - Input <Ctrlreg_wrce> is never used.
Unit <control_register_logic> synthesized.


Synthesizing Unit <watchdog_timer>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/watchdog_timer.vhd.
    Found 1-bit register for signal <OPB_timeout>.
    Found 4-bit up counter for signal <timeout_cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <watchdog_timer> synthesized.


Synthesizing Unit <opb_arbiter_core>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/opb_arbiter_core.vhd.
WARNING:Xst:647 - Input <OPB_BE> is never used.
WARNING:Xst:647 - Input <OPB_RNW> is never used.
WARNING:Xst:647 - Input <OPB_Dbus> is never used.
WARNING:Xst:647 - Input <OPB_Abus> is never used.
WARNING:Xst:647 - Input <OPB_seqAddr> is never used.
WARNING:Xst:646 - Signal <priority_register> is assigned but never used.
WARNING:Xst:646 - Signal <bus2ip_reg_rdce> is assigned but never used.
WARNING:Xst:1780 - Signal <arb2bus_data> is never used or assigned.
WARNING:Xst:1780 - Signal <arb2bus_rdack> is never used or assigned.
WARNING:Xst:646 - Signal <ctrl_reg<1>> is assigned but never used.
WARNING:Xst:646 - Signal <ctrl_reg<3>> is assigned but never used.
WARNING:Xst:646 - Signal <ctrl_reg<6:30>> is assigned but never used.
WARNING:Xst:1780 - Signal <arb2bus_wrack> is never used or assigned.
Unit <opb_arbiter_core> synthesized.


Synthesizing Unit <opb_arbiter>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_d/hdl/vhdl/opb_arbiter.vhd.
Unit <opb_arbiter> synthesized.


Synthesizing Unit <or_gate4>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd.
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate4> synthesized.


Synthesizing Unit <or_gate3>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd.
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate3> synthesized.


Synthesizing Unit <or_gate2>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd.
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate2> synthesized.


Synthesizing Unit <or_gate1>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd.
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate1> synthesized.


Synthesizing Unit <or_gate0>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd.
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate0> synthesized.


Synthesizing Unit <or_gate>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd.
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate> synthesized.


Synthesizing Unit <opb_v20>.
    Related source file is C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_b/hdl/vhdl/opb_v20.vhd.
WARNING:Xst:647 - Input <Sl_DBusEn> is never used.
WARNING:Xst:647 - Input <Sl_DBusEn32_63> is never used.
WARNING:Xst:647 - Input <M_DBusEn32_63> is never used.
WARNING:Xst:647 - Input <M_DBusEn> is never used.
WARNING:Xst:646 - Signal <arb_errack> is assigned but never used.
WARNING:Xst:646 - Signal <arb_dbus> is assigned but never used.
WARNING:Xst:646 - Signal <arb_toutsup> is assigned but never used.
WARNING:Xst:646 - Signal <arb_retry> is assigned but never used.
WARNING:Xst:646 - Signal <arb_xferack> is assigned but never used.
Unit <opb_v20> synthesized.


Synthesizing Unit <mb_opb_wrapper>.
    Related source file is C:/edk_user_repository/lab1/synthesis/../hdl/mb_opb_wrapper.vhd.
Unit <mb_opb_wrapper> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 4-bit up counter                  : 1
# Registers                        : 7
 1-bit register                    : 6
 2-bit register                    : 1
# Multiplexers                     : 3
 2-bit 2-to-1 multiplexer          : 1
 1-bit 2-to-1 multiplexer          : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <OPB_ARBITER_I/OPB_ARBITER_CORE_I/PRIORITY_REGS_I/LOW_PRIOR_REG1/master_id_0> (without init value) is constant in block <opb_v20>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <OPB_ARBITER_I/OPB_ARBITER_CORE_I/PRIORITY_REGS_I/PRIOR_REG0/master_id_0> (without init value) is constant in block <opb_v20>.

Optimizing unit <mb_opb_wrapper> ...

Optimizing unit <or_gate> ...

Optimizing unit <or_gate4> ...

Optimizing unit <arbitration_logic> ...

Optimizing unit <park_lock_logic> ...

Optimizing unit <watchdog_timer> ...

Optimizing unit <opb_v20> ...

Mapping all equations...
Building and optimizing final netlist ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ../implementation/mb_opb_wrapper/mb_opb_wrapper.ngr
Top Level Output File Name         : ../implementation/mb_opb_wrapper/mb_opb_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 696

Macro Statistics :
# Registers                        : 8
#      1-bit register              : 6
#      2-bit register              : 1
#      4-bit register              : 1
# Multiplexers                     : 3
#      2-to-1 multiplexer          : 3

Cell Usage :
# BELS                             : 252
#      GND                         : 1
#      LUT1                        : 1
#      LUT2                        : 77
#      LUT2_D                      : 1
#      LUT2_L                      : 2
#      LUT3                        : 78
#      LUT4                        : 87
#      LUT4_D                      : 1
#      LUT4_L                      : 1
#      MUXCY                       : 2
#      VCC                         : 1
# FlipFlops/Latches                : 11
#      FDR                         : 4
#      FDRE                        : 6
#      FDS                         : 1
# Shifters                         : 1
#      SRL16                       : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400ft256-4 

 Number of Slices:                     145  out of   3584     4%  
 Number of Slice Flip Flops:            11  out of   7168     0%  
 Number of 4 input LUTs:               249  out of   7168     3%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
OPB_Clk                            | NONE                   | 12    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 3.986ns (Maximum Frequency: 250.878MHz)
   Minimum input arrival time before clock: 5.178ns
   Maximum output required time after clock: 0.720ns
   Maximum combinational path delay: 2.924ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'OPB_Clk'
Delay:               3.986ns (Levels of Logic = 2)
  Source:            mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/timeout_cnt_3 (FF)
  Destination:       mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout (FF)
  Source Clock:      OPB_Clk rising
  Destination Clock: OPB_Clk rising

  Data Path: mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/timeout_cnt_3 to mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             5   0.720   0.658  mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/timeout_cnt_3 (mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/timeout_cnt_3)
     LUT4:I1->O            1   0.551   0.240  mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/_n0003_SW111 (CHOICE400)
     LUT4:I3->O            1   0.551   0.240  mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/_n0003_SW115 (mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/_n0003)
     FDR:R                     1.026          mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout
    ----------------------------------------
    Total                      3.986ns (2.848ns logic, 1.138ns route)
                                       (71.5% logic, 28.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'OPB_Clk'
Offset:              5.178ns (Levels of Logic = 5)
  Source:            Sl_xferAck<1> (PAD)
  Destination:       mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout (FF)
  Destination Clock: OPB_Clk rising

  Data Path: Sl_xferAck<1> to mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I0->O            1   0.551   0.240  mb_opb/OPB_xferAck_I/_n00098 (CHOICE83)
     LUT4:I3->O            1   0.551   0.240  mb_opb/OPB_xferAck_I/_n000913_SW0 (N10527)
     LUT4:I3->O            3   0.551   0.577  mb_opb/OPB_xferAck_I/_n000913 (OPB_xferAck)
     LUT4_D:I1->LO         1   0.551   0.100  mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/SF72621 (N10623)
     LUT4:I2->O            1   0.551   0.240  mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/_n0003_SW115 (mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/_n0003)
     FDR:R                     1.026          mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout
    ----------------------------------------
    Total                      5.178ns (3.781ns logic, 1.397ns route)
                                       (73.0% logic, 27.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'OPB_Clk'
Offset:              0.720ns (Levels of Logic = 0)
  Source:            mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout (FF)
  Destination:       OPB_timeout (PAD)
  Source Clock:      OPB_Clk rising

  Data Path: mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout to OPB_timeout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              0   0.720   0.000  mb_opb/OPB_ARBITER_I/OPB_ARBITER_CORE_I/WATCHDOG_TIMER_I/OPB_timeout (OPB_timeout)
    ----------------------------------------
    Total                      0.720ns (0.720ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               2.924ns (Levels of Logic = 4)
  Source:            Sl_DBus<32> (PAD)
  Destination:       OPB_DBus<0> (PAD)

  Data Path: Sl_DBus<32> to OPB_DBus<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I0->O            1   0.551   0.240  mb_opb/OPB_rdDBus_I/_n00098 (CHOICE67)
     LUT4:I3->O            1   0.551   0.240  mb_opb/OPB_rdDBus_I/_n000913_SW0 (N10487)
     LUT4:I3->O            1   0.551   0.240  mb_opb/OPB_rdDBus_I/_n000913 (OPB_rdDBus<0>)
     LUT3:I2->O            0   0.551   0.000  mb_opb/OPB_DBus_I/_n00021 (OPB_DBus<0>)
    ----------------------------------------
    Total                      2.924ns (2.204ns logic, 0.720ns route)
                                       (75.4% logic, 24.6% route)

=========================================================================
CPU : 8.02 / 53.50 s | Elapsed : 8.00 / 9.00 s
 
--> 

Total memory usage is 126320 kilobytes


