Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : ilmb_wrapper_xst.prj

---- Target Parameters
Target Device                      : XC3S200FT256-4
Output File Name                   : ../implementation/ilmb_wrapper/ilmb_wrapper.ngc

---- Source Options
Top Module Name                    : ilmb_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Effort                : 2
Optimization Goal                  : speed
RTL Output                         : YES
Hierarchy Separator                : /

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/hdl/vhdl/lmb_v10.vhd in Library lmb_v10_v1_00_a.
Entity <lmb_v10> (Architecture <IMP>) compiled.
Compiling vhdl file C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/ilmb_wrapper.vhd in Library work.
Entity <ilmb_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ilmb_wrapper> (Architecture <STRUCTURE>).
Instantiating component <lmb_v10> from Library <lmb_v10_v1_00_a>.
Entity <ilmb_wrapper> analyzed. Unit <ilmb_wrapper> generated.

Analyzing generic Entity <lmb_v10> (Architecture <imp>).
	C_LMB_NUM_SLAVES = 1
	C_LMB_AWIDTH = 32
	C_LMB_DWIDTH = 32
	C_EXT_RESET_HIGH = 1
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/hdl/vhdl/lmb_v10.vhd line 145: Generating a Black Box for component <SRL16>.
    Set user-defined property "INIT =  FFFF" for instance <POR_SRL_I> in unit <lmb_v10>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/hdl/vhdl/lmb_v10.vhd line 159: Generating a Black Box for component <FDS>.
Entity <lmb_v10> analyzed. Unit <lmb_v10> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lmb_v10>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/hdl/vhdl/lmb_v10.vhd.
Unit <lmb_v10> synthesized.


Synthesizing Unit <ilmb_wrapper>.
    Related source file is C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/ilmb_wrapper.vhd.
Unit <ilmb_wrapper> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ilmb_wrapper> ...

Mapping all equations...
Building and optimizing final netlist ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ../implementation/ilmb_wrapper/ilmb_wrapper.ngr
Top Level Output File Name         : ../implementation/ilmb_wrapper/ilmb_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 211

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# FlipFlops/Latches                : 1
#      FDS                         : 1
# Shifters                         : 1
#      SRL16                       : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                       1  out of   1920     0%  
 Number of Slice Flip Flops:             1  out of   3840     0%  
 Number of 4 input LUTs:                 1  out of   3840     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
LMB_Clk                            | NONE                   | 2     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 3.638ns (Maximum Frequency: 274.876MHz)
   Minimum input arrival time before clock: 1.026ns
   Maximum output required time after clock: 0.720ns
   Maximum combinational path delay: 0.000ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'LMB_Clk'
Delay:               3.638ns (Levels of Logic = 0)
  Source:            ilmb/POR_SRL_I (FF)
  Destination:       ilmb/POR_FF_I (FF)
  Source Clock:      LMB_Clk rising
  Destination Clock: LMB_Clk rising

  Data Path: ilmb/POR_SRL_I to ilmb/POR_FF_I
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     SRL16:CLK->Q          1   3.195   0.240  ilmb/POR_SRL_I (ilmb/srl_time_out)
     FDS:D                     0.203          ilmb/POR_FF_I
    ----------------------------------------
    Total                      3.638ns (3.398ns logic, 0.240ns route)
                                       (93.4% logic, 6.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'LMB_Clk'
Offset:              1.026ns (Levels of Logic = 0)
  Source:            SYS_Rst (PAD)
  Destination:       ilmb/POR_FF_I (FF)
  Destination Clock: LMB_Clk rising

  Data Path: SYS_Rst to ilmb/POR_FF_I
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:S                     1.026          ilmb/POR_FF_I
    ----------------------------------------
    Total                      1.026ns (1.026ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'LMB_Clk'
Offset:              0.720ns (Levels of Logic = 0)
  Source:            ilmb/POR_FF_I (FF)
  Destination:       LMB_Rst (PAD)
  Source Clock:      LMB_Clk rising

  Data Path: ilmb/POR_FF_I to LMB_Rst
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              0   0.720   0.000  ilmb/POR_FF_I (LMB_Rst)
    ----------------------------------------
    Total                      0.720ns (0.720ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               0.000ns (Levels of Logic = 0)
  Source:            M_AddrStrobe (PAD)
  Destination:       LMB_AddrStrobe (PAD)

  Data Path: M_AddrStrobe to LMB_AddrStrobe
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    ----------------------------------------
    Total                      0.000ns (0.000ns logic, 0.000ns route)

=========================================================================
CPU : 3.34 / 217.00 s | Elapsed : 3.00 / 4.00 s
 
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Total memory usage is 238948 kilobytes


