####################################################
## FileName: fpga.flw
##
## Flow File to run Xilinx FPGA Flow
##
## Version: 6.1.1
## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/flowfiles/fpga.flw,v 1.28 2003/02/11 00:52:47 jpan Exp $
####################################################

ExportDir: <workdir>;        # Directory to copy program outputs
ReportDir: <workdir>;        # Directory to copy program reports

#
# Global user-defined variables
#
Variables
$simulation_output = time_sim;

###################################################################
# Xflow generated *.scr on UNIX and *.bat script on PC by default, 
# if the $scripts_to_generate variable is empty.  
#
# You can specify the script to be generated by setting the 
# $scripts_to_generate variable.
# To generate multiple scripts, list each script separated by commas.
#
# Accepted values (case insensitive, comma separated): 
#   bat, scr, tcl 
#
# Ex: $scripts_to_generate = "bat"; 
#  -- Generates *.bat file (regardless of platform).
# Ex: $scripts_to_generate = "bat, tcl"; 
#  -- Generates *.bat and *.tcl file (regardless of platform).
#
# Note: DO NOT change the $scripts_to_generate variable name. 
#       Make sure the variable is uncommented if you specify its value(s).
###################################################################
#$scripts_to_generate = "";

End Variables

#
# Flow Info for XST
#
Program xst
Flag: ENABLED;
Input:<synthdesign>;
Triggers: <design>.prj, <design>.xcf;
Exports: <design>.ngc;
End Program xst

#
# Flow Info for Exemplar
#
Program spectrum 
Flag: ENABLED;
Input:<synthdesign>;
Triggers: <design>_exem.tcl;
$srclist = "";
Exports: <design>.edf;
End Program spectrum 

#
# Flow Info for Synplicity
#
Program  synplify_pro
Flag: ENABLED;
Input:<synthdesign>;
Triggers: <design>_syn.prj;
$srclist = "";
Exports: <design>.edf;
End Program  synplify_pro

#
# Flow Info for Translator
#
Program ngdbuild
Flag : ENABLED;
Input: <userdesign>;
Triggers: <design>.ucf, <design>.urf, <design>.ncf, <design>.bmm, netlist.lst;
Exports : <design>.ngd;
Reports : <design>.bld;
End Program ngdbuild

#
# Flow Info for Mapper
#
Program map
Flag: ENABLED;
Input: <design>.ngd;
Triggers: <design>.mfp;
Exports : <design>_map.ncd;
Reports : <design>_map.mrp;
End Program map

#
# Flow Info for Post Map Trace
#
Program post_map_trce
Flag: DISABLED;
Executable: trce;
Input: <design>_map.ncd;
Reports: <design>_map.twr, <design>_map.tsi, <design>_map.twx;
End Program post_map_trce

#
# Flow Info for Place and Route
#
Program par
Flag : ENABLED;
Input: <design>_map.ncd;
Triggers: <design>.pcf;
Exports : <design>.ncd;
Reports: <design>.par, <design>.dly, <design>.pad;
End Program par

#
# Flow Info for Post Par Trace
#
Program post_par_trce
Flag: ENABLED;
Executable: trce;
Input: <design>.ncd;
Reports: <design>.twr, <design>.tsi, <design>.twx;
End Program post_par_trce

#
# Flow Info for Netgen
#
Program netgen 
Flag: ENABLED;
Input: <design>.ncd;
Triggers: <design>.pcf, <design>.elf, <design>.mem, <design>.ngm;
$input_extension = ncd;
Exports: $simulation_output.v, 
         $simulation_output.vhd,
         $simulation_output.sdf,
         $simulation_output.tv,
         $simulation_output.tvhd;
Reports : <design>.nlf;
End Program netgen 

#
# Flow Info for Netgen
#
Program netgen_ecn
Flag: ENABLED;
Executable: netgen;
Input: <design>.ncd;
Triggers: <design>.pcf, <design>.elf, <design>.mem, <design>.ngm;
$input_extension = ncd;
Exports: <design>_ecn.v;
Reports : <design>.nlf;
End Program netgen_ecn 

#
# Flow Info for Netgen
#
Program netgen_sta
Flag: ENABLED;
Executable: netgen;
Input: <design>.ncd;
Triggers: <design>.pcf, <design>.elf, <design>.mem, <design>.ngm;
$input_extension = ncd;
Exports: <design>_sta.v;
Reports : <design>.nlf;
End Program netgen_sta 

#
# Flow Info for Bitgen
#
Program bitgen
Flag: ENABLED;
Input: <design>.ncd;
Triggers: <design>.elf;
Exports: <design>.bit, <design>.ll, <design>.msk, <design>.rbt;
Reports: <design>.bgn, <design>.drc;
End Program bitgen
