Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : rs232_wrapper_xst.prj

---- Target Parameters
Target Device                      : XC3S200FT256-4
Output File Name                   : ../implementation/rs232_wrapper/rs232_wrapper.ngc

---- Source Options
Top Module Name                    : rs232_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Effort                : 2
Optimization Goal                  : speed
RTL Output                         : YES
Hierarchy Separator                : /

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd in Library opb_uartlite_v1_00_b.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/baudrate.vhd in Library opb_uartlite_v1_00_b.
Entity <Baud_Rate> (Architecture <VHDL_RTL>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd in Library opb_uartlite_v1_00_b.
Entity <OPB_UARTLITE_RX> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd in Library opb_uartlite_v1_00_b.
Entity <OPB_UARTLITE_TX> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd in Library common_v1_00_a.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd in Library opb_uartlite_v1_00_b.
Entity <OPB_UARTLITE_Core> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite.vhd in Library opb_uartlite_v1_00_b.
Entity <OPB_UARTLITE> (Architecture <IMP>) compiled.
Compiling vhdl file C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/rs232_wrapper.vhd in Library work.
Entity <rs232_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <rs232_wrapper> (Architecture <STRUCTURE>).
Instantiating component <opb_uartlite> from Library <opb_uartlite_v1_00_b>.
Entity <rs232_wrapper> analyzed. Unit <rs232_wrapper> generated.

Analyzing generic Entity <opb_uartlite> (Architecture <imp>).
	C_BASEADDR = <u>10000000001000000000001100000000
	C_HIGHADDR = <u>10000000001000000000001111111111
	C_OPB_DWIDTH = 32
	C_OPB_AWIDTH = 32
	C_DATA_BITS = 8
	C_CLK_FREQ = 50000000
	C_BAUDRATE = 9600
	C_USE_PARITY = 0
	C_ODD_PARITY = 0
Instantiating component <pselect> from Library <Common_v1_00_a>.
Entity <opb_uartlite> analyzed. Unit <opb_uartlite> generated.

Analyzing generic Entity <pselect> (Architecture <imp>).
	C_AB = 24
	C_AW = 32
	C_BAR = <u>10000000001000000000001100000000
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
Entity <pselect> analyzed. Unit <pselect> generated.

Analyzing generic Entity <OPB_UARTLITE_Core> (Architecture <imp>).
	C_DATA_BITS = 8
	C_CLK_FREQ = 50000000
	C_BAUDRATE = 9600
	C_USE_PARITY = 0
	C_ODD_PARITY = 0
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 241: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 284: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 292: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 339: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 372: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 372: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 372: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 372: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 372: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 372: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 372: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd line 372: Generating a Black Box for component <FDRE>.
Entity <OPB_UARTLITE_Core> analyzed. Unit <OPB_UARTLITE_Core> generated.

Analyzing generic Entity <Baud_Rate> (Architecture <vhdl_rtl>).
	C_RATIO = 325
	C_INACCURACY = 20
Entity <Baud_Rate> analyzed. Unit <Baud_Rate> generated.

Analyzing generic Entity <OPB_UARTLITE_RX> (Architecture <imp>).
	C_DATA_BITS = 8
	C_USE_PARITY = 0
	C_ODD_PARITY = 0
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd line 279: Generating a Black Box for component <SRL16E>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd line 299: Generating a Black Box for component <SRL16E>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd line 388: Generating a Black Box for component <FDSE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd line 402: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd line 402: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd line 402: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd line 402: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd line 402: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd line 402: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd line 402: Generating a Black Box for component <FDRE>.
Entity <OPB_UARTLITE_RX> analyzed. Unit <OPB_UARTLITE_RX> generated.

Analyzing generic Entity <SRL_FIFO> (Architecture <imp>).
	C_DATA_BITS = 8
	C_DEPTH = 16
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 203: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 211: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 217: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 203: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 211: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 217: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 203: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 211: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 217: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 211: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 217: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 228: Generating a Black Box for component <SRL16E>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 228: Generating a Black Box for component <SRL16E>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 228: Generating a Black Box for component <SRL16E>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 228: Generating a Black Box for component <SRL16E>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 228: Generating a Black Box for component <SRL16E>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 228: Generating a Black Box for component <SRL16E>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 228: Generating a Black Box for component <SRL16E>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd line 228: Generating a Black Box for component <SRL16E>.
Entity <SRL_FIFO> analyzed. Unit <SRL_FIFO> generated.

Analyzing generic Entity <OPB_UARTLITE_TX> (Architecture <imp>).
	C_DATA_BITS = 8
	C_USE_PARITY = 0
	C_ODD_PARITY = 0
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd line 249: Generating a Black Box for component <SRL16E>.
    Set user-defined property "INIT =  0001" for instance <DIV16_SRL16E> in unit <OPB_UARTLITE_TX>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd line 264: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd line 314: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd line 322: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd line 314: Generating a Black Box for component <MUXCY_L>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd line 322: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd line 322: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd line 390: Generating a Black Box for component <MUXF5>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd line 397: Generating a Black Box for component <MUXF5>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd line 404: Generating a Black Box for component <MUXF6>.
Entity <OPB_UARTLITE_TX> analyzed. Unit <OPB_UARTLITE_TX> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <SRL_FIFO>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/srl_fifo.vhd.
WARNING:Xst:1780 - Signal <addr_cy<4>> is never used or assigned.
    Found 1-bit xor2 for signal <$n0007> created at line 199.
    Found 1-bit xor2 for signal <$n0008> created at line 199.
    Found 1-bit xor2 for signal <$n0009> created at line 199.
    Found 1-bit xor2 for signal <$n0010> created at line 199.
    Found 1-bit register for signal <data_Exists_I>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <SRL_FIFO> synthesized.


Synthesizing Unit <OPB_UARTLITE_TX>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_tx.vhd.
WARNING:Xst:1780 - Signal <parity> is never used or assigned.
WARNING:Xst:1780 - Signal <cnt_cy<0>> is never used or assigned.
WARNING:Xst:1780 - Signal <tx_Run1> is never used or assigned.
WARNING:Xst:1780 - Signal <calc_Parity> is never used or assigned.
    Found 1-bit register for signal <TX>.
    Found 1-bit register for signal <fifo_Read>.
    Found 3-bit register for signal <mux_sel>.
    Found 1-bit register for signal <serial_Data>.
    Found 1-bit register for signal <tx_DataBits>.
    Found 1-bit register for signal <tx_Start>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <OPB_UARTLITE_TX> synthesized.


Synthesizing Unit <OPB_UARTLITE_RX>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_rx.vhd.
WARNING:Xst:1305 - Output <RX_Parity_Error> is never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <parity> is never used or assigned.
WARNING:Xst:1780 - Signal <calc_Parity> is never used or assigned.
    Found 1-bit register for signal <FIFO_Write>.
    Found 1-bit register for signal <previous_RX>.
    Found 1-bit register for signal <running<0>>.
    Found 1-bit register for signal <rx_1>.
    Found 1-bit register for signal <rx_2>.
    Found 1-bit register for signal <start_Edge_Detected<0>>.
    Found 1-bit register for signal <stop_Bit_Position>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   7 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <OPB_UARTLITE_RX> synthesized.


Synthesizing Unit <Baud_Rate>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/baudrate.vhd.
    Found 1-bit register for signal <EN_16x_Baud>.
    Found 9-bit down counter for signal <Count>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <Baud_Rate> synthesized.


Synthesizing Unit <OPB_UARTLITE_Core>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite_core.vhd.
WARNING:Xst:646 - Signal <rx_Parity_Error> is assigned but never used.
    Register <xfer_Ack> equivalent to <uart_CS_3> has been removed
    Found 1-bit register for signal <Interrupt>.
    Found 1-bit register for signal <enable_interrupts>.
    Found 1-bit register for signal <opb_RNW_1>.
    Found 1-bit register for signal <reset_RX_FIFO>.
    Found 1-bit register for signal <reset_TX_FIFO>.
    Found 1-bit register for signal <uart_CS_2>.
    Found 1-bit register for signal <uart_CS_3>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   7 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <OPB_UARTLITE_Core> synthesized.


Synthesizing Unit <pselect>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd.
WARNING:Xst:647 - Input <A<24:31>> is never used.
WARNING:Xst:1780 - Signal <lut_out<6>> is never used or assigned.
Unit <pselect> synthesized.


Synthesizing Unit <opb_uartlite>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_uartlite_v1_00_b/hdl/vhdl/opb_uartlite.vhd.
WARNING:Xst:647 - Input <OPB_BE> is never used.
WARNING:Xst:647 - Input <OPB_DBus<0:23>> is never used.
WARNING:Xst:647 - Input <OPB_seqAddr> is never used.
Unit <opb_uartlite> synthesized.


Synthesizing Unit <rs232_wrapper>.
    Related source file is C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/rs232_wrapper.vhd.
Unit <rs232_wrapper> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 9-bit down counter                : 1
# Registers                        : 23
 1-bit register                    : 22
 3-bit register                    : 1
# Multiplexers                     : 13
 8-bit 2-to-1 multiplexer          : 1
 1-bit 2-to-1 multiplexer          : 12
# Xors                             : 8
 1-bit xor2                        : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <rs232_wrapper> ...

Optimizing unit <pselect> ...

Optimizing unit <SRL_FIFO> ...

Optimizing unit <OPB_UARTLITE_RX> ...

Optimizing unit <OPB_UARTLITE_TX> ...

Optimizing unit <OPB_UARTLITE_Core> ...

Mapping all equations...
Building and optimizing final netlist ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ../implementation/rs232_wrapper/rs232_wrapper.ngr
Top Level Output File Name         : ../implementation/rs232_wrapper/rs232_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 112

Macro Statistics :
# Registers                        : 32
#      1-bit register              : 31
#      3-bit register              : 1
# Multiplexers                     : 13
#      2-to-1 multiplexer          : 13
# Adders/Subtractors               : 1
#      9-bit subtractor            : 1

Cell Usage :
# BELS                             : 127
#      GND                         : 1
#      LUT1                        : 14
#      LUT2                        : 2
#      LUT2_L                      : 1
#      LUT3                        : 6
#      LUT3_D                      : 1
#      LUT3_L                      : 7
#      LUT4                        : 17
#      LUT4_D                      : 6
#      LUT4_L                      : 26
#      MUXCY                       : 14
#      MUXCY_L                     : 8
#      MUXF5                       : 2
#      MUXF6                       : 1
#      VCC                         : 1
#      XORCY                       : 20
# FlipFlops/Latches                : 63
#      FDC                         : 11
#      FDCE                        : 5
#      FDP                         : 5
#      FDPE                        : 3
#      FDR                         : 8
#      FDRE                        : 27
#      FDS                         : 3
#      FDSE                        : 1
# Shifters                         : 19
#      SRL16E                      : 19
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                      54  out of   1920     2%  
 Number of Slice Flip Flops:            63  out of   3840     1%  
 Number of 4 input LUTs:                99  out of   3840     2%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
OPB_Clk                            | NONE                   | 82    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 5.513ns (Maximum Frequency: 181.389MHz)
   Minimum input arrival time before clock: 3.525ns
   Maximum output required time after clock: 0.720ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'OPB_Clk'
Delay:               5.513ns (Levels of Logic = 1)
  Source:            rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Delay_16 (FF)
  Destination:       rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/stop_Bit_Position (FF)
  Source Clock:      OPB_Clk rising
  Destination Clock: OPB_Clk rising

  Data Path: rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Delay_16 to rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/stop_Bit_Position
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     SRL16E:CLK->Q        14   3.195   0.925  rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/Delay_16 (rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/sample_Point)
     LUT3:I1->O            1   0.551   0.240  rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/_n00351 (rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/_n0035)
     FDCE:CE                   0.602          rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_RX_I/stop_Bit_Position
    ----------------------------------------
    Total                      5.513ns (4.348ns logic, 1.165ns route)
                                       (78.9% logic, 21.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'OPB_Clk'
Offset:              3.525ns (Levels of Logic = 6)
  Source:            OPB_ABus<28> (PAD)
  Destination:       rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FDRE_I3 (FF)
  Destination Clock: OPB_Clk rising

  Data Path: OPB_ABus<28> to rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FDRE_I3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT4_D:I0->O          6   0.551   0.688  rs232/OPB_UARTLITE_Core_I/write_TX_FIFO1 (rs232/OPB_UARTLITE_Core_I/write_TX_FIFO)
     LUT4_L:I0->LO         1   0.551   0.000  rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/_n00581 (rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/hsum_A<0>)
     MUXCY_L:S->LO         1   0.500   0.000  rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/MUXCY_L_I0 (rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/addr_cy<1>)
     MUXCY_L:CI->LO        1   0.064   0.000  rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/MUXCY_L_I1 (rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/addr_cy<2>)
     MUXCY_L:CI->LO        0   0.064   0.000  rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/MUXCY_L_I2 (rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/addr_cy<3>)
     XORCY:CI->O           1   0.904   0.000  rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/XORCY_I3 (rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/sum_A<3>)
     FDRE:D                    0.203          rs232/OPB_UARTLITE_Core_I/OPB_UARTLITE_TX_I/SRL_FIFO_I/FDRE_I3
    ----------------------------------------
    Total                      3.525ns (2.837ns logic, 0.688ns route)
                                       (80.5% logic, 19.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'OPB_Clk'
Offset:              0.720ns (Levels of Logic = 0)
  Source:            rs232/OPB_UARTLITE_Core_I/Interrupt (FF)
  Destination:       Interrupt (PAD)
  Source Clock:      OPB_Clk rising

  Data Path: rs232/OPB_UARTLITE_Core_I/Interrupt to Interrupt
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              0   0.720   0.000  rs232/OPB_UARTLITE_Core_I/Interrupt (Interrupt)
    ----------------------------------------
    Total                      0.720ns (0.720ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 4.79 / 241.40 s | Elapsed : 5.00 / 6.00 s
 
--> 

Total memory usage is 263524 kilobytes


