Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : sram_256kx32_util_bus_split_0_wrapper_xst.prj

---- Target Parameters
Target Device                      : XC3S200FT256-4
Output File Name                   : ../implementation/sram_256kx32_util_bus_split_0_wrapper/sram_256kx32_util_bus_split_0_wrapper.ngc

---- Source Options
Top Module Name                    : sram_256kx32_util_bus_split_0_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Effort                : 2
Optimization Goal                  : speed
RTL Output                         : YES
Hierarchy Separator                : /

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/util_bus_split_v1_00_a/hdl/vhdl/util_bus_split.vhd in Library util_bus_split_v1_00_a.
Entity <util_bus_split> (Architecture <IMP>) compiled.
Compiling vhdl file C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/sram_256kx32_util_bus_split_0_wrapper.vhd in Library work.
Entity <sram_256kx32_util_bus_split_0_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sram_256kx32_util_bus_split_0_wrapper> (Architecture <STRUCTURE>).
Instantiating component <util_bus_split> from Library <util_bus_split_v1_00_a>.
Entity <sram_256kx32_util_bus_split_0_wrapper> analyzed. Unit <sram_256kx32_util_bus_split_0_wrapper> generated.

Analyzing generic Entity <util_bus_split> (Architecture <imp>).
	C_SIZE_IN = 32
	C_LEFT_POS = 12
	C_SPLIT = 30
Entity <util_bus_split> analyzed. Unit <util_bus_split> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <util_bus_split>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/util_bus_split_v1_00_a/hdl/vhdl/util_bus_split.vhd.
WARNING:Xst:647 - Input <Sig<0:11>> is never used.
Unit <util_bus_split> synthesized.


Synthesizing Unit <sram_256kx32_util_bus_split_0_wrapper>.
    Related source file is C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/sram_256kx32_util_bus_split_0_wrapper.vhd.
Unit <sram_256kx32_util_bus_split_0_wrapper> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <sram_256kx32_util_bus_split_0_wrapper> ...

Mapping all equations...
Building and optimizing final netlist ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ../implementation/sram_256kx32_util_bus_split_0_wrapper/sram_256kx32_util_bus_split_0_wrapper.ngr
Top Level Output File Name         : ../implementation/sram_256kx32_util_bus_split_0_wrapper/sram_256kx32_util_bus_split_0_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 52

Cell Usage :
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 



=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 0.000ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               0.000ns (Levels of Logic = 0)
  Source:            Sig<12> (PAD)
  Destination:       Out1<12> (PAD)

  Data Path: Sig<12> to Out1<12>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    ----------------------------------------
    Total                      0.000ns (0.000ns logic, 0.000ns route)

=========================================================================
CPU : 3.07 / 310.36 s | Elapsed : 3.00 / 4.00 s
 
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Total memory usage is 340836 kilobytes


