Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : sram_256kx32_wrapper_xst.prj

---- Target Parameters
Target Device                      : XC3S200FT256-4
Output File Name                   : ../implementation/sram_256kx32_wrapper/sram_256kx32_wrapper.ngc

---- Source Options
Top Module Name                    : sram_256kx32_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Effort                : 2
Optimization Goal                  : speed
RTL Output                         : YES
Hierarchy Separator                : /

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/inferred_lut4.vhd in Library proc_common_v1_00_b.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/pf_counter_bit.vhd in Library opb_ipif_v2_00_a.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd in Library proc_common_v1_00_b.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/pf_adder_bit.vhd in Library opb_ipif_v2_00_a.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/pf_counter.vhd in Library opb_ipif_v2_00_a.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/pf_occ_counter.vhd in Library opb_ipif_v2_00_a.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/dma_sg_pkg.vhd in Library opb_ipif_v2_00_a.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_a/hdl/vhdl/ipif_pkg.vhd in Library ipif_common_v1_00_a.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd in Library opb_ipif_v2_00_a.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/pf_counter_top.vhd in Library opb_ipif_v2_00_a.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/pf_adder.vhd in Library opb_ipif_v2_00_a.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/pf_dly1_mux.vhd in Library opb_ipif_v2_00_a.
Entity <pf_dly1_mux> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd in Library proc_common_v1_00_b.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/dma_sg.vhd in Library opb_ipif_v2_00_a.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/dma_sg_cmp.vhd in Library opb_ipif_v2_00_a.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ctrl_reg.vhd in Library opb_ipif_v2_00_a.
Entity <ctrl_reg> (Architecture <sim>) compiled.
Entity <ctrl_reg_0_to_6> (Architecture <sim>) compiled.
Entity <ctrl_reg_0_to_0> (Architecture <sim>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd in Library proc_common_v1_00_b.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/srl_fifo.vhd in Library proc_common_v1_00_b.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ipif_control_wr.vhd in Library opb_ipif_v2_00_a.
Entity <ipif_control_wr> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/wrpfifo_dp_cntl.vhd in Library opb_ipif_v2_00_a.
Entity <wrpfifo_dp_cntl> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/pf_dpram_select.vhd in Library opb_ipif_v2_00_a.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/srl16_fifo.vhd in Library opb_ipif_v2_00_a.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ipif_control_rd.vhd in Library opb_ipif_v2_00_a.
Entity <ipif_control_rd> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/rdpfifo_dp_cntl.vhd in Library opb_ipif_v2_00_a.
Entity <rdpfifo_dp_cntl> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ipif_reset.vhd in Library opb_ipif_v2_00_a.
Entity <ipif_reset> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd in Library proc_common_v1_00_b.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/down_counter.vhd in Library proc_common_v1_00_b.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ip2bus_dmux.vhd in Library opb_ipif_v2_00_a.
Entity <ip2bus_dmux> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ip2bus_srmux.vhd in Library opb_ipif_v2_00_a.
Entity <ip2bus_srmux> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd in Library proc_common_v1_00_b.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/addr_load_and_incr.vhd in Library opb_ipif_v2_00_a.
Entity <addr_load_and_incr> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/mst_module.vhd in Library opb_ipif_v2_00_a.
Entity <mst_module> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/family.vhd in Library proc_common_v1_00_b.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/master_attachment.vhd in Library opb_ipif_v2_00_a.
Entity <master_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/address_decoder.vhd in Library opb_ipif_v2_00_a.
Entity <address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ip2bus_srmux_blk.vhd in Library opb_ipif_v2_00_a.
Entity <ip2bus_srmux_blk> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/bus2ip_amux.vhd in Library opb_ipif_v2_00_a.
Entity <bus2ip_amux> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ip2bus_dmux_blk.vhd in Library opb_ipif_v2_00_a.
Entity <ip2bus_dmux_blk> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/slave_attachment.vhd in Library opb_ipif_v2_00_a.
Entity <slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_a/hdl/vhdl/ipif_steer.vhd in Library ipif_common_v1_00_a.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/reset_control.vhd in Library opb_ipif_v2_00_a.
Entity <reset_control> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_a/hdl/vhdl/interrupt_control.vhd in Library ipif_common_v1_00_a.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/rdpfifo_top.vhd in Library opb_ipif_v2_00_a.
Entity <rdpfifo_top> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/wrpfifo_top.vhd in Library opb_ipif_v2_00_a.
Entity <wrpfifo_top> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/dma_sg_sim.vhd in Library opb_ipif_v2_00_a.
Entity <dma_sg> (Architecture <sim>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/io_registers.vhd in Library emc_common_v1_10_b.
Entity <io_registers> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd in Library proc_common_v1_00_b.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/wait_states.vhd in Library emc_common_v1_10_b.
Entity <Wait_States> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/mem_state_machine.vhd in Library emc_common_v1_10_b.
Entity <Mem_State_Machine> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd in Library emc_common_v1_10_b.
Entity <data_path> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/select_param.vhd in Library emc_common_v1_10_b.
Entity <select_param> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/addr_counter_mux.vhd in Library emc_common_v1_10_b.
Entity <addr_counter_mux> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ipif.vhd in Library opb_ipif_v2_00_a.
Entity <ipif> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/opb_ipif.vhd in Library opb_ipif_v2_00_a.
Entity <opb_ipif> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/emc.vhd in Library emc_common_v1_10_b.
Entity <EMC> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd in Library opb_emc_v1_10_b.
Entity <opb_emc> (Architecture <implementation>) compiled.
Compiling vhdl file C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/sram_256kx32_wrapper.vhd in Library work.
Entity <sram_256kx32_wrapper> (Architecture <STRUCTURE>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/valid_be.vhd in Library proc_common_v1_00_b.
Entity <valid_be> (Architecture <implementation>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sram_256kx32_wrapper> (Architecture <STRUCTURE>).
Instantiating component <opb_emc> from Library <opb_emc_v1_10_b>.
Entity <sram_256kx32_wrapper> analyzed. Unit <sram_256kx32_wrapper> generated.

Analyzing generic Entity <opb_emc> (Architecture <implementation>).
	C_NUM_BANKS_MEM = 1
	C_INCLUDE_NEGEDGE_IOREGS = 0
	C_BASEADDR = <u>10000000001000000000010000000000
	C_HIGHADDR = <u>10000000001000000000010111111111
	C_MEM0_BASEADDR = <u>10000000001100000000000000000000
	C_MEM0_HIGHADDR = <u>10000000001111111111111111111111
	C_MEM1_BASEADDR = <u>11111111111111111111111111111111
	C_MEM1_HIGHADDR = <u>00000000000000000000000000000000
	C_MEM2_BASEADDR = <u>11111111111111111111111111111111
	C_MEM2_HIGHADDR = <u>00000000000000000000000000000000
	C_MEM3_BASEADDR = <u>11111111111111111111111111111111
	C_MEM3_HIGHADDR = <u>00000000000000000000000000000000
	C_MEM4_BASEADDR = <u>11111111111111111111111111111111
	C_MEM4_HIGHADDR = <u>00000000000000000000000000000000
	C_MEM5_BASEADDR = <u>11111111111111111111111111111111
	C_MEM5_HIGHADDR = <u>00000000000000000000000000000000
	C_MEM6_BASEADDR = <u>11111111111111111111111111111111
	C_MEM6_HIGHADDR = <u>00000000000000000000000000000000
	C_MEM7_BASEADDR = <u>11111111111111111111111111111111
	C_MEM7_HIGHADDR = <u>00000000000000000000000000000000
	C_MEM0_WIDTH = 32
	C_MEM1_WIDTH = 32
	C_MEM2_WIDTH = 32
	C_MEM3_WIDTH = 32
	C_MEM4_WIDTH = 32
	C_MEM5_WIDTH = 32
	C_MEM6_WIDTH = 32
	C_MEM7_WIDTH = 32
	C_MAX_MEM_WIDTH = 32
	C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_1 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_2 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_3 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_4 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_5 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_6 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_7 = 1
	C_SYNCH_MEM_0 = 0
	C_SYNCH_PIPEDELAY_0 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_0 = 10000
	C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 8000
	C_WRITE_MIN_PULSE_WIDTH_PS_0 = 8000
	C_READ_ADDR_TO_OUT_FAST_PS_0 = 10000
	C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 8000
	C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 0
	C_SYNCH_MEM_1 = 0
	C_SYNCH_PIPEDELAY_1 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_1 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_1 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_1 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_1 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_1 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_1 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_1 = 0
	C_SYNCH_MEM_2 = 0
	C_SYNCH_PIPEDELAY_2 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_2 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_2 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_2 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_2 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_2 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_2 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_2 = 0
	C_SYNCH_MEM_3 = 0
	C_SYNCH_PIPEDELAY_3 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_3 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_3 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_3 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_3 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_3 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_3 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_3 = 0
	C_SYNCH_MEM_4 = 0
	C_SYNCH_PIPEDELAY_4 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_4 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_4 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_4 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_4 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_4 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_4 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_4 = 0
	C_SYNCH_MEM_5 = 0
	C_SYNCH_PIPEDELAY_5 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_5 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_5 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_5 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_5 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_5 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_5 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_5 = 0
	C_SYNCH_MEM_6 = 0
	C_SYNCH_PIPEDELAY_6 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_6 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_6 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_6 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_6 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_6 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_6 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_6 = 0
	C_SYNCH_MEM_7 = 0
	C_SYNCH_PIPEDELAY_7 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_7 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_7 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_7 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_7 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_7 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_7 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_7 = 0
	C_OPB_DWIDTH = 32
	C_OPB_AWIDTH = 32
	C_OPB_CLK_PERIOD_PS = 20000
	C_DEV_BLK_ID = 1
	C_DEV_MIR_ENABLE = 0
Instantiating component <opb_ipif> from Library <opb_ipif_v2_00_a>.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Mn_ABus' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Bus2IP_MstWrAck' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Bus2IP_MstRdAck' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Bus2IP_MstRetry' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Bus2IP_MstError' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Bus2IP_MstTimeOut' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Bus2IP_MstLastAck' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Mn_request' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Mn_busLock' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Mn_select' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Mn_RNW' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Mn_BE' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Mn_seqAddr' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'RFIFO2IP_AlmostFull' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'RFIFO2IP_Full' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'RFIFO2IP_Vacancy' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'RFIFO2IP_WrAck' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'WFIFO2IP_AlmostEmpty' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'WFIFO2IP_Data' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'WFIFO2IP_Empty' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'WFIFO2IP_Occupancy' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'WFIFO2IP_RdAck' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Bus2IP_DMA_Ack' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'Bus2IP_Freeze' of component 'opb_ipif'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd line 1213: Unconnected output port 'IP2INTC_Irpt' of component 'opb_ipif'.
Instantiating component <emc> from Library <emc_common_v1_10_b>.
Entity <opb_emc> analyzed. Unit <opb_emc> generated.

Analyzing generic Entity <opb_ipif> (Architecture <implementation>).
	C_ARD_ID_ARRAY = (120, 121, 122, 123, 124, 125, 126, 127, 128, 2)
	C_ARD_ADDR_RANGE_ARRAY = (<u>0000000000000000000000000000000010000000001000000000010000000000, <u>0000000000000000000000000000000010000000001000000000010011111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001000000000010101000000, <u>0000000000000000000000000000000010000000001000000000010111111111)
	C_ARD_DWIDTH_ARRAY = (32, 32, 32, 32, 32, 32, 32, 32, 32, 32)
	C_ARD_NUM_CE_ARRAY = (8, 1, 1, 1, 1, 1, 1, 1, 1, 1)
	C_DEV_BLK_ID = 1
	C_DEV_MIR_ENABLE = 0
	C_DEV_BURST_ENABLE = 0
	C_DEV_MAX_BURST_SIZE = 0
	C_INCLUDE_DEV_ISC = 0
	C_INCLUDE_DEV_PENCODER = 0
	C_IP_INTR_MODE_ARRAY = (0, 0)
	C_IP_MASTER_PRESENT = 0
	C_DMA_CHAN_TYPE_ARRAY = (2, 3)
	C_DMA_LENGTH_WIDTH_ARRAY = (11, 11)
	C_DMA_PKT_LEN_FIFO_ADDR_ARRAY = (<u>0000000000000000000000000000000000000000000000000000000000000000, <u>0000000000000000000000000000000000000000000000000000000000000000)
	C_DMA_PKT_STAT_FIFO_ADDR_ARRAY = (<u>0000000000000000000000000000000000000000000000000000000000000000, <u>0000000000000000000000000000000000000000000000000000000000000000)
	C_DMA_INTR_COALESCE_ARRAY = (0, 0)
	C_DMA_ALLOW_BURST = 1
	C_DMA_PACKET_WAIT_UNIT_NS = 1000000
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_OPB_CLK_PERIOD_PS = 20000
	C_IPIF_DWIDTH = 32
	C_FAMILY = "virtex2"
Entity <opb_ipif> analyzed. Unit <opb_ipif> generated.

Analyzing generic Entity <ipif> (Architecture <implementation>).
	C_ARD_ID_ARRAY = (120, 121, 122, 123, 124, 125, 126, 127, 128, 2)
	C_ARD_ADDR_RANGE_ARRAY = (<u>0000000000000000000000000000000010000000001000000000010000000000, <u>0000000000000000000000000000000010000000001000000000010011111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001000000000010101000000, <u>0000000000000000000000000000000010000000001000000000010111111111)
	C_ARD_DWIDTH_ARRAY = (32, 32, 32, 32, 32, 32, 32, 32, 32, 32)
	C_ARD_NUM_CE_ARRAY = (8, 1, 1, 1, 1, 1, 1, 1, 1, 1)
	C_DEV_BLK_ID = 1
	C_DEV_MIR_ENABLE = <u>0
	C_DEV_BURST_ENABLE = <u>0
	C_DEV_MAX_BURST_SIZE = 0
	C_INCLUDE_DEV_ISC = <u>0
	C_INCLUDE_DEV_PENCODER = <u>0
	C_IP_INTR_MODE_ARRAY = (0, 0)
	C_IP_MASTER_PRESENT = <u>0
	C_DMA_CHAN_TYPE_ARRAY = (2, 3)
	C_DMA_LENGTH_WIDTH_ARRAY = (11, 11)
	C_DMA_PKT_LEN_FIFO_ADDR_ARRAY = (<u>0000000000000000000000000000000000000000000000000000000000000000, <u>0000000000000000000000000000000000000000000000000000000000000000)
	C_DMA_PKT_STAT_FIFO_ADDR_ARRAY = (<u>0000000000000000000000000000000000000000000000000000000000000000, <u>0000000000000000000000000000000000000000000000000000000000000000)
	C_DMA_INTR_COALESCE_ARRAY = (0, 0)
	C_DMA_ALLOW_BURST = <u>1
	C_DMA_PACKET_WAIT_UNIT_NS = 1000000
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_OPB_CLK_PERIOD_PS = 20000
	C_IPIF_DWIDTH = 32
	C_FAMILY = "virtex2"
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ipif.vhd line 1497: Unconnected output port 'Addr_Match' of component 'address_decoder'.
WARNING:Xst:752 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ipif.vhd line 1606: Unconnected input port 'MA2SA_Retry' of component 'slave_attachment' is tied to default value.
Instantiating component <IPIF_Steer> from Library <ipif_common_v1_00_a>.
Entity <ipif> analyzed. Unit <ipif> generated.

Analyzing generic Entity <address_decoder> (Architecture <imp>).
	C_BUS_AWIDTH = 21
	C_USE_REG_OUTPUTS = <u>1
	C_ARD_ADDR_RANGE_ARRAY = (<u>0000000000000000000000000000000010000000001000000000010000000000, <u>0000000000000000000000000000000010000000001000000000010011111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001100000000000000000000, <u>0000000000000000000000000000000010000000001111111111111111111111, <u>0000000000000000000000000000000010000000001000000000010101000000, <u>0000000000000000000000000000000010000000001000000000010111111111)
	C_ARD_DWIDTH_ARRAY = (32, 32, 32, 32, 32, 32, 32, 32, 32, 32)
	C_ARD_NUM_CE_ARRAY = (8, 1, 1, 1, 1, 1, 1, 1, 1, 1)
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <or_gate> from Library <proc_common_v1_00_b>.
Instantiating component <or_gate> from Library <proc_common_v1_00_b>.
Entity <address_decoder> analyzed. Unit <address_decoder> generated.

Analyzing generic Entity <pselect> (Architecture <imp>).
	C_AB = 13
	C_AW = 21
	C_BAR = <u>000000000010000000000
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
Entity <pselect> analyzed. Unit <pselect> generated.

Analyzing generic Entity <pselect> (Architecture <imp>).
	C_AB = 1
	C_AW = 21
	C_BAR = <u>100000000000000000000
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
Entity <pselect> analyzed. Unit <pselect0> generated.

Analyzing generic Entity <pselect> (Architecture <imp>).
	C_AB = 13
	C_AW = 21
	C_BAR = <u>000000000010101000000
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
Entity <pselect> analyzed. Unit <pselect1> generated.

Analyzing generic Entity <or_gate> (Architecture <imp>).
	C_OR_WIDTH = 10
	C_BUS_WIDTH = 3
	C_USE_LUT_OR = <u>1
Entity <or_gate> analyzed. Unit <or_gate> generated.

Analyzing generic Entity <or_gate> (Architecture <imp>).
	C_OR_WIDTH = 10
	C_BUS_WIDTH = 1
	C_USE_LUT_OR = <u>1
Entity <or_gate> analyzed. Unit <or_gate2> generated.

Analyzing Entity <ip2bus_srmux_blk> (Architecture <implementation>).
Entity <ip2bus_srmux_blk> analyzed. Unit <ip2bus_srmux_blk> generated.

Analyzing Entity <ip2bus_srmux> (Architecture <implementation>).
Entity <ip2bus_srmux> analyzed. Unit <ip2bus_srmux> generated.

Analyzing generic Entity <bus2ip_amux> (Architecture <implementation>).
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
Entity <bus2ip_amux> analyzed. Unit <bus2ip_amux> generated.

Analyzing generic Entity <ip2bus_dmux_blk> (Architecture <implementation>).
	C_DBUS_WIDTH = 32
Entity <ip2bus_dmux_blk> analyzed. Unit <ip2bus_dmux_blk> generated.

Analyzing generic Entity <ip2bus_dmux> (Architecture <implementation>).
	C_DBUS_WIDTH = 32
Entity <ip2bus_dmux> analyzed. Unit <ip2bus_dmux> generated.

Analyzing generic Entity <slave_attachment> (Architecture <implementation>).
	C_OPB_ABUS_WIDTH = 32
	C_OPB_DBUS_WIDTH = 32
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
	C_DEV_ADDR_DECODE_WIDTH = 11
	C_DEV_BASEADDR = <u>10000000001000000000010000000000
	C_DEV_BURST_ENABLE = <u>0
	C_DEV_IS_SLAVE_ONLY = <u>1
	C_MA2SA_NUM_WIDTH = 4
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
Entity <slave_attachment> analyzed. Unit <slave_attachment> generated.

Analyzing generic Entity <pselect> (Architecture <imp>).
	C_AB = 11
	C_AW = 32
	C_BAR = <u>10000000001000000000010000000000
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
Entity <pselect> analyzed. Unit <pselect3> generated.

Analyzing generic Entity <IPIF_Steer> (Architecture <imp>).
	C_DWIDTH = 32
	C_SMALLEST = 32
	C_AWIDTH = 32
Entity <IPIF_Steer> analyzed. Unit <IPIF_Steer> generated.

Analyzing generic Entity <reset_control> (Architecture <implementation>).
	C_IPIF_MIR_ENABLE = <u>0
	C_IPIF_TYPE = 1
	C_IPIF_BLK_ID = 1
	C_IPIF_REVISION = 0
	C_IPIF_MINOR_VERSION = 0
	C_IPIF_MAJOR_VERSION = 2
	C_OPB_DBUS_WIDTH = 32
Entity <reset_control> analyzed. Unit <reset_control> generated.

Analyzing generic Entity <ipif_reset> (Architecture <implementation>).
	C_DBUS_WIDTH = 32
	C_IPIF_MIR_ENABLE = <u>0
	C_IPIF_TYPE = 1
	C_IPIF_BLK_ID = 1
	C_IPIF_REVISION = 0
	C_IPIF_MINOR_VERSION = 0
	C_IPIF_MAJOR_VERSION = 2
Entity <ipif_reset> analyzed. Unit <ipif_reset> generated.

Analyzing generic Entity <emc> (Architecture <imp>).
	C_NUM_BANKS_MEM = 1
	C_INCLUDE_NEGEDGE_IOREGS = 0
	C_INCLUDE_BURST = 0
	C_IPIF_DWIDTH = 32
	C_IPIF_AWIDTH = 32
	C_MEM0_WIDTH = 32
	C_MEM1_WIDTH = 32
	C_MEM2_WIDTH = 32
	C_MEM3_WIDTH = 32
	C_MEM4_WIDTH = 32
	C_MEM5_WIDTH = 32
	C_MEM6_WIDTH = 32
	C_MEM7_WIDTH = 32
	C_MAX_MEM_WIDTH = 32
	C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_1 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_2 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_3 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_4 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_5 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_6 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_7 = 1
	C_BUS_CLOCK_PERIOD_PS = 20000
	C_SYNCH_MEM_0 = 0
	C_SYNCH_PIPEDELAY_0 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_0 = 10000
	C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 8000
	C_WRITE_MIN_PULSE_WIDTH_PS_0 = 8000
	C_READ_ADDR_TO_OUT_FAST_PS_0 = 10000
	C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 8000
	C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 0
	C_SYNCH_MEM_1 = 0
	C_SYNCH_PIPEDELAY_1 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_1 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_1 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_1 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_1 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_1 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_1 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_1 = 0
	C_SYNCH_MEM_2 = 0
	C_SYNCH_PIPEDELAY_2 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_2 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_2 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_2 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_2 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_2 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_2 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_2 = 0
	C_SYNCH_MEM_3 = 0
	C_SYNCH_PIPEDELAY_3 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_3 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_3 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_3 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_3 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_3 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_3 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_3 = 0
	C_SYNCH_MEM_4 = 0
	C_SYNCH_PIPEDELAY_4 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_4 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_4 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_4 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_4 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_4 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_4 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_4 = 0
	C_SYNCH_MEM_5 = 0
	C_SYNCH_PIPEDELAY_5 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_5 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_5 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_5 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_5 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_5 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_5 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_5 = 0
	C_SYNCH_MEM_6 = 0
	C_SYNCH_PIPEDELAY_6 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_6 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_6 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_6 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_6 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_6 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_6 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_6 = 0
	C_SYNCH_MEM_7 = 0
	C_SYNCH_PIPEDELAY_7 = 2
	C_READ_ADDR_TO_OUT_SLOW_PS_7 = 0
	C_WRITE_ADDR_TO_OUT_SLOW_PS_7 = 0
	C_WRITE_MIN_PULSE_WIDTH_PS_7 = 0
	C_READ_ADDR_TO_OUT_FAST_PS_7 = 0
	C_WRITE_ADDR_TO_OUT_FAST_PS_7 = 0
	C_READ_RECOVERY_BEFORE_WRITE_PS_7 = 0
	C_WRITE_RECOVERY_BEFORE_READ_PS_7 = 0
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <mux_onehot> from Library <proc_common_v1_00_b>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/emc.vhd line 1304: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/emc.vhd line 1312: Generating a Black Box for component <FDRE>.
Entity <emc> analyzed. Unit <emc> generated.

Analyzing generic Entity <io_registers> (Architecture <imp>).
	C_GLOBAL_DATAWIDTH_MATCH = 1
	C_INCLUDE_NEGEDGE_IOREGS = 0
	C_IPIF_AWIDTH = 32
	C_MAX_MEM_WIDTH = 32
	C_NUM_BANKS_MEM = 1
Entity <io_registers> analyzed. Unit <io_registers> generated.

Analyzing generic Entity <mux_onehot> (Architecture <imp>).
	C_DW = 2
	C_NB = 1
Entity <mux_onehot> analyzed. Unit <mux_onehot> generated.

Analyzing generic Entity <Wait_States> (Architecture <imp>).
	C_NUM_BANKS_MEM = 1
	C_RD_SLOW_0 = 2
	C_RD_FAST_0 = 2
	C_WR_SLOW_0 = 2
	C_WR_FAST_0 = 2
	C_RD_RECOVERY_0 = 0
	C_WR_RECOVERY_0 = 0
	C_RD_SLOW_1 = 2
	C_RD_FAST_1 = 2
	C_WR_SLOW_1 = 2
	C_WR_FAST_1 = 2
	C_RD_RECOVERY_1 = 0
	C_WR_RECOVERY_1 = 0
	C_RD_SLOW_2 = 2
	C_RD_FAST_2 = 2
	C_WR_SLOW_2 = 2
	C_WR_FAST_2 = 2
	C_RD_RECOVERY_2 = 0
	C_WR_RECOVERY_2 = 0
	C_RD_SLOW_3 = 2
	C_RD_FAST_3 = 2
	C_WR_SLOW_3 = 2
	C_WR_FAST_3 = 2
	C_RD_RECOVERY_3 = 0
	C_WR_RECOVERY_3 = 0
	C_RD_SLOW_4 = 2
	C_RD_FAST_4 = 2
	C_WR_SLOW_4 = 2
	C_WR_FAST_4 = 2
	C_RD_RECOVERY_4 = 0
	C_WR_RECOVERY_4 = 0
	C_RD_SLOW_5 = 2
	C_RD_FAST_5 = 2
	C_WR_SLOW_5 = 2
	C_WR_FAST_5 = 2
	C_RD_RECOVERY_5 = 0
	C_WR_RECOVERY_5 = 0
	C_RD_SLOW_6 = 2
	C_RD_FAST_6 = 2
	C_WR_SLOW_6 = 2
	C_WR_FAST_6 = 2
	C_RD_RECOVERY_6 = 0
	C_WR_RECOVERY_6 = 0
	C_RD_SLOW_7 = 2
	C_RD_FAST_7 = 2
	C_WR_SLOW_7 = 2
	C_WR_FAST_7 = 2
	C_RD_RECOVERY_7 = 0
	C_WR_RECOVERY_7 = 0
Entity <Wait_States> analyzed. Unit <Wait_States> generated.

Analyzing generic Entity <Mem_State_Machine> (Architecture <imp>).
	C_ADDR_CNTR_WIDTH = 2
	C_INCLUDE_BURST = 0
WARNING:Xst:819 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/mem_state_machine.vhd line 233: The following signals are missing in the process sensitivity list:
   Two_pipe_delay, Valid_Memory_Access.
INFO:Xst:1304 - Contents of register <read_xfer_next> in unit <Mem_State_Machine> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <Mem_Wrcycle_Done> in unit <Mem_State_Machine> never changes during circuit operation. The register is replaced by logic.
Entity <Mem_State_Machine> analyzed. Unit <Mem_State_Machine> generated.

Analyzing generic Entity <data_path> (Architecture <imp>).
	C_MAX_MEM_WIDTH = 32
	C_MIN_MEM_WIDTH = 8
	C_IPIF_DWIDTH = 32
	C_ADDR_CNTR_WIDTH = 2
	C_GLOBAL_DATAWIDTH_MATCH = 1
	C_GLOBAL_SYNC_MEM = 0
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 439: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 607: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 615: Generating a Black Box for component <FDR>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd line 635: Generating a Black Box for component <FDR>.
Entity <data_path> analyzed. Unit <data_path> generated.

Analyzing generic Entity <select_param> (Architecture <imp>).
	C_NUM_BANKS_MEM = 1
	C_GLOBAL_SYNC_MEM = 0
	C_SYNCH_MEM_0 = 0
	C_SYNCH_MEM_1 = 0
	C_SYNCH_MEM_2 = 0
	C_SYNCH_MEM_3 = 0
	C_SYNCH_MEM_4 = 0
	C_SYNCH_MEM_5 = 0
	C_SYNCH_MEM_6 = 0
	C_SYNCH_MEM_7 = 0
	C_ACCESS_CNTR_0 = <u>00
	C_ACCESS_CNTR_1 = <u>00
	C_ACCESS_CNTR_2 = <u>00
	C_ACCESS_CNTR_3 = <u>00
	C_ACCESS_CNTR_4 = <u>00
	C_ACCESS_CNTR_5 = <u>00
	C_ACCESS_CNTR_6 = <u>00
	C_ACCESS_CNTR_7 = <u>00
	C_ADDR_CNTR_WIDTH = 2
	C_MEM0_WIDTH = 32
	C_MEM1_WIDTH = 32
	C_MEM2_WIDTH = 32
	C_MEM3_WIDTH = 32
	C_MEM4_WIDTH = 32
	C_MEM5_WIDTH = 32
	C_MEM6_WIDTH = 32
	C_MEM7_WIDTH = 32
	C_SYNCH_PIPEDELAY_0 = 2
	C_SYNCH_PIPEDELAY_1 = 2
	C_SYNCH_PIPEDELAY_2 = 2
	C_SYNCH_PIPEDELAY_3 = 2
	C_SYNCH_PIPEDELAY_4 = 2
	C_SYNCH_PIPEDELAY_5 = 2
	C_SYNCH_PIPEDELAY_6 = 2
	C_SYNCH_PIPEDELAY_7 = 2
	C_GLOBAL_DATAWIDTH_MATCH = 1
	C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_1 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_2 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_3 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_4 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_5 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_6 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_7 = 1
Entity <select_param> analyzed. Unit <select_param> generated.

Analyzing generic Entity <addr_counter_mux> (Architecture <imp>).
	C_ADDR_CNTR_WIDTH = 2
	C_IPIF_AWIDTH = 32
	C_ADDR_OFFSET = 2
	C_GLOBAL_DATAWIDTH_MATCH = 1
Instantiating component <ld_arith_reg> from Library <proc_common_v1_00_b>.
Entity <addr_counter_mux> analyzed. Unit <addr_counter_mux> generated.

Analyzing generic Entity <ld_arith_reg> (Architecture <imp>).
	C_ADD_SUB_NOT = <u>1
	C_REG_WIDTH = 2
	C_RESET_VALUE = <u>00
	C_LD_WIDTH = 2
	C_LD_OFFSET = 0
	C_AD_WIDTH = 1
	C_AD_OFFSET = 0
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd line 232: Generating a Black Box for component <MULT_AND>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd line 242: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd line 253: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd line 269: Generating a Black Box for component <FDRE>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd line 232: Generating a Black Box for component <MULT_AND>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd line 242: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd line 253: Generating a Black Box for component <XORCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd line 269: Generating a Black Box for component <FDRE>.
Entity <ld_arith_reg> analyzed. Unit <ld_arith_reg> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ld_arith_reg>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd.
WARNING:Xst:646 - Signal <cry<0>> is assigned but never used.
Unit <ld_arith_reg> synthesized.


Synthesizing Unit <addr_counter_mux>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/addr_counter_mux.vhd.
WARNING:Xst:647 - Input <Rst> is never used.
    Found 32 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  32 Multiplexer(s).
Unit <addr_counter_mux> synthesized.


Synthesizing Unit <select_param>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/select_param.vhd.
WARNING:Xst:1780 - Signal <synch_mem_sig> is never used or assigned.
    Using one-hot encoding for signal <mem_width>.
Unit <select_param> synthesized.


Synthesizing Unit <data_path>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/data_path.vhd.
WARNING:Xst:647 - Input <Mem_OEN> is never used.
WARNING:Xst:647 - Input <Mem_Wrcycle_Done> is never used.
WARNING:Xst:1780 - Signal <mem_oen_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <mem_oen_d2> is never used or assigned.
WARNING:Xst:1780 - Signal <mem_rdcycle_done_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <mem_rdcycle_done_d2> is never used or assigned.
    Found 2-bit register for signal <addr_cnt_d1>.
    Found 2-bit register for signal <addr_cnt_d2>.
    Found 32-bit register for signal <mem_readdata_reg>.
    Found 4-bit register for signal <read_ce>.
    Found 1-bit register for signal <read_ce0_d1>.
    Found 4-bit register for signal <read_ce_reg1>.
    Found 33 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  45 D-type flip-flop(s).
	inferred  33 Multiplexer(s).
Unit <data_path> synthesized.


Synthesizing Unit <Mem_State_Machine>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/mem_state_machine.vhd.
WARNING:Xst:646 - Signal <count_wait_1> is assigned but never used.
WARNING:Xst:1780 - Signal <counter_recover> is never used or assigned.
WARNING:Xst:646 - Signal <count_recover_2> is assigned but never used.
WARNING:Xst:646 - Signal <read_xfer_next> is assigned but never used.
WARNING:Xst:1780 - Signal <write_xfer_next> is never used or assigned.
WARNING:Xst:1780 - Signal <write_xfer> is never used or assigned.
WARNING:Xst:1780 - Signal <read_xfer> is never used or assigned.
    Found finite state machine <FSM_0> for signal <current_State>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 40                                             |
    | Inputs             | 15                                             |
    | Outputs            | 13                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | $n0075 (positive)                              |
    | Reset type         | synchronous                                    |
    | Reset State        | start_state                                    |
    | Power Up State     | start_state                                    |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <Reg_RdAck>.
    Found 1-bit register for signal <Mem_WrAck>.
    Found 1-bit register for signal <Reg_WrAck>.
    Found 1-bit register for signal <Mem_Rdcycle_Done>.
    Found 2-bit comparator equal for signal <$n0076> created at line 305.
    Found 32-bit subtractor for signal <$n0092> created at line 260.
    Found 32-bit subtractor for signal <$n0098>.
    Found 32-bit register for signal <count_recover_current>.
    Found 32-bit register for signal <count_wait_current>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  68 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <Mem_State_Machine> synthesized.


Synthesizing Unit <Wait_States>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/wait_states.vhd.
WARNING:Xst:646 - Signal <rec_wait_states> is assigned but never used.
WARNING:Xst:646 - Signal <rw_wait_states> is assigned but never used.
Unit <Wait_States> synthesized.


Synthesizing Unit <mux_onehot>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd.
WARNING:Xst:1780 - Signal <lutout> is never used or assigned.
WARNING:Xst:1780 - Signal <cyout> is never used or assigned.
WARNING:Xst:1780 - Signal <one> is never used or assigned.
WARNING:Xst:1780 - Signal <zero> is never used or assigned.
WARNING:Xst:646 - Signal <sel<0:1>> is assigned but never used.
WARNING:Xst:1780 - Signal <sel<2:3>> is never used or assigned.
WARNING:Xst:646 - Signal <Dreord<0:1>> is assigned but never used.
WARNING:Xst:1780 - Signal <Dreord<2:3>> is never used or assigned.
Unit <mux_onehot> synthesized.


Synthesizing Unit <io_registers>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/io_registers.vhd.
    Register <mem_lbon_reg> equivalent to <mem_adv_ldn_reg> has been removed
    Register <mem_cken_reg> equivalent to <mem_adv_ldn_reg> has been removed
    Found 32-bit register for signal <Mem_DQ_I_int>.
    Found 32-bit register for signal <mem_a_reg>.
    Found 1-bit register for signal <mem_adv_ldn_reg>.
    Found 4-bit register for signal <mem_ben_reg>.
    Found 1-bit register for signal <mem_ce_reg<0>>.
    Found 1-bit register for signal <mem_cen_reg<0>>.
    Found 32-bit register for signal <mem_dq_o_reg>.
    Found 32-bit register for signal <mem_dq_t_reg>.
    Found 1-bit register for signal <mem_oen_reg<0>>.
    Found 1-bit register for signal <mem_oen_reg_d1<0>>.
    Found 4-bit register for signal <mem_qwen_reg>.
    Found 1-bit register for signal <mem_rnw_reg>.
    Found 1-bit register for signal <mem_rpn_reg>.
    Found 1-bit register for signal <mem_wen_reg>.
    Summary:
	inferred 144 D-type flip-flop(s).
Unit <io_registers> synthesized.


Synthesizing Unit <ipif_reset>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ipif_reset.vhd.
WARNING:Xst:647 - Input <Bus_DBus<0:27>> is never used.
WARNING:Xst:647 - Input <IP_Reset_RdCE> is never used.
    Found finite state machine <FSM_1> for signal <sw_reset_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 6                                              |
    | Inputs             | 2                                              |
    | Outputs            | 3                                              |
    | Clock              | Bus2IP_Clk_i (rising_edge)                     |
    | Reset              | Reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <error_reply>.
    Found 1-bit register for signal <sm_reset>.
    Found 1-bit register for signal <sm_wrack>.
    Found 1-bit register for signal <strt_sm_reset>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   4 D-type flip-flop(s).
Unit <ipif_reset> synthesized.


Synthesizing Unit <pselect3>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd.
WARNING:Xst:647 - Input <A<11:31>> is never used.
WARNING:Xst:1780 - Signal <lut_out<3>> is never used or assigned.
Unit <pselect3> synthesized.


Synthesizing Unit <ip2bus_dmux>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ip2bus_dmux.vhd.
Unit <ip2bus_dmux> synthesized.


Synthesizing Unit <ip2bus_srmux>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ip2bus_srmux.vhd.
Unit <ip2bus_srmux> synthesized.


Synthesizing Unit <or_gate2>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd.
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate2> synthesized.


Synthesizing Unit <or_gate>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd.
WARNING:Xst:1780 - Signal <test> is never used or assigned.
Unit <or_gate> synthesized.


Synthesizing Unit <pselect1>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd.
WARNING:Xst:647 - Input <A<13:20>> is never used.
WARNING:Xst:1780 - Signal <lut_out<4>> is never used or assigned.
Unit <pselect1> synthesized.


Synthesizing Unit <pselect0>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd.
WARNING:Xst:647 - Input <A<1:20>> is never used.
WARNING:Xst:1780 - Signal <lut_out<1>> is never used or assigned.
Unit <pselect0> synthesized.


Synthesizing Unit <pselect>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd.
WARNING:Xst:647 - Input <A<13:20>> is never used.
WARNING:Xst:1780 - Signal <lut_out<4>> is never used or assigned.
Unit <pselect> synthesized.


Synthesizing Unit <reset_control>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/reset_control.vhd.
Unit <reset_control> synthesized.


Synthesizing Unit <IPIF_Steer>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_a/hdl/vhdl/ipif_steer.vhd.
WARNING:Xst:647 - Input <Addr> is never used.
WARNING:Xst:647 - Input <Decode_size> is never used.
Unit <IPIF_Steer> synthesized.


Synthesizing Unit <slave_attachment>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/slave_attachment.vhd.
WARNING:Xst:647 - Input <MA2SA_Num> is never used.
WARNING:Xst:1305 - Output <SA2MA_Error> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <SA2MA_Retry> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <MA2SA_XferAck> is never used.
WARNING:Xst:647 - Input <MA2SA_Rd> is never used.
WARNING:Xst:647 - Input <MA2SA_Retry> is never used.
WARNING:Xst:647 - Input <MA2SA_Select> is never used.
WARNING:Xst:647 - Input <Bus_MnGrant> is never used.
WARNING:Xst:647 - Input <OPB_SeqAddr> is never used.
WARNING:Xst:1780 - Signal <opb_burst> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_burst_mstr> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_devicesel_mstr> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_devicesel_opb_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <addrcntr_ce_opb> is never used or assigned.
WARNING:Xst:1780 - Signal <sln_dbus_data> is never used or assigned.
WARNING:Xst:1780 - Signal <opb_seqaddr_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <ma2sa_rd_flag> is never used or assigned.
WARNING:Xst:1780 - Signal <addrcntr_ce_mstr_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_devicesel_dec> is never used or assigned.
WARNING:Xst:1780 - Signal <addrcntr_ce_opb_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <mstr_burst_fe> is never used or assigned.
WARNING:Xst:1780 - Signal <mstr_burstcntr_ld> is never used or assigned.
WARNING:Xst:1780 - Signal <addr_sel_opb_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <sa2ma_rdrdy_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_rdreq_opb_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <devicesel_rst> is never used or assigned.
WARNING:Xst:1780 - Signal <sln_rst_mstr> is never used or assigned.
WARNING:Xst:1780 - Signal <addr_sel_mstr_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <valid_decode_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <ma2sa_rd_flag_rst> is never used or assigned.
WARNING:Xst:1780 - Signal <mstr_burstcntr_reset> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_wrreq_mstr_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <addr_sel_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <sob_ctrlsm_ns> is never used or assigned.
WARNING:Xst:1780 - Signal <sa2ma_wrack_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <mstr_busy> is never used or assigned.
WARNING:Xst:1780 - Signal <ma2sa_rd_re> is never used or assigned.
WARNING:Xst:1780 - Signal <sa2ma_rdrdy_i> is never used or assigned.
WARNING:Xst:1780 - Signal <slv_opbsm_cs> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_burst_opb> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_devicesel_mstr_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <slv_mstrsm_cs> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_wrreq_mstr> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_wrreq_opb_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <addr_sel_vec> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_devicesel_i> is never used or assigned.
WARNING:Xst:1780 - Signal <ma2sa_select_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <ma2sa_select_d2> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_rdreq_mstr_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <mstr_burst> is never used or assigned.
WARNING:Xst:1780 - Signal <mstr_busy_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <addr_sel_mstr> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_burst_reg> is never used or assigned.
WARNING:Xst:1780 - Signal <sln_dbus_fifo_notmt> is never used or assigned.
WARNING:Xst:1780 - Signal <addr_cntr_clken_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_burst_opb_reg> is never used or assigned.
WARNING:Xst:1780 - Signal <sln_dbus_fifo_rd> is never used or assigned.
WARNING:Xst:1780 - Signal <ma2sa_xferack_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <ma2sa_xferack_d2> is never used or assigned.
WARNING:Xst:1780 - Signal <sa2ma_retry_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <opb_busy_reg> is never used or assigned.
WARNING:Xst:1780 - Signal <slv_opbsm_ns> is never used or assigned.
WARNING:Xst:1780 - Signal <slv_mstrsm_ns> is never used or assigned.
WARNING:Xst:1780 - Signal <addr_sel_i> is never used or assigned.
WARNING:Xst:1780 - Signal <sln_dbus_rst> is never used or assigned.
WARNING:Xst:1780 - Signal <read_buf_data> is never used or assigned.
WARNING:Xst:1780 - Signal <sln_dbus_ce> is never used or assigned.
WARNING:Xst:1780 - Signal <sln_dbus_fifo_wr> is never used or assigned.
WARNING:Xst:1780 - Signal <addr_sel_opb> is never used or assigned.
WARNING:Xst:1780 - Signal <opb_busy_set> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_rdreq_mstr> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_wrreq_opb> is never used or assigned.
WARNING:Xst:1780 - Signal <opb_busy_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <ma2sa_rd_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <sln_dbus_fifo_rst> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_devicesel_opb> is never used or assigned.
WARNING:Xst:1780 - Signal <ma2sa_select_re> is never used or assigned.
WARNING:Xst:1780 - Signal <mstr_burst_cnt> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_rdreq_opb> is never used or assigned.
WARNING:Xst:1780 - Signal <mstr_burstcntr_ce> is never used or assigned.
WARNING:Xst:1780 - Signal <devicesel_set> is never used or assigned.
WARNING:Xst:1780 - Signal <sob_ctrlsm_cs> is never used or assigned.
WARNING:Xst:1780 - Signal <opb_busy> is never used or assigned.
WARNING:Xst:1780 - Signal <mstr_burst_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <bus2ip_devicesel_d1> is never used or assigned.
WARNING:Xst:1780 - Signal <addr_sel_vec_cmb> is never used or assigned.
WARNING:Xst:1780 - Signal <burst> is never used or assigned.
    Found finite state machine <FSM_2> for signal <sonb_ctrlsm_cs>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 18                                             |
    | Inputs             | 5                                              |
    | Outputs            | 3                                              |
    | Clock              | OPB_Clk (rising_edge)                          |
    | Reset              | Reset (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <bus2ip_rdreq_dec>.
    Found 1-bit register for signal <bus2ip_wrreq_dec>.
    Found 32-bit register for signal <opb_abus_d1>.
    Found 4-bit register for signal <opb_be_d1>.
    Found 32-bit register for signal <opb_dbus_d1>.
    Found 1-bit register for signal <opb_rnw_d1>.
    Found 1-bit register for signal <opb_select_d1>.
    Found 32-bit register for signal <sln_dbus_i>.
    Found 1-bit register for signal <sln_errack_i>.
    Found 1-bit register for signal <sln_retry_i>.
    Found 1-bit register for signal <sln_rst>.
    Found 1-bit register for signal <sln_xferack_i>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred 108 D-type flip-flop(s).
Unit <slave_attachment> synthesized.


Synthesizing Unit <ip2bus_dmux_blk>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ip2bus_dmux_blk.vhd.
Unit <ip2bus_dmux_blk> synthesized.


Synthesizing Unit <bus2ip_amux>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/bus2ip_amux.vhd.
    Found 30-bit adder for signal <$n0002> created at line 208.
    Found 32-bit register for signal <reg_addr_plus1>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  32 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   4 Multiplexer(s).
Unit <bus2ip_amux> synthesized.


Synthesizing Unit <ip2bus_srmux_blk>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ip2bus_srmux_blk.vhd.
Unit <ip2bus_srmux_blk> synthesized.


Synthesizing Unit <address_decoder>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/address_decoder.vhd.
    Found 17-bit register for signal <CE_Out_i_reg>.
    Found 10-bit register for signal <CS_Out_i_reg>.
    Found 3-bit register for signal <CS_Size_i_reg>.
    Found 1-bit register for signal <decode_hit_reg>.
    Found 17-bit register for signal <RdCE_Out_i_reg>.
    Found 17-bit register for signal <WrCE_Out_i_reg>.
    Summary:
	inferred  65 D-type flip-flop(s).
Unit <address_decoder> synthesized.


Synthesizing Unit <ipif>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/ipif.vhd.
WARNING:Xst:647 - Input <IP2DMA_RxLength_Empty> is never used.
WARNING:Xst:647 - Input <IP2Bus_DMA_Req> is never used.
WARNING:Xst:647 - Input <IP2RFIFO_WrRelease> is never used.
WARNING:Xst:647 - Input <OPB_timeout> is never used.
WARNING:Xst:647 - Input <IP2Bus_MstWrReq> is never used.
WARNING:Xst:647 - Input <IP2Bus_MstBusLock> is never used.
WARNING:Xst:647 - Input <IP2RFIFO_WrRestore> is never used.
WARNING:Xst:647 - Input <IP2RFIFO_WrMark> is never used.
WARNING:Xst:647 - Input <IP2WFIFO_RdMark> is never used.
WARNING:Xst:647 - Input <IP2Bus_Clk> is never used.
WARNING:Xst:647 - Input <OPB_MnGrant> is never used.
WARNING:Xst:647 - Input <IP2DMA_RxStatus_Empty> is never used.
WARNING:Xst:647 - Input <IP2Bus_MstBurst> is never used.
WARNING:Xst:647 - Input <OPB_errAck> is never used.
WARNING:Xst:647 - Input <OPB_xferAck> is never used.
WARNING:Xst:647 - Input <IP2DMA_TxLength_Full> is never used.
WARNING:Xst:647 - Input <IP2Bus_MstBE> is never used.
WARNING:Xst:647 - Input <IP2RFIFO_Data> is never used.
WARNING:Xst:647 - Input <IP2Bus_IntrEvent<1>> is never used.
WARNING:Xst:647 - Input <OPB_retry> is never used.
WARNING:Xst:647 - Input <IP2RFIFO_WrReq> is never used.
WARNING:Xst:647 - Input <IP2DMA_TxStatus_Empty> is never used.
WARNING:Xst:647 - Input <IP2WFIFO_RdRelease> is never used.
WARNING:Xst:647 - Input <IP2Bus_Addr> is never used.
WARNING:Xst:647 - Input <IP2WFIFO_RdReq> is never used.
WARNING:Xst:647 - Input <IP2WFIFO_RdRestore> is never used.
WARNING:Xst:647 - Input <IP2Bus_MstRdReq> is never used.
WARNING:Xst:646 - Signal <WFIFO2DMA_Vacancy> is assigned but never used.
WARNING:Xst:646 - Signal <DMA2Bus_MstBE> is assigned but never used.
WARNING:Xst:646 - Signal <SA2MA_WrAck> is assigned but never used.
WARNING:Xst:646 - Signal <DMA2Bus_MstRdReq> is assigned but never used.
WARNING:Xst:646 - Signal <SA2MA_RdRdy> is assigned but never used.
WARNING:Xst:653 - Signal <CONST_ALL_IP_BYTES_ENABLED> is used but never assigned. Tied to value 1111.
WARNING:Xst:646 - Signal <WFIFO2DMA_Full> is assigned but never used.
WARNING:Xst:646 - Signal <DMA2Intr_Intr> is assigned but never used.
WARNING:Xst:646 - Signal <IPIF_Reg_Interrupts> is assigned but never used.
WARNING:Xst:646 - Signal <SA2MA_Error> is assigned but never used.
WARNING:Xst:646 - Signal <DMA2Bus_MstWrReq> is assigned but never used.
WARNING:Xst:646 - Signal <SA2MA_Retry> is assigned but never used.
WARNING:Xst:646 - Signal <DMA2Bus_MstBusLock> is assigned but never used.
WARNING:Xst:646 - Signal <RFIFO2DMA_Empty> is assigned but never used.
WARNING:Xst:646 - Signal <DMA2Bus_MstBurst> is assigned but never used.
WARNING:Xst:646 - Signal <RFIFO2DMA_AlmostEmpty> is assigned but never used.
WARNING:Xst:646 - Signal <RFIFO2DMA_Occupancy> is assigned but never used.
WARNING:Xst:646 - Signal <DMA2Bus_Addr> is assigned but never used.
WARNING:Xst:646 - Signal <Bus2IP_Freeze_i> is assigned but never used.
WARNING:Xst:1780 - Signal <WFIFO2DMA_AlmostFull> is never used or assigned.
WARNING:Xst:646 - Signal <IPIF_Lvl_Interrupts> is assigned but never used.
Unit <ipif> synthesized.


Synthesizing Unit <emc>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/emc_common_v1_10_b/hdl/vhdl/emc.vhd.
WARNING:Xst:1780 - Signal <IP2Bus_WrAck_Out> is never used or assigned.
WARNING:Xst:1780 - Signal <IP2Bus_RdAck_Out> is never used or assigned.
WARNING:Xst:646 - Signal <burst_rdack> is assigned but never used.
WARNING:Xst:646 - Signal <sync_mem_cs> is assigned but never used.
WARNING:Xst:1780 - Signal <ReadReg2_ReadMux> is never used or assigned.
WARNING:Xst:1780 - Signal <reg_Select> is never used or assigned.
WARNING:Xst:646 - Signal <burst_wrack> is assigned but never used.
WARNING:Xst:1780 - Signal <Bus2IP_RNW_d1> is never used or assigned.
    Found 29-bit comparator equal for signal <$n0009> created at line 1555.
    Found 1-bit register for signal <input_datareg_rst>.
    Found 1-bit register for signal <prev_Access_Read>.
    Found 29-bit register for signal <prev_Addr>.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  31 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <emc> synthesized.


Synthesizing Unit <opb_ipif>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v2_00_a/hdl/vhdl/opb_ipif.vhd.
Unit <opb_ipif> synthesized.


Synthesizing Unit <opb_emc>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd.
WARNING:Xst:653 - Signal <ZERO_DWIDTH> is used but never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:646 - Signal <Bus2IP_RdCE<1:16>> is assigned but never used.
WARNING:Xst:646 - Signal <Bus2IP_WrCE<1:16>> is assigned but never used.
WARNING:Xst:653 - Signal <ZERO_AWIDTH> is used but never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:653 - Signal <ZERO_BE> is used but never assigned. Tied to value 0000.
WARNING:Xst:646 - Signal <IP2Bus_errAck> is assigned but never used.
WARNING:Xst:646 - Signal <Bus2IP_CE> is assigned but never used.
WARNING:Xst:646 - Signal <Bus2IP_CS<9>> is assigned but never used.
WARNING:Xst:646 - Signal <memcon_cs_bus_full<1:7>> is assigned but never used.
Unit <opb_emc> synthesized.


Synthesizing Unit <sram_256kx32_wrapper>.
    Related source file is C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/sram_256kx32_wrapper.vhd.
Unit <sram_256kx32_wrapper> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <sonb_ctrlsm_cs> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <sw_reset_state> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <current_State> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# Adders/Subtractors               : 3
 30-bit adder                      : 1
 32-bit subtractor                 : 2
# Registers                        : 72
 1-bit register                    : 48
 29-bit register                   : 1
 17-bit register                   : 3
 3-bit register                    : 1
 10-bit register                   : 1
 32-bit register                   : 11
 4-bit register                    : 5
 2-bit register                    : 2
# Comparators                      : 2
 29-bit comparator equal           : 1
 2-bit comparator equal            : 1
# Multiplexers                     : 6
 1-bit 2-to-1 multiplexer          : 3
 4-bit 2-to-1 multiplexer          : 1
 32-bit 2-to-1 multiplexer         : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <mem_adv_ldn_reg> (without init value) is constant in block <io_registers>.
WARNING:Xst:1291 - FF/Latch <decode_hit_reg> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CS_Out_i_reg_9> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CS_Out_i_reg_8> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_0> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_0> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CS_Size_i_reg_0> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1290 - Hierarchical block <I_OR_CS> is unconnected in block <I_ADDRESS_DECODER>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <I_OR_SIZES> is unconnected in block <I_ADDRESS_DECODER>.
   It will be removed from the design.
WARNING:Xst:1291 - FF/Latch <CS_Out_i_reg_7> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CS_Size_i_reg_1> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CS_Size_i_reg_2> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CS_Out_i_reg_4> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CS_Out_i_reg_5> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CS_Out_i_reg_6> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_1> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CS_Out_i_reg_3> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CS_Out_i_reg_2> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_15> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_14> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_13> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_12> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_11> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_10> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_9> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_8> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_7> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_6> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_5> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_4> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_3> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_2> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <WrCE_Out_i_reg_1> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_16> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_15> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_14> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_13> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_12> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_11> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_10> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_9> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_8> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_7> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_6> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_5> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_4> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_3> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_2> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <RdCE_Out_i_reg_1> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_16> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_15> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_14> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_13> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_12> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_11> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_10> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_9> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_8> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_7> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_6> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_5> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_4> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_3> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <CE_Out_i_reg_2> is unconnected in block <I_ADDRESS_DECODER>.
WARNING:Xst:1291 - FF/Latch <addr_cnt_d1_1> is unconnected in block <DATA_PATH_I>.
WARNING:Xst:1291 - FF/Latch <addr_cnt_d2_1> is unconnected in block <DATA_PATH_I>.
WARNING:Xst:1291 - FF/Latch <addr_cnt_d2_0> is unconnected in block <DATA_PATH_I>.
WARNING:Xst:1291 - FF/Latch <addr_cnt_d1_0> is unconnected in block <DATA_PATH_I>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_3> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_4> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_2> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_1> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_5> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_6> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_7> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_8> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_9> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_0> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_10> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_11> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_12> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_13> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_14> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_15> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_16> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_17> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_18> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_19> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_20> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_21> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_22> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_23> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_24> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_25> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_26> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_27> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_28> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_29> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_30> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <reg_addr_plus1_31> is unconnected in block <I_BUS2IP_AMUX>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_24> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_29> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_30> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_27> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_28> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_26> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_23> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_31> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_31> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_25> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_5> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_6> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_7> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_8> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_9> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_10> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_11> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_12> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_13> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_14> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_15> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_16> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_17> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_18> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_19> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_20> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_21> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_22> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_23> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_24> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_25> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_26> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_27> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_28> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_29> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_recover_current_30> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_5> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_6> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_7> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_8> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_9> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_10> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_11> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_12> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_13> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_14> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_15> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_16> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_17> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_18> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_19> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_20> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_21> is unconnected in block <Mem_State_Machine>.
WARNING:Xst:1291 - FF/Latch <count_wait_current_22> is unconnected in block <Mem_State_Machine>.

Optimizing unit <sram_256kx32_wrapper> ...

Optimizing unit <or_gate> ...

Optimizing unit <or_gate2> ...

Optimizing unit <ip2bus_dmux> ...

Optimizing unit <Wait_States> ...

Optimizing unit <bus2ip_amux> ...

Optimizing unit <pselect> ...

Optimizing unit <pselect1> ...

Optimizing unit <pselect3> ...

Optimizing unit <ipif_reset> ...

Optimizing unit <io_registers> ...

Optimizing unit <data_path> ...

Optimizing unit <address_decoder> ...

Optimizing unit <slave_attachment> ...

Optimizing unit <Mem_State_Machine> ...

Optimizing unit <addr_counter_mux> ...

Optimizing unit <emc> ...

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_14> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_13> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_12> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_11> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_10> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_9> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_8> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_7> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_6> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_5> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_4> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_3> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/sln_retry_i> is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_EMC/IO_REGISTERS_I/mem_a_reg_31> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_EMC/IO_REGISTERS_I/mem_a_reg_30> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_EMC/MEM_STATE_MACHINE_I/current_State_FFd9> is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_EMC/MEM_STATE_MACHINE_I/current_State_FFd7> is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_EMC/MEM_STATE_MACHINE_I/current_State_FFd5> is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_EMC/MEM_STATE_MACHINE_I/current_State_FFd1> is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_2> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_1> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_0> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_31> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_30> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_29> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_28> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_27> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_26> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_25> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_24> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_23> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_22> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_21> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_20> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_19> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_18> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_17> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_16> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_OPB_IPIf/IPIF_I/I_BUS2IP_AMUX/reg_addr_plus1_15> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/decode_hit_reg> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Out_i_reg_9> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Out_i_reg_8> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_0> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_0> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Size_i_reg_0> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Out_i_reg_7> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Size_i_reg_1> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Size_i_reg_2> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Out_i_reg_4> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Out_i_reg_5> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Out_i_reg_6> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_1> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Out_i_reg_3> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Out_i_reg_2> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_15> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_14> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_13> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_12> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_11> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_10> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_9> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_8> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_7> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_6> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_5> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_4> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_3> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_2> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_1> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_16> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_15> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_14> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_13> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_12> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_11> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_10> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_9> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_8> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_7> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_6> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_5> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_4> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_3> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_2> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/RdCE_Out_i_reg_1> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_16> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_15> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_14> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_13> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_12> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_11> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_10> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_9> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_8> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_7> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_6> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_5> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_4> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_3> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i_reg_2> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_0> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_1> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_3> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_4> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_2> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_5> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_6> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_7> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_8> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_9> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_28> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_27> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_26> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_25> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_24> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_23> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_22> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_21> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_20> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_19> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_18> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_17> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_16> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_15> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_14> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_13> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_12> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_11> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/prev_Addr_10> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/opb_abus_d1_31> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/opb_abus_d1_30> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <sram_256kx32/I_EMC/prev_Access_Read> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1710 - FF/Latch  <sram_256kx32/I_EMC/MEM_STATE_MACHINE_I/count_recover_current_4> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_EMC/MEM_STATE_MACHINE_I/count_recover_current_3> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_EMC/MEM_STATE_MACHINE_I/count_recover_current_2> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_EMC/MEM_STATE_MACHINE_I/count_recover_current_1> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <sram_256kx32/I_EMC/MEM_STATE_MACHINE_I/count_recover_current_0> (without init value) is constant in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/DATA_PATH_I/addr_cnt_d1_1> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/DATA_PATH_I/addr_cnt_d1_0> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/DATA_PATH_I/addr_cnt_d2_1> is unconnected in block <sram_256kx32_wrapper>.
WARNING:Xst:1291 - FF/Latch <sram_256kx32/I_EMC/DATA_PATH_I/addr_cnt_d2_0> is unconnected in block <sram_256kx32_wrapper>.
Building and optimizing final netlist ...
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_15 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_14 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_13 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_12 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_11 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_4 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_5 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_6 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_7 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_8 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_9 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_10 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_30 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_29 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_28 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_27 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_26 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_16 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_17 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_18 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_19 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_20 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_21 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_22 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_23 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_24 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_25 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 has been removed
Register sram_256kx32/I_EMC/DATA_PATH_I/read_ce_reg1_3 equivalent to sram_256kx32/I_EMC/DATA_PATH_I/read_ce_reg1_0 has been removed
Register sram_256kx32/I_OPB_IPIf/IPIF_I/I_RESET_CONTROL/I_RESET_CONTROLLER/sm_wrack equivalent to sram_256kx32/I_OPB_IPIf/IPIF_I/I_RESET_CONTROL/I_RESET_CONTROLLER/sw_reset_state_FFd3 has been removed
Register sram_256kx32/I_EMC/DATA_PATH_I/read_ce_0 equivalent to sram_256kx32/I_EMC/DATA_PATH_I/read_ce_3 has been removed
Register sram_256kx32/I_EMC/DATA_PATH_I/read_ce_reg1_0 equivalent to sram_256kx32/I_EMC/DATA_PATH_I/read_ce_reg1_2 has been removed
Register sram_256kx32/I_EMC/DATA_PATH_I/read_ce_reg1_2 equivalent to sram_256kx32/I_EMC/DATA_PATH_I/read_ce_reg1_1 has been removed
Register sram_256kx32/I_EMC/DATA_PATH_I/read_ce_1 equivalent to sram_256kx32/I_EMC/DATA_PATH_I/read_ce_2 has been removed
Register sram_256kx32/I_EMC/DATA_PATH_I/read_ce_3 equivalent to sram_256kx32/I_EMC/DATA_PATH_I/read_ce_2 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_0 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_3 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_31 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_3 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_1 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_3 has been removed
Register sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_2 equivalent to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_dq_t_reg_3 has been removed
Register sram_256kx32/I_EMC/DATA_PATH_I/read_ce0_d1 equivalent to sram_256kx32/I_EMC/DATA_PATH_I/FINAL_READCE has been removed
FlipFlop sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Out_i_reg_1 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ../implementation/sram_256kx32_wrapper/sram_256kx32_wrapper.ngr
Top Level Output File Name         : ../implementation/sram_256kx32_wrapper/sram_256kx32_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 254

Macro Statistics :
# Registers                        : 52
#      1-bit register              : 28
#      10-bit register             : 1
#      17-bit register             : 3
#      2-bit register              : 2
#      29-bit register             : 1
#      3-bit register              : 1
#      32-bit register             : 11
#      4-bit register              : 5
# Multiplexers                     : 6
#      2-to-1 multiplexer          : 6
# Adders/Subtractors               : 3
#      30-bit adder                : 1
#      32-bit subtractor           : 2
# Comparators                      : 1
#      29-bit comparator equal     : 1

Cell Usage :
# BELS                             : 252
#      GND                         : 1
#      LUT1                        : 15
#      LUT1_L                      : 1
#      LUT2                        : 58
#      LUT2_D                      : 2
#      LUT2_L                      : 3
#      LUT3                        : 16
#      LUT3_D                      : 2
#      LUT3_L                      : 1
#      LUT4                        : 105
#      LUT4_D                      : 2
#      LUT4_L                      : 10
#      MULT_AND                    : 2
#      MUXCY                       : 25
#      MUXF5                       : 1
#      VCC                         : 1
#      XORCY                       : 7
# FlipFlops/Latches                : 322
#      FDC                         : 6
#      FDP                         : 1
#      FDR                         : 193
#      FDRE                        : 101
#      FDRS                        : 4
#      FDS                         : 17
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     201  out of   1920    10%  
 Number of Slice Flip Flops:           322  out of   3840     8%  
 Number of 4 input LUTs:               215  out of   3840     5%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
OPB_Clk                            | NONE                   | 322   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 6.369ns (Maximum Frequency: 157.010MHz)
   Minimum input arrival time before clock: 2.946ns
   Maximum output required time after clock: 3.871ns
   Maximum combinational path delay: 0.551ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'OPB_Clk'
Delay:               6.369ns (Levels of Logic = 10)
  Source:            sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/opb_abus_d1_1 (FF)
  Destination:       sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_0 (FF)
  Source Clock:      OPB_Clk rising
  Destination Clock: OPB_Clk rising

  Data Path: sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/opb_abus_d1_1 to sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.720   0.465  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/opb_abus_d1_1 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/opb_abus_d1_1)
     LUT4_L:I0->LO         1   0.551   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/_n00201 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/lut_out<0>)
     MUXCY:S->O            1   0.500   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/MUXCY_I0 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/carry_chain<1>)
     MUXCY:CI->O           1   0.064   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/MUXCY_I1 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/carry_chain<2>)
     MUXCY:CI->O           7   0.303   0.717  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/MUXCY_I2 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/valid_decode)
     LUT4:I0->O           10   0.551   0.806  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_devicesel_dec_cmb1 (sram_256kx32/I_OPB_IPIf/IPIF_I/Bus2IP_DeviceSel)
     MUXCY:CI->O           1   0.064   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/MEM_SELECT_I0/MUXCY_I0 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/MEM_SELECT_I0/carry_chain<1>)
     MUXCY:CI->O           1   0.064   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/MEM_SELECT_I0/MUXCY_I1 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/MEM_SELECT_I0/carry_chain<2>)
     MUXCY:CI->O           1   0.064   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/MEM_SELECT_I0/MUXCY_I2 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/MEM_SELECT_I0/carry_chain<3>)
     MUXCY:CI->O           2   0.281   0.465  sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/MEM_SELECT_I0/MUXCY_I3 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CS_Out_i<0>)
     LUT4_L:I2->LO         1   0.551   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/_n00351 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/CE_Out_i<0>)
     FDR:D                     0.203          sram_256kx32/I_OPB_IPIf/IPIF_I/I_ADDRESS_DECODER/WrCE_Out_i_reg_0
    ----------------------------------------
    Total                      6.369ns (3.916ns logic, 2.453ns route)
                                       (61.5% logic, 38.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'OPB_Clk'
Offset:              2.946ns (Levels of Logic = 1)
  Source:            OPB_Rst (PAD)
  Destination:       sram_256kx32/I_EMC/IO_REGISTERS_I/mem_qwen_reg_2 (FF)
  Destination Clock: OPB_Clk rising

  Data Path: OPB_Rst to sram_256kx32/I_EMC/IO_REGISTERS_I/mem_qwen_reg_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT2:I0->O           80   0.551   1.369  sram_256kx32/I_OPB_IPIf/IPIF_I/I_RESET_CONTROL/I_RESET_CONTROLLER/Reset2IP_Reset1 (sram_256kx32/Bus2IP_Reset)
     FDRE:R                    1.026          sram_256kx32/I_EMC/MCCR_PAGE_MODE_I0
    ----------------------------------------
    Total                      2.946ns (1.577ns logic, 1.369ns route)
                                       (53.5% logic, 46.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'OPB_Clk'
Offset:              3.871ns (Levels of Logic = 5)
  Source:            sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/opb_abus_d1_1 (FF)
  Destination:       Sln_toutSup (PAD)
  Source Clock:      OPB_Clk rising

  Data Path: sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/opb_abus_d1_1 to Sln_toutSup
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.720   0.465  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/opb_abus_d1_1 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/opb_abus_d1_1)
     LUT4_L:I0->LO         1   0.551   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/_n00201 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/lut_out<0>)
     MUXCY:S->O            1   0.500   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/MUXCY_I0 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/carry_chain<1>)
     MUXCY:CI->O           1   0.064   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/MUXCY_I1 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/carry_chain<2>)
     MUXCY:CI->O           7   0.303   0.717  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/SL_ATTCH_PSELECT_I/MUXCY_I2 (sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/valid_decode)
     LUT2:I1->O            0   0.551   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/Sln_toutSup1 (Sln_toutSup)
    ----------------------------------------
    Total                      3.871ns (2.689ns logic, 1.182ns route)
                                       (69.5% logic, 30.5% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               0.551ns (Levels of Logic = 1)
  Source:            OPB_select (PAD)
  Destination:       Sln_xferAck (PAD)

  Data Path: OPB_select to Sln_xferAck
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT2:I0->O            0   0.551   0.000  sram_256kx32/I_OPB_IPIf/IPIF_I/I_SLAVE_ATTACHMENT/Sln_errAck1 (Sln_errAck)
    ----------------------------------------
    Total                      0.551ns (0.551ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 18.92 / 276.03 s | Elapsed : 19.00 / 20.00 s
 
--> 

Total memory usage is 310116 kilobytes


