vhdl proc_common_v1_00_b C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd
vhdl proc_common_v1_00_b C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/srl_fifo.vhd
vhdl proc_common_v1_00_b C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/pselect.vhd
vhdl proc_common_v1_00_b C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/valid_be.vhd
vhdl proc_common_v1_00_b C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/ld_arith_reg.vhd
vhdl proc_common_v1_00_b C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/down_counter.vhd
vhdl proc_common_v1_00_b C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/inferred_lut4.vhd
vhdl proc_common_v1_00_b C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd
vhdl proc_common_v1_00_b C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/or_gate.vhd
vhdl proc_common_v1_00_b C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/family.vhd
vhdl proc_common_v1_00_b C:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v1_00_b/hdl/vhdl/mux_onehot.vhd
vhdl ipif_common_v1_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\ipif_common_v1_00_a/hdl/vhdl/ipif_pkg.vhd
vhdl ipif_common_v1_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\ipif_common_v1_00_a/hdl/vhdl/interrupt_control.vhd
vhdl ipif_common_v1_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\ipif_common_v1_00_a/hdl/vhdl/ipif_steer.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/address_decoder.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/slave_attachment.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/pf_counter_bit.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/pf_counter.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/pf_counter_top.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/pf_occ_counter.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/pf_adder_bit.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/pf_adder.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/pf_dpram_select.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/srl16_fifo.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/pf_dly1_mux.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/rdpfifo_dp_cntl.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/ipif_control_rd.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/rdpfifo_top.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/wrpfifo_dp_cntl.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/ipif_control_wr.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/wrpfifo_top.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/bus2ip_amux.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/ip2bus_dmux.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/ip2bus_dmux_blk.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/ip2bus_srmux.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/ip2bus_srmux_blk.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/ipif_reset.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/reset_control.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/dma_sg_pkg.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/dma_sg_cmp.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/ctrl_reg.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/dma_sg.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/dma_sg_sim.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/addr_load_and_incr.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/mst_module.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/master_attachment.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/ipif.vhd
vhdl opb_ipif_v2_00_a C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v2_00_a/hdl/vhdl/opb_ipif.vhd
vhdl emc_common_v1_10_b C:\EDK\hw\XilinxProcessorIPLib\pcores\emc_common_v1_10_b/hdl/vhdl/io_registers.vhd
vhdl emc_common_v1_10_b C:\EDK\hw\XilinxProcessorIPLib\pcores\emc_common_v1_10_b/hdl/vhdl/wait_states.vhd
vhdl emc_common_v1_10_b C:\EDK\hw\XilinxProcessorIPLib\pcores\emc_common_v1_10_b/hdl/vhdl/mem_state_machine.vhd
vhdl emc_common_v1_10_b C:\EDK\hw\XilinxProcessorIPLib\pcores\emc_common_v1_10_b/hdl/vhdl/select_param.vhd
vhdl emc_common_v1_10_b C:\EDK\hw\XilinxProcessorIPLib\pcores\emc_common_v1_10_b/hdl/vhdl/addr_counter_mux.vhd
vhdl emc_common_v1_10_b C:\EDK\hw\XilinxProcessorIPLib\pcores\emc_common_v1_10_b/hdl/vhdl/data_path.vhd
vhdl emc_common_v1_10_b C:\EDK\hw\XilinxProcessorIPLib\pcores\emc_common_v1_10_b/hdl/vhdl/emc.vhd
vhdl opb_emc_v1_10_b C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_emc_v1_10_b/hdl/vhdl/opb_emc.vhd
vhdl work ../hdl/sram_256kx32_wrapper.vhd
