Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : leds_8bit_wrapper_xst.prj

---- Target Parameters
Target Device                      : XC3S200FT256-4
Output File Name                   : ../implementation/leds_8bit_wrapper/leds_8bit_wrapper.ngc

---- Source Options
Top Module Name                    : leds_8bit_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Effort                : 2
Optimization Goal                  : speed
RTL Output                         : YES
Hierarchy Separator                : /

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd in Library proc_common_v1_00_b.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_c/hdl/vhdl/ipif_pkg.vhd in Library ipif_common_v1_00_c.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd in Library proc_common_v1_00_b.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd in Library proc_common_v1_00_b.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_c/hdl/vhdl/ipif_steer.vhd in Library ipif_common_v1_00_c.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/reset_mir.vhd in Library opb_ipif_v3_00_a.
Entity <reset_mir> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_c/hdl/vhdl/interrupt_control.vhd in Library ipif_common_v1_00_c.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd in Library opb_ipif_v3_00_a.
Entity <opb_bam> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_gate.vhd in Library proc_common_v1_00_b.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_ipif.vhd in Library opb_ipif_v3_00_a.
Entity <opb_ipif> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/opb_ipif_ssp1.vhd in Library opb_gpio_v3_01_a.
Entity <opb_ipif_ssp1> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/gpio_core.vhd in Library opb_gpio_v3_01_a.
Entity <GPIO_Core> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/opb_gpio.vhd in Library opb_gpio_v3_01_a.
Entity <opb_gpio> (Architecture <imp>) compiled.
Compiling vhdl file C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/leds_8bit_wrapper.vhd in Library work.
Entity <leds_8bit_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <leds_8bit_wrapper> (Architecture <STRUCTURE>).
Instantiating component <opb_gpio> from Library <opb_gpio_v3_01_a>.
WARNING:Xst:37 - Unknown property "IP_GROUP".
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Clk> in unit <opb_gpio>.
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Rst> in unit <opb_gpio>.
WARNING:Xst:37 - Unknown property "SIGIS".
Entity <leds_8bit_wrapper> analyzed. Unit <leds_8bit_wrapper> generated.

Analyzing generic Entity <opb_gpio> (Architecture <imp>).
	C_BASEADDR = <u>10000000001000000000100000000000
	C_HIGHADDR = <u>10000000001000000000100111111111
	C_USER_ID_CODE = 3
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_FAMILY = "spartan3"
	C_GPIO_WIDTH = 8
	C_ALL_INPUTS = 0
	C_INTERRUPT_PRESENT = 0
	C_IS_BIDIR = 0
	C_DOUT_DEFAULT = <u>00000000000000000000000000000000
	C_TRI_DEFAULT = <u>11111111111111111111111111111111
	C_IS_DUAL = 0
	C_ALL_INPUTS_2 = 0
	C_IS_BIDIR_2 = 1
	C_DOUT_DEFAULT_2 = <u>00000000000000000000000000000000
	C_TRI_DEFAULT_2 = <u>11111111111111111111111111111111
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Clk> in unit <opb_gpio> (previous value was "10000").
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Rst> in unit <opb_gpio> (previous value was "10000").
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Clk> in unit <opb_ipif_ssp1>.
    Set property "MAX_FANOUT = 10000" for signal <OPB_Rst> in unit <opb_ipif_ssp1>.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/opb_gpio.vhd line 264: Unconnected output port 'GPIO_errAck' of component 'GPIO_Core'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/opb_gpio.vhd line 264: Unconnected output port 'GPIO_retry' of component 'GPIO_Core'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/opb_gpio.vhd line 264: Unconnected output port 'GPIO_toutSup' of component 'GPIO_Core'.
Entity <opb_gpio> analyzed. Unit <opb_gpio> generated.

Analyzing generic Entity <opb_ipif_ssp1> (Architecture <imp>).
	C_BASEADDR = <u>10000000001000000000100000000000
	C_HIGHADDR = <u>10000000001000000000100000001111
	C_INTR_BASEADDR = <u>10000000001000000000100100000000
	C_INTR_HIGHADDR = <u>10000000001000000000100111111111
	C_USER_ID_CODE = 3
	C_PIPELINE_MODEL = 5
	C_INCLUDE_INTR = <u>0
	C_NUM_USER_INTR = 2
	C_USER_INTR_TYPE = 5
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_FAMILY = "spartan3"
    Set property "MAX_FANOUT = 10000" for signal <OPB_Clk> in unit <opb_ipif_ssp1> (previous value was "10000").
    Set property "MAX_FANOUT = 10000" for signal <OPB_Rst> in unit <opb_ipif_ssp1> (previous value was "10000").
Instantiating component <opb_ipif> from Library <opb_ipif_v3_00_a>.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/opb_ipif_ssp1.vhd line 429: Unconnected output port 'Bus2IP_CE' of component 'opb_ipif'.
Entity <opb_ipif_ssp1> analyzed. Unit <opb_ipif_ssp1> generated.

Analyzing generic Entity <opb_ipif> (Architecture <imp>).
	C_ARD_ID_ARRAY = (100)
	C_ARD_ADDR_RANGE_ARRAY = (<u>0000000000000000000000000000000010000000001000000000100000000000, <u>0000000000000000000000000000000010000000001000000000100000001111)
	C_ARD_DWIDTH_ARRAY = (32)
	C_ARD_NUM_CE_ARRAY = (1)
	C_ARD_DEPENDENT_PROPS_ARRAY = ((0, 0, 0, 0, 0, 0), (0, 0, 0, 0, 0, 0))
	C_PIPELINE_MODEL = 5
	C_DEV_BLK_ID = 3
	C_DEV_MIR_ENABLE = 1
	C_AWIDTH = 32
	C_DWIDTH = 32
	C_FAMILY = "spartan3"
	C_IP_INTR_MODE_ARRAY = (5, 5)
	C_INCLUDE_DEV_ISC = 0
	C_INCLUDE_DEV_IID = 0
	C_DEV_BURST_ENABLE = 0
Entity <opb_ipif> analyzed. Unit <opb_ipif> generated.

Analyzing generic Entity <opb_bam> (Architecture <implementation>).
	C_ARD_ID_ARRAY = (100)
	C_ARD_ADDR_RANGE_ARRAY = (<u>0000000000000000000000000000000010000000001000000000100000000000, <u>0000000000000000000000000000000010000000001000000000100000001111)
	C_ARD_DWIDTH_ARRAY = (32)
	C_ARD_NUM_CE_ARRAY = (1)
	C_ARD_DEPENDENT_PROPS_ARRAY = ((0, 0, 0, 0, 0, 0), (0, 0, 0, 0, 0, 0))
	C_PIPELINE_MODEL = 5
	C_DEV_BLK_ID = 3
	C_DEV_MIR_ENABLE = 1
	C_AWIDTH = 32
	C_DWIDTH = 32
	C_FAMILY = "spartan3"
	C_IP_INTR_MODE_ARRAY = (5, 5)
	C_INCLUDE_DEV_ISC = 0
	C_INCLUDE_DEV_IID = 0
	C_DEV_BURST_ENABLE = 0
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
Instantiating component <IPIF_Steer> from Library <ipif_common_v1_00_c>.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd line 1260: Unconnected output port 'Rd_Data_Out' of component 'IPIF_Steer'.
Instantiating component <IPIF_Steer> from Library <ipif_common_v1_00_c>.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd line 1284: Unconnected output port 'Wr_Data_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd line 1284: Unconnected output port 'BE_Out' of component 'IPIF_Steer'.
WARNING:Xst:819 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd line 1307: The following signals are missing in the process sensitivity list:
   bus2ip_cs_enable_s0.
INFO:Xst:1304 - Contents of register <opb_seqaddr_s0> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <opb_seqaddr_d1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
Entity <opb_bam> analyzed. Unit <opb_bam> generated.

Analyzing generic Entity <pselect> (Architecture <imp>).
	C_AB = 28
	C_AW = 32
	C_BAR = <u>10000000001000000000100000000000
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
Entity <pselect> analyzed. Unit <pselect> generated.

Analyzing generic Entity <pselect> (Architecture <imp>).
	C_AB = 0
	C_AW = 4
	C_BAR = <u>0000
Entity <pselect> analyzed. Unit <pselect0> generated.

Analyzing generic Entity <IPIF_Steer> (Architecture <imp>).
	C_DWIDTH = 32
	C_SMALLEST = 32
	C_AWIDTH = 32
Entity <IPIF_Steer> analyzed. Unit <IPIF_Steer> generated.

Analyzing generic Entity <GPIO_Core> (Architecture <imp>).
	C_DW = 32
	C_AW = 32
	C_GPIO_WIDTH = 8
	C_OPB_DWIDTH = 32
	C_INTERRUPT_PRESENT = <u>0
	C_ALL_INPUTS = <u>0
	C_IS_BIDIR = <u>0
	C_DOUT_DEFAULT = <u>00000000000000000000000000000000
	C_TRI_DEFAULT = <u>11111111111111111111111111111111
	C_IS_DUAL = <u>0
	C_ALL_INPUTS_2 = <u>0
	C_IS_BIDIR_2 = <u>1
	C_DOUT_DEFAULT_2 = <u>00000000000000000000000000000000
	C_TRI_DEFAULT_2 = <u>11111111111111111111111111111111
WARNING:Xst:819 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/gpio_core.vhd line 272: The following signals are missing in the process sensitivity list:
   dout_default_i.
WARNING:Xst:819 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/gpio_core.vhd line 289: The following signals are missing in the process sensitivity list:
   tri_default_i.
Entity <GPIO_Core> analyzed. Unit <GPIO_Core> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <IPIF_Steer>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_c/hdl/vhdl/ipif_steer.vhd.
WARNING:Xst:647 - Input <Addr> is never used.
WARNING:Xst:647 - Input <Decode_size> is never used.
Unit <IPIF_Steer> synthesized.


Synthesizing Unit <pselect0>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd.
WARNING:Xst:647 - Input <A> is never used.
WARNING:Xst:1780 - Signal <lut_out> is never used or assigned.
Unit <pselect0> synthesized.


Synthesizing Unit <pselect>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd.
WARNING:Xst:647 - Input <A<28:31>> is never used.
WARNING:Xst:1780 - Signal <lut_out<7>> is never used or assigned.
Unit <pselect> synthesized.


Synthesizing Unit <opb_bam>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd.
WARNING:Xst:647 - Input <IP2Bus_Clk> is never used.
WARNING:Xst:647 - Input <OPB_xferAck> is never used.
WARNING:Xst:1305 - Output <Device_Intr> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <IP2Bus_Intr> is never used.
WARNING:Xst:647 - Input <OPB_seqAddr> is never used.
WARNING:Xst:1780 - Signal <reset2bus_toutsup> is never used or assigned.
WARNING:Xst:1780 - Signal <cs_to_or_for_dsize_bit<0><0>> is never used or assigned.
WARNING:Xst:1780 - Signal <cs_to_or_for_dsize_bit<1>> is never used or assigned.
WARNING:Xst:646 - Signal <cs_to_or_for_dsize_bit<1><0>> is assigned but never used.
WARNING:Xst:646 - Signal <cs_to_or_for_dsize_bit<2>> is assigned but never used.
WARNING:Xst:1780 - Signal <bus2ip_addr_s0> is never used or assigned.
WARNING:Xst:646 - Signal <opb_seqaddr_d1> is assigned but never used.
WARNING:Xst:1780 - Signal <reset2bus_error> is never used or assigned.
WARNING:Xst:1780 - Signal <reset2bus_retry> is never used or assigned.
WARNING:Xst:653 - Signal <intr2bus_wrack> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <intr2bus_data> is never used or assigned.
WARNING:Xst:646 - Signal <intr2bus_postedwrinh> is assigned but never used.
WARNING:Xst:646 - Signal <reset2bus_postedwrinh> is assigned but never used.
WARNING:Xst:1780 - Signal <intr2bus_error> is never used or assigned.
WARNING:Xst:1780 - Signal <intr2bus_retry> is never used or assigned.
WARNING:Xst:1780 - Signal <reset2bus_data> is never used or assigned.
WARNING:Xst:646 - Signal <intr2bus_ack> is assigned but never used.
WARNING:Xst:646 - Signal <last_xferack_d2> is assigned but never used.
WARNING:Xst:646 - Signal <last_wr_xferack_d2> is assigned but never used.
WARNING:Xst:646 - Signal <last_pw_xferack_d2> is assigned but never used.
WARNING:Xst:1780 - Signal <reset2bus_ack> is never used or assigned.
WARNING:Xst:1780 - Signal <intr2bus_toutsup> is never used or assigned.
WARNING:Xst:646 - Signal <inh_cs_when_pw<0>> is assigned but never used.
WARNING:Xst:646 - Signal <opb_select_s0_d1> is assigned but never used.
WARNING:Xst:653 - Signal <last_wr_xferack> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <intr2bus_rdack> is used but never assigned. Tied to value 0.
    Found 1-bit register for signal <last_pw_xferack_d1>.
    Found 1-bit register for signal <last_xferack_d1>.
    Found 32-bit register for signal <opb_abus_s0>.
    Found 4-bit register for signal <opb_be_s0>.
    Found 32-bit register for signal <opb_dbus_s0>.
    Found 1-bit register for signal <opb_rnw_s0>.
    Found 1-bit register for signal <opb_select_s0>.
    Found 1-bit register for signal <postedwrack_s2>.
    Found 32-bit register for signal <sln_dbus_s2>.
    Found 1-bit register for signal <sln_errack_s2>.
    Found 1-bit register for signal <sln_retry_s2>.
    Found 1-bit register for signal <sln_toutsup_s2>.
    Found 1-bit register for signal <sln_xferack_s1_d1>.
    Found 1-bit register for signal <sln_xferack_s1_d2>.
    Found 1-bit register for signal <sln_xferack_s2>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred 111 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <opb_bam> synthesized.


Synthesizing Unit <opb_ipif>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_ipif.vhd.
Unit <opb_ipif> synthesized.


Synthesizing Unit <GPIO_Core>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/gpio_core.vhd.
WARNING:Xst:647 - Input <select_Reg> is never used.
WARNING:Xst:647 - Input <ABus_Reg<0:28>> is never used.
WARNING:Xst:647 - Input <ABus_Reg<30:31>> is never used.
WARNING:Xst:647 - Input <GPIO2_IO_I> is never used.
WARNING:Xst:647 - Input <BE_Reg<0:2>> is never used.
WARNING:Xst:1305 - Output <GPIO2_IO_O> is never assigned. Tied to value 00000000.
WARNING:Xst:1305 - Output <GPIO2_IO_T> is never assigned. Tied to value 00000000.
WARNING:Xst:1305 - Output <GPIO2_t_out> is never assigned. Tied to value 00000000.
WARNING:Xst:647 - Input <GPIO2_in> is never used.
WARNING:Xst:1305 - Output <GPIO2_d_out> is never assigned. Tied to value 00000000.
WARNING:Xst:647 - Input <seqAddr_Reg> is never used.
WARNING:Xst:647 - Input <GPIO_IO_I> is never used.
WARNING:Xst:1780 - Signal <gpio2_data_in_xor_reg> is never used or assigned.
WARNING:Xst:1780 - Signal <or_ints> is never used or assigned.
WARNING:Xst:1780 - Signal <gpio2_Data_Out> is never used or assigned.
WARNING:Xst:1780 - Signal <gpio2_Data_In> is never used or assigned.
WARNING:Xst:1780 - Signal <gpio_data_in_xor> is never used or assigned.
WARNING:Xst:646 - Signal <dout2_default_i> is assigned but never used.
WARNING:Xst:1780 - Signal <gpio_data_in_xor_reg> is never used or assigned.
WARNING:Xst:1780 - Signal <or_ints2> is never used or assigned.
WARNING:Xst:646 - Signal <tri2_default_i> is assigned but never used.
WARNING:Xst:1780 - Signal <gpio2_data_in_xor> is never used or assigned.
WARNING:Xst:1780 - Signal <gpio2_OE> is never used or assigned.
    Found 8-bit register for signal <gpio_Data_In>.
    Found 8-bit register for signal <gpio_Data_Out>.
    Found 8-bit register for signal <gpio_OE>.
    Found 1-bit register for signal <gpio_xferAck_Reg>.
    Found 1-bit register for signal <iGPIO_xferAck>.
    Summary:
	inferred  26 D-type flip-flop(s).
Unit <GPIO_Core> synthesized.


Synthesizing Unit <opb_ipif_ssp1>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/opb_ipif_ssp1.vhd.
Unit <opb_ipif_ssp1> synthesized.


Synthesizing Unit <opb_gpio>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_gpio_v3_01_a/hdl/vhdl/opb_gpio.vhd.
WARNING:Xst:1780 - Signal <GPIO2_intr> is never used or assigned.
WARNING:Xst:646 - Signal <Bus2IP_Data<0:23>> is assigned but never used.
WARNING:Xst:646 - Signal <Bus2IP_RdCE> is assigned but never used.
WARNING:Xst:646 - Signal <Bus2IP_WrCE> is assigned but never used.
WARNING:Xst:1780 - Signal <GPIO_intr> is never used or assigned.
WARNING:Xst:646 - Signal <Bus2IP_Burst> is assigned but never used.
WARNING:Xst:1780 - Signal <GPIO_DBus> is never used or assigned.
WARNING:Xst:1780 - Signal <Bus2IP_Data_i<8:31>> is never used or assigned.
Unit <opb_gpio> synthesized.


Synthesizing Unit <leds_8bit_wrapper>.
    Related source file is C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/leds_8bit_wrapper.vhd.
Unit <leds_8bit_wrapper> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 33
 1-bit register                    : 28
 8-bit register                    : 1
 32-bit register                   : 3
 4-bit register                    : 1
# Multiplexers                     : 1
 1-bit 2-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <opb_be_s0_0> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_0> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_be_s0_2> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_be_s0_1> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_23> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_22> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_21> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_20> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_19> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_18> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_17> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_16> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_15> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_14> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_13> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_12> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_11> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_10> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_9> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_8> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_7> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_6> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_5> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_4> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_3> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_2> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_dbus_s0_1> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_abus_s0_31> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_abus_s0_30> is unconnected in block <OPB_BAM_I>.
WARNING:Xst:1291 - FF/Latch <opb_abus_s0_28> is unconnected in block <OPB_BAM_I>.

Optimizing unit <leds_8bit_wrapper> ...

Optimizing unit <GPIO_Core> ...

Optimizing unit <pselect> ...

Optimizing unit <opb_bam> ...

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_1> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_2> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_3> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_4> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_5> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_6> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_7> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_8> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_9> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_10> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_11> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_12> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_13> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_14> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_15> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_16> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_17> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_18> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_19> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_20> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_21> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_22> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_23> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_retry_s2> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_errack_s2> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_toutsup_s2> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_0> (without init value) is constant in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_be_s0_0> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_0> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_be_s0_2> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_be_s0_1> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_23> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_22> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_21> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_20> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_19> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_18> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_17> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_16> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_15> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_14> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_13> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_12> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_11> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_10> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_9> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_8> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_7> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_6> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_5> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_4> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_3> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_2> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_dbus_s0_1> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_abus_s0_31> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_abus_s0_30> is unconnected in block <leds_8bit_wrapper>.
WARNING:Xst:1291 - FF/Latch <leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_abus_s0_28> is unconnected in block <leds_8bit_wrapper>.
Building and optimizing final netlist ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ../implementation/leds_8bit_wrapper/leds_8bit_wrapper.ngr
Top Level Output File Name         : ../implementation/leds_8bit_wrapper/leds_8bit_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 206

Macro Statistics :
# Registers                        : 33
#      1-bit register              : 28
#      32-bit register             : 3
#      4-bit register              : 1
#      8-bit register              : 1
# Multiplexers                     : 1
#      2-to-1 multiplexer          : 1

Cell Usage :
# BELS                             : 46
#      GND                         : 1
#      LUT2                        : 3
#      LUT3                        : 9
#      LUT3_L                      : 4
#      LUT4                        : 4
#      LUT4_D                      : 1
#      LUT4_L                      : 17
#      MUXCY                       : 7
# FlipFlops/Latches                : 87
#      FD                          : 49
#      FDC                         : 2
#      FDCE                        : 8
#      FDPE                        : 8
#      FDR                         : 12
#      FDRE                        : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                      56  out of   1920     2%  
 Number of Slice Flip Flops:            87  out of   3840     2%  
 Number of 4 input LUTs:                38  out of   3840     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
OPB_Clk                            | NONE                   | 87    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 5.931ns (Maximum Frequency: 168.606MHz)
   Minimum input arrival time before clock: 3.115ns
   Maximum output required time after clock: 1.736ns
   Maximum combinational path delay: 0.551ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'OPB_Clk'
Delay:               5.931ns (Levels of Logic = 9)
  Source:            leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_abus_s0_0 (FF)
  Destination:       leds_8bit/gpio_core_1/READ_REG_FF_I3 (FF)
  Source Clock:      OPB_Clk rising
  Destination Clock: OPB_Clk rising

  Data Path: leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_abus_s0_0 to leds_8bit/gpio_core_1/READ_REG_FF_I3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.720   0.240  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_abus_s0_0 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/opb_abus_s0_0)
     LUT4_L:I0->LO         1   0.551   0.000  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/_n00361 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/lut_out<0>)
     MUXCY:S->O            1   0.500   0.000  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I0 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<1>)
     MUXCY:CI->O           1   0.064   0.000  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I1 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<2>)
     MUXCY:CI->O           1   0.064   0.000  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I2 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<3>)
     MUXCY:CI->O           1   0.064   0.000  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I3 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<4>)
     MUXCY:CI->O           1   0.064   0.000  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I4 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<5>)
     MUXCY:CI->O           1   0.064   0.000  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I5 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<6>)
     MUXCY:CI->O          16   0.281   0.995  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I6 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/devicesel_s0)
     LUT4:I0->O            8   0.551   0.747  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/_n00141 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/_n0014)
     FDR:R                     1.026          leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_31
    ----------------------------------------
    Total                      5.931ns (3.949ns logic, 1.982ns route)
                                       (66.6% logic, 33.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'OPB_Clk'
Offset:              3.115ns (Levels of Logic = 2)
  Source:            OPB_Rst (PAD)
  Destination:       leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_31 (FF)
  Destination Clock: OPB_Clk rising

  Data Path: OPB_Rst to leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I2->O            1   0.551   0.240  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s1_SW115_SW0 (N71059)
     LUT4:I3->O            8   0.551   0.747  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/_n00141 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/_n0014)
     FDR:R                     1.026          leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_dbus_s2_31
    ----------------------------------------
    Total                      3.115ns (2.128ns logic, 0.987ns route)
                                       (68.3% logic, 31.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'OPB_Clk'
Offset:              1.736ns (Levels of Logic = 1)
  Source:            leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s2 (FF)
  Destination:       Sln_xferAck (PAD)
  Source Clock:      OPB_Clk rising

  Data Path: leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s2 to Sln_xferAck
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.720   0.465  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s2 (leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/sln_xferack_s2)
     LUT2:I0->O            0   0.551   0.000  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/Sln_xferAck1 (Sln_xferAck)
    ----------------------------------------
    Total                      1.736ns (1.271ns logic, 0.465ns route)
                                       (73.2% logic, 26.8% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               0.551ns (Levels of Logic = 1)
  Source:            OPB_select (PAD)
  Destination:       Sln_xferAck (PAD)

  Data Path: OPB_select to Sln_xferAck
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT2:I1->O            0   0.551   0.000  leds_8bit/OPB_IPIF_SSP1_I/OPB_IPIF_I/OPB_BAM_I/Sln_xferAck1 (Sln_xferAck)
    ----------------------------------------
    Total                      0.551ns (0.551ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 6.11 / 248.87 s | Elapsed : 6.00 / 7.00 s
 
--> 

Total memory usage is 271716 kilobytes


