Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : dlmb_cntlr_wrapper_xst.prj

---- Target Parameters
Target Device                      : XC3S200FT256-4
Output File Name                   : ../implementation/dlmb_cntlr_wrapper/dlmb_cntlr_wrapper.ngc

---- Source Options
Top Module Name                    : dlmb_cntlr_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Effort                : 2
Optimization Goal                  : speed
RTL Output                         : YES
Hierarchy Separator                : /

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_c/hdl/vhdl/pselect_mask.vhd in Library proc_common_v1_00_c.
Entity <pselect_mask> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/hdl/vhdl/lmb_bram_if_cntlr.vhd in Library lmb_bram_if_cntlr_v1_00_b.
Entity <lmb_bram_if_cntlr> (Architecture <imp>) compiled.
Compiling vhdl file C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/dlmb_cntlr_wrapper.vhd in Library work.
Entity <dlmb_cntlr_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <dlmb_cntlr_wrapper> (Architecture <STRUCTURE>).
Instantiating component <lmb_bram_if_cntlr> from Library <lmb_bram_if_cntlr_v1_00_b>.
Entity <dlmb_cntlr_wrapper> analyzed. Unit <dlmb_cntlr_wrapper> generated.

Analyzing generic Entity <lmb_bram_if_cntlr> (Architecture <imp>).
	C_BASEADDR = <u>00000000000000000000000000000000
	C_HIGHADDR = <u>00000000000000000001111111111111
	C_MASK = <u>00000000001000000000000000000000
	C_LMB_AWIDTH = 32
	C_LMB_DWIDTH = 32
Instantiating component <pselect_mask> from Library <proc_common_v1_00_c>.
Entity <lmb_bram_if_cntlr> analyzed. Unit <lmb_bram_if_cntlr> generated.

Analyzing generic Entity <pselect_mask> (Architecture <imp>).
	C_AW = 32
	C_BAR = <u>00000000000000000000000000000000
	C_MASK = <u>00000000001000000000000000000000
Entity <pselect_mask> analyzed. Unit <pselect_mask> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <pselect_mask>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_c/hdl/vhdl/pselect_mask.vhd.
WARNING:Xst:647 - Input <A<0:9>> is never used.
WARNING:Xst:647 - Input <A<11:31>> is never used.
Unit <pselect_mask> synthesized.


Synthesizing Unit <lmb_bram_if_cntlr>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/hdl/vhdl/lmb_bram_if_cntlr.vhd.
WARNING:Xst:647 - Input <LMB_ReadStrobe> is never used.
    Found 1-bit register for signal <Sl_Ready>.
    Found 1-bit register for signal <lmb_select_1>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <lmb_bram_if_cntlr> synthesized.


Synthesizing Unit <dlmb_cntlr_wrapper>.
    Related source file is C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/dlmb_cntlr_wrapper.vhd.
Unit <dlmb_cntlr_wrapper> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <dlmb_cntlr_wrapper> ...

Optimizing unit <lmb_bram_if_cntlr> ...

Mapping all equations...
Building and optimizing final netlist ...
Register dlmb_cntlr/Sl_Ready equivalent to dlmb_cntlr/lmb_select_1 has been removed

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ../implementation/dlmb_cntlr_wrapper/dlmb_cntlr_wrapper.ngr
Top Level Output File Name         : ../implementation/dlmb_cntlr_wrapper/dlmb_cntlr_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 209

Macro Statistics :
# Registers                        : 2
#      1-bit register              : 2

Cell Usage :
# BELS                             : 7
#      GND                         : 1
#      LUT2                        : 1
#      LUT3                        : 4
#      VCC                         : 1
# FlipFlops/Latches                : 1
#      FDC                         : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                       3  out of   1920     0%  
 Number of Slice Flip Flops:             1  out of   3840     0%  
 Number of 4 input LUTs:                 5  out of   3840     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
LMB_Clk                            | NONE                   | 1     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: 0.754ns
   Maximum output required time after clock: 1.900ns
   Maximum combinational path delay: 0.551ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'LMB_Clk'
Offset:              0.754ns (Levels of Logic = 1)
  Source:            LMB_AddrStrobe (PAD)
  Destination:       dlmb_cntlr/lmb_select_1 (FF)
  Destination Clock: LMB_Clk rising

  Data Path: LMB_AddrStrobe to dlmb_cntlr/lmb_select_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT2:I0->O            1   0.551   0.000  dlmb_cntlr/lmb_select1 (dlmb_cntlr/lmb_select)
     FDC:D                     0.203          dlmb_cntlr/lmb_select_1
    ----------------------------------------
    Total                      0.754ns (0.754ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'LMB_Clk'
Offset:              1.900ns (Levels of Logic = 1)
  Source:            dlmb_cntlr/lmb_select_1 (FF)
  Destination:       BRAM_WEN_A<0> (PAD)
  Source Clock:      LMB_Clk rising

  Data Path: dlmb_cntlr/lmb_select_1 to BRAM_WEN_A<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              4   0.720   0.629  dlmb_cntlr/lmb_select_1 (Sl_Ready)
     LUT3:I0->O            0   0.551   0.000  dlmb_cntlr/_n00081 (BRAM_WEN_A<3>)
    ----------------------------------------
    Total                      1.900ns (1.271ns logic, 0.629ns route)
                                       (66.9% logic, 33.1% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               0.551ns (Levels of Logic = 1)
  Source:            LMB_BE<0> (PAD)
  Destination:       BRAM_WEN_A<0> (PAD)

  Data Path: LMB_BE<0> to BRAM_WEN_A<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I1->O            0   0.551   0.000  dlmb_cntlr/_n00021 (BRAM_WEN_A<0>)
    ----------------------------------------
    Total                      0.551ns (0.551ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 3.11 / 225.97 s | Elapsed : 3.00 / 4.00 s
 
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Total memory usage is 248164 kilobytes


