Release 6.3i Par G.38
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

ASUS05::  Thu Jul 28 13:34:30 2005


par -w -ol std system_map.ncd system.ncd system.pcf 


Constraints file: system.pcf

Loading device database for application Par from file "system_map.ncd".
   "system" is an NCD, version 2.38, device xc3s400, package ft256, speed -4
Loading device for application Par from file '3s400.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.35 2004-11-11.


Resolved that IOB <sys_clk_pin> must be placed at site T9.
Resolved that IOB <fpga_0_RS232_RX_pin> must be placed at site T13.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<20>> must be placed at site E4.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<12>> must be placed at site L3.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<21>> must be placed at site E3.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<13>> must be placed at site K5.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<22>> must be placed at site F4.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<14>> must be placed at site K3.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<23>> must be placed at site F3.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<15>> must be placed at site J3.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<24>> must be placed at site G4.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<16>> must be placed at site J4.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<25>> must be placed at site L4.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<17>> must be placed at site H4.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<26>> must be placed at site M3.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<18>> must be placed at site H3.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<27>> must be placed at site M4.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<19>> must be placed at site G5.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<28>> must be placed at site N3.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_A_pin<29>> must be placed at site L5.
Resolved that IOB <fpga_0_RS232_TX_pin> must be placed at site R13.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_CEN_pin<0>> must be placed at site
P7.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_CEN_1_pin<0>> must be placed at site
N5.
Resolved that IOB <cathode<0>> must be placed at site E14.
Resolved that IOB <cathode<1>> must be placed at site G13.
Resolved that IOB <cathode<2>> must be placed at site N15.
Resolved that IOB <cathode<3>> must be placed at site P15.
Resolved that IOB <cathode<4>> must be placed at site R16.
Resolved that IOB <cathode<5>> must be placed at site F13.
Resolved that IOB <cathode<6>> must be placed at site N16.
Resolved that IOB <cathode<7>> must be placed at site P16.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_OEN_pin<0>> must be placed at site
K4.
Resolved that IOB <fpga_0_Push_Buttons_3Bit_GPIO_in_pin<0>> must be placed at
site L13.
Resolved that IOB <fpga_0_Push_Buttons_3Bit_GPIO_in_pin<1>> must be placed at
site M14.
Resolved that IOB <fpga_0_Push_Buttons_3Bit_GPIO_in_pin<2>> must be placed at
site M13.
Resolved that IOB <sys_rst_pin> must be placed at site L14.
Resolved that IOB <anode<0>> must be placed at site E13.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_WEN_pin> must be placed at site G3.
Resolved that IOB <anode<1>> must be placed at site F14.
Resolved that IOB <anode<2>> must be placed at site G14.
Resolved that IOB <anode<3>> must be placed at site D14.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<10>> must be placed at site
G2.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<11>> must be placed at site
J1.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<20>> must be placed at site
H1.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<12>> must be placed at site
K1.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<21>> must be placed at site
F2.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<13>> must be placed at site
M2.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<30>> must be placed at site
T8.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<22>> must be placed at site
P8.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<14>> must be placed at site
N2.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<31>> must be placed at site
N7.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<23>> must be placed at site
D3.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<15>> must be placed at site
P2.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<24>> must be placed at site
B1.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<16>> must be placed at site
R1.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<25>> must be placed at site
C1.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<17>> must be placed at site
P1.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<26>> must be placed at site
C2.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<18>> must be placed at site
L2.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<27>> must be placed at site
R5.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<19>> must be placed at site
J2.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<28>> must be placed at site
T5.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<29>> must be placed at site
R6.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<0>> must be placed at site N1.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<1>> must be placed at site M1.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<2>> must be placed at site K2.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<3>> must be placed at site C3.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<4>> must be placed at site F5.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<5>> must be placed at site G1.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<6>> must be placed at site E2.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<7>> must be placed at site D2.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<8>> must be placed at site D1.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_DQ_pin<9>> must be placed at site E1.
Resolved that IOB <fpga_0_LEDs_8Bit_GPIO_d_out_pin<0>> must be placed at site
K12.
Resolved that IOB <fpga_0_LEDs_8Bit_GPIO_d_out_pin<1>> must be placed at site
P14.
Resolved that IOB <fpga_0_LEDs_8Bit_GPIO_d_out_pin<2>> must be placed at site
L12.
Resolved that IOB <fpga_0_LEDs_8Bit_GPIO_d_out_pin<3>> must be placed at site
N14.
Resolved that IOB <fpga_0_LEDs_8Bit_GPIO_d_out_pin<4>> must be placed at site
P13.
Resolved that IOB <fpga_0_LEDs_8Bit_GPIO_d_out_pin<5>> must be placed at site
N12.
Resolved that IOB <fpga_0_LEDs_8Bit_GPIO_d_out_pin<6>> must be placed at site
P12.
Resolved that IOB <fpga_0_LEDs_8Bit_GPIO_d_out_pin<7>> must be placed at site
P11.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_BEN_pin<0>> must be placed at site
R4.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_BEN_pin<1>> must be placed at site
P5.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_BEN_pin<2>> must be placed at site
T4.
Resolved that IOB <fpga_0_SRAM_256Kx32_Mem_BEN_pin<3>> must be placed at site
P6.


Device utilization summary:

   Number of External IOBs            85 out of 173    49%
      Number of LOCed External IOBs   85 out of 85    100%

   Number of MULT18X18s                3 out of 16     18%
   Number of RAMB16s                   8 out of 16     50%
   Number of Slices                 1595 out of 3584   44%
      Number of SLICEMs              321 out of 1792   17%

   Number of BSCANs                    1 out of 1     100%
   Number of BUFGMUXs                  2 out of 8      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 2 secs 
Finished initial Timing Analysis.  REAL time: 5 secs 


Phase 1.1
Phase 1.1 (Checksum:98e0bd) REAL time: 6 secs 

.
Phase 3.8
.........................................
.....
Phase 3.8 (Checksum:bc94ab) REAL time: 13 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 13 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 20 secs 

Writing design to file system.ncd.

Total REAL time to Placer completion: 22 secs 
Total CPU time to Placer completion: 20 secs 


Phase 1: 12500 unrouted;       REAL time: 22 secs 

Phase 2: 10838 unrouted;       REAL time: 24 secs 

Phase 3: 4951 unrouted;       REAL time: 27 secs 

Phase 4: 4951 unrouted; (0)      REAL time: 28 secs 

Phase 5: 4951 unrouted; (0)      REAL time: 29 secs 

Phase 6: 4951 unrouted; (0)      REAL time: 30 secs 

Phase 7: 0 unrouted; (0)      REAL time: 1 mins 6 secs 

Total REAL time to Router completion: 1 mins 8 secs 
Total CPU time to Router completion: 1 mins 7 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         DBG_CLK_s       |  BUFGMUX7| No   |  140 |  0.020     |  1.034      |
+-------------------------+----------+------+------+------------+-------------+
|dlmb_port_BRAM_Clk       |  BUFGMUX0| No   | 1108 |  0.060     |  1.074      |
+-------------------------+----------+------+------+------------+-------------+
|debug_module/bscan_updat |          |      |      |            |             |
|                       e |   Local  |      |    1 |  0.000     |  1.002      |
+-------------------------+----------+------+------+------------+-------------+
|opb_intc_0/opb_intc_0/IN |          |      |      |            |             |
|TC_CORE_I/INTR_DET_I/int |          |      |      |            |             |
|              errupts<0> |   Local  |      |    1 |  0.000     |  0.688      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 306


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.730
   The MAXIMUM PIN DELAY IS:                               7.680
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   6.674

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 8.00  d >= 8.00
   ---------   ---------   ---------   ---------   ---------   ---------
        2995        5107        2975        1045         378           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "bufgp_71/IBUFG" PERIOD =  20 nS   HI | 20.000ns   | 19.993ns   | 20   
  GH 50.000000 %                            |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 1 mins 13 secs 
Total CPU time to PAR completion: 1 mins 11 secs 

Peak Memory Usage:  112 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file system.ncd.


PAR done.
