Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : opb_bram_if_cntlr_1_bram_wrapper_xst.prj

---- Target Parameters
Target Device                      : XC3S200FT256-4
Output File Name                   : ../implementation/opb_bram_if_cntlr_1_bram_wrapper/opb_bram_if_cntlr_1_bram_wrapper.ngc

---- Source Options
Top Module Name                    : opb_bram_if_cntlr_1_bram_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Effort                : 2
Optimization Goal                  : speed
RTL Output                         : YES
Hierarchy Separator                : /

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd in Library opb_bram_if_cntlr_1_bram_elaborate_v1_00_a.
Entity <opb_bram_if_cntlr_1_bram_elaborate> (Architecture <STRUCTURE>) compiled.
Compiling vhdl file C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/opb_bram_if_cntlr_1_bram_wrapper.vhd in Library work.
Entity <opb_bram_if_cntlr_1_bram_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <opb_bram_if_cntlr_1_bram_wrapper> (Architecture <STRUCTURE>).
    Set user-defined property "KEEP_HIERARCHY =  yes" for unit <opb_bram_if_cntlr_1_bram_wrapper>.
Instantiating component <opb_bram_if_cntlr_1_bram_elaborate> from Library <opb_bram_if_cntlr_1_bram_elaborate_v1_00_a>.
Entity <opb_bram_if_cntlr_1_bram_wrapper> analyzed. Unit <opb_bram_if_cntlr_1_bram_wrapper> generated.

Analyzing generic Entity <opb_bram_if_cntlr_1_bram_elaborate> (Architecture <structure>).
	C_MEMSIZE = 8192
	C_PORT_DWIDTH = 32
	C_PORT_AWIDTH = 32
	C_NUM_WE = 4
	C_FAMILY = "spartan3"
WARNING:Xst:753 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 89: Unconnected output port 'DOPA' of component 'RAMB16_S9_S9'.
WARNING:Xst:753 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 89: Unconnected output port 'DOPB' of component 'RAMB16_S9_S9'.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for unit <RAMB16_S9_S9>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for unit <RAMB16_S9_S9>.
WARNING:Xst:766 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 89: Generating a Black Box for component <RAMB16_S9_S9>.
WARNING:Xst:753 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 115: Unconnected output port 'DOPA' of component 'RAMB16_S9_S9'.
WARNING:Xst:753 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 115: Unconnected output port 'DOPB' of component 'RAMB16_S9_S9'.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for unit <RAMB16_S9_S9>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for unit <RAMB16_S9_S9>.
WARNING:Xst:766 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 115: Generating a Black Box for component <RAMB16_S9_S9>.
WARNING:Xst:753 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 141: Unconnected output port 'DOPA' of component 'RAMB16_S9_S9'.
WARNING:Xst:753 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 141: Unconnected output port 'DOPB' of component 'RAMB16_S9_S9'.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for unit <RAMB16_S9_S9>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for unit <RAMB16_S9_S9>.
WARNING:Xst:766 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 141: Generating a Black Box for component <RAMB16_S9_S9>.
WARNING:Xst:753 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 167: Unconnected output port 'DOPA' of component 'RAMB16_S9_S9'.
WARNING:Xst:753 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 167: Unconnected output port 'DOPB' of component 'RAMB16_S9_S9'.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for unit <RAMB16_S9_S9>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for unit <RAMB16_S9_S9>.
WARNING:Xst:766 - C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd line 167: Generating a Black Box for component <RAMB16_S9_S9>.
Entity <opb_bram_if_cntlr_1_bram_elaborate> analyzed. Unit <opb_bram_if_cntlr_1_bram_elaborate> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <opb_bram_if_cntlr_1_bram_elaborate>.
    Related source file is C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/hdl/elaborate/opb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/opb_bram_if_cntlr_1_bram_elaborate.vhd.
WARNING:Xst:647 - Input <BRAM_Addr_A<0:18>> is never used.
WARNING:Xst:647 - Input <BRAM_Addr_A<30:31>> is never used.
WARNING:Xst:647 - Input <BRAM_Addr_B<0:18>> is never used.
WARNING:Xst:647 - Input <BRAM_Addr_B<30:31>> is never used.
Unit <opb_bram_if_cntlr_1_bram_elaborate> synthesized.


Synthesizing Unit <opb_bram_if_cntlr_1_bram_wrapper>.
    Related source file is C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/opb_bram_if_cntlr_1_bram_wrapper.vhd.
Unit <opb_bram_if_cntlr_1_bram_wrapper> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <opb_bram_if_cntlr_1_bram_wrapper> ...

Optimizing unit <opb_bram_if_cntlr_1_bram_elaborate> ...

Mapping all equations...
Building and optimizing final netlist ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ../implementation/opb_bram_if_cntlr_1_bram_wrapper/opb_bram_if_cntlr_1_bram_wrapper.ngr
Top Level Output File Name         : ../implementation/opb_bram_if_cntlr_1_bram_wrapper/opb_bram_if_cntlr_1_bram_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 206

Cell Usage :
# BELS                             : 1
#      GND                         : 1
# RAMS                             : 4
#      RAMB16_S9_S9                : 4
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of BRAMs:                        4  out of     12    33%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
BRAM_Clk_A                         | NONE                   | 4     |
BRAM_Clk_B                         | NONE                   | 4     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: 0.497ns
   Maximum output required time after clock: 2.382ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'BRAM_Clk_A'
Offset:              0.497ns (Levels of Logic = 1)
  Source:            BRAM_Rst_A (PAD)
  Destination:       opb_bram_if_cntlr_1_bram/ramb16_s9_s9_3 (RAM)
  Destination Clock: BRAM_Clk_A rising

  Data Path: BRAM_Rst_A to opb_bram_if_cntlr_1_bram/ramb16_s9_s9_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     begin scope: 'opb_bram_if_cntlr_1_bram'
     RAMB16_S9_S9:SSRA         0.497          ramb16_s9_s9_0
    ----------------------------------------
    Total                      0.497ns (0.497ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'BRAM_Clk_B'
Offset:              0.497ns (Levels of Logic = 1)
  Source:            BRAM_Rst_B (PAD)
  Destination:       opb_bram_if_cntlr_1_bram/ramb16_s9_s9_3 (RAM)
  Destination Clock: BRAM_Clk_B rising

  Data Path: BRAM_Rst_B to opb_bram_if_cntlr_1_bram/ramb16_s9_s9_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     begin scope: 'opb_bram_if_cntlr_1_bram'
     RAMB16_S9_S9:SSRB         0.497          ramb16_s9_s9_0
    ----------------------------------------
    Total                      0.497ns (0.497ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'BRAM_Clk_B'
Offset:              2.382ns (Levels of Logic = 1)
  Source:            opb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 (RAM)
  Destination:       BRAM_Din_B<0> (PAD)
  Source Clock:      BRAM_Clk_B rising

  Data Path: opb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 to BRAM_Din_B<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S9_S9:CLKB->DOB7    0   2.382   0.000  ramb16_s9_s9_0 (BRAM_Din_B<0>)
     end scope: 'opb_bram_if_cntlr_1_bram'
    ----------------------------------------
    Total                      2.382ns (2.382ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'BRAM_Clk_A'
Offset:              2.382ns (Levels of Logic = 1)
  Source:            opb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 (RAM)
  Destination:       BRAM_Din_A<0> (PAD)
  Source Clock:      BRAM_Clk_A rising

  Data Path: opb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 to BRAM_Din_A<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S9_S9:CLKA->DOA7    0   2.382   0.000  ramb16_s9_s9_0 (BRAM_Din_A<0>)
     end scope: 'opb_bram_if_cntlr_1_bram'
    ----------------------------------------
    Total                      2.382ns (2.382ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 3.54 / 287.84 s | Elapsed : 4.00 / 5.00 s
 
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Total memory usage is 319332 kilobytes


