Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : opb_bram_if_cntlr_1_wrapper_xst.prj

---- Target Parameters
Target Device                      : XC3S200FT256-4
Output File Name                   : ../implementation/opb_bram_if_cntlr_1_wrapper/opb_bram_if_cntlr_1_wrapper.ngc

---- Source Options
Top Module Name                    : opb_bram_if_cntlr_1_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Effort                : 2
Optimization Goal                  : speed
RTL Output                         : YES
Hierarchy Separator                : /

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd in Library proc_common_v1_00_b.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_c/hdl/vhdl/ipif_pkg.vhd in Library ipif_common_v1_00_c.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd in Library proc_common_v1_00_b.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/or_muxcy.vhd in Library proc_common_v1_00_b.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_c/hdl/vhdl/ipif_steer.vhd in Library ipif_common_v1_00_c.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/reset_mir.vhd in Library opb_ipif_v3_00_a.
Entity <reset_mir> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_c/hdl/vhdl/interrupt_control.vhd in Library ipif_common_v1_00_c.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd in Library opb_ipif_v3_00_a.
Entity <opb_bam> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/direct_path_cntr.vhd in Library proc_common_v1_00_b.
Entity <direct_path_cntr> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_ipif.vhd in Library opb_ipif_v3_00_a.
Entity <opb_ipif> (Architecture <imp>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_a/hdl/vhdl/bram_if.vhd in Library bram_if_cntlr_v1_00_a.
Entity <bram_if> (Architecture <implementation>) compiled.
Compiling vhdl file //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_bram_if_cntlr_v1_00_a/hdl/vhdl/opb_bram_if_cntlr.vhd in Library opb_bram_if_cntlr_v1_00_a.
Entity <opb_bram_if_cntlr> (Architecture <implementation>) compiled.
Compiling vhdl file C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/opb_bram_if_cntlr_1_wrapper.vhd in Library work.
Entity <opb_bram_if_cntlr_1_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <opb_bram_if_cntlr_1_wrapper> (Architecture <STRUCTURE>).
Instantiating component <opb_bram_if_cntlr> from Library <opb_bram_if_cntlr_v1_00_a>.
WARNING:Xst:37 - Unknown property "SPECIAL".
WARNING:Xst:37 - Unknown property "ADDR_SLICE".
WARNING:Xst:37 - Unknown property "NUM_WRITE_ENABLES".
WARNING:Xst:37 - Unknown property "AWIDTH".
WARNING:Xst:37 - Unknown property "DWIDTH".
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Clk> in unit <opb_bram_if_cntlr>.
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Rst> in unit <opb_bram_if_cntlr>.
Entity <opb_bram_if_cntlr_1_wrapper> analyzed. Unit <opb_bram_if_cntlr_1_wrapper> generated.

Analyzing generic Entity <opb_bram_if_cntlr> (Architecture <implementation>).
	c_baseaddr = <u>10000000001000000010000000000000
	c_highaddr = <u>10000000001000000011111111111111
	c_include_burst_support = 0
	c_opb_dwidth = 32
	c_opb_awidth = 32
	c_opb_clk_period_ps = 20000
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Clk> in unit <opb_bram_if_cntlr> (previous value was "10000").
WARNING:Xst:37 - Unknown property "SIGIS".
    Set property "MAX_FANOUT = 10000" for signal <OPB_Rst> in unit <opb_bram_if_cntlr> (previous value was "10000").
Instantiating component <opb_ipif> from Library <opb_ipif_v3_00_a>.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_bram_if_cntlr_v1_00_a/hdl/vhdl/opb_bram_if_cntlr.vhd line 602: Unconnected output port 'Device_Intr' of component 'opb_ipif'.
Instantiating component <bram_if> from Library <bram_if_cntlr_v1_00_a>.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_bram_if_cntlr_v1_00_a/hdl/vhdl/opb_bram_if_cntlr.vhd line 659: Unconnected output port 'IP2Bus_RdAck' of component 'bram_if'.
Entity <opb_bram_if_cntlr> analyzed. Unit <opb_bram_if_cntlr> generated.

Analyzing generic Entity <opb_ipif> (Architecture <imp>).
	C_ARD_ID_ARRAY = (120)
	C_ARD_ADDR_RANGE_ARRAY = (<u>0000000000000000000000000000000010000000001000000010000000000000, <u>0000000000000000000000000000000010000000001000000011111111111111)
	C_ARD_DWIDTH_ARRAY = (32)
	C_ARD_NUM_CE_ARRAY = (1)
	C_ARD_DEPENDENT_PROPS_ARRAY = ((0, 0, 0, 0, 0, 0), (0, 0, 0, 0, 0, 0), (0, 0, 0, 0, 0, 0))
	C_PIPELINE_MODEL = 4
	C_DEV_BLK_ID = 1
	C_DEV_MIR_ENABLE = 0
	C_AWIDTH = 32
	C_DWIDTH = 32
	C_FAMILY = "virtexe"
	C_IP_INTR_MODE_ARRAY = (1, 1)
	C_INCLUDE_DEV_ISC = 0
	C_INCLUDE_DEV_IID = 0
	C_DEV_BURST_ENABLE = 0
Entity <opb_ipif> analyzed. Unit <opb_ipif> generated.

Analyzing generic Entity <opb_bam> (Architecture <implementation>).
	C_ARD_ID_ARRAY = (120)
	C_ARD_ADDR_RANGE_ARRAY = (<u>0000000000000000000000000000000010000000001000000010000000000000, <u>0000000000000000000000000000000010000000001000000011111111111111)
	C_ARD_DWIDTH_ARRAY = (32)
	C_ARD_NUM_CE_ARRAY = (1)
	C_ARD_DEPENDENT_PROPS_ARRAY = ((0, 0, 0, 0, 0, 0), (0, 0, 0, 0, 0, 0), (0, 0, 0, 0, 0, 0))
	C_PIPELINE_MODEL = 4
	C_DEV_BLK_ID = 1
	C_DEV_MIR_ENABLE = 0
	C_AWIDTH = 32
	C_DWIDTH = 32
	C_FAMILY = "virtexe"
	C_IP_INTR_MODE_ARRAY = (1, 1)
	C_INCLUDE_DEV_ISC = 0
	C_INCLUDE_DEV_IID = 0
	C_DEV_BURST_ENABLE = 0
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
WARNING:Xst:1748 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/proc_common_pkg.vhd line 243: VHDL Assertion Statement with non constant condition is ignored.
Instantiating component <pselect> from Library <proc_common_v1_00_b>.
Instantiating component <IPIF_Steer> from Library <ipif_common_v1_00_c>.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd line 1260: Unconnected output port 'Rd_Data_Out' of component 'IPIF_Steer'.
Instantiating component <IPIF_Steer> from Library <ipif_common_v1_00_c>.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd line 1284: Unconnected output port 'Wr_Data_Out' of component 'IPIF_Steer'.
WARNING:Xst:753 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd line 1284: Unconnected output port 'BE_Out' of component 'IPIF_Steer'.
WARNING:Xst:819 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd line 1307: The following signals are missing in the process sensitivity list:
   bus2ip_cs_enable_s0.
INFO:Xst:1304 - Contents of register <opb_seqaddr_d1> in unit <opb_bam> never changes during circuit operation. The register is replaced by logic.
Entity <opb_bam> analyzed. Unit <opb_bam> generated.

Analyzing generic Entity <pselect> (Architecture <imp>).
	C_AB = 19
	C_AW = 32
	C_BAR = <u>10000000001000000010000000000000
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
WARNING:Xst:766 - //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd line 195: Generating a Black Box for component <MUXCY>.
Entity <pselect> analyzed. Unit <pselect> generated.

Analyzing generic Entity <pselect> (Architecture <imp>).
	C_AB = 0
	C_AW = 13
	C_BAR = <u>0000000000000
Entity <pselect> analyzed. Unit <pselect0> generated.

Analyzing generic Entity <IPIF_Steer> (Architecture <imp>).
	C_DWIDTH = 32
	C_SMALLEST = 32
	C_AWIDTH = 32
Entity <IPIF_Steer> analyzed. Unit <IPIF_Steer> generated.

Analyzing generic Entity <bram_if> (Architecture <implementation>).
	C_IPIF_AWIDTH = 32
	C_IPIF_DWIDTH = 32
Entity <bram_if> analyzed. Unit <bram_if> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <IPIF_Steer>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_c/hdl/vhdl/ipif_steer.vhd.
WARNING:Xst:647 - Input <Addr> is never used.
WARNING:Xst:647 - Input <Decode_size> is never used.
Unit <IPIF_Steer> synthesized.


Synthesizing Unit <pselect0>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd.
WARNING:Xst:647 - Input <A> is never used.
WARNING:Xst:1780 - Signal <lut_out> is never used or assigned.
Unit <pselect0> synthesized.


Synthesizing Unit <pselect>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/proc_common_v1_00_b/hdl/vhdl/pselect.vhd.
WARNING:Xst:647 - Input <A<19:31>> is never used.
WARNING:Xst:1780 - Signal <lut_out<5>> is never used or assigned.
Unit <pselect> synthesized.


Synthesizing Unit <opb_bam>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd.
WARNING:Xst:647 - Input <IP2Bus_Clk> is never used.
WARNING:Xst:647 - Input <OPB_xferAck> is never used.
WARNING:Xst:1305 - Output <Device_Intr> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <IP2Bus_Intr> is never used.
WARNING:Xst:647 - Input <OPB_seqAddr> is never used.
WARNING:Xst:1780 - Signal <reset2bus_toutsup> is never used or assigned.
WARNING:Xst:1780 - Signal <cs_to_or_for_dsize_bit<0><0>> is never used or assigned.
WARNING:Xst:1780 - Signal <cs_to_or_for_dsize_bit<1>> is never used or assigned.
WARNING:Xst:646 - Signal <cs_to_or_for_dsize_bit<1><0>> is assigned but never used.
WARNING:Xst:646 - Signal <cs_to_or_for_dsize_bit<2>> is assigned but never used.
WARNING:Xst:1780 - Signal <bus2ip_addr_s0> is never used or assigned.
WARNING:Xst:646 - Signal <opb_seqaddr_d1> is assigned but never used.
WARNING:Xst:646 - Signal <sln_xferack_s1_d2> is assigned but never used.
WARNING:Xst:1780 - Signal <reset2bus_error> is never used or assigned.
WARNING:Xst:1780 - Signal <reset2bus_retry> is never used or assigned.
WARNING:Xst:653 - Signal <intr2bus_wrack> is used but never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <intr2bus_data> is never used or assigned.
WARNING:Xst:646 - Signal <intr2bus_postedwrinh> is assigned but never used.
WARNING:Xst:646 - Signal <reset2bus_postedwrinh> is assigned but never used.
WARNING:Xst:1780 - Signal <intr2bus_error> is never used or assigned.
WARNING:Xst:1780 - Signal <intr2bus_retry> is never used or assigned.
WARNING:Xst:1780 - Signal <reset2bus_data> is never used or assigned.
WARNING:Xst:646 - Signal <intr2bus_ack> is assigned but never used.
WARNING:Xst:646 - Signal <new_select_s0_d1<0>> is assigned but never used.
WARNING:Xst:646 - Signal <last_xferack_d2> is assigned but never used.
WARNING:Xst:646 - Signal <last_wr_xferack_d2> is assigned but never used.
WARNING:Xst:646 - Signal <last_pw_xferack_d2> is assigned but never used.
WARNING:Xst:1780 - Signal <reset2bus_ack> is never used or assigned.
WARNING:Xst:1780 - Signal <intr2bus_toutsup> is never used or assigned.
WARNING:Xst:646 - Signal <inh_cs_when_pw<0>> is assigned but never used.
WARNING:Xst:646 - Signal <opb_select_s0_d1> is assigned but never used.
WARNING:Xst:653 - Signal <last_wr_xferack> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <intr2bus_rdack> is used but never assigned. Tied to value 0.
    Found 1-bit register for signal <last_xferack_d1>.
    Found 1-bit register for signal <postedwrack_s2>.
    Found 32-bit register for signal <sln_dbus_s2>.
    Found 1-bit register for signal <sln_errack_s2>.
    Found 1-bit register for signal <sln_retry_s2>.
    Found 1-bit register for signal <sln_toutsup_s2>.
    Found 1-bit register for signal <sln_xferack_s1_d1>.
    Found 1-bit register for signal <sln_xferack_s2>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <opb_bam> synthesized.


Synthesizing Unit <bram_if>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/bram_if_cntlr_v1_00_a/hdl/vhdl/bram_if.vhd.
WARNING:Xst:647 - Input <Bus2IP_RNW> is never used.
WARNING:Xst:1780 - Signal <IP2Bus_WrAck_i> is never used or assigned.
    Found 1-bit register for signal <IP2Bus_RdAck_i>.
    Found 1-bit register for signal <read_enable_dly1>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <bram_if> synthesized.


Synthesizing Unit <opb_ipif>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_ipif.vhd.
Unit <opb_ipif> synthesized.


Synthesizing Unit <opb_bram_if_cntlr>.
    Related source file is //farside/proj/embedded/build/EDK_Gmm.HEADn/rtf/hw/XilinxProcessorIPLib/pcores/opb_bram_if_cntlr_v1_00_a/hdl/vhdl/opb_bram_if_cntlr.vhd.
WARNING:Xst:1780 - Signal <bus2ip_rdce_d1> is never used or assigned.
WARNING:Xst:646 - Signal <Bus2IP_Burst> is assigned but never used.
WARNING:Xst:646 - Signal <Bus2IP_CE<0>> is assigned but never used.
    Found 1-bit register for signal <ip2bus_rdack>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <opb_bram_if_cntlr> synthesized.


Synthesizing Unit <opb_bram_if_cntlr_1_wrapper>.
    Related source file is C:/Data/EDKexamples/MB_Spartan3_Tutorial_6_3/synthesis/../hdl/opb_bram_if_cntlr_1_wrapper.vhd.
Unit <opb_bram_if_cntlr_1_wrapper> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 10
 1-bit register                    : 9
 32-bit register                   : 1
# Multiplexers                     : 1
 1-bit 2-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <IP2Bus_RdAck_i> is unconnected in block <I_BRAM_CONTROLLER>.
WARNING:Xst:1291 - FF/Latch <read_enable_dly1> is unconnected in block <I_BRAM_CONTROLLER>.

Optimizing unit <opb_bram_if_cntlr_1_wrapper> ...

Optimizing unit <bram_if> ...

Optimizing unit <pselect> ...

Optimizing unit <opb_bam> ...

Mapping all equations...
WARNING:Xst:1710 - FF/Latch  <opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_toutsup_s2> (without init value) is constant in block <opb_bram_if_cntlr_1_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_errack_s2> (without init value) is constant in block <opb_bram_if_cntlr_1_wrapper>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_retry_s2> (without init value) is constant in block <opb_bram_if_cntlr_1_wrapper>.
WARNING:Xst:1291 - FF/Latch <opb_bram_if_cntlr_1/I_BRAM_CONTROLLER/IP2Bus_RdAck_i> is unconnected in block <opb_bram_if_cntlr_1_wrapper>.
WARNING:Xst:1291 - FF/Latch <opb_bram_if_cntlr_1/I_BRAM_CONTROLLER/read_enable_dly1> is unconnected in block <opb_bram_if_cntlr_1_wrapper>.
Building and optimizing final netlist ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ../implementation/opb_bram_if_cntlr_1_wrapper/opb_bram_if_cntlr_1_wrapper.ngr
Top Level Output File Name         : ../implementation/opb_bram_if_cntlr_1_wrapper/opb_bram_if_cntlr_1_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 212

Macro Statistics :
# Registers                        : 10
#      1-bit register              : 9
#      32-bit register             : 1
# Multiplexers                     : 1
#      2-to-1 multiplexer          : 1

Cell Usage :
# BELS                             : 24
#      GND                         : 1
#      LUT2                        : 3
#      LUT3                        : 3
#      LUT4                        : 11
#      LUT4_D                      : 1
#      MUXCY                       : 5
# FlipFlops/Latches                : 36
#      FD                          : 1
#      FDR                         : 35
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                      27  out of   1920     1%  
 Number of Slice Flip Flops:            36  out of   3840     0%  
 Number of 4 input LUTs:                18  out of   3840     0%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
opb_clk                            | NONE                   | 36    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.660ns (Maximum Frequency: 214.592MHz)
   Minimum input arrival time before clock: 5.693ns
   Maximum output required time after clock: 2.077ns
   Maximum combinational path delay: 2.881ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'opb_clk'
Delay:               4.660ns (Levels of Logic = 2)
  Source:            opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_xferack_s2 (FF)
  Destination:       opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_dbus_s2_11 (FF)
  Source Clock:      opb_clk rising
  Destination Clock: opb_clk rising

  Data Path: opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_xferack_s2 to opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_dbus_s2_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.720   0.577  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_xferack_s2 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_xferack_s2)
     LUT4_D:I2->O          1   0.551   0.240  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/_n00131_SW0 (N96620)
     LUT4:I3->O           16   0.551   0.995  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/_n00131 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/_n0013)
     FDR:R                     1.026          opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_dbus_s2_16
    ----------------------------------------
    Total                      4.660ns (2.848ns logic, 1.812ns route)
                                       (61.1% logic, 38.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'opb_clk'
Offset:              5.693ns (Levels of Logic = 8)
  Source:            opb_abus<1> (PAD)
  Destination:       opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_dbus_s2_11 (FF)
  Destination Clock: opb_clk rising

  Data Path: opb_abus<1> to opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_dbus_s2_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT4:I0->O            1   0.551   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/_n00281 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/lut_out<0>)
     MUXCY:S->O            1   0.500   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I0 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<1>)
     MUXCY:CI->O           1   0.064   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I1 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<2>)
     MUXCY:CI->O           1   0.064   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I2 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<3>)
     MUXCY:CI->O           1   0.064   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I3 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<4>)
     MUXCY:CI->O          10   0.281   0.806  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I4 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/devicesel_s0)
     LUT4_D:I1->O          1   0.551   0.240  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/_n00131_SW0 (N96620)
     LUT4:I3->O           16   0.551   0.995  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/_n00131 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/_n0013)
     FDR:R                     1.026          opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_dbus_s2_16
    ----------------------------------------
    Total                      5.693ns (3.652ns logic, 2.041ns route)
                                       (64.1% logic, 35.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'opb_clk'
Offset:              2.077ns (Levels of Logic = 1)
  Source:            opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_xferack_s1_d1 (FF)
  Destination:       bram_en (PAD)
  Source Clock:      opb_clk rising

  Data Path: opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_xferack_s1_d1 to bram_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              10   0.720   0.806  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_xferack_s1_d1 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/sln_xferack_s1_d1)
     LUT2:I1->O            0   0.551   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/_n00261 (bram_en)
    ----------------------------------------
    Total                      2.077ns (1.271ns logic, 0.806ns route)
                                       (61.2% logic, 38.8% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               2.881ns (Levels of Logic = 7)
  Source:            opb_abus<1> (PAD)
  Destination:       bram_en (PAD)

  Data Path: opb_abus<1> to bram_en
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT4:I0->O            1   0.551   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/_n00281 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/lut_out<0>)
     MUXCY:S->O            1   0.500   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I0 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<1>)
     MUXCY:CI->O           1   0.064   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I1 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<2>)
     MUXCY:CI->O           1   0.064   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I2 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<3>)
     MUXCY:CI->O           1   0.064   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I3 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/carry_chain<4>)
     MUXCY:CI->O          10   0.281   0.806  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/DEVICESEL_S0_I/MUXCY_I4 (opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/devicesel_s0)
     LUT2:I0->O            0   0.551   0.000  opb_bram_if_cntlr_1/I_opb_ipif/OPB_BAM_I/_n00261 (bram_en)
    ----------------------------------------
    Total                      2.881ns (2.075ns logic, 0.806ns route)
                                       (72.0% logic, 28.0% route)

=========================================================================
CPU : 5.48 / 282.94 s | Elapsed : 5.00 / 7.00 s
 
--> 

Total memory usage is 314212 kilobytes


