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--     design files limited to Xilinx devices or technologies. Use            --
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-- You must compile the wrapper file mult_s8_s8.vhd when simulating
-- the core, mult_s8_s8. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY mult_s8_s8 IS
	port (
	a: IN std_logic_VECTOR(7 downto 0);
	b: IN std_logic_VECTOR(7 downto 0);
	o: OUT std_logic_VECTOR(15 downto 0));
END mult_s8_s8;

ARCHITECTURE mult_s8_s8_a OF mult_s8_s8 IS

component wrapped_mult_s8_s8
	port (
	a: IN std_logic_VECTOR(7 downto 0);
	b: IN std_logic_VECTOR(7 downto 0);
	o: OUT std_logic_VECTOR(15 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_mult_s8_s8 use entity XilinxCoreLib.mult_gen_v7_0(behavioral)
		generic map(
			c_a_type => 0,
			c_mem_type => 0,
			c_has_sclr => 0,
			c_has_q => 0,
			c_reg_a_b_inputs => 0,
			c_has_o => 1,
			bram_addr_width => 8,
			c_v2_speed => 0,
			c_baat => 8,
			c_output_hold => 0,
			c_b_constant => 0,
			c_has_loadb => 0,
			c_has_b => 1,
			c_use_luts => 1,
			c_has_rdy => 0,
			c_has_nd => 0,
			c_pipeline => 0,
			c_has_a_signed => 0,
			c_b_type => 0,
			c_sqm_type => 0,
			c_standalone => 1,
			c_b_value => "0000000000000001",
			c_enable_rlocs => 0,
			c_mult_type => 0,
			c_has_aclr => 0,
			c_mem_init_prefix => "mem",
			c_has_load_done => 0,
			c_has_swapb => 0,
			c_out_width => 16,
			c_b_width => 8,
			c_a_width => 8,
			c_has_rfd => 0,
			c_sync_enable => 1,
			c_has_ce => 0,
			c_stack_adders => 1);
BEGIN

U0 : wrapped_mult_s8_s8
		port map (
			a => a,
			b => b,
			o => o);
END mult_s8_s8_a;

-- synopsys translate_on

