PBD VERSION 1
SCHEMATIC VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    ATTR MhsPort_fpga_0_RS232_RX_pin "fpga_0_RS232_RX_pin:fpga_0_RS232_RX:*:Input:External:Normal:None"
    ATTR MhsPort_fpga_0_RS232_TX_pin "fpga_0_RS232_TX_pin:fpga_0_RS232_TX:*:Output:External:Normal:None"
    ATTR MhsPort_fpga_0_LEDs_8Bit_GPIO_d_out_pin "fpga_0_LEDs_8Bit_GPIO_d_out_pin:fpga_0_LEDs_8Bit_GPIO_d_out:[0;7]:Output:External:Normal:None"
    ATTR MhsPort_fpga_0_Push_Buttons_3Bit_GPIO_in_pin "fpga_0_Push_Buttons_3Bit_GPIO_in_pin:fpga_0_Push_Buttons_3Bit_GPIO_in:[0;2]:Input:External:Normal:None"
    ATTR MhsPort_fpga_0_SRAM_256Kx32_Mem_A_pin "fpga_0_SRAM_256Kx32_Mem_A_pin:fpga_0_SRAM_256Kx32_Mem_A:[12;29]:Output:External:Normal:None"
    ATTR MhsPort_fpga_0_SRAM_256Kx32_Mem_DQ_pin "fpga_0_SRAM_256Kx32_Mem_DQ_pin:fpga_0_SRAM_256Kx32_Mem_DQ:[0;31]:BiDirectional:External:Normal:None"
    ATTR MhsPort_fpga_0_SRAM_256Kx32_Mem_OEN_pin "fpga_0_SRAM_256Kx32_Mem_OEN_pin:fpga_0_SRAM_256Kx32_Mem_OEN:[0;0]:Output:External:Normal:None"
    ATTR MhsPort_fpga_0_SRAM_256Kx32_Mem_CEN_pin "fpga_0_SRAM_256Kx32_Mem_CEN_pin:fpga_0_SRAM_256Kx32_Mem_CEN:[0;0]:Output:External:Normal:None"
    ATTR MhsPort_fpga_0_SRAM_256Kx32_Mem_CEN_1_pin "fpga_0_SRAM_256Kx32_Mem_CEN_1_pin:fpga_0_SRAM_256Kx32_Mem_CEN:[0;0]:Output:External:Normal:None"
    ATTR MhsPort_fpga_0_SRAM_256Kx32_Mem_WEN_pin "fpga_0_SRAM_256Kx32_Mem_WEN_pin:fpga_0_SRAM_256Kx32_Mem_WEN:*:Output:External:Normal:None"
    ATTR MhsPort_fpga_0_SRAM_256Kx32_Mem_BEN_pin "fpga_0_SRAM_256Kx32_Mem_BEN_pin:fpga_0_SRAM_256Kx32_Mem_BEN:[0;3]:Output:External:Normal:None"
    ATTR MhsPort_sys_clk_pin "sys_clk_pin:sys_clk_s:*:Input:External:Clock:None"
    ATTR MhsPort_sys_rst_pin "sys_rst_pin:sys_rst_s:*:Input:External:Normal:None"
    ATTR MhsPort_cathode "cathode:fpga_0_LED_cathode_GPIO_d_out:[0;7]:Output:External:Normal:None"
    ATTR MhsPort_anode "anode:fpga_0_LED_anode_GPIO_d_out:[0;3]:Output:External:Normal:None"
    BEGIN NETLIST
        BEGIN SIGNAL mb_opb
            ATTR MpdName "opb_v20"
            ATTR MpdHwVersion "1.10.b"
            ATTR C_EXT_RESET_HIGH "1"
            ATTR MhsPort_SYS_Rst "SYS_Rst:sys_rst_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk_s:*:Input:Internal:Normal:None"
        END SIGNAL
        BEGIN SIGNAL opb_bram_if_cntlr_1_port
            ATTR MpdName "Transparent"
            ATTR MpdHwVersion "1.00.a"
        END SIGNAL
        BEGIN SIGNAL dlmb
            ATTR MpdName "lmb_v10"
            ATTR MpdHwVersion "1.00.a"
            ATTR C_EXT_RESET_HIGH "1"
            ATTR MhsPort_SYS_Rst "SYS_Rst:sys_rst_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_LMB_Clk "LMB_Clk:sys_clk_s:*:Input:Internal:Normal:None"
        END SIGNAL
        BEGIN SIGNAL ilmb
            ATTR MpdName "lmb_v10"
            ATTR MpdHwVersion "1.00.a"
            ATTR C_EXT_RESET_HIGH "1"
            ATTR MhsPort_SYS_Rst "SYS_Rst:sys_rst_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_LMB_Clk "LMB_Clk:sys_clk_s:*:Input:Internal:Normal:None"
        END SIGNAL
        BEGIN SIGNAL ilmb_port
            ATTR MpdName "Transparent"
            ATTR MpdHwVersion "1.00.a"
        END SIGNAL
        BEGIN SIGNAL dlmb_port
            ATTR MpdName "Transparent"
            ATTR MpdHwVersion "1.00.a"
        END SIGNAL
        BEGIN BLOCKDEF microblaze_0
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 128 
            LINE N 0 32 32 32 
            LINE N 128 32 96 32 
            LINE N 128 64 96 64 
            LINE N 128 96 96 96 
        END BLOCKDEF
        BEGIN BLOCKDEF opb_intc_0
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 64 
            LINE N 0 32 32 32 
        END BLOCKDEF
        BEGIN BLOCKDEF opb_bram_if_cntlr_1
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 96 
            LINE N 0 32 32 32 
            LINE N 0 64 32 64 
        END BLOCKDEF
        BEGIN BLOCKDEF ilmb_cntlr
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 96 
            LINE N 0 32 32 32 
            LINE N 0 64 32 64 
        END BLOCKDEF
        BEGIN BLOCKDEF dlmb_cntlr
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 96 
            LINE N 0 32 32 32 
            LINE N 0 64 32 64 
        END BLOCKDEF
        BEGIN BLOCKDEF debug_module
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 64 
            LINE N 0 32 32 32 
        END BLOCKDEF
        BEGIN BLOCKDEF SRAM_256Kx32
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 64 
            LINE N 0 32 32 32 
        END BLOCKDEF
        BEGIN BLOCKDEF RS232
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 64 
            LINE N 0 32 32 32 
        END BLOCKDEF
        BEGIN BLOCKDEF Push_Buttons_3Bit
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 64 
            LINE N 0 32 32 32 
        END BLOCKDEF
        BEGIN BLOCKDEF LEDs_8Bit
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 64 
            LINE N 0 32 32 32 
        END BLOCKDEF
        BEGIN BLOCKDEF LED_cathodes
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 64 
            LINE N 0 32 32 32 
        END BLOCKDEF
        BEGIN BLOCKDEF LED_anodes
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 64 
            LINE N 0 32 32 32 
        END BLOCKDEF
        BEGIN BLOCKDEF opb_bram_if_cntlr_1_bram
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 64 
            LINE N 0 32 32 32 
        END BLOCKDEF
        BEGIN BLOCKDEF lmb_bram
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 96 
            LINE N 0 32 32 32 
            LINE N 0 64 32 64 
        END BLOCKDEF
        BEGIN BLOCKDEF SRAM_256Kx32_util_bus_split_0
            TIMESTAMP 2005 7 28 7 5 5
            RECTANGLE N 32 0 96 64 
        END BLOCKDEF
        BEGIN BLOCK microblaze_0 microblaze_0
            ATTR MpdName "microblaze"
            ATTR MpdHwVersion "3.00.a"
            ATTR C_DEBUG_ENABLED "1"
            ATTR C_NUMBER_OF_PC_BRK "2"
            ATTR C_NUMBER_OF_RD_ADDR_BRK "1"
            ATTR C_NUMBER_OF_WR_ADDR_BRK "1"
            ATTR MhsPort_CLK "CLK:sys_clk_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_CAPTURE "DBG_CAPTURE:DBG_CAPTURE_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_CLK "DBG_CLK:DBG_CLK_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_REG_EN "DBG_REG_EN:DBG_REG_EN_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_TDI "DBG_TDI:DBG_TDI_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_TDO "DBG_TDO:DBG_TDO_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_UPDATE "DBG_UPDATE:DBG_UPDATE_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_Interrupt "Interrupt:Interrupt:*:Input:Internal:Normal:None"
            ATTR MpdSymbolInstructions "W64:H64:L=DLMB:T:R=ILMB,DOPB,IOPB:B"
            PIN DLMB dlmb
            PIN ILMB ilmb
            PIN DOPB mb_opb
            PIN IOPB mb_opb
        END BLOCK
        BEGIN BLOCK opb_intc_0 opb_intc_0
            ATTR MpdName "opb_intc"
            ATTR MpdHwVersion "1.00.c"
            ATTR C_BASEADDR "0x80200100"
            ATTR C_HIGHADDR "0x802001ff"
            ATTR MhsPort_Irq "Irq:Interrupt:*:Input:Internal:Normal:None"
            ATTR MhsPort_Intr "Intr:RS232_Interrupt:*:Input:Internal:Normal:None"
            ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
            PIN SOPB mb_opb
        END BLOCK
        BEGIN BLOCK opb_bram_if_cntlr_1 opb_bram_if_cntlr_1
            ATTR MpdName "opb_bram_if_cntlr"
            ATTR MpdHwVersion "1.00.a"
            ATTR c_opb_clk_period_ps "20000"
            ATTR c_baseaddr "0x80202000"
            ATTR c_highaddr "0x80203fff"
            ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk_s:*:Input:Internal:Normal:None"
            ATTR MpdSymbolInstructions "W64:H64:L=SOPB,PORTA:T:R:B"
            PIN SOPB mb_opb
            PIN PORTA opb_bram_if_cntlr_1_port
        END BLOCK
        BEGIN BLOCK ilmb_cntlr ilmb_cntlr
            ATTR MpdName "lmb_bram_if_cntlr"
            ATTR MpdHwVersion "1.00.b"
            ATTR C_BASEADDR "0x00000000"
            ATTR C_HIGHADDR "0x00001fff"
            ATTR MpdSymbolInstructions "W64:H64:L=SLMB,BRAM_PORT:T:R:B"
            PIN SLMB ilmb
            PIN BRAM_PORT ilmb_port
        END BLOCK
        BEGIN BLOCK dlmb_cntlr dlmb_cntlr
            ATTR MpdName "lmb_bram_if_cntlr"
            ATTR MpdHwVersion "1.00.b"
            ATTR C_BASEADDR "0x00000000"
            ATTR C_HIGHADDR "0x00001fff"
            ATTR MpdSymbolInstructions "W64:H64:L=SLMB,BRAM_PORT:T:R:B"
            PIN SLMB dlmb
            PIN BRAM_PORT dlmb_port
        END BLOCK
        BEGIN BLOCK debug_module debug_module
            ATTR MpdName "opb_mdm"
            ATTR MpdHwVersion "2.00.a"
            ATTR C_MB_DBG_PORTS "1"
            ATTR C_USE_UART "1"
            ATTR C_UART_WIDTH "8"
            ATTR C_BASEADDR "0x80200200"
            ATTR C_HIGHADDR "0x802002ff"
            ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_CAPTURE_0 "DBG_CAPTURE_0:DBG_CAPTURE_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_CLK_0 "DBG_CLK_0:DBG_CLK_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_REG_EN_0 "DBG_REG_EN_0:DBG_REG_EN_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_TDI_0 "DBG_TDI_0:DBG_TDI_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_TDO_0 "DBG_TDO_0:DBG_TDO_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_DBG_UPDATE_0 "DBG_UPDATE_0:DBG_UPDATE_s:*:Input:Internal:Normal:None"
            ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
            PIN SOPB mb_opb
        END BLOCK
        BEGIN BLOCK SRAM_256Kx32 SRAM_256Kx32
            ATTR MpdName "opb_emc"
            ATTR MpdHwVersion "1.10.b"
            ATTR C_OPB_CLK_PERIOD_PS "20000"
            ATTR C_NUM_BANKS_MEM "1"
            ATTR C_DEV_MIR_ENABLE "0"
            ATTR C_READ_ADDR_TO_OUT_SLOW_PS_0 "10000"
            ATTR C_WRITE_ADDR_TO_OUT_SLOW_PS_0 "8000"
            ATTR C_WRITE_MIN_PULSE_WIDTH_PS_0 "8000"
            ATTR C_READ_ADDR_TO_OUT_FAST_PS_0 "10000"
            ATTR C_WRITE_ADDR_TO_OUT_FAST_PS_0 "8000"
            ATTR C_BASEADDR "0x80200400"
            ATTR C_HIGHADDR "0x802005ff"
            ATTR C_MEM0_BASEADDR "0x80300000"
            ATTR C_MEM0_HIGHADDR "0x803fffff"
            ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_Mem_A "Mem_A:fpga_0_SRAM_256Kx32_Mem_A_split:*:Input:Internal:Normal:None"
            ATTR MhsPort_Mem_DQ "Mem_DQ:fpga_0_SRAM_256Kx32_Mem_DQ:*:Input:Internal:Normal:None"
            ATTR MhsPort_Mem_OEN "Mem_OEN:fpga_0_SRAM_256Kx32_Mem_OEN:*:Input:Internal:Normal:None"
            ATTR MhsPort_Mem_CEN "Mem_CEN:fpga_0_SRAM_256Kx32_Mem_CEN:*:Input:Internal:Normal:None"
            ATTR MhsPort_Mem_WEN "Mem_WEN:fpga_0_SRAM_256Kx32_Mem_WEN:*:Input:Internal:Normal:None"
            ATTR MhsPort_Mem_BEN "Mem_BEN:fpga_0_SRAM_256Kx32_Mem_BEN:*:Input:Internal:Normal:None"
            ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
            PIN SOPB mb_opb
        END BLOCK
        BEGIN BLOCK RS232 RS232
            ATTR MpdName "opb_uartlite"
            ATTR MpdHwVersion "1.00.b"
            ATTR C_BAUDRATE "9600"
            ATTR C_DATA_BITS "8"
            ATTR C_ODD_PARITY "0"
            ATTR C_USE_PARITY "0"
            ATTR C_CLK_FREQ "50000000"
            ATTR C_BASEADDR "0x80200300"
            ATTR C_HIGHADDR "0x802003ff"
            ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_Interrupt "Interrupt:RS232_Interrupt:*:Input:Internal:Normal:None"
            ATTR MhsPort_RX "RX:fpga_0_RS232_RX:*:Input:Internal:Normal:None"
            ATTR MhsPort_TX "TX:fpga_0_RS232_TX:*:Input:Internal:Normal:None"
            ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
            PIN SOPB mb_opb
        END BLOCK
        BEGIN BLOCK Push_Buttons_3Bit Push_Buttons_3Bit
            ATTR MpdName "opb_gpio"
            ATTR MpdHwVersion "3.01.a"
            ATTR C_GPIO_WIDTH "3"
            ATTR C_IS_DUAL "0"
            ATTR C_IS_BIDIR "0"
            ATTR C_ALL_INPUTS "1"
            ATTR C_BASEADDR "0x80200600"
            ATTR C_HIGHADDR "0x802007ff"
            ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_GPIO_in "GPIO_in:fpga_0_Push_Buttons_3Bit_GPIO_in:*:Input:Internal:Normal:None"
            ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
            PIN SOPB mb_opb
        END BLOCK
        BEGIN BLOCK LEDs_8Bit LEDs_8Bit
            ATTR MpdName "opb_gpio"
            ATTR MpdHwVersion "3.01.a"
            ATTR C_GPIO_WIDTH "8"
            ATTR C_IS_DUAL "0"
            ATTR C_IS_BIDIR "0"
            ATTR C_ALL_INPUTS "0"
            ATTR C_BASEADDR "0x80200800"
            ATTR C_HIGHADDR "0x802009ff"
            ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_GPIO_d_out "GPIO_d_out:fpga_0_LEDs_8Bit_GPIO_d_out:*:Input:Internal:Normal:None"
            ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
            PIN SOPB mb_opb
        END BLOCK
        BEGIN BLOCK LED_cathodes LED_cathodes
            ATTR MpdName "opb_gpio"
            ATTR MpdHwVersion "3.01.a"
            ATTR C_BASEADDR "0x80200a00"
            ATTR C_HIGHADDR "0x80200bff"
            ATTR C_GPIO_WIDTH "8"
            ATTR C_ALL_INPUTS "0"
            ATTR C_IS_BIDIR "0"
            ATTR C_IS_DUAL "0"
            ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_GPIO_d_out "GPIO_d_out:fpga_0_LED_cathode_GPIO_d_out:*:Input:Internal:Normal:None"
            ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
            PIN SOPB mb_opb
        END BLOCK
        BEGIN BLOCK LED_anodes LED_anodes
            ATTR MpdName "opb_gpio"
            ATTR MpdHwVersion "3.01.a"
            ATTR C_BASEADDR "0x80200c00"
            ATTR C_HIGHADDR "0x80200dff"
            ATTR C_GPIO_WIDTH "4"
            ATTR C_IS_DUAL "0"
            ATTR C_IS_BIDIR "0"
            ATTR C_ALL_INPUTS "0"
            ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk_s:*:Input:Internal:Normal:None"
            ATTR MhsPort_GPIO_d_out "GPIO_d_out:fpga_0_LED_anode_GPIO_d_out:*:Input:Internal:Normal:None"
            ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
            PIN SOPB mb_opb
        END BLOCK
        BEGIN BLOCK opb_bram_if_cntlr_1_bram opb_bram_if_cntlr_1_bram
            ATTR MpdName "bram_block"
            ATTR MpdHwVersion "1.00.a"
            ATTR MpdSymbolInstructions "W64:H64:L=PORTA:T:R:B"
            PIN PORTA opb_bram_if_cntlr_1_port
        END BLOCK
        BEGIN BLOCK lmb_bram lmb_bram
            ATTR MpdName "bram_block"
            ATTR MpdHwVersion "1.00.a"
            ATTR MpdSymbolInstructions "W64:H64:L=PORTA,PORTB:T:R:B"
            PIN PORTA ilmb_port
            PIN PORTB dlmb_port
        END BLOCK
        BEGIN BLOCK SRAM_256Kx32_util_bus_split_0 SRAM_256Kx32_util_bus_split_0
            ATTR MpdName "util_bus_split"
            ATTR MpdHwVersion "1.00.a"
            ATTR C_SIZE_IN "32"
            ATTR C_LEFT_POS "12"
            ATTR C_SPLIT "30"
            ATTR MhsPort_Sig "Sig:fpga_0_SRAM_256Kx32_Mem_A_split:*:Input:Internal:Normal:None"
            ATTR MhsPort_Out1 "Out1:fpga_0_SRAM_256Kx32_Mem_A:*:Input:Internal:Normal:None"
            ATTR MpdSymbolInstructions "W64:H64:L:T:R:B"
        END BLOCK
    END NETLIST
    BEGIN SHEET 1 1440 1520
        BEGIN BRANCH mb_opb
            WIRE 208 192 432 192
            WIRE 432 192 432 224
            WIRE 432 224 432 320
            WIRE 432 320 464 320
            WIRE 432 320 432 448
            WIRE 432 448 656 448
            WIRE 432 448 432 832
            WIRE 432 832 464 832
            WIRE 432 832 432 928
            WIRE 432 928 464 928
            WIRE 432 928 432 1024
            WIRE 432 1024 464 1024
            WIRE 432 1024 432 1120
            WIRE 432 1120 464 1120
            WIRE 432 1120 432 1216
            WIRE 432 1216 464 1216
            WIRE 432 1216 432 1312
            WIRE 432 1312 464 1312
            WIRE 432 1312 432 1408
            WIRE 432 1408 432 1472
            WIRE 432 1408 464 1408
            WIRE 208 224 432 224
            WIRE 432 48 432 192
            BEGIN DISPLAY 432 48 ATTR Name
                ALIGNMENT HARD-BCENTER
            END DISPLAY
            BEGIN DISPLAY 432 1472 ATTR Name
                ALIGNMENT HARD-TCENTER
            END DISPLAY
        END BRANCH
        BEGIN BRANCH opb_bram_if_cntlr_1_port
            WIRE 624 48 624 320
            WIRE 624 320 624 480
            WIRE 624 480 624 1472
            WIRE 624 480 656 480
            WIRE 624 320 656 320
            BEGIN DISPLAY 624 48 ATTR Name
                ALIGNMENT HARD-BCENTER
            END DISPLAY
            BEGIN DISPLAY 624 1472 ATTR Name
                ALIGNMENT HARD-TCENTER
            END DISPLAY
        END BRANCH
        BEGIN BRANCH dlmb
            WIRE 48 48 48 160
            WIRE 48 160 80 160
            WIRE 48 160 48 704
            WIRE 48 704 48 1472
            WIRE 48 704 1040 704
            BEGIN DISPLAY 48 48 ATTR Name
                ALIGNMENT HARD-BCENTER
            END DISPLAY
            BEGIN DISPLAY 48 1472 ATTR Name
                ALIGNMENT HARD-TCENTER
            END DISPLAY
        END BRANCH
        BEGIN BRANCH ilmb
            WIRE 208 160 240 160
            WIRE 240 160 240 576
            WIRE 240 576 240 1472
            WIRE 240 576 848 576
            WIRE 240 48 240 160
            BEGIN DISPLAY 240 48 ATTR Name
                ALIGNMENT HARD-BCENTER
            END DISPLAY
            BEGIN DISPLAY 240 1472 ATTR Name
                ALIGNMENT HARD-TCENTER
            END DISPLAY
        END BRANCH
        BEGIN BRANCH ilmb_port
            WIRE 816 48 816 320
            WIRE 816 320 816 608
            WIRE 816 608 816 1472
            WIRE 816 608 848 608
            WIRE 816 320 1040 320
            BEGIN DISPLAY 816 48 ATTR Name
                ALIGNMENT HARD-BCENTER
            END DISPLAY
            BEGIN DISPLAY 816 1472 ATTR Name
                ALIGNMENT HARD-TCENTER
            END DISPLAY
        END BRANCH
        BEGIN BRANCH dlmb_port
            WIRE 1008 48 1008 352
            WIRE 1008 352 1008 736
            WIRE 1008 736 1008 1472
            WIRE 1008 736 1040 736
            WIRE 1008 352 1040 352
            BEGIN DISPLAY 1008 48 ATTR Name
                ALIGNMENT HARD-BCENTER
            END DISPLAY
            BEGIN DISPLAY 1008 1472 ATTR Name
                ALIGNMENT HARD-TCENTER
            END DISPLAY
        END BRANCH
        INSTANCE microblaze_0 80 128 R0
        INSTANCE opb_intc_0 464 288 R0
        INSTANCE opb_bram_if_cntlr_1 656 416 R0
        INSTANCE ilmb_cntlr 848 544 R0
        INSTANCE dlmb_cntlr 1040 672 R0
        INSTANCE debug_module 464 800 R0
        INSTANCE SRAM_256Kx32 464 896 R0
        INSTANCE RS232 464 992 R0
        INSTANCE Push_Buttons_3Bit 464 1088 R0
        INSTANCE LEDs_8Bit 464 1184 R0
        INSTANCE LED_cathodes 464 1280 R0
        INSTANCE LED_anodes 464 1376 R0
        INSTANCE opb_bram_if_cntlr_1_bram 656 288 R0
        INSTANCE lmb_bram 1040 288 R0
        INSTANCE SRAM_256Kx32_util_bus_split_0 1232 288 R0
    END SHEET
END SCHEMATIC
