## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
## You may copy and modify these files for your own internal use solely with
## Xilinx programmable logic devices and  Xilinx EDK system or create IP
## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
## No rights are granted to distribute any files unless they are distributed in
## Xilinx programmable logic devices.
###################################################################
##
## Name     : video_emc_controller
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN video_emc_controller

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER


## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB
PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB
PARAMETER C_OPB_CLK_PERIOD_PS = 20000, DT = INTEGER, BUS = SOPB
PARAMETER C_NUM_BANKS_MEM = 1, DT = INTEGER
PARAMETER C_DEV_MIR_ENABLE = 0, DT = INTEGER
PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 10000, DT = INTEGER
PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 8000, DT = INTEGER
PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 8000, DT = INTEGER
PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 10000, DT = INTEGER
PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 8000, DT = INTEGER
PARAMETER C_BASEADDR = 0xc0000000, DT = std_logic_vectorstd_logic_vector(31 downto 0), ADDRESS = BASE, PAIR = C_HIGHADDR
PARAMETER C_HIGHADDR = 0xc0001fff, DT = std_logic_vectorstd_logic_vector(31 downto 0), ADDRESS = HIGH, PAIR = C_BASEADDR
PARAMETER C_MEM0_BASEADDR = 0xc0002000, DT = std_logic_vectorstd_logic_vector(31 downto 0), BUS = SOPB, ADDRESS = BASE, PAIR = C_MEM0_HIGHADDR, MIN_SIZE = 0x10000
PARAMETER C_MEM0_HIGHADDR = 0xffffffff, DT = std_logic_vectorstd_logic_vector(31 downto 0), BUS = SOPB, ADDRESS = HIGH, PAIR = C_MEM0_BASEADDR

## Ports
PORT OPB_Clk = "", DIR = I, BUS = SOPB
PORT OPB_Rst = OPB_Rst, DIR = I, BUS = SOPB
PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = SOPB
PORT OPB_BE = OPB_BE, DIR = I, VEC = [3:0], ENDIAN = LITTLE, BUS = SOPB
PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = SOPB
PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB
PORT OPB_select = OPB_select, DIR = I, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB
PORT EMC_DBus = Sl_DBus, DIR = O, VEC = [31:0], ENDIAN = LITTLE, BUS = SOPB
PORT EMC_errAck = Sl_errAck, DIR = O, BUS = SOPB
PORT EMC_retry = Sl_retry, DIR = O, BUS = SOPB
PORT EMC_toutSup = Sl_toutSup, DIR = O, BUS = SOPB
PORT EMC_xferAck = Sl_xferAck, DIR = O, BUS = SOPB
PORT Pixel_Clock_2x = "", DIR = I
PORT VIDOUT_CLK = "", DIR = O
PORT VIDOUT_RED = "", DIR = O
PORT VIDOUT_GREEN = "", DIR = O
PORT VIDOUT_BLUE = "", DIR = O
PORT VIDOUT_HSYNC = "", DIR = O
PORT VIDOUT_VSYNC = "", DIR = O
PORT Mem_A = "", DIR = O, VEC = [0:31]
PORT Mem_DQ = "", DIR = IO, VEC = [0:31], THREE_STATE = TRUE, ENABLE = MULTI
PORT Mem_OEN = "", DIR = O
PORT Mem_CEN = "", DIR = O
PORT Mem_WEN = "", DIR = O
PORT Mem_BEN = "", DIR = O, VEC = [0:3]

END
