############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin LOC=T9;
Net sys_rst_pin LOC=l14;
## System level constraints
Net sys_clk_pin PERIOD = 20000 ps;
Net sys_rst_pin TIG;

## FPGA pin constraints
Net fpga_0_RS232_RX_pin LOC=t13;
Net fpga_0_RS232_TX_pin LOC=r13;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<0> LOC=k12;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<1> LOC=p14;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<2> LOC=l12;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<3> LOC=n14;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<4> LOC=p13;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<5> LOC=n12;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<6> LOC=p12;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<7> LOC=p11;

# Seven-segment display cathode (segment) control
# active-low: 0 = lit segment
Net "cathode<0>"  LOC=e14; # segment A
Net "cathode<1>"  LOC=g13;
Net "cathode<2>"  LOC=n15;
Net "cathode<3>"  LOC=p15;
Net "cathode<4>"  LOC=r16;
Net "cathode<5>"  LOC=f13;
Net "cathode<6>"  LOC=n16; # segment G
Net "cathode<7>"  LOC=p16; # Decimal Point

# Seven-segment display anode (digit) control
# Active-low: 0 = enable digit
Net "anode<0>"  LOC=e13;
Net "anode<1>"  LOC=f14;
Net "anode<2>"  LOC=g14;
Net "anode<3>"  LOC=d14;

# 
NET "blu"  LOC = "R11"  ;
NET "grn"  LOC = "T12"  ;
NET "hs"  LOC = "R9"  ;
NET "red"  LOC = "R12"  ;
NET "vs"  LOC = "T10"  ;

Net fpga_0_Push_Buttons_3Bit_GPIO_in_pin<0> LOC=l13;
Net fpga_0_Push_Buttons_3Bit_GPIO_in_pin<1> LOC=m14;
Net fpga_0_Push_Buttons_3Bit_GPIO_in_pin<2> LOC=m13;

Net fpga_0_SRAM_256Kx32_Mem_A_pin<29> LOC=l5;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<28> LOC=n3;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<27> LOC=m4;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<26> LOC=m3;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<25> LOC=l4;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<24> LOC=g4;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<23> LOC=f3;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<22> LOC=f4;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<21> LOC=e3;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<20> LOC=e4;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<19> LOC=g5;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<18> LOC=h3;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<17> LOC=h4;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<16> LOC=j4;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<15> LOC=j3;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<14> LOC=k3;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<13> LOC=k5;
Net fpga_0_SRAM_256Kx32_Mem_A_pin<12> LOC=l3;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<31> LOC=n7;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<30> LOC=t8;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<29> LOC=R6;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<28> LOC=T5;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<27> LOC=R5;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<26> LOC=c2;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<25> LOC=c1;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<24> LOC=b1;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<23> LOC=d3;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<22> LOC=P8;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<21> LOC=f2;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<20> LOC=h1;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<19> LOC=j2;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<18> LOC=l2;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<17> LOC=p1;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<16> LOC=r1;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<15> LOC=p2;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<14> LOC=n2;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<13> LOC=m2;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<12> LOC=k1;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<11> LOC=j1;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<10> LOC=g2;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<9> LOC=e1;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<8> LOC=d1;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<7> LOC=d2;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<6> LOC=e2;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<5> LOC=g1;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<4> LOC=f5;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<3> LOC=c3;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<2> LOC=k2;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<1> LOC=m1;
Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<0> LOC=n1;
Net fpga_0_SRAM_256Kx32_Mem_OEN_pin<0> LOC=k4;
Net fpga_0_SRAM_256Kx32_Mem_CEN_pin<0> LOC=p7;
Net fpga_0_SRAM_256Kx32_Mem_CEN_1_pin<0> LOC=n5;
Net fpga_0_SRAM_256Kx32_Mem_WEN_pin LOC=g3;
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<3> LOC=p6;
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<2> LOC=t4;
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<1> LOC=p5;
Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<0> LOC=r4;
