# Makefile for VHDL simulation
#
# Stephen A. Edwards for CSEE 4840

VHDL_SOURCEFILES = design2.vhdl
ROOT_ENTITY = testbench
ROOT_ARCHITECTURE = behavioral

# You shouldn't have to modify anything below this line

WORK_DIR = ./work

MAIN_INCLUDE = /usr/cad/ldv/tools.lnx86/inca/files/cdsvhdl.lib

CDSBIN = /usr/cad/ldv/tools/bin
NCVHDL = $(CDSBIN)/ncvhdl
NCELAB = $(CDSBIN)/ncelab
NCSIM = $(CDSBIN)/ncsim

NCVHDLARGS = -V93
NCSIMARGS = -gui
NCELABARGS = -ACCESS +r

.PHONY : simulate
simulate : elaborated
	$(NCSIM) $(NCSIMARGS) $(ROOT_ENTITY)

elaborate elaborated : analyzed
	rm -f elaborated
	$(NCELAB) $(NCELABARGS) $(ROOT_ENTITY):$(ROOT_ARCHITECTURE)
	touch elaborated

analyze analyzed : hdl.var cds.lib $(WORK_DIR) $(VHDL_SOURCEFILES)
	rm -f analyzed
	$(NCVHDL) $(NCVHDLARGS) $(VHDL_SOURCEFILES)
	touch analyzed

hdl.var : Makefile
	echo "DEFINE WORK mywork" > hdl.var

cds.lib : Makefile
	echo "DEFINE mywork $(WORK_DIR)" > cds.lib
	echo "SOFTINCLUDE $(MAIN_INCLUDE)" >> cds.lib

$(WORK_DIR) :
	-mkdir $(WORK_DIR)

clean :
	rm -rf hdl.var cds.lib $(WORK_DIR) ncvhdl.log ncelab.log \
	analyzed elaborated waves.shm ncsim.log ncsim.key .simcontrol
