# do guitar_effects_run_msim_rtl_vhdl.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -work work +incdir+/home/user6/spring07/yy2223/Project3/Project /home/user6/spring07/yy2223/Project3/Project/de2_i2c_av_config.v
# Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
# -- Compiling module de2_i2c_av_config
# 
# Top level modules:
# 	de2_i2c_av_config
# vlog -work work +incdir+/home/user6/spring07/yy2223/Project3/Project /home/user6/spring07/yy2223/Project3/Project/de2_i2c_controller.v
# Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
# -- Compiling module de2_i2c_controller
# 
# Top level modules:
# 	de2_i2c_controller
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/effector.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity effector
# -- Compiling architecture rtl of effector
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/LRRequstBuffer_out.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity lrrequestbuffer_out
# -- Compiling architecture behavioral of lrrequestbuffer_out
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/LRRequstBuffer_in.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity lrrequestbuffer_in
# -- Compiling architecture behavioral of lrrequestbuffer_in
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/ram_1633_16.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity ram_1633_16
# -- Compiling architecture myram of ram_1633_16
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/vibrato.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity vibrato
# -- Compiling architecture rtl of vibrato
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/distortion.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity distortion
# -- Compiling architecture rtl of distortion
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/de2_wm8731_audio_in.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity de2_wm8731_audio_in
# -- Compiling architecture behavioral of de2_wm8731_audio_in
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/de2_wm8731_audio_out.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity de2_wm8731_audio_out
# -- Compiling architecture behavioral of de2_wm8731_audio_out
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/guitar_effects_top.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity guitar_effects_top
# -- Compiling architecture datapath of guitar_effects_top
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/sine_table.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity sine_table
# -- Compiling architecture rtl of sine_table
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/vibrato_button_ctl.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity vibrato_button_ctl
# -- Compiling architecture rtl of vibrato_button_ctl
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/dist_amp.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity dist_amp
# -- Compiling architecture rtl of dist_amp
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/vibrato_button_ctl2.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity vibrato_button_ctl2
# -- Compiling architecture rtl of vibrato_button_ctl2
# 
# vcom -work work /home/user6/spring07/yy2223/Project3/Project/sine_table_TB.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity sine_table_tb
# -- Compiling architecture rtl of sine_table_tb
# 
# vsim -t 1ps -L lpm -L altera -L altera_mf -L sgate -L cycloneii -L work sine_table_TB
# vsim -L lpm -L altera -L altera_mf -L sgate -L cycloneii -L work -t 1ps sine_table_TB 
# //  ModelSim ALTERA 6.1g Aug 12 2006 Linux 2.6.9-42.0.2.ELsmp
# //
# //  Copyright 2006 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../std.standard
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../ieee.std_logic_1164(body)
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../ieee.std_logic_arith(body)
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../ieee.std_logic_unsigned(body)
# Loading rtl_work.sine_table_tb(rtl)
# Loading rtl_work.sine_table(rtl)
# 
# add wave *
# view structure
# .main_pane.workspace
# view signals
# .main_pane.signals.interior.cs
# run 100 us
