# do final_project_run_msim_rtl_vhdl.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vcom -work work /home/user4/spring07/jmg2048/final_project/board_mem.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity board_mem
# -- Compiling architecture syn of board_mem
# vcom -work work /home/user4/spring07/jmg2048/final_project/final_project.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity final_project
# -- Compiling architecture datapath of final_project
# vcom -work work /home/user4/spring07/jmg2048/final_project/video_display.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity vga_raster
# -- Compiling architecture rtl of vga_raster
# 
# vcom -work work /home/user4/spring07/jmg2048/final_project/../sim/tb.vhd
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity tb
# -- Compiling architecture behav of tb
# 
# vsim -t 1ps -L lpm -L altera -L altera_mf -L sgate -L cycloneii -L work tb
# vsim -L lpm -L altera -L altera_mf -L sgate -L cycloneii -L work -t 1ps tb 
# //  ModelSim ALTERA 6.1g Aug 12 2006 Linux 2.6.9-42.0.2.ELsmp
# //
# //  Copyright 2006 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../std.standard
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../ieee.std_logic_1164(body)
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../ieee.std_logic_arith(body)
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../ieee.std_logic_unsigned(body)
# Loading rtl_work.tb(behav)
# Loading rtl_work.board_mem(syn)
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../std.textio(body)
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../altera/vhdl/altera_mf.altera_common_conversion(body)
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../altera/vhdl/altera_mf.altera_device_families(body)
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../altera/vhdl/altera_mf.altsyncram(translated)
# Loading /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../ieee.numeric_std(body)
# Loading rtl_work.vga_raster(rtl)
# 
# add wave *
# view structure
# .main_pane.workspace
# view signals
# .main_pane.signals.interior.cs
# run 90 sec
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tb/v1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tb/v1
# ** Error: (vsim-7) Failed to open VHDL file "final_project.mif" in r mode.
# No such file or directory. (errno = ENOENT)
#    Time: 0 ps  Iteration: 0  Instance: /tb/v1/nextram/altsyncram_component
# ** Fatal: (vsim-7) Failed to open VHDL file "final_project.mif" in r mode.
# No such file or directory. (errno = ENOENT)
#    Time: 0 ps  Iteration: 0  Process: /tb/v1/nextram/altsyncram_component/memory File: /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../altera/vhdl/src/altera_mf/altera_mf.vhd
# Fatal error at /work/tools4/altera/6.1/modelsim_ae/modeltech/linuxaloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 33486
# 
