library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- This is to test the video generator on the board and make sure we see the 
-- right stuff on the screen.

entity video_generator_tester_board is
port(
	CLOCK_50 	: in std_logic;
	KEY 	: in std_logic_vector (3 downto 0);
	
	-- Signals for the vga chip
	VGA_CLK,
	VGA_HS : OUT STD_LOGIC;
	VGA_VS : OUT STD_LOGIC;
	VGA_BLANK : OUT STD_LOGIC;
	VGA_SYNC : OUT STD_LOGIC;
	VGA_R : OUT unsigned (9 DOWNTO 0);
	VGA_G : OUT unsigned  (9 DOWNTO 0);
	VGA_B : OUT unsigned  (9 DOWNTO 0)
);
end video_generator_tester_board;

architecture test of video_generator_tester_board is
	signal reset : std_logic;
	
	signal color : std_logic_vector(17 downto 0);
	
	-- outputs
	signal column		:unsigned (8 downto 0);
	signal start_screen :std_logic;
	signal start_row	:std_logic;

begin
	reset <= not KEY(0);
	
	video_generator_instance: entity work.video_generator port map (
		clock => CLOCK_50,
		reset => reset,

		color => color,
		col_to_read => column,

		start_row => start_row,
		start_screen => start_screen,

		vga_clock => vga_clk,
		vga_h_sync => vga_hs,
		vga_v_sync => vga_vs,
		vga_blank => vga_blank,
		vga_sync => vga_sync,
		vga_r => vga_r,
		vga_g => vga_g,
		vga_b => vga_b
	);
	
	process (CLOCK_50)
	begin
		if rising_edge(CLOCK_50) then
			if column = 0 then
				color <= (others => '1');
			elsif column >= 1 and column <= 46 then
				color <= "111111111111111111";
			elsif column >= 47 and column <= 91 then
				color <= "111111111111000000";
			elsif column >= 92 and column <= 137 then
				color <= "000000111111111111";
			elsif column >= 138 and column <= 183 then
				color <= "000000111111000000";
			elsif column >= 184 and column <= 228 then
				color <= "111111000000111111";
			elsif column >= 229 and column <= 274 then
				color <= "111111000000000000";
			elsif column >= 275 and column <= 318 then
				color <= "000000000000111111";
			elsif column = 319 then
				color <= (others => '1');
			else
				color <= (others => '0');
			end if;
		end if;
	end process;

end test;