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--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ray_tracer_avalon_module_inst is 
        port (
              -- inputs:
                 signal address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
                 signal chipselect : IN STD_LOGIC;
                 signal clock : IN STD_LOGIC;
                 signal debug_address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
                 signal read : IN STD_LOGIC;
                 signal reset : IN STD_LOGIC;
                 signal write : IN STD_LOGIC;
                 signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

              -- outputs:
                 signal debug_data : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
                 signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal vga_b : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                 signal vga_blank : OUT STD_LOGIC;
                 signal vga_clock : OUT STD_LOGIC;
                 signal vga_g : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                 signal vga_h_sync : OUT STD_LOGIC;
                 signal vga_r : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                 signal vga_sync : OUT STD_LOGIC;
                 signal vga_v_sync : OUT STD_LOGIC
              );
end entity ray_tracer_avalon_module_inst;


architecture europa of ray_tracer_avalon_module_inst is
component ray_tracer_avalon_module is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
                    signal chipselect : IN STD_LOGIC;
                    signal clock : IN STD_LOGIC;
                    signal debug_address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
                    signal read : IN STD_LOGIC;
                    signal reset : IN STD_LOGIC;
                    signal write : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

                 -- outputs:
                    signal debug_data : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
                    signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal vga_b : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                    signal vga_blank : OUT STD_LOGIC;
                    signal vga_clock : OUT STD_LOGIC;
                    signal vga_g : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                    signal vga_h_sync : OUT STD_LOGIC;
                    signal vga_r : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
                    signal vga_sync : OUT STD_LOGIC;
                    signal vga_v_sync : OUT STD_LOGIC
                 );
end component ray_tracer_avalon_module;

                signal internal_debug_data :  STD_LOGIC_VECTOR (8 DOWNTO 0);
                signal internal_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                signal internal_vga_b :  STD_LOGIC_VECTOR (9 DOWNTO 0);
                signal internal_vga_blank :  STD_LOGIC;
                signal internal_vga_clock :  STD_LOGIC;
                signal internal_vga_g :  STD_LOGIC_VECTOR (9 DOWNTO 0);
                signal internal_vga_h_sync :  STD_LOGIC;
                signal internal_vga_r :  STD_LOGIC_VECTOR (9 DOWNTO 0);
                signal internal_vga_sync :  STD_LOGIC;
                signal internal_vga_v_sync :  STD_LOGIC;

begin

  --the_ray_tracer_avalon_module, which is an e_instance
  the_ray_tracer_avalon_module : ray_tracer_avalon_module
    port map(
      debug_data => internal_debug_data,
      readdata => internal_readdata,
      vga_b => internal_vga_b,
      vga_blank => internal_vga_blank,
      vga_clock => internal_vga_clock,
      vga_g => internal_vga_g,
      vga_h_sync => internal_vga_h_sync,
      vga_r => internal_vga_r,
      vga_sync => internal_vga_sync,
      vga_v_sync => internal_vga_v_sync,
      address => address,
      chipselect => chipselect,
      clock => clock,
      debug_address => debug_address,
      read => read,
      reset => reset,
      write => write,
      writedata => writedata
    );


  --vhdl renameroo for output signals
  debug_data <= internal_debug_data;
  --vhdl renameroo for output signals
  readdata <= internal_readdata;
  --vhdl renameroo for output signals
  vga_b <= internal_vga_b;
  --vhdl renameroo for output signals
  vga_blank <= internal_vga_blank;
  --vhdl renameroo for output signals
  vga_clock <= internal_vga_clock;
  --vhdl renameroo for output signals
  vga_g <= internal_vga_g;
  --vhdl renameroo for output signals
  vga_h_sync <= internal_vga_h_sync;
  --vhdl renameroo for output signals
  vga_r <= internal_vga_r;
  --vhdl renameroo for output signals
  vga_sync <= internal_vga_sync;
  --vhdl renameroo for output signals
  vga_v_sync <= internal_vga_v_sync;

end europa;

