library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ray_tracer_renderer_tester is
end ray_tracer_renderer_tester;

architecture test of ray_tracer_renderer_tester is
	signal clock : std_logic := '0';
	signal reset : std_logic := '0';
	
	signal camera_x,
	camera_y,
	camera_z : unsigned (8 downto 0);
	
	signal rect_memory_address : unsigned (7 downto 0) := (others => '0');
	signal rect_memory_data : unsigned (8 downto 0) := (others => '0');

	signal vga_clock,
	vga_h_sync,
	vga_v_sync,
	vga_blank,
	vga_sync : std_logic;
	signal vga_r,
	vga_g,
	vga_b : unsigned(9 downto 0);
	
begin
	process
	begin
		loop
			wait for 10 ns;
			clock <= '1';
			wait for 10 ns;
			clock <= '0';
		end loop;
	end process;
	
	process (rect_memory_address)
	begin
		if rect_memory_address = x"00" then
			rect_memory_data <= "000000000";
		elsif rect_memory_address = x"01" then
			rect_memory_data <= "000000001";
		elsif rect_memory_address = x"02" then
			rect_memory_data <= "000000010";
		elsif rect_memory_address = x"03" then
			rect_memory_data <= "000000011";
		elsif rect_memory_address = x"04" then
			rect_memory_data <= "000000100";
		elsif rect_memory_address = x"05" then
			rect_memory_data <= "000000101";
		elsif rect_memory_address = x"06" then
			rect_memory_data <= "000000110";
		elsif rect_memory_address = x"07" then
			rect_memory_data <= "000000111";
		elsif rect_memory_address = x"08" then
			rect_memory_data <= "000001000";
		elsif rect_memory_address = x"09" then
			rect_memory_data <= "000001001";
		elsif rect_memory_address = x"0a" then
			rect_memory_data <= "000001010";
		elsif rect_memory_address = x"0b" then
			rect_memory_data <= "000001011";
		elsif rect_memory_address = x"0c" then
			rect_memory_data <= "000001100";
		elsif rect_memory_address = x"0d" then
			rect_memory_data <= "000001101";
		else
			report "Illegal rect memory access." severity error;
			rect_memory_data <= "011111111";
		end if;
	end process;
	
	renderer : entity work.ray_tracer_renderer
    port map (
		clock => clock,
		reset => reset,
		camera_x => "000000000",
		camera_y => "000000000",
		camera_z => "000000000",
		rect_memory_address => rect_memory_address,
		rect_memory_data => rect_memory_data,
		vga_clock => vga_clock,
		vga_h_sync => vga_h_sync,
		vga_v_sync => vga_v_sync,
		vga_blank => vga_blank,
		vga_sync => vga_sync,
		vga_r => vga_r,
		vga_g => vga_g,
		vga_b => vga_b
	);
	
	process
	begin
		reset <= '1';
		wait for 20 ns;
		reset <= '0';
		wait for 20 ns;
		
		wait for 20 ms;
		report "Don't worry, it's just the end of the simulation." severity failure;
	end process;
end test;
