-- The entire project. We will build this as the top level thing to put on the fpga.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ray_tracer_project is
	port (
		signal CLOCK_50 : IN STD_LOGIC;
		--signal reset_n : IN STD_LOGIC;

		signal SRAM_ADDR : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
		signal SRAM_DQ :  INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
		signal SRAM_CE_N : OUT STD_LOGIC;
		signal SRAM_LB_N : OUT STD_LOGIC;
		signal SRAM_OE_N : OUT STD_LOGIC;
		signal SRAM_UB_N : OUT STD_LOGIC;
		signal SRAM_WE_N : OUT STD_LOGIC;

		signal VGA_CLK : OUT STD_LOGIC;
		signal VGA_HS : OUT STD_LOGIC;
		signal VGA_VS : OUT STD_LOGIC;
		signal VGA_BLANK : OUT STD_LOGIC;
		signal VGA_SYNC : OUT STD_LOGIC;
		signal VGA_R : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		signal VGA_G : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		signal VGA_B : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		signal SW : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
		signal LEDR : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
		
		signal PS2_CLK : INOUT STD_LOGIC;
		signal PS2_DAT : INOUT STD_LOGIC
	);
end entity ray_tracer_project;

architecture rtl of ray_tracer_project is
	signal rect_memory_address : unsigned (7 downto 0) := (others => '0');
	signal screen_col_color : std_logic_vector (17 downto 0);
	signal done : std_logic := '0';
begin
	
	core: entity work.ray_tracer_system port map (
		clk => CLOCK_50,
		reset_n => '1', --KEY0,

		SRAM_ADDR_from_the_de2_sram_controller_inst => SRAM_ADDR,
		SRAM_CE_N_from_the_de2_sram_controller_inst => SRAM_CE_N,
		SRAM_DQ_to_and_from_the_de2_sram_controller_inst => SRAM_DQ,
		SRAM_LB_N_from_the_de2_sram_controller_inst => SRAM_LB_N,
		SRAM_OE_N_from_the_de2_sram_controller_inst => SRAM_OE_N,
		SRAM_UB_N_from_the_de2_sram_controller_inst => SRAM_UB_N,
		SRAM_WE_N_from_the_de2_sram_controller_inst => SRAM_WE_N,

		vga_b_from_the_ray_tracer_avalon_module_inst => VGA_B,
		vga_blank_from_the_ray_tracer_avalon_module_inst => VGA_BLANK,
		vga_clock_from_the_ray_tracer_avalon_module_inst => VGA_CLK,
		vga_g_from_the_ray_tracer_avalon_module_inst => VGA_G,
		vga_h_sync_from_the_ray_tracer_avalon_module_inst => VGA_HS,
		vga_r_from_the_ray_tracer_avalon_module_inst => VGA_R,
		vga_sync_from_the_ray_tracer_avalon_module_inst => VGA_SYNC,
		vga_v_sync_from_the_ray_tracer_avalon_module_inst => VGA_VS,
		debug_address_to_the_ray_tracer_avalon_module_inst => SW(6 downto 0),
		debug_data_from_the_ray_tracer_avalon_module_inst => LEDR(8 downto 0),

		PS2_CLK_to_and_from_the_Altera_UP_Avalon_PS2_inst => PS2_CLK,
		PS2_DAT_to_and_from_the_Altera_UP_Avalon_PS2_inst => PS2_DAT
	);
end rtl;
