library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity divider_tester is
end divider_tester;

architecture test of divider_tester is
	signal clk : std_logic := '0';
	signal reset : std_logic := '0';
	signal numerator : signed(17 downto 0) := (others => '0');
	signal denominator : signed(8 downto 0) := (others => '0');
	signal result : signed(17 downto 0) := (others => '0');
	signal done : std_logic := '0';
begin
	divider_instance: entity work.divider port map (
		clk => clk,
		reset => reset,
		numerator => numerator,
		denominator => denominator,
		result => result,
		done => done
	);

	process
	begin
		loop
			wait for 10 ns;
			clk <= '1';
			wait for 10 ns;
			clk <= '0';
		end loop;
	end process;
	
	process
	begin
		numerator <= "00" & x"0001";
		denominator <= "0" & x"01";
		reset <= '1'; wait for 20 ns;
		reset <= '0'; wait for 400 ns;
		assert result = "00" & x"0001" report "1 / 1 wrong" severity error;
		
		numerator <= "00" & x"0010";
		denominator <= "0" & x"10";
		reset <= '1'; wait for 20 ns;
		reset <= '0'; wait for 400 ns;
		assert result = "00" & x"0001" report "16 / 16 wrong" severity error;

		numerator <= "00" & x"0010";
		denominator <= "0" & x"08";
		reset <= '1'; wait for 20 ns;
		reset <= '0'; wait for 400 ns;
		assert result = "00" & x"0002" report "16 / 8 wrong" severity error;

		numerator <= "00" & x"0010";
		denominator <= "0" & x"03";
		reset <= '1'; wait for 20 ns;
		reset <= '0'; wait for 400 ns;
		assert result = "00" & x"0005" report "16 / 3 wrong" severity error;

		numerator <= "00" & x"0344";
		denominator <= "0" & x"2D";
		reset <= '1'; wait for 20 ns;
		reset <= '0'; wait for 400 ns;
		assert result = "00" & x"0012" report "836 / 45 wrong" severity error;

		report "NONE. End of simulation." severity failure;
	end process;
end test;
