library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pixel_ram_tester is
end pixel_ram_tester;

architecture pr_test of pixel_ram_tester is
	signal clk : std_logic := '0';
	signal we :	std_logic := '0';			-- write enabled
	signal write_a, read_a : unsigned(4 downto 0) := (others => '0');
	signal di :	unsigned(17 downto 0) := (others => '0'); -- data in
	signal do :	unsigned(17 downto 0) := (others => '0'); -- data out
	constant VAL_1 : unsigned(17 downto 0) := "101010001010101001";
	constant VAL_2 : unsigned(17 downto 0) := "110101001000001010";
	constant VAL_3 : unsigned(17 downto 0) := "000101010101001111";
	constant VAL_4 : unsigned(17 downto 0) := "111111111000000000";
	constant VAL_5 : unsigned(17 downto 0) := "000101010101111101";
begin
	process
	begin
		loop
			wait for 10 ns;
			clk <= '1';
			wait for 10 ns;
			clk <= '0';
		end loop;
	end process;
	
	pixel_ram_instance : entity work.pixel_ram port map (
		clk => clk,
		we => we,
		write_a => write_a,
		read_a => read_a,
		di => di,
		do => do
	);
	
	process
	begin
		write_a <= "00000"; di <= VAL_1; we <= '1';
		wait for 20 ns;
		we <= '0'; read_a <= "00000";
		wait for 20 ns;
		assert do = VAL_1 report "First" severity error;
		write_a <= "00001"; di <= VAL_2; we <= '1';
		wait for 20 ns;
		write_a <= "00010"; di <= VAL_3;
		wait for 20 ns;
		write_a <= "00011"; di <= VAL_4; read_a <= "00010";
		wait for 20 ns;
		we <= '0';
		assert do = VAL_3 report "Second" severity error;
		read_a <= "00000";
		wait for 20 ns;
		assert do = VAL_1 report "Third" severity error;
		report "NONE. End of simulation." severity failure;
	end process;
end pr_test;