library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pixel_ram is
	port (
		clk : in std_logic := '0';
		we : in std_logic := '0'; -- write enabled
		write_a, read_a : in unsigned(4 downto 0) := (others => '0');
		di : in unsigned(17 downto 0) := (others => '0'); -- data in
		do : out unsigned(17 downto 0) := (others => '0') -- data out
	);
end pixel_ram;

architecture rtl of pixel_ram is
	type ram_type is array (31 downto 0) of unsigned(17 downto 0);
	signal RAM : ram_type := (others => "000000000000000000");
	signal read_a_s : unsigned(4 downto 0) := (others => '0');
begin
	process (clk)
	begin
		if clk = '1' then
			if we = '1' then
				RAM(to_integer(write_a)) <= di;
			end if;
			read_a_s <= read_a;
		end if;
	end process;
	
	do <= RAM(to_integer(read_a_s));
end rtl;