# do simulate_buffer_line_generator_tester.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Modifying modelsim.ini
# 
# vcom -93 -work work {divider.vhd}
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity divider
# -- Compiling architecture rtl of divider
# 
# vcom -93 -work work {core_math.vhd}
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity core_math
# -- Compiling architecture math of core_math
# -- Loading entity divider
# 
# vcom -93 -work work {pixel_ram.vhd}
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity pixel_ram
# -- Compiling architecture rtl of pixel_ram
# 
# vcom -93 -work work {ray_unit.vhd}
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity ray_unit
# -- Compiling architecture unit of ray_unit
# -- Loading entity core_math
# 
# vcom -93 -work work {buffered_line_generator.vhd}
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity buffered_line_generator
# -- Compiling architecture caster of buffered_line_generator
# -- Loading entity ray_unit
# -- Loading entity pixel_ram
# 
# vcom -93 -work work {buffered_line_generator_tester.vhd}
# Model Technology ModelSim ALTERA vcom 6.1g Compiler 2006.08 Aug 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity buffered_line_generator_tester
# -- Compiling architecture test of buffered_line_generator_tester
# -- Loading entity buffered_line_generator
# 
# vsim -t 1ps -L lpm -L altera -L altera_mf -L sgate -L cycloneii -L rtl_work -L work buffered_line_generator_tester
# vsim -L lpm -L altera -L altera_mf -L sgate -L cycloneii -L rtl_work -L work -t 1ps buffered_line_generator_tester 
# //  ModelSim ALTERA 6.1g Aug 12 2006 Linux 2.6.9-42.0.3.ELsmp
# //
# //  Copyright 2006 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading /opt/e4840/altera7.2/modelsim_ae/linuxaloem/../std.standard
# Loading /opt/e4840/altera7.2/modelsim_ae/linuxaloem/../ieee.std_logic_1164(body)
# Loading /opt/e4840/altera7.2/modelsim_ae/linuxaloem/../ieee.numeric_std(body)
# Loading rtl_work.buffered_line_generator_tester(test)
# Loading rtl_work.buffered_line_generator(caster)
# Loading rtl_work.ray_unit(unit)
# Loading rtl_work.core_math(math)
# Loading rtl_work.divider(rtl)
# Loading rtl_work.pixel_ram(rtl)
# 
# add wave *
# view structure
# .main_pane.workspace
# view signals
# .main_pane.signals.interior.cs
run -all
# ** Failure: Don't worry, it's just the end of the simulation.
#    Time: 14144310 ns  Iteration: 2  Process: /buffered_line_generator_tester/line__144 File: buffered_line_generator_tester.vhd
# Break at buffered_line_generator_tester.vhd line 15084
