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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity xy_pos is 
        port (
              -- inputs:
                 signal address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
                 signal chipselect : IN STD_LOGIC;
                 signal clk50 : IN STD_LOGIC;
                 signal h_pos : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal read : IN STD_LOGIC;
                 signal read_data : IN STD_LOGIC_VECTOR (29 DOWNTO 0);
                 signal reset_n : IN STD_LOGIC;
                 signal v_pos : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal write : IN STD_LOGIC;
                 signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

              -- outputs:
                 signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
              );
end entity xy_pos;


architecture europa of xy_pos is
component xy_detector is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
                    signal chipselect : IN STD_LOGIC;
                    signal clk50 : IN STD_LOGIC;
                    signal h_pos : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal read : IN STD_LOGIC;
                    signal read_data : IN STD_LOGIC_VECTOR (29 DOWNTO 0);
                    signal reset_n : IN STD_LOGIC;
                    signal v_pos : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal write : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

                 -- outputs:
                    signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
                 );
end component xy_detector;

                signal internal_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);

begin

  --the_xy_detector, which is an e_instance
  the_xy_detector : xy_detector
    port map(
      readdata => internal_readdata,
      address => address,
      chipselect => chipselect,
      clk50 => clk50,
      h_pos => h_pos,
      read => read,
      read_data => read_data,
      reset_n => reset_n,
      v_pos => v_pos,
      write => write,
      writedata => writedata
    );


  --vhdl renameroo for output signals
  readdata <= internal_readdata;

end europa;

