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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity isp1362 is 
        port (
              -- inputs:
                 signal OTG_INT0 : IN STD_LOGIC;
                 signal OTG_INT1 : IN STD_LOGIC;
                 signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal chipselect_n : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal read_n : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal write_n : IN STD_LOGIC;
                 signal write_n_avalon_slave_1 : IN STD_LOGIC;
                 signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal writedata_avalon_slave_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

              -- outputs:
                 signal OTG_ADDR : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal OTG_CS_N : OUT STD_LOGIC;
                 signal OTG_DACK0_N : OUT STD_LOGIC;
                 signal OTG_DACK1_N : OUT STD_LOGIC;
                 signal OTG_DATA : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal OTG_FSPEED : OUT STD_LOGIC;
                 signal OTG_LSPEED : OUT STD_LOGIC;
                 signal OTG_RD_N : OUT STD_LOGIC;
                 signal OTG_RST_N : OUT STD_LOGIC;
                 signal OTG_WR_N : OUT STD_LOGIC;
                 signal irq_n : OUT STD_LOGIC;
                 signal irq_n_avalon_slave_1 : OUT STD_LOGIC;
                 signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
              );
end entity isp1362;


architecture europa of isp1362 is
component isp1362_ctrl is 
           port (
                 -- inputs:
                    signal OTG_INT0 : IN STD_LOGIC;
                    signal OTG_INT1 : IN STD_LOGIC;
                    signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal chipselect_n : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal read_n : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal write_n : IN STD_LOGIC;
                    signal write_n_avalon_slave_1 : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal writedata_avalon_slave_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                 -- outputs:
                    signal OTG_ADDR : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal OTG_CS_N : OUT STD_LOGIC;
                    signal OTG_DACK0_N : OUT STD_LOGIC;
                    signal OTG_DACK1_N : OUT STD_LOGIC;
                    signal OTG_DATA : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal OTG_FSPEED : OUT STD_LOGIC;
                    signal OTG_LSPEED : OUT STD_LOGIC;
                    signal OTG_RD_N : OUT STD_LOGIC;
                    signal OTG_RST_N : OUT STD_LOGIC;
                    signal OTG_WR_N : OUT STD_LOGIC;
                    signal irq_n : OUT STD_LOGIC;
                    signal irq_n_avalon_slave_1 : OUT STD_LOGIC;
                    signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
                 );
end component isp1362_ctrl;

                signal internal_OTG_ADDR :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_OTG_CS_N :  STD_LOGIC;
                signal internal_OTG_DACK0_N :  STD_LOGIC;
                signal internal_OTG_DACK1_N :  STD_LOGIC;
                signal internal_OTG_FSPEED :  STD_LOGIC;
                signal internal_OTG_LSPEED :  STD_LOGIC;
                signal internal_OTG_RD_N :  STD_LOGIC;
                signal internal_OTG_RST_N :  STD_LOGIC;
                signal internal_OTG_WR_N :  STD_LOGIC;
                signal internal_irq_n :  STD_LOGIC;
                signal internal_irq_n_avalon_slave_1 :  STD_LOGIC;
                signal internal_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);

begin

  --the_isp1362_ctrl, which is an e_instance
  the_isp1362_ctrl : isp1362_ctrl
    port map(
      OTG_ADDR => internal_OTG_ADDR,
      OTG_CS_N => internal_OTG_CS_N,
      OTG_DACK0_N => internal_OTG_DACK0_N,
      OTG_DACK1_N => internal_OTG_DACK1_N,
      OTG_DATA => OTG_DATA,
      OTG_FSPEED => internal_OTG_FSPEED,
      OTG_LSPEED => internal_OTG_LSPEED,
      OTG_RD_N => internal_OTG_RD_N,
      OTG_RST_N => internal_OTG_RST_N,
      OTG_WR_N => internal_OTG_WR_N,
      irq_n => internal_irq_n,
      irq_n_avalon_slave_1 => internal_irq_n_avalon_slave_1,
      readdata => internal_readdata,
      OTG_INT0 => OTG_INT0,
      OTG_INT1 => OTG_INT1,
      address => address,
      chipselect_n => chipselect_n,
      clk => clk,
      read_n => read_n,
      reset_n => reset_n,
      write_n => write_n,
      write_n_avalon_slave_1 => write_n_avalon_slave_1,
      writedata => writedata,
      writedata_avalon_slave_1 => writedata_avalon_slave_1
    );


  --vhdl renameroo for output signals
  OTG_ADDR <= internal_OTG_ADDR;
  --vhdl renameroo for output signals
  OTG_CS_N <= internal_OTG_CS_N;
  --vhdl renameroo for output signals
  OTG_DACK0_N <= internal_OTG_DACK0_N;
  --vhdl renameroo for output signals
  OTG_DACK1_N <= internal_OTG_DACK1_N;
  --vhdl renameroo for output signals
  OTG_FSPEED <= internal_OTG_FSPEED;
  --vhdl renameroo for output signals
  OTG_LSPEED <= internal_OTG_LSPEED;
  --vhdl renameroo for output signals
  OTG_RD_N <= internal_OTG_RD_N;
  --vhdl renameroo for output signals
  OTG_RST_N <= internal_OTG_RST_N;
  --vhdl renameroo for output signals
  OTG_WR_N <= internal_OTG_WR_N;
  --vhdl renameroo for output signals
  irq_n <= internal_irq_n;
  --vhdl renameroo for output signals
  irq_n_avalon_slave_1 <= internal_irq_n_avalon_slave_1;
  --vhdl renameroo for output signals
  readdata <= internal_readdata;

end europa;

