library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity line_buffer is
  port (
    reset	  : in std_logic;
    wclk	  : in std_logic;
    rclk	  : in std_logic;
    write_enable  : in std_logic;
	rgb : in std_logic_vector(29 downto 0);
    write_address : in unsigned(15 downto 0);
    read_data	  : out std_logic_vector(29 downto 0);
    read_address  : in unsigned(15 downto 0);
    -- page = 0: write to line1, read from line2
    -- page = 1: write to line2, read from line1
    page          : in std_logic
  );
end line_buffer;

architecture RTL of line_buffer is

  type ram_type is array(0 to 800) of std_logic_vector(29 downto 0);

  signal line1: ram_type;
  signal line2: ram_type;

begin

  WriteLine : process (wclk)
  begin
    if rising_edge(wclk) then
      if write_enable = '1' then
        if page = '0' then
          line1(to_integer(write_address)) <= rgb;
        else
          line2(to_integer(write_address)) <= rgb;
        end if;
      end if;
    end if;
  end process;

  ReadLine : process (rclk)
  begin
    if rising_edge(rclk) then
      if page = '0' then
        read_data <= line2(to_integer(write_address));
      else
        read_data <= line1(to_integer(write_address));
      end if;
    end if;
  end process;

end RTL;
