library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity usb is

port (
    CLOCK_27 : in std_logic;                                      -- 27 MHz
	signal CLOCK_50 : in std_logic; --50 MHz
	signal LEDR : out std_logic_vector(17 downto 0); --LEDs

	
	SRAM_DQ : inout std_logic_vector(15 downto 0);
	SRAM_ADDR : out std_logic_vector(17 downto 0);
	SRAM_UB_N, --Highbyte Data Mask
	SRAM_LB_N, --Lowbyte Data Mask
	SRAM_WE_N, --Write Enable
	SRAM_CE_N, --Chip Enable
	SRAM_OE_N : out std_logic; --Output Enable

    KEY : in std_logic_vector(3 downto 0);         -- Push buttons

   	OTG_ADDR: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
        OTG_CS_N: OUT STD_LOGIC;
        OTG_DACK0_N: OUT STD_LOGIC;
        OTG_DACK1_N: OUT STD_LOGIC;
        OTG_DATA: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
        OTG_FSPEED: OUT STD_LOGIC;
        OTG_INT0: IN STD_LOGIC;
        OTG_INT1: IN STD_LOGIC;
        OTG_LSPEED: OUT STD_LOGIC;
        OTG_RD_N: OUT STD_LOGIC;
        OTG_RST_N: OUT STD_LOGIC;
        OTG_WR_N: OUT STD_LOGIC;


    -- I2C bus
    
    I2C_SDAT : inout std_logic; -- I2C Data
    I2C_SCLK : out std_logic;   -- I2C Clock    
    
    -- Video Decoder
    
    TD_DATA : in std_logic_vector(7 downto 0);  -- Data bus 8 bits
    TD_HS,                                      -- H_SYNC
    TD_VS : in std_logic;                       -- V_SYNC
    TD_RESET : out std_logic;                   -- Reset    
        
    -- VGA output
    
    VGA_CLK,                                            -- Clock
    VGA_HS,                                             -- H_SYNC
    VGA_VS,                                             -- V_SYNC
    VGA_BLANK,                                          -- BLANK
    VGA_SYNC : out std_logic;                           -- SYNC
    VGA_R,                                              -- Red[9:0]
    VGA_G,                                              -- Green[9:0]
    VGA_B : out unsigned(9 downto 0)	                -- Blue[9:0]
);
end usb;
architecture rtl of usb is
	

	component I2C_AV_Config is
		port (
			iCLK : in std_logic;
			iRST_N : in std_logic;
			I2C_SCLK : out std_logic;
			I2C_SDAT : inout std_logic
		);
	end component;
	
	signal r_sig, g_sig, b_sig : unsigned(9 downto 0);
	signal counter : unsigned(15 downto 0);
	signal reset_n : std_logic := '0';
	signal clk25: std_logic := '0';
	signal hc_sig: unsigned(15 downto 0);
	signal vc_sig: unsigned(15 downto 0);
	
begin
	--LEDR(17) <= OTG_ADDR(1);
	--LEDR(16) <= OTG_ADDR(0);
	
  TD_RESET <= KEY(0);

  V1: entity work.ntsc2vga port map (
    reset => '0',
	clk25 => clk25,
    clk27 => CLOCK_27,
	clk50 => CLOCK_50,
	td_data => TD_DATA,
	td_hs => TD_HS,
	td_vs => TD_VS,
    VGA_CLK => VGA_CLK,
    VGA_HS => VGA_HS,
    VGA_VS => VGA_VS,
    VGA_BLANK => VGA_BLANK,
    VGA_SYNC => VGA_SYNC,
    VGA_R => r_sig,
    VGA_G => g_sig,
    VGA_B => b_sig,
	hcount => hc_sig,
	vcount => vc_sig
  );
  
  i2c: I2C_AV_Config port map(
	iCLK => CLOCK_50,
	iRST_N => KEY(2),
	I2C_SCLK => I2C_SCLK,
	I2C_SDAT => I2C_SDAT
	);
	
process (CLOCK_50)
begin
	if rising_edge(CLOCK_50) then
	  if counter = x"ffff" then
		reset_n <= '1';
	  else
		reset_n <= '0';
		counter <= counter + 1;
	  end if;
	end if;
end process;

nios : entity work.nios_system port map (
			clk => CLOCK_50,
			reset_n => reset_n,
			--leds_from_the_leds => LEDR(15 downto 0),
			SRAM_ADDR_from_the_sram => SRAM_ADDR,
			SRAM_CE_N_from_the_sram => SRAM_CE_N,
			SRAM_DQ_to_and_from_the_sram => SRAM_DQ,
			SRAM_LB_N_from_the_sram => SRAM_LB_N,
			SRAM_OE_N_from_the_sram => SRAM_OE_N,
			SRAM_UB_N_from_the_sram => SRAM_UB_N,
			SRAM_WE_N_from_the_sram => SRAM_WE_N,

                 	-- the_isp1362_ctrl_inst
                    	OTG_ADDR_from_the_isp1362 => OTG_ADDR,						
                    	OTG_CS_N_from_the_isp1362=> OTG_CS_N,
                    	OTG_DACK0_N_from_the_isp1362 => OTG_DACK0_N,
                    	OTG_DACK1_N_from_the_isp1362 => OTG_DACK1_N,
                    	OTG_DATA_to_and_from_the_isp1362 => OTG_DATA,
                    	OTG_FSPEED_from_the_isp1362 => OTG_FSPEED,
                    	OTG_INT0_to_the_isp1362 => OTG_INT0,
                    	OTG_INT1_to_the_isp1362 => OTG_INT1,
                    	OTG_LSPEED_from_the_isp1362 => OTG_LSPEED,
                    	OTG_RD_N_from_the_isp1362 => OTG_RD_N,
                    	OTG_RST_N_from_the_isp1362 => OTG_RST_N,
                    	OTG_WR_N_from_the_isp1362 => OTG_WR_N,

						h_pos_to_the_xy_pos => std_logic_vector(hc_sig),
						read_data_to_the_xy_pos => std_logic_vector(r_sig & g_sig & b_sig),
						v_pos_to_the_xy_pos => std_logic_vector(vc_sig)

);

VGA_R <= r_sig;
VGA_G <= g_sig;
VGA_B <= b_sig;

end rtl;
