//Legal Notice: (C)2007 Altera Corporation. All rights reserved.  Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.

// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module vga (
             // inputs:
              address,
              avm_read_master_readdata,
              avm_read_master_waitrequest,
              chipselect,
              clk,
              reset,
              write,
              writedata,

             // outputs:
              VGA_B,
              VGA_BLANK,
              VGA_CLK,
              VGA_G,
              VGA_HS,
              VGA_R,
              VGA_SYNC,
              VGA_VS,
              avm_read_master_address,
              avm_read_master_read
           )
;

  output  [  9: 0] VGA_B;
  output           VGA_BLANK;
  output           VGA_CLK;
  output  [  9: 0] VGA_G;
  output           VGA_HS;
  output  [  9: 0] VGA_R;
  output           VGA_SYNC;
  output           VGA_VS;
  output  [ 31: 0] avm_read_master_address;
  output           avm_read_master_read;
  input            address;
  input   [ 31: 0] avm_read_master_readdata;
  input            avm_read_master_waitrequest;
  input            chipselect;
  input            clk;
  input            reset;
  input            write;
  input   [ 31: 0] writedata;

  wire    [  9: 0] VGA_B;
  wire             VGA_BLANK;
  wire             VGA_CLK;
  wire    [  9: 0] VGA_G;
  wire             VGA_HS;
  wire    [  9: 0] VGA_R;
  wire             VGA_SYNC;
  wire             VGA_VS;
  wire    [ 31: 0] avm_read_master_address;
  wire             avm_read_master_read;
  de2_vga_raster the_de2_vga_raster
    (
      .VGA_B                       (VGA_B),
      .VGA_BLANK                   (VGA_BLANK),
      .VGA_CLK                     (VGA_CLK),
      .VGA_G                       (VGA_G),
      .VGA_HS                      (VGA_HS),
      .VGA_R                       (VGA_R),
      .VGA_SYNC                    (VGA_SYNC),
      .VGA_VS                      (VGA_VS),
      .address                     (address),
      .avm_read_master_address     (avm_read_master_address),
      .avm_read_master_read        (avm_read_master_read),
      .avm_read_master_readdata    (avm_read_master_readdata),
      .avm_read_master_waitrequest (avm_read_master_waitrequest),
      .chipselect                  (chipselect),
      .clk                         (clk),
      .reset                       (reset),
      .write                       (write),
      .writedata                   (writedata)
    );


endmodule

