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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity irComp2_inst is 
        port (
              -- inputs:
                 signal address : IN STD_LOGIC;
                 signal chipselect : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal read : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal write : IN STD_LOGIC;
                 signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

              -- outputs:
                 signal GPIO_1 : INOUT STD_LOGIC_VECTOR (35 DOWNTO 0);
                 signal HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
                 signal hex0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
                 signal irq : OUT STD_LOGIC;
                 signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
              );
end entity irComp2_inst;


architecture europa of irComp2_inst is
component irComp2 is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC;
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal read : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal write : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

                 -- outputs:
                    signal GPIO_1 : INOUT STD_LOGIC_VECTOR (35 DOWNTO 0);
                    signal HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
                    signal hex0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
                    signal irq : OUT STD_LOGIC;
                    signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
                 );
end component irComp2;

                signal internal_HEX2 :  STD_LOGIC_VECTOR (6 DOWNTO 0);
                signal internal_hex0 :  STD_LOGIC_VECTOR (6 DOWNTO 0);
                signal internal_irq :  STD_LOGIC;
                signal internal_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);

begin

  --the_irComp2, which is an e_instance
  the_irComp2 : irComp2
    port map(
      GPIO_1 => GPIO_1,
      HEX2 => internal_HEX2,
      hex0 => internal_hex0,
      irq => internal_irq,
      readdata => internal_readdata,
      address => address,
      chipselect => chipselect,
      clk => clk,
      read => read,
      reset_n => reset_n,
      write => write,
      writedata => writedata
    );


  --vhdl renameroo for output signals
  HEX2 <= internal_HEX2;
  --vhdl renameroo for output signals
  hex0 <= internal_hex0;
  --vhdl renameroo for output signals
  irq <= internal_irq;
  --vhdl renameroo for output signals
  readdata <= internal_readdata;

end europa;

