library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer_bugdie is

  port (
  clk : in std_logic;
  output: out unsigned (1 downto 0)
  );
  end timer_bugdie;

architecture arch of timer_bugdie is
signal count : integer :=0;
begin
process (clk)
begin
if rising_edge(clk) then
        if count <= 5000000 then 
		count <= count+1;
        output <= "00";
        elsif count <= 10000000 then 
		count <= count+1;
        output <= "01";
		else count <=0;
		end if; 
end if;
end process;
end arch;