library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer_ball is

  port (
  clk : in std_logic;
  output: out unsigned (2 downto 0)
  );
  end timer_ball;

architecture arch of timer_ball is
signal count : integer :=0;
begin
	process (clk)
	begin
		if rising_edge(clk) then
				if count <= 5000000 then 
					count <= count+1;
					output <= "000";
				elsif count <= 10000000 then 
					count <= count+1;
					output <= "001";
				elsif count <= 15000000 then 
					count <= count+1;
					output <= "010";
				elsif count <= 20000000 then 
					count <= count+1;
					output <= "011";		
				elsif count <= 25000000 then 
					count <= count+1;
					output <= "100";
					count <=0;
				end if;
		end if;
	end process;
end arch;