/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * /home/user4/spring12/jl3784/Desktop/lab3/nios_system.ptf
 *
 * Generated: 2012-05-10 12:00:27.159
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "nios_system"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONEII"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x001a1040
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x001a1040
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x001a1040
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 50000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "tiny"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x00080020
#define NIOS2_RESET_ADDR 0x00080000
#define NIOS2_BREAK_ADDR 0x001a0820

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __DE2_SRAM_CONTROLLER
#define __DE2_LED_FLASHER
#define __ALTERA_AVALON_JTAG_UART
#define __DE2_VGA_RASTER
#define __IRCOMP2
#define __IRCOMP
#define __DE2_WM8731_AUDIO

/*
 * sram configuration
 *
 */

#define SRAM_NAME "/dev/sram"
#define SRAM_TYPE "de2_sram_controller"
#define SRAM_BASE 0x00080000
#define SRAM_SPAN 524288
#define ALT_MODULE_CLASS_sram de2_sram_controller

/*
 * leds configuration
 *
 */

#define LEDS_NAME "/dev/leds"
#define LEDS_TYPE "de2_led_flasher"
#define LEDS_BASE 0x001a1000
#define LEDS_SPAN 64
#define ALT_MODULE_CLASS_leds de2_led_flasher

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x001a1040
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 0
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart

/*
 * vga configuration
 *
 */

#define VGA_NAME "/dev/vga"
#define VGA_TYPE "de2_vga_raster"
#define VGA_BASE 0x00100000
#define VGA_SPAN 524288
#define VGA_IRQ 1
#define ALT_MODULE_CLASS_vga de2_vga_raster

/*
 * irComp2_inst configuration
 *
 */

#define IRCOMP2_INST_NAME "/dev/irComp2_inst"
#define IRCOMP2_INST_TYPE "irComp2"
#define IRCOMP2_INST_BASE 0x001a1048
#define IRCOMP2_INST_SPAN 4
#define IRCOMP2_INST_IRQ 2
#define ALT_MODULE_CLASS_irComp2_inst irComp2

/*
 * irComp_inst configuration
 *
 */

#define IRCOMP_INST_NAME "/dev/irComp_inst"
#define IRCOMP_INST_TYPE "irComp"
#define IRCOMP_INST_BASE 0x001a104c
#define IRCOMP_INST_SPAN 4
#define IRCOMP_INST_IRQ 3
#define ALT_MODULE_CLASS_irComp_inst irComp

/*
 * de2_wm8731_audio_inst configuration
 *
 */

#define DE2_WM8731_AUDIO_INST_NAME "/dev/de2_wm8731_audio_inst"
#define DE2_WM8731_AUDIO_INST_TYPE "de2_wm8731_audio"
#define DE2_WM8731_AUDIO_INST_BASE 0x00180000
#define DE2_WM8731_AUDIO_INST_SPAN 131072
#define DE2_WM8731_AUDIO_INST_IRQ 4
#define ALT_MODULE_CLASS_de2_wm8731_audio_inst de2_wm8731_audio

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SRAM
#define ALT_RODATA_DEVICE     SRAM
#define ALT_RWDATA_DEVICE     SRAM
#define ALT_EXCEPTIONS_DEVICE SRAM
#define ALT_RESET_DEVICE      SRAM

/*
 * The text section is initialised so no bootloader will be required.
 * Set a variable to tell crt0.S to provide code at the reset address and
 * to initialise rwdata if appropriate.
 */

#define ALT_NO_BOOTLOADER


#endif /* __SYSTEM_H_ */
