library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timerfordie is

  port (
  reset : in std_logic;
  clk : in std_logic;
  output: out std_logic
  );
  end timerfordie;

architecture arch of timerfordie is
signal count : integer;
begin
process (clk)
begin

	if rising_edge(clk) then
			if reset ='1' then
				count <=0;
			end if;
			if count <= 50000000 then 
				count <= count+1;
				output <= '1';
			else
				output <= '0';
			end if; 
	end if;
end process;
end arch;