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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity uart_bus is 
        port (
              -- inputs:
                 signal address : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal read : IN STD_LOGIC;
                 signal readdata_from_the_uart : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal status_from_the_uart : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

              -- outputs:
                 signal data_to_nios : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal uart_addr : OUT STD_LOGIC
              );
end entity uart_bus;


architecture europa of uart_bus is
component uart_bus_interf is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal read : IN STD_LOGIC;
                    signal readdata_from_the_uart : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal status_from_the_uart : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                 -- outputs:
                    signal data_to_nios : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal uart_addr : OUT STD_LOGIC
                 );
end component uart_bus_interf;

                signal internal_data_to_nios :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal internal_uart_addr :  STD_LOGIC;

begin

  --the_uart_bus_interf, which is an e_instance
  the_uart_bus_interf : uart_bus_interf
    port map(
      data_to_nios => internal_data_to_nios,
      uart_addr => internal_uart_addr,
      address => address,
      clk => clk,
      read => read,
      readdata_from_the_uart => readdata_from_the_uart,
      status_from_the_uart => status_from_the_uart
    );


  --vhdl renameroo for output signals
  data_to_nios <= internal_data_to_nios;
  --vhdl renameroo for output signals
  uart_addr <= internal_uart_addr;

end europa;

