library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sound_Controller is
port (
	-- Avalon:
    clk        : in  std_logic;
    reset_n    : in  std_logic;
    read       : in  std_logic;
    write      : in  std_logic;
    chipselect : in  std_logic;
    address    : in  std_logic_vector(7 downto 0);
    readdata   : out std_logic_vector(7 downto 0);
    writedata  : in  std_logic_vector(7 downto 0);
	-- connection to the component inside:
	 irq : 		OUT STD_LOGIC ;
	AUD_ADCLRCK  : out  std_logic;   --    Audio CODEC ADC LR Clock
	AUD_ADCDAT   : in   std_logic;   --    Audio CODEC ADC Data
	AUD_DACLRCK  : out  std_logic;   --    Audio CODEC DAC LR Clock
	AUD_DACDAT   : out  std_logic;   --    Audio CODEC DAC Data
	AUD_BCLK     : inout std_logic ; --    Audio CODEC Bit-Stream Clock
	AUX_XCK     : out std_logic;  --    Audio CODEC Bit-Stream Clock
	led :			 out std_LOGIC_vector(15 downto 0)
  );
end  sound_Controller;

architecture ar of sound_Controller is
 

 --FSM
 type states is (IDLE,WAITING);
 signal state : states:=IDLE;
 --Audio Interface
 signal audio_clock : unsigned(1 downto 0) := "00";
 signal indata : std_logic_vector (7 downto 0) ;
signal data_to_music : std_logic_vector (15 downto 0);
signal we,inter:std_logic;
 signal audio_request : std_logic;
 signal counter : integer:=0;

	component de2_wm8731_audio is port(
		    clk : in std_logic;       --  Audio CODEC Chip Clock AUD_XCK (18.43 MHz)
    		 reset_n : in std_logic;
		    test_mode : in std_logic;       --    Audio CODEC controller test mode
		    audio_request : out std_logic;  --    Audio controller request new data
		    data : in std_logic_vector(15 downto 0);
  
		    -- Audio interface signals
    		    AUD_ADCLRCK  : out  std_logic;   --    Audio CODEC ADC LR Clock
		    AUD_ADCDAT   : in   std_logic;   --    Audio CODEC ADC Data
		    AUD_DACLRCK  : out  std_logic;   --    Audio CODEC DAC LR Clock
		    AUD_DACDAT   : out  std_logic;   --    Audio CODEC DAC Data
		    AUD_BCLK     : inout std_logic  --    Audio CODEC Bit-Stream Clock
		 
		
		);
	end component de2_wm8731_audio; 

begin
	

  V1: de2_wm8731_audio port map (
    clk => audio_clock(1),
    reset_n => reset_n,
    test_mode => '0',                   -- Don t output a sine wave
    audio_request => audio_request,
    data => data_to_music,
  
    -- Audio interface signals
    AUD_ADCLRCK  => AUD_ADCLRCK,
    AUD_ADCDAT   => AUD_ADCDAT,
    AUD_DACLRCK  => AUD_DACLRCK,
    AUD_DACDAT   => AUD_DACDAT,
    AUD_BCLK     => AUD_BCLK
	 --AUD_DACDAT   => led
  );




--Audio clock generation 
process (clk)
begin
  if rising_edge(clk) then
--	we      <= '1' when chipselect = '1'and write ='1'  else '0' ;
	data_to_music <= indata & x"00"; --Since the audio is on 16 bits, we pad the data with 0s
	--led <= data_to_music;
    audio_clock <= audio_clock + "1";
  end if;
end process;

AUX_XCK<=audio_clock(1);


--FSM next state
--process(clk)
--begin
--	if(rising_edge(clk)) then 
--		if( reset_n='0' )
--		then
--			state <= IDLE;
--		else
--			state <= next_state;				
--		end if;
--	end if;
--end process;


--Combinational process
process (clk)
begin
	--By default reset the interuption signal
	
--	next_state <= state;
if (rising_edge(clk)) then
	
	if reset_n = '0' then
		state <= IDLE;
		irq<= '0';
		led <= "0000000000000000";
	end if;
		
	case state is

	--Waiting for a note request
	when IDLE =>
		led <= "1111100000000000";
		indata <=indata;
		if (audio_request = '1') 	then 
			state <= WAITING;
			irq <= '1';
		else
			irq <='0';
			state <= IDLE;
		end if;


	--A request has come. wait for writing
	when WAITING =>
	led <= "0000000000001111";
		--irq <='0';
		if (write ='1' and chipselect = '1') then 	--chipselect = '1' and write ='1'
			indata <=writedata;
			state <= IDLE;
			irq <= '0';
		else
			--if(counter=1000) then counter<=0;
			--else counter<=counter +1;
			--end if;
			--if(counter=0) then
				state <=WAITING;
				irq<= '1';
			--end if;
		end if;

	when others =>
		irq <= '0';
		state <= IDLE;

	end case;
end if;

end process;



end architecture;
