-- sound_controller_0.vhd

-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity sound_controller_0 is
	port (
		clk         : in    std_logic                     := '0';             --            clock.clk
		reset_n     : in    std_logic                     := '0';             --            reset.reset_n
		read        : in    std_logic                     := '0';             --   avalon_slave_0.read
		write       : in    std_logic                     := '0';             --                 .write
		chipselect  : in    std_logic                     := '0';             --                 .chipselect
		address     : in    std_logic_vector(7 downto 0)  := (others => '0'); --                 .address
		readdata    : out   std_logic_vector(7 downto 0);                     --                 .readdata
		writedata   : in    std_logic_vector(7 downto 0)  := (others => '0'); --                 .writedata
		AUD_BCLK    : inout std_logic                     := '0';             --      conduit_end.export
		AUX_XCK     : out   std_logic;                                        --                 .export
		led         : out   std_logic_vector(15 downto 0);                    --                 .export
		AUD_DACDAT  : out   std_logic;                                        --                 .export
		AUD_DACLRCK : out   std_logic;                                        --                 .export
		AUD_ADCLRCK : out   std_logic;                                        --                 .export
		AUD_ADCDAT  : in    std_logic                     := '0';             --                 .export
		irq         : out   std_logic                                         -- interrupt_sender.irq
	);
end entity sound_controller_0;

architecture rtl of sound_controller_0 is
	component sound_Controller is
		port (
			clk         : in    std_logic                     := 'X';             -- clk
			reset_n     : in    std_logic                     := 'X';             -- reset_n
			read        : in    std_logic                     := 'X';             -- read
			write       : in    std_logic                     := 'X';             -- write
			chipselect  : in    std_logic                     := 'X';             -- chipselect
			address     : in    std_logic_vector(7 downto 0)  := (others => 'X'); -- address
			readdata    : out   std_logic_vector(7 downto 0);                     -- readdata
			writedata   : in    std_logic_vector(7 downto 0)  := (others => 'X'); -- writedata
			AUD_BCLK    : inout std_logic                     := 'X';             -- export
			AUX_XCK     : out   std_logic;                                        -- export
			led         : out   std_logic_vector(15 downto 0);                    -- export
			AUD_DACDAT  : out   std_logic;                                        -- export
			AUD_DACLRCK : out   std_logic;                                        -- export
			AUD_ADCLRCK : out   std_logic;                                        -- export
			AUD_ADCDAT  : in    std_logic                     := 'X';             -- export
			irq         : out   std_logic                                         -- irq
		);
	end component sound_Controller;

begin

	sound_controller_0 : component sound_Controller
		port map (
			clk         => clk,         --            clock.clk
			reset_n     => reset_n,     --            reset.reset_n
			read        => read,        --   avalon_slave_0.read
			write       => write,       --                 .write
			chipselect  => chipselect,  --                 .chipselect
			address     => address,     --                 .address
			readdata    => readdata,    --                 .readdata
			writedata   => writedata,   --                 .writedata
			AUD_BCLK    => AUD_BCLK,    --      conduit_end.export
			AUX_XCK     => AUX_XCK,     --                 .export
			led         => led,         --                 .export
			AUD_DACDAT  => AUD_DACDAT,  --                 .export
			AUD_DACLRCK => AUD_DACLRCK, --                 .export
			AUD_ADCLRCK => AUD_ADCLRCK, --                 .export
			AUD_ADCDAT  => AUD_ADCDAT,  --                 .export
			irq         => irq          -- interrupt_sender.irq
		);

end architecture rtl; -- of sound_controller_0
