-- nes_controller.vhd

-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity nes_controller is
	port (
		clk        : in  std_logic                     := '0';             --          clock.clk
		reset_n    : in  std_logic                     := '0';             --          reset.reset_n
		read       : in  std_logic                     := '0';             -- avalon_slave_0.read
		write      : in  std_logic                     := '0';             --               .write
		chipselect : in  std_logic                     := '0';             --               .chipselect
		address    : in  std_logic_vector(3 downto 0)  := (others => '0'); --               .address
		readdata   : out std_logic_vector(31 downto 0);                    --               .readdata
		writedata  : in  std_logic_vector(31 downto 0) := (others => '0'); --               .writedata
		latch1     : out std_logic;                                        --    conduit_end.export
		data1      : in  std_logic                     := '0';             --               .export
		latch2     : out std_logic;                                        --               .export
		pulse2     : out std_logic;                                        --               .export
		data2      : in  std_logic                     := '0';             --               .export
		pulse1     : out std_logic                                         --               .export
	);
end entity nes_controller;

architecture rtl of nes_controller is
	component de2_nes_controller is
		port (
			clk        : in  std_logic                     := 'X';             -- clk
			reset_n    : in  std_logic                     := 'X';             -- reset_n
			read       : in  std_logic                     := 'X';             -- read
			write      : in  std_logic                     := 'X';             -- write
			chipselect : in  std_logic                     := 'X';             -- chipselect
			address    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- address
			readdata   : out std_logic_vector(31 downto 0);                    -- readdata
			writedata  : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			latch1     : out std_logic;                                        -- export
			data1      : in  std_logic                     := 'X';             -- export
			latch2     : out std_logic;                                        -- export
			pulse2     : out std_logic;                                        -- export
			data2      : in  std_logic                     := 'X';             -- export
			pulse1     : out std_logic                                         -- export
		);
	end component de2_nes_controller;

begin

	nes_controller : component de2_nes_controller
		port map (
			clk        => clk,        --          clock.clk
			reset_n    => reset_n,    --          reset.reset_n
			read       => read,       -- avalon_slave_0.read
			write      => write,      --               .write
			chipselect => chipselect, --               .chipselect
			address    => address,    --               .address
			readdata   => readdata,   --               .readdata
			writedata  => writedata,  --               .writedata
			latch1     => latch1,     --    conduit_end.export
			data1      => data1,      --               .export
			latch2     => latch2,     --               .export
			pulse2     => pulse2,     --               .export
			data2      => data2,      --               .export
			pulse1     => pulse1      --               .export
		);

end architecture rtl; -- of nes_controller
