module ROMdecoder(
input logic clk,
input logic[23:0] charap1,
input logic[23:0] charap2,
input logic[23:0] charap3,
input logic[23:0] planep,
//multi
input logic[9:0] h,
input logic[9:0] v,
input logic[9:0] h1,
input logic[9:0] v1,

//chara1
output logic[7:0] chara1R,
output logic[7:0] chara1G,
output logic[7:0] chara1B,
output logic[13:0] chara1add,

//chara2
output logic[7:0] chara2R,
output logic[7:0] chara2G,
output logic[7:0] chara2B,
output logic[13:0] chara2add,

//chara3
output logic[7:0] chara3R,
output logic[7:0] chara3G,
output logic[7:0] chara3B,
output logic[13:0] chara3add,
////////////////////////
///plane
output logic[7:0] planeR,
output logic[7:0] planeG,
output logic[7:0] planeB,
output logic[13:0] planeadd


);

//chara1
assign chara1add=v*64+h;
assign chara1B=charap1[7:0];
assign chara1G=charap1[15:8];
assign chara1R=charap1[23:16];

//chara2
assign chara2add=v*64+h;
assign chara2B=charap2[7:0];
assign chara2G=charap2[15:8];
assign chara2R=charap2[23:16];

//chara3
assign chara3add=v*64+h;
assign chara3B=charap3[7:0];
assign chara3G=charap3[15:8];
assign chara3R=charap3[23:16];

//plane
assign planeadd=v1*100+h1;
assign planeB=planep[7:0];
assign planeG=planep[15:8];
assign planeR=planep[23:16];

endmodule
//every second read from the ROM 24bit data and parse it into 3 R G B data
//output to the VGA
