Info: Starting: Create block symbol file (.bsf)
Info: ip-generate --project-directory=/user5/spring14/qw2164/Desktop/newpro_test/ --output-directory=/user5/spring14/qw2164/Desktop/newpro_test/lab3/ --report-file=bsf:/user5/spring14/qw2164/Desktop/newpro_test/lab3.bsf --system-info=DEVICE_FAMILY="Cyclone V" --system-info=DEVICE=5CSXFC6D6F31C8ES --system-info=DEVICE_SPEEDGRADE=8_H6 --component-file=/user5/spring14/qw2164/Desktop/newpro_test/lab3.qsys
Progress: Loading newpro_test/lab3.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 13.1]
Progress: Parameterizing module clk_0
Progress: Adding hps_0 [altera_hps 13.1.1]
Progress: Parameterizing module hps_0
Progress: Adding master_0 [altera_jtag_avalon_master 13.1]
Progress: Parameterizing module master_0
Progress: Adding vga_led_0 [vga_led 1.0]
Progress: Parameterizing module vga_led_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: ip-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: ip-generate --project-directory=/user5/spring14/qw2164/Desktop/newpro_test/ --output-directory=/user5/spring14/qw2164/Desktop/newpro_test/lab3/synthesis/ --file-set=QUARTUS_SYNTH --report-file=html:/user5/spring14/qw2164/Desktop/newpro_test/lab3.html --report-file=sopcinfo:/user5/spring14/qw2164/Desktop/newpro_test/lab3.sopcinfo --report-file=cmp:/user5/spring14/qw2164/Desktop/newpro_test/lab3.cmp --report-file=qip:/user5/spring14/qw2164/Desktop/newpro_test/lab3/synthesis/lab3.qip --report-file=svd --report-file=regmap:/user5/spring14/qw2164/Desktop/newpro_test/lab3/synthesis/lab3.regmap --report-file=debuginfo:/user5/spring14/qw2164/Desktop/newpro_test/lab3/synthesis/lab3.debuginfo --system-info=DEVICE_FAMILY="Cyclone V" --system-info=DEVICE=5CSXFC6D6F31C8ES --system-info=DEVICE_SPEEDGRADE=8_H6 --component-file=/user5/spring14/qw2164/Desktop/newpro_test/lab3.qsys --language=VERILOG
Progress: Loading newpro_test/lab3.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 13.1]
Progress: Parameterizing module clk_0
Progress: Adding hps_0 [altera_hps 13.1.1]
Progress: Parameterizing module hps_0
Progress: Adding master_0 [altera_jtag_avalon_master 13.1]
Progress: Parameterizing module master_0
Progress: Adding vga_led_0 [vga_led 1.0]
Progress: Parameterizing module vga_led_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: lab3: Generating lab3 "lab3" for QUARTUS_SYNTH
Info: pipeline_bridge_swap_transform: After transform: 4 modules, 9 connections
Info: No custom instruction connections, skipping transform 
Info: merlin_initial_interconnect_transform: After transform: 4 modules, 7 connections
Info: merlin_translator_transform: After transform: 6 modules, 13 connections
Info: merlin_domain_transform: After transform: 12 modules, 44 connections
Info: merlin_router_transform: After transform: 16 modules, 56 connections
Info: merlin_burst_transform: After transform: 17 modules, 59 connections
Info: merlin_network_to_switch_transform: After transform: 24 modules, 73 connections
Info: merlin_width_transform: After transform: 26 modules, 79 connections
Info: merlin_clock_and_reset_bridge_transform: After transform: 30 modules, 107 connections
Info: merlin_hierarchy_transform: After transform: 5 modules, 14 connections
Info: merlin_mm_transform: After transform: 5 modules, 14 connections
Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper.sender
Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper.sender
Warning: hps_0.f2h_irq1: Cannot connect clock for irq_mapper_001.sender
Warning: hps_0.f2h_irq1: Cannot connect reset for irq_mapper_001.sender
Info: merlin_interrupt_mapper_transform: After transform: 7 modules, 16 connections
Info: reset_adaptation_transform: After transform: 9 modules, 20 connections
Info: hps_0: "Doing Pretransform for module: hps_0"
Info: pipeline_bridge_swap_transform: After transform: 2 modules, 0 connections
Info: No custom instruction connections, skipping transform 
Info: hps_0: "lab3" instantiated altera_hps "hps_0"
Info: pipeline_bridge_swap_transform: After transform: 10 modules, 24 connections
Info: No custom instruction connections, skipping transform 
Info: reset_adaptation_transform: After transform: 11 modules, 26 connections
Info: master_0: "lab3" instantiated altera_jtag_avalon_master "master_0"
Info: vga_led_0: "lab3" instantiated vga_led "vga_led_0"
Info: pipeline_bridge_swap_transform: After transform: 26 modules, 74 connections
Info: No custom instruction connections, skipping transform 
Info: merlin_initial_interconnect_transform: After transform: 0 modules, 0 connections
Info: No Avalon connections, skipping transform 
Info: merlin_hierarchy_transform: After transform: 26 modules, 74 connections
Info: merlin_initial_interconnect_transform: After transform: 0 modules, 0 connections
Info: No Avalon connections, skipping transform 
Info: merlin_hierarchy_transform: After transform: 26 modules, 74 connections
Info: mm_interconnect_0: "lab3" instantiated altera_merlin_interconnect_wrapper "mm_interconnect_0"
Info: irq_mapper: "lab3" instantiated altera_irq_mapper "irq_mapper"
Info: rst_controller: "lab3" instantiated altera_reset_controller "rst_controller"
Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces"
Info: pipeline_bridge_swap_transform: After transform: 1 modules, 0 connections
Info: No custom instruction connections, skipping transform 
Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io"
Info: jtag_phy_embedded_in_jtag_master: "master_0" instantiated altera_jtag_dc_streaming "jtag_phy_embedded_in_jtag_master"
Info: timing_adt: Starting generation. 
Info: timing_adt: "master_0" instantiated timing_adapter "timing_adt"
Info: fifo: "master_0" instantiated altera_avalon_sc_fifo "fifo"
Info: b2p: "master_0" instantiated altera_avalon_st_bytes_to_packets "b2p"
Info: p2b: "master_0" instantiated altera_avalon_st_packets_to_bytes "p2b"
Info: transacto: "master_0" instantiated altera_avalon_packets_to_master "transacto"
Info: b2p_adapter: Starting generation. 
Info: b2p_adapter: "master_0" instantiated channel_adapter "b2p_adapter"
Info: p2b_adapter: Starting generation. 
Info: p2b_adapter: "master_0" instantiated channel_adapter "p2b_adapter"
Info: master_0_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "master_0_master_translator"
Info: vga_led_0_avalon_slave_0_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "vga_led_0_avalon_slave_0_translator"
Info: hps_0_h2f_lw_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_0_h2f_lw_axi_master_agent"
Info: master_0_master_translator_avalon_universal_master_0_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "master_0_master_translator_avalon_universal_master_0_agent"
Info: vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent"
Info: addr_router: "mm_interconnect_0" instantiated altera_merlin_router "addr_router"
Info: id_router: "mm_interconnect_0" instantiated altera_merlin_router "id_router"
Info: burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "burst_adapter"
Info: Reusing file /user5/spring14/qw2164/Desktop/newpro_test/lab3/synthesis/submodules/altera_merlin_address_alignment.sv
Info: cmd_xbar_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_xbar_demux"
Info: cmd_xbar_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_xbar_mux"
Info: rsp_xbar_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_xbar_demux"
Info: rsp_xbar_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_xbar_mux"
Info: Reusing file /user5/spring14/qw2164/Desktop/newpro_test/lab3/synthesis/submodules/altera_merlin_arbitrator.sv
Info: width_adapter: "mm_interconnect_0" instantiated altera_merlin_width_adapter "width_adapter"
Info: Reusing file /user5/spring14/qw2164/Desktop/newpro_test/lab3/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file /user5/spring14/qw2164/Desktop/newpro_test/lab3/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: border: "hps_io" instantiated altera_interface_generator "border"
Info: lab3: Done "lab3" with 31 modules, 86 files, 1930032 bytes
Info: ip-generate succeeded.
Info: Finished: Create HDL design files for synthesis
