set_global_assignment -entity "lab3" -library "lab3" -name IP_TOOL_NAME "Qsys"
set_global_assignment -entity "lab3" -library "lab3" -name IP_TOOL_VERSION "13.1.1"
set_global_assignment -entity "lab3" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "lab3" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../lab3.sopcinfo"]
set_global_assignment -entity "lab3" -library "lab3" -name SLD_INFO "QSYS_NAME lab3 HAS_SOPCINFO 1 GENERATION_ID 1399007758"
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "../../lab3.cmp"]
set_global_assignment -library "lab3" -name SLD_FILE [file join $::quartus(qip_path) "lab3.regmap"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "lab3_hps_0_hps.svd"]
set_global_assignment -library "lab3" -name SLD_FILE [file join $::quartus(qip_path) "lab3.debuginfo"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "../../lab3.qsys"]
set_instance_assignment -name HPS_LOCATION PIN_P19A0T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_TX_CLK[0]
set_instance_assignment -name HPS_LOCATION PIN_P19B0T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_TXD0[0]
set_instance_assignment -name HPS_LOCATION PIN_P19A1T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_TXD1[0]
set_instance_assignment -name HPS_LOCATION PIN_P19B1T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_TXD2[0]
set_instance_assignment -name HPS_LOCATION PIN_P20A0T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_TXD3[0]
set_instance_assignment -name HPS_LOCATION PIN_P20B0T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_RXD0[0]
set_instance_assignment -name HPS_LOCATION PIN_P20A1T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_MDIO[0]
set_instance_assignment -name HPS_LOCATION PIN_P20B1T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_MDC[0]
set_instance_assignment -name HPS_LOCATION PIN_P21A0T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_RX_CTL[0]
set_instance_assignment -name HPS_LOCATION PIN_P21B0T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_TX_CTL[0]
set_instance_assignment -name HPS_LOCATION PIN_P21A1T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_RX_CLK[0]
set_instance_assignment -name HPS_LOCATION PIN_P21B1T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_RXD1[0]
set_instance_assignment -name HPS_LOCATION PIN_P22A0T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_RXD2[0]
set_instance_assignment -name HPS_LOCATION PIN_P22B0T -entity lab3_hps_0 -to hps_io|border|hps_io_emac1_inst_RXD3[0]
set_instance_assignment -name HPS_LOCATION PIN_P22B1T -entity lab3_hps_0 -to hps_io|border|hps_io_qspi_inst_IO0[0]
set_instance_assignment -name HPS_LOCATION PIN_P23A0T -entity lab3_hps_0 -to hps_io|border|hps_io_qspi_inst_IO1[0]
set_instance_assignment -name HPS_LOCATION PIN_P23B0T -entity lab3_hps_0 -to hps_io|border|hps_io_qspi_inst_IO2[0]
set_instance_assignment -name HPS_LOCATION PIN_P23A1T -entity lab3_hps_0 -to hps_io|border|hps_io_qspi_inst_IO3[0]
set_instance_assignment -name HPS_LOCATION PIN_P23B1T -entity lab3_hps_0 -to hps_io|border|hps_io_qspi_inst_SS0[0]
set_instance_assignment -name HPS_LOCATION PIN_P24A0T -entity lab3_hps_0 -to hps_io|border|hps_io_qspi_inst_CLK[0]
set_instance_assignment -name HPS_LOCATION PIN_P25A0T -entity lab3_hps_0 -to hps_io|border|hps_io_sdio_inst_CMD[0]
set_instance_assignment -name HPS_LOCATION PIN_P25A1T -entity lab3_hps_0 -to hps_io|border|hps_io_sdio_inst_D0[0]
set_instance_assignment -name HPS_LOCATION PIN_P25B1T -entity lab3_hps_0 -to hps_io|border|hps_io_sdio_inst_D1[0]
set_instance_assignment -name HPS_LOCATION PIN_P27B0T -entity lab3_hps_0 -to hps_io|border|hps_io_sdio_inst_CLK[0]
set_instance_assignment -name HPS_LOCATION PIN_P27A1T -entity lab3_hps_0 -to hps_io|border|hps_io_sdio_inst_D2[0]
set_instance_assignment -name HPS_LOCATION PIN_P27B1T -entity lab3_hps_0 -to hps_io|border|hps_io_sdio_inst_D3[0]
set_instance_assignment -name HPS_LOCATION PIN_P28B0T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_D0[0]
set_instance_assignment -name HPS_LOCATION PIN_P28A1T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_D1[0]
set_instance_assignment -name HPS_LOCATION PIN_P28B1T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_D2[0]
set_instance_assignment -name HPS_LOCATION PIN_P29A0T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_D3[0]
set_instance_assignment -name HPS_LOCATION PIN_P29B0T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_D4[0]
set_instance_assignment -name HPS_LOCATION PIN_P29A1T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_D5[0]
set_instance_assignment -name HPS_LOCATION PIN_P29B1T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_D6[0]
set_instance_assignment -name HPS_LOCATION PIN_P30A0T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_D7[0]
set_instance_assignment -name HPS_LOCATION PIN_P30A1T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_CLK[0]
set_instance_assignment -name HPS_LOCATION PIN_P30B1T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_STP[0]
set_instance_assignment -name HPS_LOCATION PIN_P31A0T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_DIR[0]
set_instance_assignment -name HPS_LOCATION PIN_P31B0T -entity lab3_hps_0 -to hps_io|border|hps_io_usb1_inst_NXT[0]
set_instance_assignment -name HPS_LOCATION PIN_P16B0T -entity lab3_hps_0 -to hps_io|border|hps_io_spim0_inst_CLK[0]
set_instance_assignment -name HPS_LOCATION PIN_P16A1T -entity lab3_hps_0 -to hps_io|border|hps_io_spim0_inst_MOSI[0]
set_instance_assignment -name HPS_LOCATION PIN_P16B1T -entity lab3_hps_0 -to hps_io|border|hps_io_spim0_inst_MISO[0]
set_instance_assignment -name HPS_LOCATION PIN_P17A0T -entity lab3_hps_0 -to hps_io|border|hps_io_spim0_inst_SS0[0]
set_instance_assignment -name HPS_LOCATION PIN_P17B1T -entity lab3_hps_0 -to hps_io|border|hps_io_spim1_inst_CLK[0]
set_instance_assignment -name HPS_LOCATION PIN_P18A0T -entity lab3_hps_0 -to hps_io|border|hps_io_spim1_inst_MOSI[0]
set_instance_assignment -name HPS_LOCATION PIN_P18B0T -entity lab3_hps_0 -to hps_io|border|hps_io_spim1_inst_MISO[0]
set_instance_assignment -name HPS_LOCATION PIN_P18A1T -entity lab3_hps_0 -to hps_io|border|hps_io_spim1_inst_SS0[0]
set_instance_assignment -name HPS_LOCATION PIN_P14B0T -entity lab3_hps_0 -to hps_io|border|hps_io_uart0_inst_RX[0]
set_instance_assignment -name HPS_LOCATION PIN_P14A1T -entity lab3_hps_0 -to hps_io|border|hps_io_uart0_inst_TX[0]
set_instance_assignment -name HPS_LOCATION PIN_P14B1T -entity lab3_hps_0 -to hps_io|border|hps_io_i2c1_inst_SDA[0]
set_instance_assignment -name HPS_LOCATION PIN_P15A0T -entity lab3_hps_0 -to hps_io|border|hps_io_i2c1_inst_SCL[0]
set_instance_assignment -name HPS_LOCATION HPSPERIPHERALEMAC_X77_Y39_N111 -entity lab3_hps_0_hps_io_border -to emac1_inst
set_instance_assignment -name HPS_LOCATION HPSPERIPHERALQSPI_X87_Y58_N111 -entity lab3_hps_0_hps_io_border -to qspi_inst
set_instance_assignment -name HPS_LOCATION HPSPERIPHERALSDMMC_X87_Y39_N111 -entity lab3_hps_0_hps_io_border -to sdio_inst
set_instance_assignment -name HPS_LOCATION HPSPERIPHERALUSB_X55_Y39_N111 -entity lab3_hps_0_hps_io_border -to usb1_inst
set_instance_assignment -name HPS_LOCATION HPSPERIPHERALSPIMASTER_X87_Y55_N111 -entity lab3_hps_0_hps_io_border -to spim0_inst
set_instance_assignment -name HPS_LOCATION HPSPERIPHERALSPIMASTER_X87_Y53_N111 -entity lab3_hps_0_hps_io_border -to spim1_inst
set_instance_assignment -name HPS_LOCATION HPSPERIPHERALUART_X87_Y45_N111 -entity lab3_hps_0_hps_io_border -to uart0_inst
set_instance_assignment -name HPS_LOCATION HPSPERIPHERALI2C_X87_Y65_N111 -entity lab3_hps_0_hps_io_border -to i2c1_inst
set_instance_assignment -name hps_partition on -entity lab3_hps_0_hps_io_border -library lab3
set_instance_assignment -name HPS_LOCATION HPSINTERFACECLOCKSRESETS_X52_Y78_N111 -entity lab3_hps_0_fpga_interfaces -to clocks_resets
set_instance_assignment -name HPS_LOCATION HPSINTERFACEDBGAPB_X52_Y80_N111 -entity lab3_hps_0_fpga_interfaces -to debug_apb
set_instance_assignment -name HPS_LOCATION HPSINTERFACETPIUTRACE_X52_Y39_N111 -entity lab3_hps_0_fpga_interfaces -to tpiu
set_instance_assignment -name HPS_LOCATION HPSINTERFACEBOOTFROMFPGA_X52_Y74_N111 -entity lab3_hps_0_fpga_interfaces -to boot_from_fpga
set_instance_assignment -name HPS_LOCATION HPSINTERFACEFPGA2HPS_X52_Y45_N111 -entity lab3_hps_0_fpga_interfaces -to fpga2hps
set_instance_assignment -name HPS_LOCATION HPSINTERFACEHPS2FPGALIGHTWEIGHT_X52_Y43_N111 -entity lab3_hps_0_fpga_interfaces -to hps2fpga_light_weight
set_instance_assignment -name HPS_LOCATION HPSINTERFACEHPS2FPGA_X52_Y47_N111 -entity lab3_hps_0_fpga_interfaces -to hps2fpga
set_instance_assignment -name HPS_LOCATION HPSINTERFACEFPGA2SDRAM_X52_Y53_N111 -entity lab3_hps_0_fpga_interfaces -to f2sdram
set_instance_assignment -name HPS_LOCATION HPSINTERFACEINTERRUPTS_X52_Y40_N111 -entity lab3_hps_0_fpga_interfaces -to interrupts

set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "lab3.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_synchronizer.v"]
set_global_assignment -library "lab3" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.sdc"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_irq_mapper.sv"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_mm_interconnect_0.v"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_width_adapter.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_address_alignment.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_uncompressor.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_arbitrator.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_mm_interconnect_0_rsp_xbar_mux.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_mm_interconnect_0_rsp_xbar_demux.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_mm_interconnect_0_cmd_xbar_mux.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_mm_interconnect_0_cmd_xbar_demux.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_adapter.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_mm_interconnect_0_id_router.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_mm_interconnect_0_addr_router.sv"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_sc_fifo.v"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_agent.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_agent.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_axi_master_ni.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_translator.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_translator.sv"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/brick.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/bullet1.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/bullet2.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/chara1.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/chara2.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/chara3.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/enemyA1.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/enemyA2.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/enemyB1.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/enemyB2.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/explosion.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/falling1.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/falling2.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/fell1.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/fell2.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/fell3.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/fell4.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/floor.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/gameover.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/left1.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/left2.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/number0.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/number1.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/number2.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/number3.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/number4.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/number5.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/number6.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/number7.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/number8.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/number9.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/press.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/right1.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/right2.v"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/ROMdecoder.sv"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/shoot1.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/shoot2.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/straight1.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/straight2.v"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/VGA_LED.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/VGA_LED_Emulator.sv"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_master_0.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_master_0_p2b_adapter.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_master_0_b2p_adapter.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_packets_to_master.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_packets_to_bytes.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_bytes_to_packets.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_master_0_timing_adt.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_jtag_interface.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_jtag_dc_streaming.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_jtag_sld_node.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_jtag_streaming.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_pli_streaming.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_clock_crosser.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_pipeline_base.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_idle_remover.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_idle_inserter.v"]
set_global_assignment -library "lab3" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_jtag_interface.sdc"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_hps_0.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_hps_0_hps_io.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram.v"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_phy_csr.sv"]
set_global_assignment -library "lab3" -name TCL_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_report_timing.tcl"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_iss_probe.v"]
set_global_assignment -library "lab3" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0.ppf"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_reset_sync.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_acv_ldc.v"]
set_global_assignment -library "lab3" -name TCL_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_pin_assignments.tcl"]
set_global_assignment -library "lab3" -name TCL_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_report_timing_core.tcl"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_generic_ddio.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_altdqdqs.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_clock_pair_generator.v"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_mem_if_oct_cyclonev.sv"]
set_global_assignment -library "lab3" -name SDC_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0.sdc"]
set_global_assignment -library "lab3" -name TCL_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_timing.tcl"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_mem_if_hhp_qseq_synth_top.v"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_mem_if_dll_cyclonev.sv"]
set_global_assignment -library "lab3" -name TCL_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_parameters.tcl"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv"]
set_global_assignment -library "lab3" -name TCL_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_pin_map.tcl"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_reset.v"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_pll.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer_auto.pre.h"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer_auto.pre.h"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/emif.pre.xml"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/emif.pre.xml"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer_auto_inst_init.pre.c"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer_auto_inst_init.pre.c"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/tclrpt.pre.h"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/tclrpt.pre.h"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/tclrpt.pre.c"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/tclrpt.pre.c"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/sdram_io.pre.h"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/sdram_io.pre.h"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/system.pre.h"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/system.pre.h"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer_defines.pre.h"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer_defines.pre.h"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer.pre.c"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer.pre.c"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer_auto_ac_init.pre.c"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer_auto_ac_init.pre.c"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/alt_types.pre.h"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/alt_types.pre.h"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer.pre.h"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/sequencer/sequencer.pre.h"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_acv_hard_memphy.v"]
set_global_assignment -library "lab3" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0_acv_hard_io_pads.v"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/hps_sdram_p0.sv"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_hps_0_hps_io_border.sv"]
set_instance_assignment -entity "lab3_hps_0_hps_io_border" -library "lab3" -name HPS_ISW_FILE [file join $::quartus(qip_path) "submodules/hps.pre.xml"]
set_global_assignment -library "lab3" -name MISC_FILE [file join $::quartus(qip_path) "submodules/hps.pre.xml"]
set_global_assignment -library "lab3" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/lab3_hps_0_fpga_interfaces.sv"]

set_global_assignment -entity "altera_reset_controller" -library "lab3" -name IP_TOOL_NAME "altera_reset_controller"
set_global_assignment -entity "altera_reset_controller" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_reset_controller" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_irq_mapper" -library "lab3" -name IP_TOOL_NAME "altera_irq_mapper"
set_global_assignment -entity "lab3_irq_mapper" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_irq_mapper" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_mm_interconnect_0" -library "lab3" -name IP_TOOL_NAME "altera_merlin_interconnect_wrapper"
set_global_assignment -entity "lab3_mm_interconnect_0" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_mm_interconnect_0" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_merlin_width_adapter" -library "lab3" -name IP_TOOL_NAME "altera_merlin_width_adapter"
set_global_assignment -entity "altera_merlin_width_adapter" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_merlin_width_adapter" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_mm_interconnect_0_rsp_xbar_mux" -library "lab3" -name IP_TOOL_NAME "altera_merlin_multiplexer"
set_global_assignment -entity "lab3_mm_interconnect_0_rsp_xbar_mux" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_mm_interconnect_0_rsp_xbar_mux" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_mm_interconnect_0_rsp_xbar_demux" -library "lab3" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "lab3_mm_interconnect_0_rsp_xbar_demux" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_mm_interconnect_0_rsp_xbar_demux" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_mm_interconnect_0_cmd_xbar_mux" -library "lab3" -name IP_TOOL_NAME "altera_merlin_multiplexer"
set_global_assignment -entity "lab3_mm_interconnect_0_cmd_xbar_mux" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_mm_interconnect_0_cmd_xbar_mux" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_mm_interconnect_0_cmd_xbar_demux" -library "lab3" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "lab3_mm_interconnect_0_cmd_xbar_demux" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_mm_interconnect_0_cmd_xbar_demux" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_merlin_burst_adapter" -library "lab3" -name IP_TOOL_NAME "altera_merlin_burst_adapter"
set_global_assignment -entity "altera_merlin_burst_adapter" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_merlin_burst_adapter" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_mm_interconnect_0_id_router" -library "lab3" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "lab3_mm_interconnect_0_id_router" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_mm_interconnect_0_id_router" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_mm_interconnect_0_addr_router" -library "lab3" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "lab3_mm_interconnect_0_addr_router" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_mm_interconnect_0_addr_router" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_avalon_sc_fifo" -library "lab3" -name IP_TOOL_NAME "altera_avalon_sc_fifo"
set_global_assignment -entity "altera_avalon_sc_fifo" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_avalon_sc_fifo" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_merlin_slave_agent" -library "lab3" -name IP_TOOL_NAME "altera_merlin_slave_agent"
set_global_assignment -entity "altera_merlin_slave_agent" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_merlin_slave_agent" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_merlin_master_agent" -library "lab3" -name IP_TOOL_NAME "altera_merlin_master_agent"
set_global_assignment -entity "altera_merlin_master_agent" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_merlin_master_agent" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_merlin_axi_master_ni" -library "lab3" -name IP_TOOL_NAME "altera_merlin_axi_master_ni"
set_global_assignment -entity "altera_merlin_axi_master_ni" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_merlin_axi_master_ni" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_merlin_slave_translator" -library "lab3" -name IP_TOOL_NAME "altera_merlin_slave_translator"
set_global_assignment -entity "altera_merlin_slave_translator" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_merlin_slave_translator" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_merlin_master_translator" -library "lab3" -name IP_TOOL_NAME "altera_merlin_master_translator"
set_global_assignment -entity "altera_merlin_master_translator" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_merlin_master_translator" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_master_0" -library "lab3" -name IP_TOOL_NAME "altera_jtag_avalon_master"
set_global_assignment -entity "lab3_master_0" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_master_0" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_master_0_p2b_adapter" -library "lab3" -name IP_TOOL_NAME "channel_adapter"
set_global_assignment -entity "lab3_master_0_p2b_adapter" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_master_0_p2b_adapter" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_master_0_b2p_adapter" -library "lab3" -name IP_TOOL_NAME "channel_adapter"
set_global_assignment -entity "lab3_master_0_b2p_adapter" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_master_0_b2p_adapter" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_avalon_packets_to_master" -library "lab3" -name IP_TOOL_NAME "altera_avalon_packets_to_master"
set_global_assignment -entity "altera_avalon_packets_to_master" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_avalon_packets_to_master" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "lab3" -name IP_TOOL_NAME "altera_avalon_st_packets_to_bytes"
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_avalon_st_packets_to_bytes" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "lab3" -name IP_TOOL_NAME "altera_avalon_st_bytes_to_packets"
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_avalon_st_bytes_to_packets" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_master_0_timing_adt" -library "lab3" -name IP_TOOL_NAME "timing_adapter"
set_global_assignment -entity "lab3_master_0_timing_adt" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "lab3_master_0_timing_adt" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "lab3" -name IP_TOOL_NAME "altera_jtag_dc_streaming"
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "lab3" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "altera_avalon_st_jtag_interface" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_hps_0" -library "lab3" -name IP_TOOL_NAME "altera_hps"
set_global_assignment -entity "lab3_hps_0" -library "lab3" -name IP_TOOL_VERSION "13.1.1"
set_global_assignment -entity "lab3_hps_0" -library "lab3" -name IP_TOOL_ENV "Qsys"
set_global_assignment -entity "lab3_hps_0_hps_io" -library "lab3" -name IP_TOOL_NAME "altera_hps_io"
set_global_assignment -entity "lab3_hps_0_hps_io" -library "lab3" -name IP_TOOL_VERSION "13.1.1"
set_global_assignment -entity "lab3_hps_0_hps_io" -library "lab3" -name IP_TOOL_ENV "Qsys"
