Info (10281): Verilog HDL Declaration information at lab3_mm_interconnect_0_id_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at lab3_mm_interconnect_0_id_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Info (10281): Verilog HDL Declaration information at lab3_mm_interconnect_0_addr_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope
Info (10281): Verilog HDL Declaration information at lab3_mm_interconnect_0_addr_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope
Warning (10268): Verilog HDL information at i2c_controller.sv(36): always construct contains both blocking and non-blocking assignments
Warning (10268): Verilog HDL information at Buffer.sv(93): always construct contains both blocking and non-blocking assignments
