# TCL File Generated by Component Editor 13.1.1
# Fri May 02 01:14:51 EDT 2014
# DO NOT MODIFY


# 
# vga_led "VGA LED Emulator" v1.0
#  2014.05.02.01:14:51
# 
# 

# 
# request TCL package from ACDS 13.1
# 
package require -exact qsys 13.1


# 
# module vga_led
# 
set_module_property DESCRIPTION ""
set_module_property NAME vga_led
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "VGA LED Emulator"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL VGA_LED
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file brick.v VERILOG PATH brick.v
add_fileset_file bullet1.v VERILOG PATH bullet1.v
add_fileset_file bullet2.v VERILOG PATH bullet2.v
add_fileset_file chara1.v VERILOG PATH chara1.v
add_fileset_file chara2.v VERILOG PATH chara2.v
add_fileset_file chara3.v VERILOG PATH chara3.v
add_fileset_file enemyA1.v VERILOG PATH enemyA1.v
add_fileset_file enemyA2.v VERILOG PATH enemyA2.v
add_fileset_file enemyB1.v VERILOG PATH enemyB1.v
add_fileset_file enemyB2.v VERILOG PATH enemyB2.v
add_fileset_file explosion.v VERILOG PATH explosion.v
add_fileset_file falling1.v VERILOG PATH falling1.v
add_fileset_file falling2.v VERILOG PATH falling2.v
add_fileset_file fell1.v VERILOG PATH fell1.v
add_fileset_file fell2.v VERILOG PATH fell2.v
add_fileset_file fell3.v VERILOG PATH fell3.v
add_fileset_file fell4.v VERILOG PATH fell4.v
add_fileset_file floor.v VERILOG PATH floor.v
add_fileset_file gameover.v VERILOG PATH gameover.v
add_fileset_file left1.v VERILOG PATH left1.v
add_fileset_file left2.v VERILOG PATH left2.v
add_fileset_file number0.v VERILOG PATH number0.v
add_fileset_file number1.v VERILOG PATH number1.v
add_fileset_file number2.v VERILOG PATH number2.v
add_fileset_file number3.v VERILOG PATH number3.v
add_fileset_file number4.v VERILOG PATH number4.v
add_fileset_file number5.v VERILOG PATH number5.v
add_fileset_file number6.v VERILOG PATH number6.v
add_fileset_file number7.v VERILOG PATH number7.v
add_fileset_file number8.v VERILOG PATH number8.v
add_fileset_file number9.v VERILOG PATH number9.v
add_fileset_file press.v VERILOG PATH press.v
add_fileset_file right1.v VERILOG PATH right1.v
add_fileset_file right2.v VERILOG PATH right2.v
add_fileset_file ROMdecoder.sv SYSTEM_VERILOG PATH ROMdecoder.sv
add_fileset_file shoot1.v VERILOG PATH shoot1.v
add_fileset_file shoot2.v VERILOG PATH shoot2.v
add_fileset_file straight1.v VERILOG PATH straight1.v
add_fileset_file straight2.v VERILOG PATH straight2.v
add_fileset_file VGA_LED.sv SYSTEM_VERILOG PATH VGA_LED.sv TOP_LEVEL_FILE
add_fileset_file VGA_LED_Emulator.sv SYSTEM_VERILOG PATH VGA_LED_Emulator.sv


# 
# parameters
# 


# 
# display items
# 


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1


# 
# connection point avalon_slave_0
# 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock
set_interface_property avalon_slave_0 associatedReset reset_sink
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
set_interface_property avalon_slave_0 EXPORT_OF ""
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""

add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 chipselect chipselect Input 1
add_interface_port avalon_slave_0 address address Input 6
add_interface_port avalon_slave_0 writedata writedata Input 16
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0


# 
# connection point reset_sink
# 
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""

add_interface_port reset_sink reset reset Input 1


# 
# connection point conduit_end
# 
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock clock
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""

add_interface_port conduit_end VGA_R export Output 8
add_interface_port conduit_end VGA_G export Output 8
add_interface_port conduit_end VGA_B export Output 8
add_interface_port conduit_end VGA_CLK export Output 1
add_interface_port conduit_end VGA_HS export Output 1
add_interface_port conduit_end VGA_VS export Output 1
add_interface_port conduit_end VGA_BLANK_n export Output 1
add_interface_port conduit_end VGA_SYNC_n export Output 1

