<sld_project_info>
  <project>
    <hash md5_digest_80b="6eb0806f7ff086b855a7"/>
  </project>
  <file_info>
    <file device="5CSXFC6D6F31C8ES" path="SoCKit_Top.sof" usercode="0xFFFFFFFF"/>
  </file_info>
  <hub_info hub_ir_width="10" ir_width="10" node_addr_width="3" node_count="6"/>
  <node_info>
    <node hpath="lab3:u0|lab3_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst" instance_id="0" mfg_id="110" node_id="132" sld_node_info="0xC206E00" version="1">
      <parameters>
        <parameter name="sld_mfg_id" type="dec" value="110"/>
        <parameter name="sld_type_id" type="dec" value="132"/>
        <parameter name="sld_version" type="dec" value="1"/>
        <parameter name="sld_instance_index" type="dec" value="0"/>
        <parameter name="sld_auto_instance_index" type="string" value="YES"/>
        <parameter name="sld_ir_width" type="dec" value="3"/>
        <parameter name="SLD_NODE_INFO" type="dec" value="203451904"/>
      </parameters>
      <inputs>
        <port name="usr_tdo" source="lab3:u0|lab3_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|tdo"/>
        <port name="usr_ir_out[0]" source="lab3:u0|lab3_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|ir_out[0]"/>
        <port name="usr_ir_out[1]" source="lab3:u0|lab3_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|ir_out[1]"/>
        <port name="usr_ir_out[2]" source="lab3:u0|lab3_master_0:master_0|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|ir_out[2]"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_raw_tck" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_raw_tck"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_raw_tms" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_raw_tms"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_tdi" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_tdi"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_tlr" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_tlr"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_rti" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_rti"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_sdrs" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_sdrs"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_cdr" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_cdr"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_sdr" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_sdr"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_e1dr" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_e1dr"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_pdr" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_pdr"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_e2dr" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_e2dr"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_udr" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_udr"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_sirs" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_sirs"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_cir" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_cir"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_sir" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_sir"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_e1ir" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_e1ir"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_pir" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_pir"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_e2ir" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_e2ir"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_uir" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_jtag_state_uir"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_usr1" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_usr1"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_clr" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_clr"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_ena" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_ena"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_ir_in_0_" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_ir_in_0_"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_ir_in_1_" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_ir_in_1_"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_ir_in_2_" source="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_ir_in_2_"/>
      </inputs>
      <outputs>
        <port name="usr_tck"/>
        <port name="usr_tdi"/>
        <port name="usr_ir_in[0]"/>
        <port name="usr_ir_in[1]"/>
        <port name="usr_ir_in[2]"/>
        <port name="usr_virtual_state_cdr"/>
        <port name="usr_virtual_state_sdr"/>
        <port name="usr_virtual_state_e1dr"/>
        <port name="usr_virtual_state_pdr"/>
        <port name="usr_virtual_state_e2dr"/>
        <port name="usr_virtual_state_udr"/>
        <port name="usr_virtual_state_cir"/>
        <port name="usr_virtual_state_uir"/>
        <port name="usr_tms"/>
        <port name="usr_jtag_state_tlr"/>
        <port name="usr_jtag_state_rti"/>
        <port name="usr_jtag_state_sdrs"/>
        <port name="usr_jtag_state_cdr"/>
        <port name="usr_jtag_state_sdr"/>
        <port name="usr_jtag_state_e1dr"/>
        <port name="usr_jtag_state_pdr"/>
        <port name="usr_jtag_state_e2dr"/>
        <port name="usr_jtag_state_udr"/>
        <port name="usr_jtag_state_sirs"/>
        <port name="usr_jtag_state_cir"/>
        <port name="usr_jtag_state_sir"/>
        <port name="usr_jtag_state_e1ir"/>
        <port name="usr_jtag_state_pir"/>
        <port name="usr_jtag_state_e2ir"/>
        <port name="usr_jtag_state_uir"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_tdo"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_ir_out_0_"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_ir_out_1_"/>
        <port name="jtag.bp.u0_master_0_jtag_phy_embedded_in_jtag_master_normal.jtag_dc_streaming_jtag_streaming_node_sld_virtual_jtag_component_sld_virtual_jtag_impl_inst_ir_out_2_"/>
      </outputs>
    </node>
    <node hpath="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|sld_mod_ram_rom:mgl_prim2" instance_id="0" mfg_id="110" node_id="3" sld_node_info="0x8186E00" version="1">
      <parameters>
        <parameter name="SLD_NODE_INFO" type="dec" value="135818752"/>
        <parameter name="SLD_AUTO_INSTANCE_INDEX" type="string" value="yes"/>
        <parameter name="SLD_IP_VERSION" type="dec" value="1"/>
        <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="3"/>
        <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
        <parameter name="width_word" type="unknown" value="32"/>
        <parameter name="numwords" type="unknown" value="4096"/>
        <parameter name="widthad" type="unknown" value="12"/>
        <parameter name="shift_count_bits" type="unknown" value="6"/>
        <parameter name="cvalue" type="unknown" value="00000000000000000000000000000000"/>
        <parameter name="is_data_in_ram" type="unknown" value="1"/>
        <parameter name="is_readable" type="unknown" value="1"/>
        <parameter name="node_name" type="unknown" value="1397313112"/>
      </parameters>
      <inputs>
        <port name="data_read[0]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[0]"/>
        <port name="data_read[1]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[1]"/>
        <port name="data_read[2]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[2]"/>
        <port name="data_read[3]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[3]"/>
        <port name="data_read[4]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[4]"/>
        <port name="data_read[5]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[5]"/>
        <port name="data_read[6]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[6]"/>
        <port name="data_read[7]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[7]"/>
        <port name="data_read[8]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[8]"/>
        <port name="data_read[9]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[9]"/>
        <port name="data_read[10]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[10]"/>
        <port name="data_read[11]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[11]"/>
        <port name="data_read[12]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[12]"/>
        <port name="data_read[13]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[13]"/>
        <port name="data_read[14]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[14]"/>
        <port name="data_read[15]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[15]"/>
        <port name="data_read[16]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[16]"/>
        <port name="data_read[17]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[17]"/>
        <port name="data_read[18]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[18]"/>
        <port name="data_read[19]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[19]"/>
        <port name="data_read[20]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[20]"/>
        <port name="data_read[21]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[21]"/>
        <port name="data_read[22]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[22]"/>
        <port name="data_read[23]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[23]"/>
        <port name="data_read[24]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[24]"/>
        <port name="data_read[25]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[25]"/>
        <port name="data_read[26]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[26]"/>
        <port name="data_read[27]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[27]"/>
        <port name="data_read[28]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[28]"/>
        <port name="data_read[29]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[29]"/>
        <port name="data_read[30]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[30]"/>
        <port name="data_read[31]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_x:sinx|altsyncram:altsyncram_component|altsyncram_rhi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[31]"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_raw_tck" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_raw_tck"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_tdi" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_tdi"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_usr1" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_usr1"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_cdr" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_cdr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_sdr" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_sdr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_e1dr" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_e1dr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_udr" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_udr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_uir" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_uir"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_clr" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_clr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ena" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ena"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_in_0_" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_in_0_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_in_1_" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_in_1_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_in_2_" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_in_2_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_in_3_" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_in_3_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_in_4_" source="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_in_4_"/>
      </inputs>
      <outputs>
        <port name="tck_usr"/>
        <port name="address[0]"/>
        <port name="address[1]"/>
        <port name="address[2]"/>
        <port name="address[3]"/>
        <port name="address[4]"/>
        <port name="address[5]"/>
        <port name="address[6]"/>
        <port name="address[7]"/>
        <port name="address[8]"/>
        <port name="address[9]"/>
        <port name="address[10]"/>
        <port name="address[11]"/>
        <port name="enable_write"/>
        <port name="data_write[0]"/>
        <port name="data_write[1]"/>
        <port name="data_write[2]"/>
        <port name="data_write[3]"/>
        <port name="data_write[4]"/>
        <port name="data_write[5]"/>
        <port name="data_write[6]"/>
        <port name="data_write[7]"/>
        <port name="data_write[8]"/>
        <port name="data_write[9]"/>
        <port name="data_write[10]"/>
        <port name="data_write[11]"/>
        <port name="data_write[12]"/>
        <port name="data_write[13]"/>
        <port name="data_write[14]"/>
        <port name="data_write[15]"/>
        <port name="data_write[16]"/>
        <port name="data_write[17]"/>
        <port name="data_write[18]"/>
        <port name="data_write[19]"/>
        <port name="data_write[20]"/>
        <port name="data_write[21]"/>
        <port name="data_write[22]"/>
        <port name="data_write[23]"/>
        <port name="data_write[24]"/>
        <port name="data_write[25]"/>
        <port name="data_write[26]"/>
        <port name="data_write[27]"/>
        <port name="data_write[28]"/>
        <port name="data_write[29]"/>
        <port name="data_write[30]"/>
        <port name="data_write[31]"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_out_0_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_out_1_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_out_2_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_out_3_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_ir_out_4_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_sinx_altsyncram_component_auto_generated_mgl_prim2_tdo"/>
      </outputs>
    </node>
    <node hpath="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|sld_mod_ram_rom:mgl_prim2" instance_id="1" mfg_id="110" node_id="3" sld_node_info="0x8186E01" version="1">
      <parameters>
        <parameter name="SLD_NODE_INFO" type="dec" value="135818752"/>
        <parameter name="SLD_AUTO_INSTANCE_INDEX" type="string" value="yes"/>
        <parameter name="SLD_IP_VERSION" type="dec" value="1"/>
        <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="3"/>
        <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
        <parameter name="width_word" type="unknown" value="32"/>
        <parameter name="numwords" type="unknown" value="4096"/>
        <parameter name="widthad" type="unknown" value="12"/>
        <parameter name="shift_count_bits" type="unknown" value="6"/>
        <parameter name="cvalue" type="unknown" value="00000000000000000000000000000000"/>
        <parameter name="is_data_in_ram" type="unknown" value="1"/>
        <parameter name="is_readable" type="unknown" value="1"/>
        <parameter name="node_name" type="unknown" value="1129272152"/>
      </parameters>
      <inputs>
        <port name="data_read[0]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[0]"/>
        <port name="data_read[1]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[1]"/>
        <port name="data_read[2]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[2]"/>
        <port name="data_read[3]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[3]"/>
        <port name="data_read[4]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[4]"/>
        <port name="data_read[5]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[5]"/>
        <port name="data_read[6]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[6]"/>
        <port name="data_read[7]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[7]"/>
        <port name="data_read[8]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[8]"/>
        <port name="data_read[9]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[9]"/>
        <port name="data_read[10]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[10]"/>
        <port name="data_read[11]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[11]"/>
        <port name="data_read[12]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[12]"/>
        <port name="data_read[13]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[13]"/>
        <port name="data_read[14]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[14]"/>
        <port name="data_read[15]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[15]"/>
        <port name="data_read[16]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[16]"/>
        <port name="data_read[17]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[17]"/>
        <port name="data_read[18]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[18]"/>
        <port name="data_read[19]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[19]"/>
        <port name="data_read[20]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[20]"/>
        <port name="data_read[21]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[21]"/>
        <port name="data_read[22]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[22]"/>
        <port name="data_read[23]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[23]"/>
        <port name="data_read[24]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[24]"/>
        <port name="data_read[25]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[25]"/>
        <port name="data_read[26]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[26]"/>
        <port name="data_read[27]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[27]"/>
        <port name="data_read[28]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[28]"/>
        <port name="data_read[29]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[29]"/>
        <port name="data_read[30]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[30]"/>
        <port name="data_read[31]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_x:cosx|altsyncram:altsyncram_component|altsyncram_cei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[31]"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_raw_tck" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_raw_tck"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_tdi" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_tdi"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_usr1" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_usr1"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_cdr" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_cdr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_sdr" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_sdr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_e1dr" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_e1dr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_udr" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_udr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_uir" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_jtag_state_uir"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_clr" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_clr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ena" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ena"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_in_0_" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_in_0_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_in_1_" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_in_1_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_in_2_" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_in_2_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_in_3_" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_in_3_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_in_4_" source="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_in_4_"/>
      </inputs>
      <outputs>
        <port name="tck_usr"/>
        <port name="address[0]"/>
        <port name="address[1]"/>
        <port name="address[2]"/>
        <port name="address[3]"/>
        <port name="address[4]"/>
        <port name="address[5]"/>
        <port name="address[6]"/>
        <port name="address[7]"/>
        <port name="address[8]"/>
        <port name="address[9]"/>
        <port name="address[10]"/>
        <port name="address[11]"/>
        <port name="enable_write"/>
        <port name="data_write[0]"/>
        <port name="data_write[1]"/>
        <port name="data_write[2]"/>
        <port name="data_write[3]"/>
        <port name="data_write[4]"/>
        <port name="data_write[5]"/>
        <port name="data_write[6]"/>
        <port name="data_write[7]"/>
        <port name="data_write[8]"/>
        <port name="data_write[9]"/>
        <port name="data_write[10]"/>
        <port name="data_write[11]"/>
        <port name="data_write[12]"/>
        <port name="data_write[13]"/>
        <port name="data_write[14]"/>
        <port name="data_write[15]"/>
        <port name="data_write[16]"/>
        <port name="data_write[17]"/>
        <port name="data_write[18]"/>
        <port name="data_write[19]"/>
        <port name="data_write[20]"/>
        <port name="data_write[21]"/>
        <port name="data_write[22]"/>
        <port name="data_write[23]"/>
        <port name="data_write[24]"/>
        <port name="data_write[25]"/>
        <port name="data_write[26]"/>
        <port name="data_write[27]"/>
        <port name="data_write[28]"/>
        <port name="data_write[29]"/>
        <port name="data_write[30]"/>
        <port name="data_write[31]"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_out_0_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_out_1_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_out_2_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_out_3_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_ir_out_4_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosx_altsyncram_component_auto_generated_mgl_prim2_tdo"/>
      </outputs>
    </node>
    <node hpath="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|sld_mod_ram_rom:mgl_prim2" instance_id="2" mfg_id="110" node_id="3" sld_node_info="0x8186E02" version="1">
      <parameters>
        <parameter name="SLD_NODE_INFO" type="dec" value="135818752"/>
        <parameter name="SLD_AUTO_INSTANCE_INDEX" type="string" value="yes"/>
        <parameter name="SLD_IP_VERSION" type="dec" value="1"/>
        <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="3"/>
        <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
        <parameter name="width_word" type="unknown" value="32"/>
        <parameter name="numwords" type="unknown" value="4096"/>
        <parameter name="widthad" type="unknown" value="12"/>
        <parameter name="shift_count_bits" type="unknown" value="6"/>
        <parameter name="cvalue" type="unknown" value="00000000000000000000000000000000"/>
        <parameter name="is_data_in_ram" type="unknown" value="1"/>
        <parameter name="is_readable" type="unknown" value="1"/>
        <parameter name="node_name" type="unknown" value="1397313113"/>
      </parameters>
      <inputs>
        <port name="data_read[0]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[0]"/>
        <port name="data_read[1]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[1]"/>
        <port name="data_read[2]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[2]"/>
        <port name="data_read[3]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[3]"/>
        <port name="data_read[4]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[4]"/>
        <port name="data_read[5]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[5]"/>
        <port name="data_read[6]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[6]"/>
        <port name="data_read[7]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[7]"/>
        <port name="data_read[8]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[8]"/>
        <port name="data_read[9]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[9]"/>
        <port name="data_read[10]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[10]"/>
        <port name="data_read[11]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[11]"/>
        <port name="data_read[12]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[12]"/>
        <port name="data_read[13]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[13]"/>
        <port name="data_read[14]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[14]"/>
        <port name="data_read[15]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[15]"/>
        <port name="data_read[16]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[16]"/>
        <port name="data_read[17]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[17]"/>
        <port name="data_read[18]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[18]"/>
        <port name="data_read[19]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[19]"/>
        <port name="data_read[20]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[20]"/>
        <port name="data_read[21]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[21]"/>
        <port name="data_read[22]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[22]"/>
        <port name="data_read[23]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[23]"/>
        <port name="data_read[24]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[24]"/>
        <port name="data_read[25]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[25]"/>
        <port name="data_read[26]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[26]"/>
        <port name="data_read[27]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[27]"/>
        <port name="data_read[28]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[28]"/>
        <port name="data_read[29]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[29]"/>
        <port name="data_read[30]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[30]"/>
        <port name="data_read[31]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|sin_y:siny|altsyncram:altsyncram_component|altsyncram_shi1:auto_generated|altsyncram_j2k2:altsyncram1|q_b[31]"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_raw_tck" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_raw_tck"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_tdi" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_tdi"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_usr1" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_usr1"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_jtag_state_cdr" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_jtag_state_cdr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_jtag_state_sdr" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_jtag_state_sdr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_jtag_state_e1dr" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_jtag_state_e1dr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_jtag_state_udr" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_jtag_state_udr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_jtag_state_uir" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_jtag_state_uir"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_clr" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_clr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ena" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ena"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_in_0_" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_in_0_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_in_1_" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_in_1_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_in_2_" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_in_2_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_in_3_" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_in_3_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_in_4_" source="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_in_4_"/>
      </inputs>
      <outputs>
        <port name="tck_usr"/>
        <port name="address[0]"/>
        <port name="address[1]"/>
        <port name="address[2]"/>
        <port name="address[3]"/>
        <port name="address[4]"/>
        <port name="address[5]"/>
        <port name="address[6]"/>
        <port name="address[7]"/>
        <port name="address[8]"/>
        <port name="address[9]"/>
        <port name="address[10]"/>
        <port name="address[11]"/>
        <port name="enable_write"/>
        <port name="data_write[0]"/>
        <port name="data_write[1]"/>
        <port name="data_write[2]"/>
        <port name="data_write[3]"/>
        <port name="data_write[4]"/>
        <port name="data_write[5]"/>
        <port name="data_write[6]"/>
        <port name="data_write[7]"/>
        <port name="data_write[8]"/>
        <port name="data_write[9]"/>
        <port name="data_write[10]"/>
        <port name="data_write[11]"/>
        <port name="data_write[12]"/>
        <port name="data_write[13]"/>
        <port name="data_write[14]"/>
        <port name="data_write[15]"/>
        <port name="data_write[16]"/>
        <port name="data_write[17]"/>
        <port name="data_write[18]"/>
        <port name="data_write[19]"/>
        <port name="data_write[20]"/>
        <port name="data_write[21]"/>
        <port name="data_write[22]"/>
        <port name="data_write[23]"/>
        <port name="data_write[24]"/>
        <port name="data_write[25]"/>
        <port name="data_write[26]"/>
        <port name="data_write[27]"/>
        <port name="data_write[28]"/>
        <port name="data_write[29]"/>
        <port name="data_write[30]"/>
        <port name="data_write[31]"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_out_0_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_out_1_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_out_2_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_out_3_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_ir_out_4_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_siny_altsyncram_component_auto_generated_mgl_prim2_tdo"/>
      </outputs>
    </node>
    <node hpath="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|sld_mod_ram_rom:mgl_prim2" instance_id="3" mfg_id="110" node_id="3" sld_node_info="0x8186E03" version="1">
      <parameters>
        <parameter name="SLD_NODE_INFO" type="dec" value="135818752"/>
        <parameter name="SLD_AUTO_INSTANCE_INDEX" type="string" value="yes"/>
        <parameter name="SLD_IP_VERSION" type="dec" value="1"/>
        <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="3"/>
        <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
        <parameter name="width_word" type="unknown" value="32"/>
        <parameter name="numwords" type="unknown" value="4096"/>
        <parameter name="widthad" type="unknown" value="12"/>
        <parameter name="shift_count_bits" type="unknown" value="6"/>
        <parameter name="cvalue" type="unknown" value="00000000000000000000000000000000"/>
        <parameter name="is_data_in_ram" type="unknown" value="1"/>
        <parameter name="is_readable" type="unknown" value="1"/>
        <parameter name="node_name" type="unknown" value="1129272153"/>
      </parameters>
      <inputs>
        <port name="data_read[0]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[0]"/>
        <port name="data_read[1]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[1]"/>
        <port name="data_read[2]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[2]"/>
        <port name="data_read[3]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[3]"/>
        <port name="data_read[4]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[4]"/>
        <port name="data_read[5]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[5]"/>
        <port name="data_read[6]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[6]"/>
        <port name="data_read[7]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[7]"/>
        <port name="data_read[8]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[8]"/>
        <port name="data_read[9]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[9]"/>
        <port name="data_read[10]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[10]"/>
        <port name="data_read[11]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[11]"/>
        <port name="data_read[12]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[12]"/>
        <port name="data_read[13]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[13]"/>
        <port name="data_read[14]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[14]"/>
        <port name="data_read[15]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[15]"/>
        <port name="data_read[16]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[16]"/>
        <port name="data_read[17]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[17]"/>
        <port name="data_read[18]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[18]"/>
        <port name="data_read[19]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[19]"/>
        <port name="data_read[20]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[20]"/>
        <port name="data_read[21]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[21]"/>
        <port name="data_read[22]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[22]"/>
        <port name="data_read[23]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[23]"/>
        <port name="data_read[24]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[24]"/>
        <port name="data_read[25]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[25]"/>
        <port name="data_read[26]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[26]"/>
        <port name="data_read[27]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[27]"/>
        <port name="data_read[28]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[28]"/>
        <port name="data_read[29]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[29]"/>
        <port name="data_read[30]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[30]"/>
        <port name="data_read[31]" source="lab3:u0|VGA_LED:vga_led_0|VGA_LED_Emulator:led_emulator|cos_y:cosy|altsyncram:altsyncram_component|altsyncram_dei1:auto_generated|altsyncram_9vj2:altsyncram1|q_b[31]"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_raw_tck" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_raw_tck"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_tdi" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_tdi"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_usr1" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_usr1"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_jtag_state_cdr" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_jtag_state_cdr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_jtag_state_sdr" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_jtag_state_sdr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_jtag_state_e1dr" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_jtag_state_e1dr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_jtag_state_udr" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_jtag_state_udr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_jtag_state_uir" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_jtag_state_uir"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_clr" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_clr"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ena" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ena"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_in_0_" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_in_0_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_in_1_" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_in_1_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_in_2_" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_in_2_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_in_3_" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_in_3_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_in_4_" source="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_in_4_"/>
      </inputs>
      <outputs>
        <port name="tck_usr"/>
        <port name="address[0]"/>
        <port name="address[1]"/>
        <port name="address[2]"/>
        <port name="address[3]"/>
        <port name="address[4]"/>
        <port name="address[5]"/>
        <port name="address[6]"/>
        <port name="address[7]"/>
        <port name="address[8]"/>
        <port name="address[9]"/>
        <port name="address[10]"/>
        <port name="address[11]"/>
        <port name="enable_write"/>
        <port name="data_write[0]"/>
        <port name="data_write[1]"/>
        <port name="data_write[2]"/>
        <port name="data_write[3]"/>
        <port name="data_write[4]"/>
        <port name="data_write[5]"/>
        <port name="data_write[6]"/>
        <port name="data_write[7]"/>
        <port name="data_write[8]"/>
        <port name="data_write[9]"/>
        <port name="data_write[10]"/>
        <port name="data_write[11]"/>
        <port name="data_write[12]"/>
        <port name="data_write[13]"/>
        <port name="data_write[14]"/>
        <port name="data_write[15]"/>
        <port name="data_write[16]"/>
        <port name="data_write[17]"/>
        <port name="data_write[18]"/>
        <port name="data_write[19]"/>
        <port name="data_write[20]"/>
        <port name="data_write[21]"/>
        <port name="data_write[22]"/>
        <port name="data_write[23]"/>
        <port name="data_write[24]"/>
        <port name="data_write[25]"/>
        <port name="data_write[26]"/>
        <port name="data_write[27]"/>
        <port name="data_write[28]"/>
        <port name="data_write[29]"/>
        <port name="data_write[30]"/>
        <port name="data_write[31]"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_out_0_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_out_1_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_out_2_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_out_3_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_ir_out_4_"/>
        <port name="jtag.bp.u0_vga_led_0_led_emulator_cosy_altsyncram_component_auto_generated_mgl_prim2_tdo"/>
      </outputs>
    </node>
    <node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x30006E00" version="6">
      <parameters>
        <parameter name="lpm_type" type="string" value="sld_signaltap"/>
        <parameter name="sld_node_info" type="unknown" value="805334528"/>
        <parameter name="SLD_IP_VERSION" type="dec" value="6"/>
        <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="0"/>
        <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
        <parameter name="sld_data_bits" type="unknown" value="320"/>
        <parameter name="sld_trigger_bits" type="unknown" value="320"/>
        <parameter name="SLD_NODE_CRC_BITS" type="dec" value="32"/>
        <parameter name="sld_node_crc_hiword" type="unknown" value="30993"/>
        <parameter name="sld_node_crc_loword" type="unknown" value="17816"/>
        <parameter name="SLD_INCREMENTAL_ROUTING" type="dec" value="0"/>
        <parameter name="sld_sample_depth" type="unknown" value="128"/>
        <parameter name="sld_segment_size" type="unknown" value="128"/>
        <parameter name="sld_ram_block_type" type="unknown" value="AUTO"/>
        <parameter name="sld_state_bits" type="unknown" value="11"/>
        <parameter name="sld_buffer_full_stop" type="unknown" value="1"/>
        <parameter name="SLD_MEM_ADDRESS_BITS" type="dec" value="7"/>
        <parameter name="SLD_DATA_BIT_CNTR_BITS" type="dec" value="4"/>
        <parameter name="sld_trigger_level" type="unknown" value="1"/>
        <parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
        <parameter name="SLD_HPS_TRIGGER_IN_ENABLED" type="dec" value="0"/>
        <parameter name="SLD_HPS_TRIGGER_OUT_ENABLED" type="dec" value="0"/>
        <parameter name="SLD_HPS_EVENT_ENABLED" type="dec" value="0"/>
        <parameter name="SLD_HPS_EVENT_ID" type="dec" value="0"/>
        <parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
        <parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
        <parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
        <parameter name="SLD_ADVANCED_TRIGGER_1" type="string" value="NONE"/>
        <parameter name="SLD_ADVANCED_TRIGGER_2" type="string" value="NONE"/>
        <parameter name="SLD_ADVANCED_TRIGGER_3" type="string" value="NONE"/>
        <parameter name="SLD_ADVANCED_TRIGGER_4" type="string" value="NONE"/>
        <parameter name="SLD_ADVANCED_TRIGGER_5" type="string" value="NONE"/>
        <parameter name="SLD_ADVANCED_TRIGGER_6" type="string" value="NONE"/>
        <parameter name="SLD_ADVANCED_TRIGGER_7" type="string" value="NONE"/>
        <parameter name="SLD_ADVANCED_TRIGGER_8" type="string" value="NONE"/>
        <parameter name="SLD_ADVANCED_TRIGGER_9" type="string" value="NONE"/>
        <parameter name="SLD_ADVANCED_TRIGGER_10" type="string" value="NONE"/>
        <parameter name="sld_inversion_mask_length" type="unknown" value="981"/>
        <parameter name="sld_inversion_mask" type="unknown" value="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <parameter name="sld_power_up_trigger" type="unknown" value="0"/>
        <parameter name="SLD_STATE_FLOW_MGR_ENTITY" type="string" value="state_flow_mgr_entity.vhd"/>
        <parameter name="sld_state_flow_use_generated" type="unknown" value="0"/>
        <parameter name="sld_current_resource_width" type="unknown" value="1"/>
        <parameter name="sld_attribute_mem_mode" type="unknown" value="OFF"/>
        <parameter name="SLD_STORAGE_QUALIFIER_BITS" type="dec" value="1"/>
        <parameter name="SLD_STORAGE_QUALIFIER_GAP_RECORD" type="dec" value="0"/>
        <parameter name="SLD_STORAGE_QUALIFIER_MODE" type="string" value="OFF"/>
        <parameter name="SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION" type="dec" value="0"/>
        <parameter name="sld_storage_qualifier_inversion_mask_length" type="unknown" value="0"/>
        <parameter name="SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY" type="string" value="basic"/>
        <parameter name="SLD_STORAGE_QUALIFIER_PIPELINE" type="dec" value="0"/>
      </parameters>
      <inputs/>
      <outputs/>
    </node>
  </node_info>
  <sld_infos>
    <sld_info hpath="lab3:u0" name="u0">
      <assignment_values>
        <assignment_value text="QSYS_NAME lab3 HAS_SOPCINFO 1 GENERATION_ID 1398879777"/>
      </assignment_values>
      <parameters/>
    </sld_info>
  </sld_infos>
</sld_project_info>
