// DDR3_test_s0_mm_interconnect_0.v

// This file was auto-generated from altera_merlin_interconnect_wrapper_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 13.1.1 166 at 2014.04.03.21:21:38

`timescale 1 ps / 1 ps
module DDR3_test_s0_mm_interconnect_0 (
		input  wire        avl_clk_out_clk_clk,                          //                        avl_clk_out_clk.clk
		input  wire        cpu_inst_reset_n_reset_bridge_in_reset_reset, // cpu_inst_reset_n_reset_bridge_in_reset.reset
		input  wire [19:0] cpu_inst_data_master_address,                 //                   cpu_inst_data_master.address
		output wire        cpu_inst_data_master_waitrequest,             //                                       .waitrequest
		input  wire [3:0]  cpu_inst_data_master_byteenable,              //                                       .byteenable
		input  wire        cpu_inst_data_master_read,                    //                                       .read
		output wire [31:0] cpu_inst_data_master_readdata,                //                                       .readdata
		input  wire        cpu_inst_data_master_write,                   //                                       .write
		input  wire [31:0] cpu_inst_data_master_writedata,               //                                       .writedata
		input  wire [16:0] cpu_inst_instruction_master_address,          //            cpu_inst_instruction_master.address
		output wire        cpu_inst_instruction_master_waitrequest,      //                                       .waitrequest
		input  wire        cpu_inst_instruction_master_read,             //                                       .read
		output wire [31:0] cpu_inst_instruction_master_readdata,         //                                       .readdata
		input  wire [31:0] seq_bridge_m0_address,                        //                          seq_bridge_m0.address
		output wire        seq_bridge_m0_waitrequest,                    //                                       .waitrequest
		input  wire [0:0]  seq_bridge_m0_burstcount,                     //                                       .burstcount
		input  wire [3:0]  seq_bridge_m0_byteenable,                     //                                       .byteenable
		input  wire        seq_bridge_m0_read,                           //                                       .read
		output wire [31:0] seq_bridge_m0_readdata,                       //                                       .readdata
		output wire        seq_bridge_m0_readdatavalid,                  //                                       .readdatavalid
		input  wire        seq_bridge_m0_write,                          //                                       .write
		input  wire [31:0] seq_bridge_m0_writedata,                      //                                       .writedata
		input  wire        seq_bridge_m0_debugaccess,                    //                                       .debugaccess
		output wire [12:0] sequencer_data_mgr_inst_avl_address,          //            sequencer_data_mgr_inst_avl.address
		output wire        sequencer_data_mgr_inst_avl_write,            //                                       .write
		output wire        sequencer_data_mgr_inst_avl_read,             //                                       .read
		input  wire [31:0] sequencer_data_mgr_inst_avl_readdata,         //                                       .readdata
		output wire [31:0] sequencer_data_mgr_inst_avl_writedata,        //                                       .writedata
		input  wire        sequencer_data_mgr_inst_avl_waitrequest,      //                                       .waitrequest
		output wire [11:0] sequencer_mem_s1_address,                     //                       sequencer_mem_s1.address
		output wire        sequencer_mem_s1_write,                       //                                       .write
		input  wire [31:0] sequencer_mem_s1_readdata,                    //                                       .readdata
		output wire [31:0] sequencer_mem_s1_writedata,                   //                                       .writedata
		output wire [3:0]  sequencer_mem_s1_byteenable,                  //                                       .byteenable
		output wire        sequencer_mem_s1_chipselect,                  //                                       .chipselect
		output wire [12:0] sequencer_phy_mgr_inst_avl_address,           //             sequencer_phy_mgr_inst_avl.address
		output wire        sequencer_phy_mgr_inst_avl_write,             //                                       .write
		output wire        sequencer_phy_mgr_inst_avl_read,              //                                       .read
		input  wire [31:0] sequencer_phy_mgr_inst_avl_readdata,          //                                       .readdata
		output wire [31:0] sequencer_phy_mgr_inst_avl_writedata,         //                                       .writedata
		input  wire        sequencer_phy_mgr_inst_avl_waitrequest,       //                                       .waitrequest
		output wire [3:0]  sequencer_reg_file_inst_avl_address,          //            sequencer_reg_file_inst_avl.address
		output wire        sequencer_reg_file_inst_avl_write,            //                                       .write
		output wire        sequencer_reg_file_inst_avl_read,             //                                       .read
		input  wire [31:0] sequencer_reg_file_inst_avl_readdata,         //                                       .readdata
		output wire [31:0] sequencer_reg_file_inst_avl_writedata,        //                                       .writedata
		output wire [3:0]  sequencer_reg_file_inst_avl_byteenable,       //                                       .byteenable
		input  wire        sequencer_reg_file_inst_avl_waitrequest,      //                                       .waitrequest
		output wire [12:0] sequencer_rw_mgr_inst_avl_address,            //              sequencer_rw_mgr_inst_avl.address
		output wire        sequencer_rw_mgr_inst_avl_write,              //                                       .write
		output wire        sequencer_rw_mgr_inst_avl_read,               //                                       .read
		input  wire [31:0] sequencer_rw_mgr_inst_avl_readdata,           //                                       .readdata
		output wire [31:0] sequencer_rw_mgr_inst_avl_writedata,          //                                       .writedata
		input  wire        sequencer_rw_mgr_inst_avl_waitrequest,        //                                       .waitrequest
		output wire [12:0] sequencer_scc_mgr_inst_avl_address,           //             sequencer_scc_mgr_inst_avl.address
		output wire        sequencer_scc_mgr_inst_avl_write,             //                                       .write
		output wire        sequencer_scc_mgr_inst_avl_read,              //                                       .read
		input  wire [31:0] sequencer_scc_mgr_inst_avl_readdata,          //                                       .readdata
		output wire [31:0] sequencer_scc_mgr_inst_avl_writedata,         //                                       .writedata
		input  wire        sequencer_scc_mgr_inst_avl_waitrequest        //                                       .waitrequest
	);

	wire          cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest;                            // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
	wire    [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount;                             // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata;                              // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_address;                                // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_address
	wire          cpu_inst_data_master_translator_avalon_universal_master_0_lock;                                   // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_lock
	wire          cpu_inst_data_master_translator_avalon_universal_master_0_write;                                  // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_write
	wire          cpu_inst_data_master_translator_avalon_universal_master_0_read;                                   // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_read
	wire   [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata;                               // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
	wire          cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess;                            // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable;                             // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire          cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid;                          // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
	wire          rsp_xbar_mux_src_endofpacket;                                                                     // rsp_xbar_mux:src_endofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          rsp_xbar_mux_src_valid;                                                                           // rsp_xbar_mux:src_valid -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_valid
	wire          rsp_xbar_mux_src_startofpacket;                                                                   // rsp_xbar_mux:src_startofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [107:0] rsp_xbar_mux_src_data;                                                                            // rsp_xbar_mux:src_data -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_data
	wire    [5:0] rsp_xbar_mux_src_channel;                                                                         // rsp_xbar_mux:src_channel -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_channel
	wire          rsp_xbar_mux_src_ready;                                                                           // cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
	wire          seq_bridge_m0_translator_avalon_universal_master_0_waitrequest;                                   // seq_bridge_m0_translator_avalon_universal_master_0_agent:av_waitrequest -> seq_bridge_m0_translator:uav_waitrequest
	wire    [2:0] seq_bridge_m0_translator_avalon_universal_master_0_burstcount;                                    // seq_bridge_m0_translator:uav_burstcount -> seq_bridge_m0_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [31:0] seq_bridge_m0_translator_avalon_universal_master_0_writedata;                                     // seq_bridge_m0_translator:uav_writedata -> seq_bridge_m0_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] seq_bridge_m0_translator_avalon_universal_master_0_address;                                       // seq_bridge_m0_translator:uav_address -> seq_bridge_m0_translator_avalon_universal_master_0_agent:av_address
	wire          seq_bridge_m0_translator_avalon_universal_master_0_lock;                                          // seq_bridge_m0_translator:uav_lock -> seq_bridge_m0_translator_avalon_universal_master_0_agent:av_lock
	wire          seq_bridge_m0_translator_avalon_universal_master_0_write;                                         // seq_bridge_m0_translator:uav_write -> seq_bridge_m0_translator_avalon_universal_master_0_agent:av_write
	wire          seq_bridge_m0_translator_avalon_universal_master_0_read;                                          // seq_bridge_m0_translator:uav_read -> seq_bridge_m0_translator_avalon_universal_master_0_agent:av_read
	wire   [31:0] seq_bridge_m0_translator_avalon_universal_master_0_readdata;                                      // seq_bridge_m0_translator_avalon_universal_master_0_agent:av_readdata -> seq_bridge_m0_translator:uav_readdata
	wire          seq_bridge_m0_translator_avalon_universal_master_0_debugaccess;                                   // seq_bridge_m0_translator:uav_debugaccess -> seq_bridge_m0_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [3:0] seq_bridge_m0_translator_avalon_universal_master_0_byteenable;                                    // seq_bridge_m0_translator:uav_byteenable -> seq_bridge_m0_translator_avalon_universal_master_0_agent:av_byteenable
	wire          seq_bridge_m0_translator_avalon_universal_master_0_readdatavalid;                                 // seq_bridge_m0_translator_avalon_universal_master_0_agent:av_readdatavalid -> seq_bridge_m0_translator:uav_readdatavalid
	wire          cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest;                     // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_instruction_master_translator:uav_waitrequest
	wire    [2:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount;                      // cpu_inst_instruction_master_translator:uav_burstcount -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata;                       // cpu_inst_instruction_master_translator:uav_writedata -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_address;                         // cpu_inst_instruction_master_translator:uav_address -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_address
	wire          cpu_inst_instruction_master_translator_avalon_universal_master_0_lock;                            // cpu_inst_instruction_master_translator:uav_lock -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_lock
	wire          cpu_inst_instruction_master_translator_avalon_universal_master_0_write;                           // cpu_inst_instruction_master_translator:uav_write -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_write
	wire          cpu_inst_instruction_master_translator_avalon_universal_master_0_read;                            // cpu_inst_instruction_master_translator:uav_read -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_read
	wire   [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata;                        // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_instruction_master_translator:uav_readdata
	wire          cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess;                     // cpu_inst_instruction_master_translator:uav_debugaccess -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [3:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable;                      // cpu_inst_instruction_master_translator:uav_byteenable -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire          cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid;                   // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_instruction_master_translator:uav_readdatavalid
	wire          rsp_xbar_mux_002_src_endofpacket;                                                                 // rsp_xbar_mux_002:src_endofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          rsp_xbar_mux_002_src_valid;                                                                       // rsp_xbar_mux_002:src_valid -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
	wire          rsp_xbar_mux_002_src_startofpacket;                                                               // rsp_xbar_mux_002:src_startofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [107:0] rsp_xbar_mux_002_src_data;                                                                        // rsp_xbar_mux_002:src_data -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_data
	wire    [5:0] rsp_xbar_mux_002_src_channel;                                                                     // rsp_xbar_mux_002:src_channel -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
	wire          rsp_xbar_mux_002_src_ready;                                                                       // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_002:src_ready
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;              // sequencer_phy_mgr_inst_avl_translator:uav_waitrequest -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;               // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_phy_mgr_inst_avl_translator:uav_burstcount
	wire   [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata;                // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_phy_mgr_inst_avl_translator:uav_writedata
	wire   [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address;                  // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_phy_mgr_inst_avl_translator:uav_address
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write;                    // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_phy_mgr_inst_avl_translator:uav_write
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock;                     // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_phy_mgr_inst_avl_translator:uav_lock
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read;                     // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_phy_mgr_inst_avl_translator:uav_read
	wire   [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                 // sequencer_phy_mgr_inst_avl_translator:uav_readdata -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;            // sequencer_phy_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;              // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_phy_mgr_inst_avl_translator:uav_debugaccess
	wire    [3:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;               // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_phy_mgr_inst_avl_translator:uav_byteenable
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;       // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;             // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;     // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [108:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data;              // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;             // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;    // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;          // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;  // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [108:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;           // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;          // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;        // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;         // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;        // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_xbar_mux_src_endofpacket;                                                                     // cmd_xbar_mux:src_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          cmd_xbar_mux_src_valid;                                                                           // cmd_xbar_mux:src_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire          cmd_xbar_mux_src_startofpacket;                                                                   // cmd_xbar_mux:src_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [107:0] cmd_xbar_mux_src_data;                                                                            // cmd_xbar_mux:src_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire    [5:0] cmd_xbar_mux_src_channel;                                                                         // cmd_xbar_mux:src_channel -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_xbar_mux_src_ready;                                                                           // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;             // sequencer_data_mgr_inst_avl_translator:uav_waitrequest -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;              // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_data_mgr_inst_avl_translator:uav_burstcount
	wire   [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata;               // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_data_mgr_inst_avl_translator:uav_writedata
	wire   [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address;                 // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_data_mgr_inst_avl_translator:uav_address
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write;                   // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_data_mgr_inst_avl_translator:uav_write
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock;                    // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_data_mgr_inst_avl_translator:uav_lock
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read;                    // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_data_mgr_inst_avl_translator:uav_read
	wire   [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                // sequencer_data_mgr_inst_avl_translator:uav_readdata -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;           // sequencer_data_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;             // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_data_mgr_inst_avl_translator:uav_debugaccess
	wire    [3:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;              // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_data_mgr_inst_avl_translator:uav_byteenable
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;      // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;            // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;    // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [108:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data;             // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;            // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;   // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;         // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [108:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;          // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;         // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;       // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;        // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;       // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_xbar_mux_001_src_endofpacket;                                                                 // cmd_xbar_mux_001:src_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          cmd_xbar_mux_001_src_valid;                                                                       // cmd_xbar_mux_001:src_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire          cmd_xbar_mux_001_src_startofpacket;                                                               // cmd_xbar_mux_001:src_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [107:0] cmd_xbar_mux_001_src_data;                                                                        // cmd_xbar_mux_001:src_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire    [5:0] cmd_xbar_mux_001_src_channel;                                                                     // cmd_xbar_mux_001:src_channel -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_xbar_mux_001_src_ready;                                                                       // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;               // sequencer_rw_mgr_inst_avl_translator:uav_waitrequest -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;                // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_rw_mgr_inst_avl_translator:uav_burstcount
	wire   [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata;                 // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_rw_mgr_inst_avl_translator:uav_writedata
	wire   [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address;                   // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_rw_mgr_inst_avl_translator:uav_address
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write;                     // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_rw_mgr_inst_avl_translator:uav_write
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock;                      // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_rw_mgr_inst_avl_translator:uav_lock
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read;                      // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_rw_mgr_inst_avl_translator:uav_read
	wire   [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                  // sequencer_rw_mgr_inst_avl_translator:uav_readdata -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;             // sequencer_rw_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;               // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_rw_mgr_inst_avl_translator:uav_debugaccess
	wire    [3:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;                // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_rw_mgr_inst_avl_translator:uav_byteenable
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;        // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;              // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;      // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [108:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data;               // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;              // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;     // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;           // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;   // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [108:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;            // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;           // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;         // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;          // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;         // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_xbar_mux_002_src_endofpacket;                                                                 // cmd_xbar_mux_002:src_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          cmd_xbar_mux_002_src_valid;                                                                       // cmd_xbar_mux_002:src_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire          cmd_xbar_mux_002_src_startofpacket;                                                               // cmd_xbar_mux_002:src_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [107:0] cmd_xbar_mux_002_src_data;                                                                        // cmd_xbar_mux_002:src_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire    [5:0] cmd_xbar_mux_002_src_channel;                                                                     // cmd_xbar_mux_002:src_channel -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_xbar_mux_002_src_ready;                                                                       // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_002:src_ready
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                        // sequencer_mem_s1_translator:uav_waitrequest -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                         // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_mem_s1_translator:uav_burstcount
	wire   [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                          // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_mem_s1_translator:uav_writedata
	wire   [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address;                            // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_mem_s1_translator:uav_address
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write;                              // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_mem_s1_translator:uav_write
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock;                               // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_mem_s1_translator:uav_lock
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read;                               // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_mem_s1_translator:uav_read
	wire   [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                           // sequencer_mem_s1_translator:uav_readdata -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                      // sequencer_mem_s1_translator:uav_readdatavalid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                        // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_mem_s1_translator:uav_debugaccess
	wire    [3:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                         // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_mem_s1_translator:uav_byteenable
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                 // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                       // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;               // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [108:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                        // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                       // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;              // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                    // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;            // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [108:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                     // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                    // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                  // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                   // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                  // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_xbar_mux_003_src_endofpacket;                                                                 // cmd_xbar_mux_003:src_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          cmd_xbar_mux_003_src_valid;                                                                       // cmd_xbar_mux_003:src_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire          cmd_xbar_mux_003_src_startofpacket;                                                               // cmd_xbar_mux_003:src_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [107:0] cmd_xbar_mux_003_src_data;                                                                        // cmd_xbar_mux_003:src_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire    [5:0] cmd_xbar_mux_003_src_channel;                                                                     // cmd_xbar_mux_003:src_channel -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_xbar_mux_003_src_ready;                                                                       // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_003:src_ready
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;              // sequencer_scc_mgr_inst_avl_translator:uav_waitrequest -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;               // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_scc_mgr_inst_avl_translator:uav_burstcount
	wire   [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata;                // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_scc_mgr_inst_avl_translator:uav_writedata
	wire   [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address;                  // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_scc_mgr_inst_avl_translator:uav_address
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write;                    // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_scc_mgr_inst_avl_translator:uav_write
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock;                     // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_scc_mgr_inst_avl_translator:uav_lock
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read;                     // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_scc_mgr_inst_avl_translator:uav_read
	wire   [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                 // sequencer_scc_mgr_inst_avl_translator:uav_readdata -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;            // sequencer_scc_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;              // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_scc_mgr_inst_avl_translator:uav_debugaccess
	wire    [3:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;               // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_scc_mgr_inst_avl_translator:uav_byteenable
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;       // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;             // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;     // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [108:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data;              // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;             // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;    // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;          // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;  // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [108:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;           // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;          // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;        // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;         // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;        // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_xbar_mux_004_src_endofpacket;                                                                 // cmd_xbar_mux_004:src_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          cmd_xbar_mux_004_src_valid;                                                                       // cmd_xbar_mux_004:src_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire          cmd_xbar_mux_004_src_startofpacket;                                                               // cmd_xbar_mux_004:src_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [107:0] cmd_xbar_mux_004_src_data;                                                                        // cmd_xbar_mux_004:src_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire    [5:0] cmd_xbar_mux_004_src_channel;                                                                     // cmd_xbar_mux_004:src_channel -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_xbar_mux_004_src_ready;                                                                       // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_004:src_ready
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;             // sequencer_reg_file_inst_avl_translator:uav_waitrequest -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;              // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_reg_file_inst_avl_translator:uav_burstcount
	wire   [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata;               // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_reg_file_inst_avl_translator:uav_writedata
	wire   [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address;                 // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_reg_file_inst_avl_translator:uav_address
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write;                   // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_reg_file_inst_avl_translator:uav_write
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock;                    // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_reg_file_inst_avl_translator:uav_lock
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read;                    // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_reg_file_inst_avl_translator:uav_read
	wire   [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                // sequencer_reg_file_inst_avl_translator:uav_readdata -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;           // sequencer_reg_file_inst_avl_translator:uav_readdatavalid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;             // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_reg_file_inst_avl_translator:uav_debugaccess
	wire    [3:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;              // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_reg_file_inst_avl_translator:uav_byteenable
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;      // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;            // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;    // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [108:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data;             // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;            // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;   // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;         // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [108:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;          // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;         // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;       // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;        // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;       // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          cmd_xbar_mux_005_src_endofpacket;                                                                 // cmd_xbar_mux_005:src_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          cmd_xbar_mux_005_src_valid;                                                                       // cmd_xbar_mux_005:src_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire          cmd_xbar_mux_005_src_startofpacket;                                                               // cmd_xbar_mux_005:src_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [107:0] cmd_xbar_mux_005_src_data;                                                                        // cmd_xbar_mux_005:src_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire    [5:0] cmd_xbar_mux_005_src_channel;                                                                     // cmd_xbar_mux_005:src_channel -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_xbar_mux_005_src_ready;                                                                       // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_005:src_ready
	wire          cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket;                   // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
	wire          cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid;                         // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
	wire          cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket;                 // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
	wire  [107:0] cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data;                          // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
	wire          cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready;                         // addr_router:sink_ready -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_ready
	wire          addr_router_src_endofpacket;                                                                      // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
	wire          addr_router_src_valid;                                                                            // addr_router:src_valid -> cmd_xbar_demux:sink_valid
	wire          addr_router_src_startofpacket;                                                                    // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
	wire  [107:0] addr_router_src_data;                                                                             // addr_router:src_data -> cmd_xbar_demux:sink_data
	wire    [5:0] addr_router_src_channel;                                                                          // addr_router:src_channel -> cmd_xbar_demux:sink_channel
	wire          addr_router_src_ready;                                                                            // cmd_xbar_demux:sink_ready -> addr_router:src_ready
	wire          seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket;                          // seq_bridge_m0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
	wire          seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid;                                // seq_bridge_m0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
	wire          seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket;                        // seq_bridge_m0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
	wire  [107:0] seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_data;                                 // seq_bridge_m0_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
	wire          seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready;                                // addr_router_001:sink_ready -> seq_bridge_m0_translator_avalon_universal_master_0_agent:cp_ready
	wire          cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket;            // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
	wire          cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid;                  // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
	wire          cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket;          // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
	wire  [107:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data;                   // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
	wire          cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready;                  // addr_router_002:sink_ready -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
	wire          addr_router_002_src_endofpacket;                                                                  // addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
	wire          addr_router_002_src_valid;                                                                        // addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
	wire          addr_router_002_src_startofpacket;                                                                // addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
	wire  [107:0] addr_router_002_src_data;                                                                         // addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
	wire    [5:0] addr_router_002_src_channel;                                                                      // addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
	wire          addr_router_002_src_ready;                                                                        // cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;              // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid;                    // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;            // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
	wire  [107:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data;                     // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
	wire          sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready;                    // id_router:sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire          id_router_src_endofpacket;                                                                        // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
	wire          id_router_src_valid;                                                                              // id_router:src_valid -> rsp_xbar_demux:sink_valid
	wire          id_router_src_startofpacket;                                                                      // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
	wire  [107:0] id_router_src_data;                                                                               // id_router:src_data -> rsp_xbar_demux:sink_data
	wire    [5:0] id_router_src_channel;                                                                            // id_router:src_channel -> rsp_xbar_demux:sink_channel
	wire          id_router_src_ready;                                                                              // rsp_xbar_demux:sink_ready -> id_router:src_ready
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;             // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid;                   // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;           // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
	wire  [107:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data;                    // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
	wire          sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready;                   // id_router_001:sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire          id_router_001_src_endofpacket;                                                                    // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
	wire          id_router_001_src_valid;                                                                          // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
	wire          id_router_001_src_startofpacket;                                                                  // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
	wire  [107:0] id_router_001_src_data;                                                                           // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
	wire    [5:0] id_router_001_src_channel;                                                                        // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
	wire          id_router_001_src_ready;                                                                          // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;               // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid;                     // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;             // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
	wire  [107:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data;                      // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
	wire          sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready;                     // id_router_002:sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire          id_router_002_src_endofpacket;                                                                    // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
	wire          id_router_002_src_valid;                                                                          // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
	wire          id_router_002_src_startofpacket;                                                                  // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
	wire  [107:0] id_router_002_src_data;                                                                           // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
	wire    [5:0] id_router_002_src_channel;                                                                        // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
	wire          id_router_002_src_ready;                                                                          // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                        // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid;                              // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                      // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
	wire  [107:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data;                               // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
	wire          sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready;                              // id_router_003:sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire          id_router_003_src_endofpacket;                                                                    // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
	wire          id_router_003_src_valid;                                                                          // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
	wire          id_router_003_src_startofpacket;                                                                  // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
	wire  [107:0] id_router_003_src_data;                                                                           // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
	wire    [5:0] id_router_003_src_channel;                                                                        // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
	wire          id_router_003_src_ready;                                                                          // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;              // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid;                    // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;            // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
	wire  [107:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data;                     // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
	wire          sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready;                    // id_router_004:sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire          id_router_004_src_endofpacket;                                                                    // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
	wire          id_router_004_src_valid;                                                                          // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
	wire          id_router_004_src_startofpacket;                                                                  // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
	wire  [107:0] id_router_004_src_data;                                                                           // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
	wire    [5:0] id_router_004_src_channel;                                                                        // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
	wire          id_router_004_src_ready;                                                                          // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;             // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid;                   // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;           // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
	wire  [107:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data;                    // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
	wire          sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready;                   // id_router_005:sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire          id_router_005_src_endofpacket;                                                                    // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
	wire          id_router_005_src_valid;                                                                          // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
	wire          id_router_005_src_startofpacket;                                                                  // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
	wire  [107:0] id_router_005_src_data;                                                                           // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
	wire    [5:0] id_router_005_src_channel;                                                                        // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
	wire          id_router_005_src_ready;                                                                          // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
	wire          addr_router_001_src_endofpacket;                                                                  // addr_router_001:src_endofpacket -> limiter:cmd_sink_endofpacket
	wire          addr_router_001_src_valid;                                                                        // addr_router_001:src_valid -> limiter:cmd_sink_valid
	wire          addr_router_001_src_startofpacket;                                                                // addr_router_001:src_startofpacket -> limiter:cmd_sink_startofpacket
	wire  [107:0] addr_router_001_src_data;                                                                         // addr_router_001:src_data -> limiter:cmd_sink_data
	wire    [5:0] addr_router_001_src_channel;                                                                      // addr_router_001:src_channel -> limiter:cmd_sink_channel
	wire          addr_router_001_src_ready;                                                                        // limiter:cmd_sink_ready -> addr_router_001:src_ready
	wire          limiter_cmd_src_endofpacket;                                                                      // limiter:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
	wire          limiter_cmd_src_startofpacket;                                                                    // limiter:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
	wire  [107:0] limiter_cmd_src_data;                                                                             // limiter:cmd_src_data -> cmd_xbar_demux_001:sink_data
	wire    [5:0] limiter_cmd_src_channel;                                                                          // limiter:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
	wire          limiter_cmd_src_ready;                                                                            // cmd_xbar_demux_001:sink_ready -> limiter:cmd_src_ready
	wire          rsp_xbar_mux_001_src_endofpacket;                                                                 // rsp_xbar_mux_001:src_endofpacket -> limiter:rsp_sink_endofpacket
	wire          rsp_xbar_mux_001_src_valid;                                                                       // rsp_xbar_mux_001:src_valid -> limiter:rsp_sink_valid
	wire          rsp_xbar_mux_001_src_startofpacket;                                                               // rsp_xbar_mux_001:src_startofpacket -> limiter:rsp_sink_startofpacket
	wire  [107:0] rsp_xbar_mux_001_src_data;                                                                        // rsp_xbar_mux_001:src_data -> limiter:rsp_sink_data
	wire    [5:0] rsp_xbar_mux_001_src_channel;                                                                     // rsp_xbar_mux_001:src_channel -> limiter:rsp_sink_channel
	wire          rsp_xbar_mux_001_src_ready;                                                                       // limiter:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
	wire          limiter_rsp_src_endofpacket;                                                                      // limiter:rsp_src_endofpacket -> seq_bridge_m0_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          limiter_rsp_src_valid;                                                                            // limiter:rsp_src_valid -> seq_bridge_m0_translator_avalon_universal_master_0_agent:rp_valid
	wire          limiter_rsp_src_startofpacket;                                                                    // limiter:rsp_src_startofpacket -> seq_bridge_m0_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [107:0] limiter_rsp_src_data;                                                                             // limiter:rsp_src_data -> seq_bridge_m0_translator_avalon_universal_master_0_agent:rp_data
	wire    [5:0] limiter_rsp_src_channel;                                                                          // limiter:rsp_src_channel -> seq_bridge_m0_translator_avalon_universal_master_0_agent:rp_channel
	wire          limiter_rsp_src_ready;                                                                            // seq_bridge_m0_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
	wire          cmd_xbar_demux_src0_endofpacket;                                                                  // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
	wire          cmd_xbar_demux_src0_valid;                                                                        // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
	wire          cmd_xbar_demux_src0_startofpacket;                                                                // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
	wire  [107:0] cmd_xbar_demux_src0_data;                                                                         // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
	wire    [5:0] cmd_xbar_demux_src0_channel;                                                                      // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
	wire          cmd_xbar_demux_src0_ready;                                                                        // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
	wire          cmd_xbar_demux_src1_endofpacket;                                                                  // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
	wire          cmd_xbar_demux_src1_valid;                                                                        // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
	wire          cmd_xbar_demux_src1_startofpacket;                                                                // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
	wire  [107:0] cmd_xbar_demux_src1_data;                                                                         // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
	wire    [5:0] cmd_xbar_demux_src1_channel;                                                                      // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
	wire          cmd_xbar_demux_src1_ready;                                                                        // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
	wire          cmd_xbar_demux_src2_endofpacket;                                                                  // cmd_xbar_demux:src2_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
	wire          cmd_xbar_demux_src2_valid;                                                                        // cmd_xbar_demux:src2_valid -> cmd_xbar_mux_002:sink0_valid
	wire          cmd_xbar_demux_src2_startofpacket;                                                                // cmd_xbar_demux:src2_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
	wire  [107:0] cmd_xbar_demux_src2_data;                                                                         // cmd_xbar_demux:src2_data -> cmd_xbar_mux_002:sink0_data
	wire    [5:0] cmd_xbar_demux_src2_channel;                                                                      // cmd_xbar_demux:src2_channel -> cmd_xbar_mux_002:sink0_channel
	wire          cmd_xbar_demux_src2_ready;                                                                        // cmd_xbar_mux_002:sink0_ready -> cmd_xbar_demux:src2_ready
	wire          cmd_xbar_demux_src3_endofpacket;                                                                  // cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
	wire          cmd_xbar_demux_src3_valid;                                                                        // cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
	wire          cmd_xbar_demux_src3_startofpacket;                                                                // cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
	wire  [107:0] cmd_xbar_demux_src3_data;                                                                         // cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
	wire    [5:0] cmd_xbar_demux_src3_channel;                                                                      // cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
	wire          cmd_xbar_demux_src3_ready;                                                                        // cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
	wire          cmd_xbar_demux_src4_endofpacket;                                                                  // cmd_xbar_demux:src4_endofpacket -> cmd_xbar_mux_004:sink0_endofpacket
	wire          cmd_xbar_demux_src4_valid;                                                                        // cmd_xbar_demux:src4_valid -> cmd_xbar_mux_004:sink0_valid
	wire          cmd_xbar_demux_src4_startofpacket;                                                                // cmd_xbar_demux:src4_startofpacket -> cmd_xbar_mux_004:sink0_startofpacket
	wire  [107:0] cmd_xbar_demux_src4_data;                                                                         // cmd_xbar_demux:src4_data -> cmd_xbar_mux_004:sink0_data
	wire    [5:0] cmd_xbar_demux_src4_channel;                                                                      // cmd_xbar_demux:src4_channel -> cmd_xbar_mux_004:sink0_channel
	wire          cmd_xbar_demux_src4_ready;                                                                        // cmd_xbar_mux_004:sink0_ready -> cmd_xbar_demux:src4_ready
	wire          cmd_xbar_demux_src5_endofpacket;                                                                  // cmd_xbar_demux:src5_endofpacket -> cmd_xbar_mux_005:sink0_endofpacket
	wire          cmd_xbar_demux_src5_valid;                                                                        // cmd_xbar_demux:src5_valid -> cmd_xbar_mux_005:sink0_valid
	wire          cmd_xbar_demux_src5_startofpacket;                                                                // cmd_xbar_demux:src5_startofpacket -> cmd_xbar_mux_005:sink0_startofpacket
	wire  [107:0] cmd_xbar_demux_src5_data;                                                                         // cmd_xbar_demux:src5_data -> cmd_xbar_mux_005:sink0_data
	wire    [5:0] cmd_xbar_demux_src5_channel;                                                                      // cmd_xbar_demux:src5_channel -> cmd_xbar_mux_005:sink0_channel
	wire          cmd_xbar_demux_src5_ready;                                                                        // cmd_xbar_mux_005:sink0_ready -> cmd_xbar_demux:src5_ready
	wire          cmd_xbar_demux_001_src0_endofpacket;                                                              // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
	wire          cmd_xbar_demux_001_src0_valid;                                                                    // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux_003:sink1_valid
	wire          cmd_xbar_demux_001_src0_startofpacket;                                                            // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
	wire  [107:0] cmd_xbar_demux_001_src0_data;                                                                     // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux_003:sink1_data
	wire    [5:0] cmd_xbar_demux_001_src0_channel;                                                                  // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux_003:sink1_channel
	wire          cmd_xbar_demux_001_src0_ready;                                                                    // cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src0_ready
	wire          cmd_xbar_demux_001_src1_endofpacket;                                                              // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_005:sink1_endofpacket
	wire          cmd_xbar_demux_001_src1_valid;                                                                    // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_005:sink1_valid
	wire          cmd_xbar_demux_001_src1_startofpacket;                                                            // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_005:sink1_startofpacket
	wire  [107:0] cmd_xbar_demux_001_src1_data;                                                                     // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_005:sink1_data
	wire    [5:0] cmd_xbar_demux_001_src1_channel;                                                                  // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_005:sink1_channel
	wire          cmd_xbar_demux_001_src1_ready;                                                                    // cmd_xbar_mux_005:sink1_ready -> cmd_xbar_demux_001:src1_ready
	wire          cmd_xbar_demux_002_src0_endofpacket;                                                              // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux_003:sink2_endofpacket
	wire          cmd_xbar_demux_002_src0_valid;                                                                    // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux_003:sink2_valid
	wire          cmd_xbar_demux_002_src0_startofpacket;                                                            // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux_003:sink2_startofpacket
	wire  [107:0] cmd_xbar_demux_002_src0_data;                                                                     // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux_003:sink2_data
	wire    [5:0] cmd_xbar_demux_002_src0_channel;                                                                  // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux_003:sink2_channel
	wire          cmd_xbar_demux_002_src0_ready;                                                                    // cmd_xbar_mux_003:sink2_ready -> cmd_xbar_demux_002:src0_ready
	wire          rsp_xbar_demux_src0_endofpacket;                                                                  // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
	wire          rsp_xbar_demux_src0_valid;                                                                        // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
	wire          rsp_xbar_demux_src0_startofpacket;                                                                // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
	wire  [107:0] rsp_xbar_demux_src0_data;                                                                         // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
	wire    [5:0] rsp_xbar_demux_src0_channel;                                                                      // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
	wire          rsp_xbar_demux_src0_ready;                                                                        // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
	wire          rsp_xbar_demux_001_src0_endofpacket;                                                              // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
	wire          rsp_xbar_demux_001_src0_valid;                                                                    // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
	wire          rsp_xbar_demux_001_src0_startofpacket;                                                            // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
	wire  [107:0] rsp_xbar_demux_001_src0_data;                                                                     // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
	wire    [5:0] rsp_xbar_demux_001_src0_channel;                                                                  // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
	wire          rsp_xbar_demux_001_src0_ready;                                                                    // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
	wire          rsp_xbar_demux_002_src0_endofpacket;                                                              // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
	wire          rsp_xbar_demux_002_src0_valid;                                                                    // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
	wire          rsp_xbar_demux_002_src0_startofpacket;                                                            // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
	wire  [107:0] rsp_xbar_demux_002_src0_data;                                                                     // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
	wire    [5:0] rsp_xbar_demux_002_src0_channel;                                                                  // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
	wire          rsp_xbar_demux_002_src0_ready;                                                                    // rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
	wire          rsp_xbar_demux_003_src0_endofpacket;                                                              // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
	wire          rsp_xbar_demux_003_src0_valid;                                                                    // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
	wire          rsp_xbar_demux_003_src0_startofpacket;                                                            // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
	wire  [107:0] rsp_xbar_demux_003_src0_data;                                                                     // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
	wire    [5:0] rsp_xbar_demux_003_src0_channel;                                                                  // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
	wire          rsp_xbar_demux_003_src0_ready;                                                                    // rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
	wire          rsp_xbar_demux_003_src1_endofpacket;                                                              // rsp_xbar_demux_003:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
	wire          rsp_xbar_demux_003_src1_valid;                                                                    // rsp_xbar_demux_003:src1_valid -> rsp_xbar_mux_001:sink0_valid
	wire          rsp_xbar_demux_003_src1_startofpacket;                                                            // rsp_xbar_demux_003:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
	wire  [107:0] rsp_xbar_demux_003_src1_data;                                                                     // rsp_xbar_demux_003:src1_data -> rsp_xbar_mux_001:sink0_data
	wire    [5:0] rsp_xbar_demux_003_src1_channel;                                                                  // rsp_xbar_demux_003:src1_channel -> rsp_xbar_mux_001:sink0_channel
	wire          rsp_xbar_demux_003_src1_ready;                                                                    // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux_003:src1_ready
	wire          rsp_xbar_demux_003_src2_endofpacket;                                                              // rsp_xbar_demux_003:src2_endofpacket -> rsp_xbar_mux_002:sink0_endofpacket
	wire          rsp_xbar_demux_003_src2_valid;                                                                    // rsp_xbar_demux_003:src2_valid -> rsp_xbar_mux_002:sink0_valid
	wire          rsp_xbar_demux_003_src2_startofpacket;                                                            // rsp_xbar_demux_003:src2_startofpacket -> rsp_xbar_mux_002:sink0_startofpacket
	wire  [107:0] rsp_xbar_demux_003_src2_data;                                                                     // rsp_xbar_demux_003:src2_data -> rsp_xbar_mux_002:sink0_data
	wire    [5:0] rsp_xbar_demux_003_src2_channel;                                                                  // rsp_xbar_demux_003:src2_channel -> rsp_xbar_mux_002:sink0_channel
	wire          rsp_xbar_demux_003_src2_ready;                                                                    // rsp_xbar_mux_002:sink0_ready -> rsp_xbar_demux_003:src2_ready
	wire          rsp_xbar_demux_004_src0_endofpacket;                                                              // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
	wire          rsp_xbar_demux_004_src0_valid;                                                                    // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
	wire          rsp_xbar_demux_004_src0_startofpacket;                                                            // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
	wire  [107:0] rsp_xbar_demux_004_src0_data;                                                                     // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
	wire    [5:0] rsp_xbar_demux_004_src0_channel;                                                                  // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
	wire          rsp_xbar_demux_004_src0_ready;                                                                    // rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
	wire          rsp_xbar_demux_005_src0_endofpacket;                                                              // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux:sink5_endofpacket
	wire          rsp_xbar_demux_005_src0_valid;                                                                    // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux:sink5_valid
	wire          rsp_xbar_demux_005_src0_startofpacket;                                                            // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux:sink5_startofpacket
	wire  [107:0] rsp_xbar_demux_005_src0_data;                                                                     // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux:sink5_data
	wire    [5:0] rsp_xbar_demux_005_src0_channel;                                                                  // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux:sink5_channel
	wire          rsp_xbar_demux_005_src0_ready;                                                                    // rsp_xbar_mux:sink5_ready -> rsp_xbar_demux_005:src0_ready
	wire          rsp_xbar_demux_005_src1_endofpacket;                                                              // rsp_xbar_demux_005:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
	wire          rsp_xbar_demux_005_src1_valid;                                                                    // rsp_xbar_demux_005:src1_valid -> rsp_xbar_mux_001:sink1_valid
	wire          rsp_xbar_demux_005_src1_startofpacket;                                                            // rsp_xbar_demux_005:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
	wire  [107:0] rsp_xbar_demux_005_src1_data;                                                                     // rsp_xbar_demux_005:src1_data -> rsp_xbar_mux_001:sink1_data
	wire    [5:0] rsp_xbar_demux_005_src1_channel;                                                                  // rsp_xbar_demux_005:src1_channel -> rsp_xbar_mux_001:sink1_channel
	wire          rsp_xbar_demux_005_src1_ready;                                                                    // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_005:src1_ready
	wire    [5:0] limiter_cmd_valid_data;                                                                           // limiter:cmd_src_valid -> cmd_xbar_demux_001:sink_valid

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (20),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (1)
	) cpu_inst_data_master_translator (
		.clk                      (avl_clk_out_clk_clk),                                                     //                       clk.clk
		.reset                    (cpu_inst_reset_n_reset_bridge_in_reset_reset),                            //                     reset.reset
		.uav_address              (cpu_inst_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount           (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read                 (cpu_inst_data_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write                (cpu_inst_data_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest          (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid        (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable           (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata             (cpu_inst_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata            (cpu_inst_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock                 (cpu_inst_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess          (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address               (cpu_inst_data_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest           (cpu_inst_data_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable            (cpu_inst_data_master_byteenable),                                         //                          .byteenable
		.av_read                  (cpu_inst_data_master_read),                                               //                          .read
		.av_readdata              (cpu_inst_data_master_readdata),                                           //                          .readdata
		.av_write                 (cpu_inst_data_master_write),                                              //                          .write
		.av_writedata             (cpu_inst_data_master_writedata),                                          //                          .writedata
		.av_burstcount            (1'b1),                                                                    //               (terminated)
		.av_beginbursttransfer    (1'b0),                                                                    //               (terminated)
		.av_begintransfer         (1'b0),                                                                    //               (terminated)
		.av_chipselect            (1'b0),                                                                    //               (terminated)
		.av_readdatavalid         (),                                                                        //               (terminated)
		.av_lock                  (1'b0),                                                                    //               (terminated)
		.av_debugaccess           (1'b0),                                                                    //               (terminated)
		.uav_clken                (),                                                                        //               (terminated)
		.av_clken                 (1'b1),                                                                    //               (terminated)
		.uav_response             (2'b00),                                                                   //               (terminated)
		.av_response              (),                                                                        //               (terminated)
		.uav_writeresponserequest (),                                                                        //               (terminated)
		.uav_writeresponsevalid   (1'b0),                                                                    //               (terminated)
		.av_writeresponserequest  (1'b0),                                                                    //               (terminated)
		.av_writeresponsevalid    ()                                                                         //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) seq_bridge_m0_translator (
		.clk                      (avl_clk_out_clk_clk),                                              //                       clk.clk
		.reset                    (cpu_inst_reset_n_reset_bridge_in_reset_reset),                     //                     reset.reset
		.uav_address              (seq_bridge_m0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount           (seq_bridge_m0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read                 (seq_bridge_m0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write                (seq_bridge_m0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest          (seq_bridge_m0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid        (seq_bridge_m0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable           (seq_bridge_m0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata             (seq_bridge_m0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata            (seq_bridge_m0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock                 (seq_bridge_m0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess          (seq_bridge_m0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address               (seq_bridge_m0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest           (seq_bridge_m0_waitrequest),                                        //                          .waitrequest
		.av_burstcount            (seq_bridge_m0_burstcount),                                         //                          .burstcount
		.av_byteenable            (seq_bridge_m0_byteenable),                                         //                          .byteenable
		.av_read                  (seq_bridge_m0_read),                                               //                          .read
		.av_readdata              (seq_bridge_m0_readdata),                                           //                          .readdata
		.av_readdatavalid         (seq_bridge_m0_readdatavalid),                                      //                          .readdatavalid
		.av_write                 (seq_bridge_m0_write),                                              //                          .write
		.av_writedata             (seq_bridge_m0_writedata),                                          //                          .writedata
		.av_debugaccess           (seq_bridge_m0_debugaccess),                                        //                          .debugaccess
		.av_beginbursttransfer    (1'b0),                                                             //               (terminated)
		.av_begintransfer         (1'b0),                                                             //               (terminated)
		.av_chipselect            (1'b0),                                                             //               (terminated)
		.av_lock                  (1'b0),                                                             //               (terminated)
		.uav_clken                (),                                                                 //               (terminated)
		.av_clken                 (1'b1),                                                             //               (terminated)
		.uav_response             (2'b00),                                                            //               (terminated)
		.av_response              (),                                                                 //               (terminated)
		.uav_writeresponserequest (),                                                                 //               (terminated)
		.uav_writeresponsevalid   (1'b0),                                                             //               (terminated)
		.av_writeresponserequest  (1'b0),                                                             //               (terminated)
		.av_writeresponsevalid    ()                                                                  //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (17),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (1),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) cpu_inst_instruction_master_translator (
		.clk                      (avl_clk_out_clk_clk),                                                            //                       clk.clk
		.reset                    (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                   //                     reset.reset
		.uav_address              (cpu_inst_instruction_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount           (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read                 (cpu_inst_instruction_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write                (cpu_inst_instruction_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest          (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid        (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable           (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata             (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata            (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock                 (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess          (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address               (cpu_inst_instruction_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest           (cpu_inst_instruction_master_waitrequest),                                        //                          .waitrequest
		.av_read                  (cpu_inst_instruction_master_read),                                               //                          .read
		.av_readdata              (cpu_inst_instruction_master_readdata),                                           //                          .readdata
		.av_burstcount            (1'b1),                                                                           //               (terminated)
		.av_byteenable            (4'b1111),                                                                        //               (terminated)
		.av_beginbursttransfer    (1'b0),                                                                           //               (terminated)
		.av_begintransfer         (1'b0),                                                                           //               (terminated)
		.av_chipselect            (1'b0),                                                                           //               (terminated)
		.av_readdatavalid         (),                                                                               //               (terminated)
		.av_write                 (1'b0),                                                                           //               (terminated)
		.av_writedata             (32'b00000000000000000000000000000000),                                           //               (terminated)
		.av_lock                  (1'b0),                                                                           //               (terminated)
		.av_debugaccess           (1'b0),                                                                           //               (terminated)
		.uav_clken                (),                                                                               //               (terminated)
		.av_clken                 (1'b1),                                                                           //               (terminated)
		.uav_response             (2'b00),                                                                          //               (terminated)
		.av_response              (),                                                                               //               (terminated)
		.uav_writeresponserequest (),                                                                               //               (terminated)
		.uav_writeresponsevalid   (1'b0),                                                                           //               (terminated)
		.av_writeresponserequest  (1'b0),                                                                           //               (terminated)
		.av_writeresponsevalid    ()                                                                                //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_phy_mgr_inst_avl_translator (
		.clk                      (avl_clk_out_clk_clk),                                                                   //                      clk.clk
		.reset                    (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                          //                    reset.reset
		.uav_address              (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read                 (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write                (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid        (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata             (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata            (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock                 (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address               (sequencer_phy_mgr_inst_avl_address),                                                    //      avalon_anti_slave_0.address
		.av_write                 (sequencer_phy_mgr_inst_avl_write),                                                      //                         .write
		.av_read                  (sequencer_phy_mgr_inst_avl_read),                                                       //                         .read
		.av_readdata              (sequencer_phy_mgr_inst_avl_readdata),                                                   //                         .readdata
		.av_writedata             (sequencer_phy_mgr_inst_avl_writedata),                                                  //                         .writedata
		.av_waitrequest           (sequencer_phy_mgr_inst_avl_waitrequest),                                                //                         .waitrequest
		.av_begintransfer         (),                                                                                      //              (terminated)
		.av_beginbursttransfer    (),                                                                                      //              (terminated)
		.av_burstcount            (),                                                                                      //              (terminated)
		.av_byteenable            (),                                                                                      //              (terminated)
		.av_readdatavalid         (1'b0),                                                                                  //              (terminated)
		.av_writebyteenable       (),                                                                                      //              (terminated)
		.av_lock                  (),                                                                                      //              (terminated)
		.av_chipselect            (),                                                                                      //              (terminated)
		.av_clken                 (),                                                                                      //              (terminated)
		.uav_clken                (1'b0),                                                                                  //              (terminated)
		.av_debugaccess           (),                                                                                      //              (terminated)
		.av_outputenable          (),                                                                                      //              (terminated)
		.uav_response             (),                                                                                      //              (terminated)
		.av_response              (2'b00),                                                                                 //              (terminated)
		.uav_writeresponserequest (1'b0),                                                                                  //              (terminated)
		.uav_writeresponsevalid   (),                                                                                      //              (terminated)
		.av_writeresponserequest  (),                                                                                      //              (terminated)
		.av_writeresponsevalid    (1'b0)                                                                                   //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_data_mgr_inst_avl_translator (
		.clk                      (avl_clk_out_clk_clk),                                                                    //                      clk.clk
		.reset                    (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                           //                    reset.reset
		.uav_address              (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read                 (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write                (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid        (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata             (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata            (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock                 (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address               (sequencer_data_mgr_inst_avl_address),                                                    //      avalon_anti_slave_0.address
		.av_write                 (sequencer_data_mgr_inst_avl_write),                                                      //                         .write
		.av_read                  (sequencer_data_mgr_inst_avl_read),                                                       //                         .read
		.av_readdata              (sequencer_data_mgr_inst_avl_readdata),                                                   //                         .readdata
		.av_writedata             (sequencer_data_mgr_inst_avl_writedata),                                                  //                         .writedata
		.av_waitrequest           (sequencer_data_mgr_inst_avl_waitrequest),                                                //                         .waitrequest
		.av_begintransfer         (),                                                                                       //              (terminated)
		.av_beginbursttransfer    (),                                                                                       //              (terminated)
		.av_burstcount            (),                                                                                       //              (terminated)
		.av_byteenable            (),                                                                                       //              (terminated)
		.av_readdatavalid         (1'b0),                                                                                   //              (terminated)
		.av_writebyteenable       (),                                                                                       //              (terminated)
		.av_lock                  (),                                                                                       //              (terminated)
		.av_chipselect            (),                                                                                       //              (terminated)
		.av_clken                 (),                                                                                       //              (terminated)
		.uav_clken                (1'b0),                                                                                   //              (terminated)
		.av_debugaccess           (),                                                                                       //              (terminated)
		.av_outputenable          (),                                                                                       //              (terminated)
		.uav_response             (),                                                                                       //              (terminated)
		.av_response              (2'b00),                                                                                  //              (terminated)
		.uav_writeresponserequest (1'b0),                                                                                   //              (terminated)
		.uav_writeresponsevalid   (),                                                                                       //              (terminated)
		.av_writeresponserequest  (),                                                                                       //              (terminated)
		.av_writeresponsevalid    (1'b0)                                                                                    //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_rw_mgr_inst_avl_translator (
		.clk                      (avl_clk_out_clk_clk),                                                                  //                      clk.clk
		.reset                    (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                         //                    reset.reset
		.uav_address              (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read                 (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write                (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid        (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata             (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata            (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock                 (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address               (sequencer_rw_mgr_inst_avl_address),                                                    //      avalon_anti_slave_0.address
		.av_write                 (sequencer_rw_mgr_inst_avl_write),                                                      //                         .write
		.av_read                  (sequencer_rw_mgr_inst_avl_read),                                                       //                         .read
		.av_readdata              (sequencer_rw_mgr_inst_avl_readdata),                                                   //                         .readdata
		.av_writedata             (sequencer_rw_mgr_inst_avl_writedata),                                                  //                         .writedata
		.av_waitrequest           (sequencer_rw_mgr_inst_avl_waitrequest),                                                //                         .waitrequest
		.av_begintransfer         (),                                                                                     //              (terminated)
		.av_beginbursttransfer    (),                                                                                     //              (terminated)
		.av_burstcount            (),                                                                                     //              (terminated)
		.av_byteenable            (),                                                                                     //              (terminated)
		.av_readdatavalid         (1'b0),                                                                                 //              (terminated)
		.av_writebyteenable       (),                                                                                     //              (terminated)
		.av_lock                  (),                                                                                     //              (terminated)
		.av_chipselect            (),                                                                                     //              (terminated)
		.av_clken                 (),                                                                                     //              (terminated)
		.uav_clken                (1'b0),                                                                                 //              (terminated)
		.av_debugaccess           (),                                                                                     //              (terminated)
		.av_outputenable          (),                                                                                     //              (terminated)
		.uav_response             (),                                                                                     //              (terminated)
		.av_response              (2'b00),                                                                                //              (terminated)
		.uav_writeresponserequest (1'b0),                                                                                 //              (terminated)
		.uav_writeresponsevalid   (),                                                                                     //              (terminated)
		.av_writeresponserequest  (),                                                                                     //              (terminated)
		.av_writeresponsevalid    (1'b0)                                                                                  //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (12),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_mem_s1_translator (
		.clk                      (avl_clk_out_clk_clk),                                                         //                      clk.clk
		.reset                    (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                //                    reset.reset
		.uav_address              (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read                 (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write                (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid        (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata             (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata            (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock                 (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address               (sequencer_mem_s1_address),                                                    //      avalon_anti_slave_0.address
		.av_write                 (sequencer_mem_s1_write),                                                      //                         .write
		.av_readdata              (sequencer_mem_s1_readdata),                                                   //                         .readdata
		.av_writedata             (sequencer_mem_s1_writedata),                                                  //                         .writedata
		.av_byteenable            (sequencer_mem_s1_byteenable),                                                 //                         .byteenable
		.av_chipselect            (sequencer_mem_s1_chipselect),                                                 //                         .chipselect
		.av_read                  (),                                                                            //              (terminated)
		.av_begintransfer         (),                                                                            //              (terminated)
		.av_beginbursttransfer    (),                                                                            //              (terminated)
		.av_burstcount            (),                                                                            //              (terminated)
		.av_readdatavalid         (1'b0),                                                                        //              (terminated)
		.av_waitrequest           (1'b0),                                                                        //              (terminated)
		.av_writebyteenable       (),                                                                            //              (terminated)
		.av_lock                  (),                                                                            //              (terminated)
		.av_clken                 (),                                                                            //              (terminated)
		.uav_clken                (1'b0),                                                                        //              (terminated)
		.av_debugaccess           (),                                                                            //              (terminated)
		.av_outputenable          (),                                                                            //              (terminated)
		.uav_response             (),                                                                            //              (terminated)
		.av_response              (2'b00),                                                                       //              (terminated)
		.uav_writeresponserequest (1'b0),                                                                        //              (terminated)
		.uav_writeresponsevalid   (),                                                                            //              (terminated)
		.av_writeresponserequest  (),                                                                            //              (terminated)
		.av_writeresponsevalid    (1'b0)                                                                         //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_scc_mgr_inst_avl_translator (
		.clk                      (avl_clk_out_clk_clk),                                                                   //                      clk.clk
		.reset                    (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                          //                    reset.reset
		.uav_address              (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read                 (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write                (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid        (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata             (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata            (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock                 (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address               (sequencer_scc_mgr_inst_avl_address),                                                    //      avalon_anti_slave_0.address
		.av_write                 (sequencer_scc_mgr_inst_avl_write),                                                      //                         .write
		.av_read                  (sequencer_scc_mgr_inst_avl_read),                                                       //                         .read
		.av_readdata              (sequencer_scc_mgr_inst_avl_readdata),                                                   //                         .readdata
		.av_writedata             (sequencer_scc_mgr_inst_avl_writedata),                                                  //                         .writedata
		.av_waitrequest           (sequencer_scc_mgr_inst_avl_waitrequest),                                                //                         .waitrequest
		.av_begintransfer         (),                                                                                      //              (terminated)
		.av_beginbursttransfer    (),                                                                                      //              (terminated)
		.av_burstcount            (),                                                                                      //              (terminated)
		.av_byteenable            (),                                                                                      //              (terminated)
		.av_readdatavalid         (1'b0),                                                                                  //              (terminated)
		.av_writebyteenable       (),                                                                                      //              (terminated)
		.av_lock                  (),                                                                                      //              (terminated)
		.av_chipselect            (),                                                                                      //              (terminated)
		.av_clken                 (),                                                                                      //              (terminated)
		.uav_clken                (1'b0),                                                                                  //              (terminated)
		.av_debugaccess           (),                                                                                      //              (terminated)
		.av_outputenable          (),                                                                                      //              (terminated)
		.uav_response             (),                                                                                      //              (terminated)
		.av_response              (2'b00),                                                                                 //              (terminated)
		.uav_writeresponserequest (1'b0),                                                                                  //              (terminated)
		.uav_writeresponsevalid   (),                                                                                      //              (terminated)
		.av_writeresponserequest  (),                                                                                      //              (terminated)
		.av_writeresponsevalid    (1'b0)                                                                                   //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (4),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_reg_file_inst_avl_translator (
		.clk                      (avl_clk_out_clk_clk),                                                                    //                      clk.clk
		.reset                    (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                           //                    reset.reset
		.uav_address              (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read                 (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write                (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid        (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata             (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata            (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock                 (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address               (sequencer_reg_file_inst_avl_address),                                                    //      avalon_anti_slave_0.address
		.av_write                 (sequencer_reg_file_inst_avl_write),                                                      //                         .write
		.av_read                  (sequencer_reg_file_inst_avl_read),                                                       //                         .read
		.av_readdata              (sequencer_reg_file_inst_avl_readdata),                                                   //                         .readdata
		.av_writedata             (sequencer_reg_file_inst_avl_writedata),                                                  //                         .writedata
		.av_byteenable            (sequencer_reg_file_inst_avl_byteenable),                                                 //                         .byteenable
		.av_waitrequest           (sequencer_reg_file_inst_avl_waitrequest),                                                //                         .waitrequest
		.av_begintransfer         (),                                                                                       //              (terminated)
		.av_beginbursttransfer    (),                                                                                       //              (terminated)
		.av_burstcount            (),                                                                                       //              (terminated)
		.av_readdatavalid         (1'b0),                                                                                   //              (terminated)
		.av_writebyteenable       (),                                                                                       //              (terminated)
		.av_lock                  (),                                                                                       //              (terminated)
		.av_chipselect            (),                                                                                       //              (terminated)
		.av_clken                 (),                                                                                       //              (terminated)
		.uav_clken                (1'b0),                                                                                   //              (terminated)
		.av_debugaccess           (),                                                                                       //              (terminated)
		.av_outputenable          (),                                                                                       //              (terminated)
		.uav_response             (),                                                                                       //              (terminated)
		.av_response              (2'b00),                                                                                  //              (terminated)
		.uav_writeresponserequest (1'b0),                                                                                   //              (terminated)
		.uav_writeresponsevalid   (),                                                                                       //              (terminated)
		.av_writeresponserequest  (),                                                                                       //              (terminated)
		.av_writeresponsevalid    (1'b0)                                                                                    //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (98),
		.PKT_PROTECTION_L          (96),
		.PKT_BEGIN_BURST           (87),
		.PKT_BURSTWRAP_H           (79),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BURST_SIZE_H          (82),
		.PKT_BURST_SIZE_L          (80),
		.PKT_BURST_TYPE_H          (84),
		.PKT_BURST_TYPE_L          (83),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (91),
		.PKT_SRC_ID_L              (89),
		.PKT_DEST_ID_H             (94),
		.PKT_DEST_ID_L             (92),
		.PKT_THREAD_ID_H           (95),
		.PKT_THREAD_ID_L           (95),
		.PKT_CACHE_H               (102),
		.PKT_CACHE_L               (99),
		.PKT_DATA_SIDEBAND_H       (86),
		.PKT_DATA_SIDEBAND_L       (86),
		.PKT_QOS_H                 (88),
		.PKT_QOS_L                 (88),
		.PKT_ADDR_SIDEBAND_H       (85),
		.PKT_ADDR_SIDEBAND_L       (85),
		.PKT_RESPONSE_STATUS_H     (104),
		.PKT_RESPONSE_STATUS_L     (103),
		.PKT_ORI_BURST_SIZE_L      (105),
		.PKT_ORI_BURST_SIZE_H      (107),
		.ST_DATA_W                 (108),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (7),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) cpu_inst_data_master_translator_avalon_universal_master_0_agent (
		.clk                     (avl_clk_out_clk_clk),                                                              //       clk.clk
		.reset                   (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                     // clk_reset.reset
		.av_address              (cpu_inst_data_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write                (cpu_inst_data_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read                 (cpu_inst_data_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata            (cpu_inst_data_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata             (cpu_inst_data_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest          (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid        (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable           (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount           (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess          (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock                 (cpu_inst_data_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid                (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data                 (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket        (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket          (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready                (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid                (rsp_xbar_mux_src_valid),                                                           //        rp.valid
		.rp_data                 (rsp_xbar_mux_src_data),                                                            //          .data
		.rp_channel              (rsp_xbar_mux_src_channel),                                                         //          .channel
		.rp_startofpacket        (rsp_xbar_mux_src_startofpacket),                                                   //          .startofpacket
		.rp_endofpacket          (rsp_xbar_mux_src_endofpacket),                                                     //          .endofpacket
		.rp_ready                (rsp_xbar_mux_src_ready),                                                           //          .ready
		.av_response             (),                                                                                 // (terminated)
		.av_writeresponserequest (1'b0),                                                                             // (terminated)
		.av_writeresponsevalid   ()                                                                                  // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (98),
		.PKT_PROTECTION_L          (96),
		.PKT_BEGIN_BURST           (87),
		.PKT_BURSTWRAP_H           (79),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BURST_SIZE_H          (82),
		.PKT_BURST_SIZE_L          (80),
		.PKT_BURST_TYPE_H          (84),
		.PKT_BURST_TYPE_L          (83),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (91),
		.PKT_SRC_ID_L              (89),
		.PKT_DEST_ID_H             (94),
		.PKT_DEST_ID_L             (92),
		.PKT_THREAD_ID_H           (95),
		.PKT_THREAD_ID_L           (95),
		.PKT_CACHE_H               (102),
		.PKT_CACHE_L               (99),
		.PKT_DATA_SIDEBAND_H       (86),
		.PKT_DATA_SIDEBAND_L       (86),
		.PKT_QOS_H                 (88),
		.PKT_QOS_L                 (88),
		.PKT_ADDR_SIDEBAND_H       (85),
		.PKT_ADDR_SIDEBAND_L       (85),
		.PKT_RESPONSE_STATUS_H     (104),
		.PKT_RESPONSE_STATUS_L     (103),
		.PKT_ORI_BURST_SIZE_L      (105),
		.PKT_ORI_BURST_SIZE_H      (107),
		.ST_DATA_W                 (108),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (2),
		.BURSTWRAP_VALUE           (7),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) seq_bridge_m0_translator_avalon_universal_master_0_agent (
		.clk                     (avl_clk_out_clk_clk),                                                       //       clk.clk
		.reset                   (cpu_inst_reset_n_reset_bridge_in_reset_reset),                              // clk_reset.reset
		.av_address              (seq_bridge_m0_translator_avalon_universal_master_0_address),                //        av.address
		.av_write                (seq_bridge_m0_translator_avalon_universal_master_0_write),                  //          .write
		.av_read                 (seq_bridge_m0_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata            (seq_bridge_m0_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata             (seq_bridge_m0_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest          (seq_bridge_m0_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid        (seq_bridge_m0_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable           (seq_bridge_m0_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount           (seq_bridge_m0_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess          (seq_bridge_m0_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock                 (seq_bridge_m0_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid                (seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data                 (seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket        (seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket          (seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready                (seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid                (limiter_rsp_src_valid),                                                     //        rp.valid
		.rp_data                 (limiter_rsp_src_data),                                                      //          .data
		.rp_channel              (limiter_rsp_src_channel),                                                   //          .channel
		.rp_startofpacket        (limiter_rsp_src_startofpacket),                                             //          .startofpacket
		.rp_endofpacket          (limiter_rsp_src_endofpacket),                                               //          .endofpacket
		.rp_ready                (limiter_rsp_src_ready),                                                     //          .ready
		.av_response             (),                                                                          // (terminated)
		.av_writeresponserequest (1'b0),                                                                      // (terminated)
		.av_writeresponsevalid   ()                                                                           // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (98),
		.PKT_PROTECTION_L          (96),
		.PKT_BEGIN_BURST           (87),
		.PKT_BURSTWRAP_H           (79),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BURST_SIZE_H          (82),
		.PKT_BURST_SIZE_L          (80),
		.PKT_BURST_TYPE_H          (84),
		.PKT_BURST_TYPE_L          (83),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (91),
		.PKT_SRC_ID_L              (89),
		.PKT_DEST_ID_H             (94),
		.PKT_DEST_ID_L             (92),
		.PKT_THREAD_ID_H           (95),
		.PKT_THREAD_ID_L           (95),
		.PKT_CACHE_H               (102),
		.PKT_CACHE_L               (99),
		.PKT_DATA_SIDEBAND_H       (86),
		.PKT_DATA_SIDEBAND_L       (86),
		.PKT_QOS_H                 (88),
		.PKT_QOS_L                 (88),
		.PKT_ADDR_SIDEBAND_H       (85),
		.PKT_ADDR_SIDEBAND_L       (85),
		.PKT_RESPONSE_STATUS_H     (104),
		.PKT_RESPONSE_STATUS_L     (103),
		.PKT_ORI_BURST_SIZE_L      (105),
		.PKT_ORI_BURST_SIZE_H      (107),
		.ST_DATA_W                 (108),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (3),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) cpu_inst_instruction_master_translator_avalon_universal_master_0_agent (
		.clk                     (avl_clk_out_clk_clk),                                                                     //       clk.clk
		.reset                   (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                            // clk_reset.reset
		.av_address              (cpu_inst_instruction_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write                (cpu_inst_instruction_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read                 (cpu_inst_instruction_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata            (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata             (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest          (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid        (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable           (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount           (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess          (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock                 (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid                (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data                 (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket        (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket          (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready                (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid                (rsp_xbar_mux_002_src_valid),                                                              //        rp.valid
		.rp_data                 (rsp_xbar_mux_002_src_data),                                                               //          .data
		.rp_channel              (rsp_xbar_mux_002_src_channel),                                                            //          .channel
		.rp_startofpacket        (rsp_xbar_mux_002_src_startofpacket),                                                      //          .startofpacket
		.rp_endofpacket          (rsp_xbar_mux_002_src_endofpacket),                                                        //          .endofpacket
		.rp_ready                (rsp_xbar_mux_002_src_ready),                                                              //          .ready
		.av_response             (),                                                                                        // (terminated)
		.av_writeresponserequest (1'b0),                                                                                    // (terminated)
		.av_writeresponsevalid   ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (87),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_SRC_ID_H              (91),
		.PKT_SRC_ID_L              (89),
		.PKT_DEST_ID_H             (94),
		.PKT_DEST_ID_L             (92),
		.PKT_BURSTWRAP_H           (79),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_PROTECTION_H          (98),
		.PKT_PROTECTION_L          (96),
		.PKT_RESPONSE_STATUS_H     (104),
		.PKT_RESPONSE_STATUS_L     (103),
		.PKT_BURST_SIZE_H          (82),
		.PKT_BURST_SIZE_L          (80),
		.PKT_ORI_BURST_SIZE_L      (105),
		.PKT_ORI_BURST_SIZE_H      (107),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (108),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk_out_clk_clk),                                                                             //             clk.clk
		.reset                   (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                                    //       clk_reset.reset
		.m0_address              (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_mux_src_ready),                                                                          //              cp.ready
		.cp_valid                (cmd_xbar_mux_src_valid),                                                                          //                .valid
		.cp_data                 (cmd_xbar_mux_src_data),                                                                           //                .data
		.cp_startofpacket        (cmd_xbar_mux_src_startofpacket),                                                                  //                .startofpacket
		.cp_endofpacket          (cmd_xbar_mux_src_endofpacket),                                                                    //                .endofpacket
		.cp_channel              (cmd_xbar_mux_src_channel),                                                                        //                .channel
		.rf_sink_ready           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                                                           //     (terminated)
		.m0_writeresponserequest (),                                                                                                //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                                             //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (109),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk_out_clk_clk),                                                                             //       clk.clk
		.reset             (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                                    // clk_reset.reset
		.in_data           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                           // (terminated)
		.csr_read          (1'b0),                                                                                            // (terminated)
		.csr_write         (1'b0),                                                                                            // (terminated)
		.csr_readdata      (),                                                                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                            // (terminated)
		.almost_full_data  (),                                                                                                // (terminated)
		.almost_empty_data (),                                                                                                // (terminated)
		.in_empty          (1'b0),                                                                                            // (terminated)
		.out_empty         (),                                                                                                // (terminated)
		.in_error          (1'b0),                                                                                            // (terminated)
		.out_error         (),                                                                                                // (terminated)
		.in_channel        (1'b0),                                                                                            // (terminated)
		.out_channel       ()                                                                                                 // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (87),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_SRC_ID_H              (91),
		.PKT_SRC_ID_L              (89),
		.PKT_DEST_ID_H             (94),
		.PKT_DEST_ID_L             (92),
		.PKT_BURSTWRAP_H           (79),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_PROTECTION_H          (98),
		.PKT_PROTECTION_L          (96),
		.PKT_RESPONSE_STATUS_H     (104),
		.PKT_RESPONSE_STATUS_L     (103),
		.PKT_BURST_SIZE_H          (82),
		.PKT_BURST_SIZE_L          (80),
		.PKT_ORI_BURST_SIZE_L      (105),
		.PKT_ORI_BURST_SIZE_H      (107),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (108),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk_out_clk_clk),                                                                              //             clk.clk
		.reset                   (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                                     //       clk_reset.reset
		.m0_address              (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_mux_001_src_ready),                                                                       //              cp.ready
		.cp_valid                (cmd_xbar_mux_001_src_valid),                                                                       //                .valid
		.cp_data                 (cmd_xbar_mux_001_src_data),                                                                        //                .data
		.cp_startofpacket        (cmd_xbar_mux_001_src_startofpacket),                                                               //                .startofpacket
		.cp_endofpacket          (cmd_xbar_mux_001_src_endofpacket),                                                                 //                .endofpacket
		.cp_channel              (cmd_xbar_mux_001_src_channel),                                                                     //                .channel
		.rf_sink_ready           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                                                            //     (terminated)
		.m0_writeresponserequest (),                                                                                                 //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                                              //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (109),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk_out_clk_clk),                                                                              //       clk.clk
		.reset             (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                                     // clk_reset.reset
		.in_data           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                            // (terminated)
		.csr_read          (1'b0),                                                                                             // (terminated)
		.csr_write         (1'b0),                                                                                             // (terminated)
		.csr_readdata      (),                                                                                                 // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                             // (terminated)
		.almost_full_data  (),                                                                                                 // (terminated)
		.almost_empty_data (),                                                                                                 // (terminated)
		.in_empty          (1'b0),                                                                                             // (terminated)
		.out_empty         (),                                                                                                 // (terminated)
		.in_error          (1'b0),                                                                                             // (terminated)
		.out_error         (),                                                                                                 // (terminated)
		.in_channel        (1'b0),                                                                                             // (terminated)
		.out_channel       ()                                                                                                  // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (87),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_SRC_ID_H              (91),
		.PKT_SRC_ID_L              (89),
		.PKT_DEST_ID_H             (94),
		.PKT_DEST_ID_L             (92),
		.PKT_BURSTWRAP_H           (79),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_PROTECTION_H          (98),
		.PKT_PROTECTION_L          (96),
		.PKT_RESPONSE_STATUS_H     (104),
		.PKT_RESPONSE_STATUS_L     (103),
		.PKT_BURST_SIZE_H          (82),
		.PKT_BURST_SIZE_L          (80),
		.PKT_ORI_BURST_SIZE_L      (105),
		.PKT_ORI_BURST_SIZE_H      (107),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (108),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk_out_clk_clk),                                                                            //             clk.clk
		.reset                   (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                                   //       clk_reset.reset
		.m0_address              (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_mux_002_src_ready),                                                                     //              cp.ready
		.cp_valid                (cmd_xbar_mux_002_src_valid),                                                                     //                .valid
		.cp_data                 (cmd_xbar_mux_002_src_data),                                                                      //                .data
		.cp_startofpacket        (cmd_xbar_mux_002_src_startofpacket),                                                             //                .startofpacket
		.cp_endofpacket          (cmd_xbar_mux_002_src_endofpacket),                                                               //                .endofpacket
		.cp_channel              (cmd_xbar_mux_002_src_channel),                                                                   //                .channel
		.rf_sink_ready           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                                                          //     (terminated)
		.m0_writeresponserequest (),                                                                                               //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (109),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk_out_clk_clk),                                                                            //       clk.clk
		.reset             (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                                   // clk_reset.reset
		.in_data           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                          // (terminated)
		.csr_read          (1'b0),                                                                                           // (terminated)
		.csr_write         (1'b0),                                                                                           // (terminated)
		.csr_readdata      (),                                                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                           // (terminated)
		.almost_full_data  (),                                                                                               // (terminated)
		.almost_empty_data (),                                                                                               // (terminated)
		.in_empty          (1'b0),                                                                                           // (terminated)
		.out_empty         (),                                                                                               // (terminated)
		.in_error          (1'b0),                                                                                           // (terminated)
		.out_error         (),                                                                                               // (terminated)
		.in_channel        (1'b0),                                                                                           // (terminated)
		.out_channel       ()                                                                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (87),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_SRC_ID_H              (91),
		.PKT_SRC_ID_L              (89),
		.PKT_DEST_ID_H             (94),
		.PKT_DEST_ID_L             (92),
		.PKT_BURSTWRAP_H           (79),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_PROTECTION_H          (98),
		.PKT_PROTECTION_L          (96),
		.PKT_RESPONSE_STATUS_H     (104),
		.PKT_RESPONSE_STATUS_L     (103),
		.PKT_BURST_SIZE_H          (82),
		.PKT_BURST_SIZE_L          (80),
		.PKT_ORI_BURST_SIZE_L      (105),
		.PKT_ORI_BURST_SIZE_H      (107),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (108),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) sequencer_mem_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk_out_clk_clk),                                                                   //             clk.clk
		.reset                   (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                          //       clk_reset.reset
		.m0_address              (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_mux_003_src_ready),                                                            //              cp.ready
		.cp_valid                (cmd_xbar_mux_003_src_valid),                                                            //                .valid
		.cp_data                 (cmd_xbar_mux_003_src_data),                                                             //                .data
		.cp_startofpacket        (cmd_xbar_mux_003_src_startofpacket),                                                    //                .startofpacket
		.cp_endofpacket          (cmd_xbar_mux_003_src_endofpacket),                                                      //                .endofpacket
		.cp_channel              (cmd_xbar_mux_003_src_channel),                                                          //                .channel
		.rf_sink_ready           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                                                 //     (terminated)
		.m0_writeresponserequest (),                                                                                      //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                                   //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (109),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk_out_clk_clk),                                                                   //       clk.clk
		.reset             (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                          // clk_reset.reset
		.in_data           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                 // (terminated)
		.csr_read          (1'b0),                                                                                  // (terminated)
		.csr_write         (1'b0),                                                                                  // (terminated)
		.csr_readdata      (),                                                                                      // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                  // (terminated)
		.almost_full_data  (),                                                                                      // (terminated)
		.almost_empty_data (),                                                                                      // (terminated)
		.in_empty          (1'b0),                                                                                  // (terminated)
		.out_empty         (),                                                                                      // (terminated)
		.in_error          (1'b0),                                                                                  // (terminated)
		.out_error         (),                                                                                      // (terminated)
		.in_channel        (1'b0),                                                                                  // (terminated)
		.out_channel       ()                                                                                       // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (87),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_SRC_ID_H              (91),
		.PKT_SRC_ID_L              (89),
		.PKT_DEST_ID_H             (94),
		.PKT_DEST_ID_L             (92),
		.PKT_BURSTWRAP_H           (79),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_PROTECTION_H          (98),
		.PKT_PROTECTION_L          (96),
		.PKT_RESPONSE_STATUS_H     (104),
		.PKT_RESPONSE_STATUS_L     (103),
		.PKT_BURST_SIZE_H          (82),
		.PKT_BURST_SIZE_L          (80),
		.PKT_ORI_BURST_SIZE_L      (105),
		.PKT_ORI_BURST_SIZE_H      (107),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (108),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk_out_clk_clk),                                                                             //             clk.clk
		.reset                   (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                                    //       clk_reset.reset
		.m0_address              (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_mux_004_src_ready),                                                                      //              cp.ready
		.cp_valid                (cmd_xbar_mux_004_src_valid),                                                                      //                .valid
		.cp_data                 (cmd_xbar_mux_004_src_data),                                                                       //                .data
		.cp_startofpacket        (cmd_xbar_mux_004_src_startofpacket),                                                              //                .startofpacket
		.cp_endofpacket          (cmd_xbar_mux_004_src_endofpacket),                                                                //                .endofpacket
		.cp_channel              (cmd_xbar_mux_004_src_channel),                                                                    //                .channel
		.rf_sink_ready           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                                                           //     (terminated)
		.m0_writeresponserequest (),                                                                                                //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                                             //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (109),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk_out_clk_clk),                                                                             //       clk.clk
		.reset             (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                                    // clk_reset.reset
		.in_data           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                           // (terminated)
		.csr_read          (1'b0),                                                                                            // (terminated)
		.csr_write         (1'b0),                                                                                            // (terminated)
		.csr_readdata      (),                                                                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                            // (terminated)
		.almost_full_data  (),                                                                                                // (terminated)
		.almost_empty_data (),                                                                                                // (terminated)
		.in_empty          (1'b0),                                                                                            // (terminated)
		.out_empty         (),                                                                                                // (terminated)
		.in_error          (1'b0),                                                                                            // (terminated)
		.out_error         (),                                                                                                // (terminated)
		.in_channel        (1'b0),                                                                                            // (terminated)
		.out_channel       ()                                                                                                 // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (87),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_SRC_ID_H              (91),
		.PKT_SRC_ID_L              (89),
		.PKT_DEST_ID_H             (94),
		.PKT_DEST_ID_L             (92),
		.PKT_BURSTWRAP_H           (79),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_PROTECTION_H          (98),
		.PKT_PROTECTION_L          (96),
		.PKT_RESPONSE_STATUS_H     (104),
		.PKT_RESPONSE_STATUS_L     (103),
		.PKT_BURST_SIZE_H          (82),
		.PKT_BURST_SIZE_L          (80),
		.PKT_ORI_BURST_SIZE_L      (105),
		.PKT_ORI_BURST_SIZE_H      (107),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (108),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk_out_clk_clk),                                                                              //             clk.clk
		.reset                   (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                                     //       clk_reset.reset
		.m0_address              (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_mux_005_src_ready),                                                                       //              cp.ready
		.cp_valid                (cmd_xbar_mux_005_src_valid),                                                                       //                .valid
		.cp_data                 (cmd_xbar_mux_005_src_data),                                                                        //                .data
		.cp_startofpacket        (cmd_xbar_mux_005_src_startofpacket),                                                               //                .startofpacket
		.cp_endofpacket          (cmd_xbar_mux_005_src_endofpacket),                                                                 //                .endofpacket
		.cp_channel              (cmd_xbar_mux_005_src_channel),                                                                     //                .channel
		.rf_sink_ready           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                                                            //     (terminated)
		.m0_writeresponserequest (),                                                                                                 //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                                              //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (109),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk_out_clk_clk),                                                                              //       clk.clk
		.reset             (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                                     // clk_reset.reset
		.in_data           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                            // (terminated)
		.csr_read          (1'b0),                                                                                             // (terminated)
		.csr_write         (1'b0),                                                                                             // (terminated)
		.csr_readdata      (),                                                                                                 // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                             // (terminated)
		.almost_full_data  (),                                                                                                 // (terminated)
		.almost_empty_data (),                                                                                                 // (terminated)
		.in_empty          (1'b0),                                                                                             // (terminated)
		.out_empty         (),                                                                                                 // (terminated)
		.in_error          (1'b0),                                                                                             // (terminated)
		.out_error         (),                                                                                                 // (terminated)
		.in_channel        (1'b0),                                                                                             // (terminated)
		.out_channel       ()                                                                                                  // (terminated)
	);

	DDR3_test_s0_mm_interconnect_0_addr_router addr_router (
		.sink_ready         (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (avl_clk_out_clk_clk),                                                              //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                     // clk_reset.reset
		.src_ready          (addr_router_src_ready),                                                            //       src.ready
		.src_valid          (addr_router_src_valid),                                                            //          .valid
		.src_data           (addr_router_src_data),                                                             //          .data
		.src_channel        (addr_router_src_channel),                                                          //          .channel
		.src_startofpacket  (addr_router_src_startofpacket),                                                    //          .startofpacket
		.src_endofpacket    (addr_router_src_endofpacket)                                                       //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_addr_router_001 addr_router_001 (
		.sink_ready         (seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (seq_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (avl_clk_out_clk_clk),                                                       //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset),                              // clk_reset.reset
		.src_ready          (addr_router_001_src_ready),                                                 //       src.ready
		.src_valid          (addr_router_001_src_valid),                                                 //          .valid
		.src_data           (addr_router_001_src_data),                                                  //          .data
		.src_channel        (addr_router_001_src_channel),                                               //          .channel
		.src_startofpacket  (addr_router_001_src_startofpacket),                                         //          .startofpacket
		.src_endofpacket    (addr_router_001_src_endofpacket)                                            //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_addr_router_002 addr_router_002 (
		.sink_ready         (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (avl_clk_out_clk_clk),                                                                     //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                            // clk_reset.reset
		.src_ready          (addr_router_002_src_ready),                                                               //       src.ready
		.src_valid          (addr_router_002_src_valid),                                                               //          .valid
		.src_data           (addr_router_002_src_data),                                                                //          .data
		.src_channel        (addr_router_002_src_channel),                                                             //          .channel
		.src_startofpacket  (addr_router_002_src_startofpacket),                                                       //          .startofpacket
		.src_endofpacket    (addr_router_002_src_endofpacket)                                                          //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_id_router id_router (
		.sink_ready         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk_out_clk_clk),                                                                   //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                          // clk_reset.reset
		.src_ready          (id_router_src_ready),                                                                   //       src.ready
		.src_valid          (id_router_src_valid),                                                                   //          .valid
		.src_data           (id_router_src_data),                                                                    //          .data
		.src_channel        (id_router_src_channel),                                                                 //          .channel
		.src_startofpacket  (id_router_src_startofpacket),                                                           //          .startofpacket
		.src_endofpacket    (id_router_src_endofpacket)                                                              //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_id_router id_router_001 (
		.sink_ready         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk_out_clk_clk),                                                                    //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                           // clk_reset.reset
		.src_ready          (id_router_001_src_ready),                                                                //       src.ready
		.src_valid          (id_router_001_src_valid),                                                                //          .valid
		.src_data           (id_router_001_src_data),                                                                 //          .data
		.src_channel        (id_router_001_src_channel),                                                              //          .channel
		.src_startofpacket  (id_router_001_src_startofpacket),                                                        //          .startofpacket
		.src_endofpacket    (id_router_001_src_endofpacket)                                                           //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_id_router id_router_002 (
		.sink_ready         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk_out_clk_clk),                                                                  //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                         // clk_reset.reset
		.src_ready          (id_router_002_src_ready),                                                              //       src.ready
		.src_valid          (id_router_002_src_valid),                                                              //          .valid
		.src_data           (id_router_002_src_data),                                                               //          .data
		.src_channel        (id_router_002_src_channel),                                                            //          .channel
		.src_startofpacket  (id_router_002_src_startofpacket),                                                      //          .startofpacket
		.src_endofpacket    (id_router_002_src_endofpacket)                                                         //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_id_router_003 id_router_003 (
		.sink_ready         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk_out_clk_clk),                                                         //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                // clk_reset.reset
		.src_ready          (id_router_003_src_ready),                                                     //       src.ready
		.src_valid          (id_router_003_src_valid),                                                     //          .valid
		.src_data           (id_router_003_src_data),                                                      //          .data
		.src_channel        (id_router_003_src_channel),                                                   //          .channel
		.src_startofpacket  (id_router_003_src_startofpacket),                                             //          .startofpacket
		.src_endofpacket    (id_router_003_src_endofpacket)                                                //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_id_router id_router_004 (
		.sink_ready         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk_out_clk_clk),                                                                   //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                          // clk_reset.reset
		.src_ready          (id_router_004_src_ready),                                                               //       src.ready
		.src_valid          (id_router_004_src_valid),                                                               //          .valid
		.src_data           (id_router_004_src_data),                                                                //          .data
		.src_channel        (id_router_004_src_channel),                                                             //          .channel
		.src_startofpacket  (id_router_004_src_startofpacket),                                                       //          .startofpacket
		.src_endofpacket    (id_router_004_src_endofpacket)                                                          //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_id_router_005 id_router_005 (
		.sink_ready         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk_out_clk_clk),                                                                    //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset),                                           // clk_reset.reset
		.src_ready          (id_router_005_src_ready),                                                                //       src.ready
		.src_valid          (id_router_005_src_valid),                                                                //          .valid
		.src_data           (id_router_005_src_data),                                                                 //          .data
		.src_channel        (id_router_005_src_channel),                                                              //          .channel
		.src_startofpacket  (id_router_005_src_startofpacket),                                                        //          .startofpacket
		.src_endofpacket    (id_router_005_src_endofpacket)                                                           //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (94),
		.PKT_DEST_ID_L             (92),
		.PKT_SRC_ID_H              (91),
		.PKT_SRC_ID_L              (89),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.MAX_OUTSTANDING_RESPONSES (1),
		.PIPELINED                 (0),
		.ST_DATA_W                 (108),
		.ST_CHANNEL_W              (6),
		.VALID_WIDTH               (6),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.REORDER                   (0)
	) limiter (
		.clk                    (avl_clk_out_clk_clk),                          //       clk.clk
		.reset                  (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.cmd_sink_ready         (addr_router_001_src_ready),                    //  cmd_sink.ready
		.cmd_sink_valid         (addr_router_001_src_valid),                    //          .valid
		.cmd_sink_data          (addr_router_001_src_data),                     //          .data
		.cmd_sink_channel       (addr_router_001_src_channel),                  //          .channel
		.cmd_sink_startofpacket (addr_router_001_src_startofpacket),            //          .startofpacket
		.cmd_sink_endofpacket   (addr_router_001_src_endofpacket),              //          .endofpacket
		.cmd_src_ready          (limiter_cmd_src_ready),                        //   cmd_src.ready
		.cmd_src_data           (limiter_cmd_src_data),                         //          .data
		.cmd_src_channel        (limiter_cmd_src_channel),                      //          .channel
		.cmd_src_startofpacket  (limiter_cmd_src_startofpacket),                //          .startofpacket
		.cmd_src_endofpacket    (limiter_cmd_src_endofpacket),                  //          .endofpacket
		.rsp_sink_ready         (rsp_xbar_mux_001_src_ready),                   //  rsp_sink.ready
		.rsp_sink_valid         (rsp_xbar_mux_001_src_valid),                   //          .valid
		.rsp_sink_channel       (rsp_xbar_mux_001_src_channel),                 //          .channel
		.rsp_sink_data          (rsp_xbar_mux_001_src_data),                    //          .data
		.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket),           //          .startofpacket
		.rsp_sink_endofpacket   (rsp_xbar_mux_001_src_endofpacket),             //          .endofpacket
		.rsp_src_ready          (limiter_rsp_src_ready),                        //   rsp_src.ready
		.rsp_src_valid          (limiter_rsp_src_valid),                        //          .valid
		.rsp_src_data           (limiter_rsp_src_data),                         //          .data
		.rsp_src_channel        (limiter_rsp_src_channel),                      //          .channel
		.rsp_src_startofpacket  (limiter_rsp_src_startofpacket),                //          .startofpacket
		.rsp_src_endofpacket    (limiter_rsp_src_endofpacket),                  //          .endofpacket
		.cmd_src_valid          (limiter_cmd_valid_data)                        // cmd_valid.data
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux (
		.clk                (avl_clk_out_clk_clk),                          //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (addr_router_src_ready),                        //      sink.ready
		.sink_channel       (addr_router_src_channel),                      //          .channel
		.sink_data          (addr_router_src_data),                         //          .data
		.sink_startofpacket (addr_router_src_startofpacket),                //          .startofpacket
		.sink_endofpacket   (addr_router_src_endofpacket),                  //          .endofpacket
		.sink_valid         (addr_router_src_valid),                        //          .valid
		.src0_ready         (cmd_xbar_demux_src0_ready),                    //      src0.ready
		.src0_valid         (cmd_xbar_demux_src0_valid),                    //          .valid
		.src0_data          (cmd_xbar_demux_src0_data),                     //          .data
		.src0_channel       (cmd_xbar_demux_src0_channel),                  //          .channel
		.src0_startofpacket (cmd_xbar_demux_src0_startofpacket),            //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_src0_endofpacket),              //          .endofpacket
		.src1_ready         (cmd_xbar_demux_src1_ready),                    //      src1.ready
		.src1_valid         (cmd_xbar_demux_src1_valid),                    //          .valid
		.src1_data          (cmd_xbar_demux_src1_data),                     //          .data
		.src1_channel       (cmd_xbar_demux_src1_channel),                  //          .channel
		.src1_startofpacket (cmd_xbar_demux_src1_startofpacket),            //          .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_src1_endofpacket),              //          .endofpacket
		.src2_ready         (cmd_xbar_demux_src2_ready),                    //      src2.ready
		.src2_valid         (cmd_xbar_demux_src2_valid),                    //          .valid
		.src2_data          (cmd_xbar_demux_src2_data),                     //          .data
		.src2_channel       (cmd_xbar_demux_src2_channel),                  //          .channel
		.src2_startofpacket (cmd_xbar_demux_src2_startofpacket),            //          .startofpacket
		.src2_endofpacket   (cmd_xbar_demux_src2_endofpacket),              //          .endofpacket
		.src3_ready         (cmd_xbar_demux_src3_ready),                    //      src3.ready
		.src3_valid         (cmd_xbar_demux_src3_valid),                    //          .valid
		.src3_data          (cmd_xbar_demux_src3_data),                     //          .data
		.src3_channel       (cmd_xbar_demux_src3_channel),                  //          .channel
		.src3_startofpacket (cmd_xbar_demux_src3_startofpacket),            //          .startofpacket
		.src3_endofpacket   (cmd_xbar_demux_src3_endofpacket),              //          .endofpacket
		.src4_ready         (cmd_xbar_demux_src4_ready),                    //      src4.ready
		.src4_valid         (cmd_xbar_demux_src4_valid),                    //          .valid
		.src4_data          (cmd_xbar_demux_src4_data),                     //          .data
		.src4_channel       (cmd_xbar_demux_src4_channel),                  //          .channel
		.src4_startofpacket (cmd_xbar_demux_src4_startofpacket),            //          .startofpacket
		.src4_endofpacket   (cmd_xbar_demux_src4_endofpacket),              //          .endofpacket
		.src5_ready         (cmd_xbar_demux_src5_ready),                    //      src5.ready
		.src5_valid         (cmd_xbar_demux_src5_valid),                    //          .valid
		.src5_data          (cmd_xbar_demux_src5_data),                     //          .data
		.src5_channel       (cmd_xbar_demux_src5_channel),                  //          .channel
		.src5_startofpacket (cmd_xbar_demux_src5_startofpacket),            //          .startofpacket
		.src5_endofpacket   (cmd_xbar_demux_src5_endofpacket)               //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_demux_001 cmd_xbar_demux_001 (
		.clk                (avl_clk_out_clk_clk),                          //        clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), //  clk_reset.reset
		.sink_ready         (limiter_cmd_src_ready),                        //       sink.ready
		.sink_channel       (limiter_cmd_src_channel),                      //           .channel
		.sink_data          (limiter_cmd_src_data),                         //           .data
		.sink_startofpacket (limiter_cmd_src_startofpacket),                //           .startofpacket
		.sink_endofpacket   (limiter_cmd_src_endofpacket),                  //           .endofpacket
		.sink_valid         (limiter_cmd_valid_data),                       // sink_valid.data
		.src0_ready         (cmd_xbar_demux_001_src0_ready),                //       src0.ready
		.src0_valid         (cmd_xbar_demux_001_src0_valid),                //           .valid
		.src0_data          (cmd_xbar_demux_001_src0_data),                 //           .data
		.src0_channel       (cmd_xbar_demux_001_src0_channel),              //           .channel
		.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket),        //           .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_001_src0_endofpacket),          //           .endofpacket
		.src1_ready         (cmd_xbar_demux_001_src1_ready),                //       src1.ready
		.src1_valid         (cmd_xbar_demux_001_src1_valid),                //           .valid
		.src1_data          (cmd_xbar_demux_001_src1_data),                 //           .data
		.src1_channel       (cmd_xbar_demux_001_src1_channel),              //           .channel
		.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket),        //           .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_001_src1_endofpacket)           //           .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_demux_002 cmd_xbar_demux_002 (
		.clk                (avl_clk_out_clk_clk),                          //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (addr_router_002_src_ready),                    //      sink.ready
		.sink_channel       (addr_router_002_src_channel),                  //          .channel
		.sink_data          (addr_router_002_src_data),                     //          .data
		.sink_startofpacket (addr_router_002_src_startofpacket),            //          .startofpacket
		.sink_endofpacket   (addr_router_002_src_endofpacket),              //          .endofpacket
		.sink_valid         (addr_router_002_src_valid),                    //          .valid
		.src0_ready         (cmd_xbar_demux_002_src0_ready),                //      src0.ready
		.src0_valid         (cmd_xbar_demux_002_src0_valid),                //          .valid
		.src0_data          (cmd_xbar_demux_002_src0_data),                 //          .data
		.src0_channel       (cmd_xbar_demux_002_src0_channel),              //          .channel
		.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_002_src0_endofpacket)           //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_mux cmd_xbar_mux (
		.clk                 (avl_clk_out_clk_clk),                          //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_src_ready),                       //       src.ready
		.src_valid           (cmd_xbar_mux_src_valid),                       //          .valid
		.src_data            (cmd_xbar_mux_src_data),                        //          .data
		.src_channel         (cmd_xbar_mux_src_channel),                     //          .channel
		.src_startofpacket   (cmd_xbar_mux_src_startofpacket),               //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_src_endofpacket),                 //          .endofpacket
		.sink0_ready         (cmd_xbar_demux_src0_ready),                    //     sink0.ready
		.sink0_valid         (cmd_xbar_demux_src0_valid),                    //          .valid
		.sink0_channel       (cmd_xbar_demux_src0_channel),                  //          .channel
		.sink0_data          (cmd_xbar_demux_src0_data),                     //          .data
		.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (cmd_xbar_demux_src0_endofpacket)               //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_mux cmd_xbar_mux_001 (
		.clk                 (avl_clk_out_clk_clk),                          //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_001_src_ready),                   //       src.ready
		.src_valid           (cmd_xbar_mux_001_src_valid),                   //          .valid
		.src_data            (cmd_xbar_mux_001_src_data),                    //          .data
		.src_channel         (cmd_xbar_mux_001_src_channel),                 //          .channel
		.src_startofpacket   (cmd_xbar_mux_001_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_001_src_endofpacket),             //          .endofpacket
		.sink0_ready         (cmd_xbar_demux_src1_ready),                    //     sink0.ready
		.sink0_valid         (cmd_xbar_demux_src1_valid),                    //          .valid
		.sink0_channel       (cmd_xbar_demux_src1_channel),                  //          .channel
		.sink0_data          (cmd_xbar_demux_src1_data),                     //          .data
		.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (cmd_xbar_demux_src1_endofpacket)               //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_mux cmd_xbar_mux_002 (
		.clk                 (avl_clk_out_clk_clk),                          //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_002_src_ready),                   //       src.ready
		.src_valid           (cmd_xbar_mux_002_src_valid),                   //          .valid
		.src_data            (cmd_xbar_mux_002_src_data),                    //          .data
		.src_channel         (cmd_xbar_mux_002_src_channel),                 //          .channel
		.src_startofpacket   (cmd_xbar_mux_002_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_002_src_endofpacket),             //          .endofpacket
		.sink0_ready         (cmd_xbar_demux_src2_ready),                    //     sink0.ready
		.sink0_valid         (cmd_xbar_demux_src2_valid),                    //          .valid
		.sink0_channel       (cmd_xbar_demux_src2_channel),                  //          .channel
		.sink0_data          (cmd_xbar_demux_src2_data),                     //          .data
		.sink0_startofpacket (cmd_xbar_demux_src2_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (cmd_xbar_demux_src2_endofpacket)               //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_mux_003 cmd_xbar_mux_003 (
		.clk                 (avl_clk_out_clk_clk),                          //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_003_src_ready),                   //       src.ready
		.src_valid           (cmd_xbar_mux_003_src_valid),                   //          .valid
		.src_data            (cmd_xbar_mux_003_src_data),                    //          .data
		.src_channel         (cmd_xbar_mux_003_src_channel),                 //          .channel
		.src_startofpacket   (cmd_xbar_mux_003_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_003_src_endofpacket),             //          .endofpacket
		.sink0_ready         (cmd_xbar_demux_src3_ready),                    //     sink0.ready
		.sink0_valid         (cmd_xbar_demux_src3_valid),                    //          .valid
		.sink0_channel       (cmd_xbar_demux_src3_channel),                  //          .channel
		.sink0_data          (cmd_xbar_demux_src3_data),                     //          .data
		.sink0_startofpacket (cmd_xbar_demux_src3_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (cmd_xbar_demux_src3_endofpacket),              //          .endofpacket
		.sink1_ready         (cmd_xbar_demux_001_src0_ready),                //     sink1.ready
		.sink1_valid         (cmd_xbar_demux_001_src0_valid),                //          .valid
		.sink1_channel       (cmd_xbar_demux_001_src0_channel),              //          .channel
		.sink1_data          (cmd_xbar_demux_001_src0_data),                 //          .data
		.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket),        //          .startofpacket
		.sink1_endofpacket   (cmd_xbar_demux_001_src0_endofpacket),          //          .endofpacket
		.sink2_ready         (cmd_xbar_demux_002_src0_ready),                //     sink2.ready
		.sink2_valid         (cmd_xbar_demux_002_src0_valid),                //          .valid
		.sink2_channel       (cmd_xbar_demux_002_src0_channel),              //          .channel
		.sink2_data          (cmd_xbar_demux_002_src0_data),                 //          .data
		.sink2_startofpacket (cmd_xbar_demux_002_src0_startofpacket),        //          .startofpacket
		.sink2_endofpacket   (cmd_xbar_demux_002_src0_endofpacket)           //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_mux cmd_xbar_mux_004 (
		.clk                 (avl_clk_out_clk_clk),                          //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_004_src_ready),                   //       src.ready
		.src_valid           (cmd_xbar_mux_004_src_valid),                   //          .valid
		.src_data            (cmd_xbar_mux_004_src_data),                    //          .data
		.src_channel         (cmd_xbar_mux_004_src_channel),                 //          .channel
		.src_startofpacket   (cmd_xbar_mux_004_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_004_src_endofpacket),             //          .endofpacket
		.sink0_ready         (cmd_xbar_demux_src4_ready),                    //     sink0.ready
		.sink0_valid         (cmd_xbar_demux_src4_valid),                    //          .valid
		.sink0_channel       (cmd_xbar_demux_src4_channel),                  //          .channel
		.sink0_data          (cmd_xbar_demux_src4_data),                     //          .data
		.sink0_startofpacket (cmd_xbar_demux_src4_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (cmd_xbar_demux_src4_endofpacket)               //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_mux_005 cmd_xbar_mux_005 (
		.clk                 (avl_clk_out_clk_clk),                          //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_005_src_ready),                   //       src.ready
		.src_valid           (cmd_xbar_mux_005_src_valid),                   //          .valid
		.src_data            (cmd_xbar_mux_005_src_data),                    //          .data
		.src_channel         (cmd_xbar_mux_005_src_channel),                 //          .channel
		.src_startofpacket   (cmd_xbar_mux_005_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_005_src_endofpacket),             //          .endofpacket
		.sink0_ready         (cmd_xbar_demux_src5_ready),                    //     sink0.ready
		.sink0_valid         (cmd_xbar_demux_src5_valid),                    //          .valid
		.sink0_channel       (cmd_xbar_demux_src5_channel),                  //          .channel
		.sink0_data          (cmd_xbar_demux_src5_data),                     //          .data
		.sink0_startofpacket (cmd_xbar_demux_src5_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (cmd_xbar_demux_src5_endofpacket),              //          .endofpacket
		.sink1_ready         (cmd_xbar_demux_001_src1_ready),                //     sink1.ready
		.sink1_valid         (cmd_xbar_demux_001_src1_valid),                //          .valid
		.sink1_channel       (cmd_xbar_demux_001_src1_channel),              //          .channel
		.sink1_data          (cmd_xbar_demux_001_src1_data),                 //          .data
		.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket),        //          .startofpacket
		.sink1_endofpacket   (cmd_xbar_demux_001_src1_endofpacket)           //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_demux_002 rsp_xbar_demux (
		.clk                (avl_clk_out_clk_clk),                          //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (id_router_src_ready),                          //      sink.ready
		.sink_channel       (id_router_src_channel),                        //          .channel
		.sink_data          (id_router_src_data),                           //          .data
		.sink_startofpacket (id_router_src_startofpacket),                  //          .startofpacket
		.sink_endofpacket   (id_router_src_endofpacket),                    //          .endofpacket
		.sink_valid         (id_router_src_valid),                          //          .valid
		.src0_ready         (rsp_xbar_demux_src0_ready),                    //      src0.ready
		.src0_valid         (rsp_xbar_demux_src0_valid),                    //          .valid
		.src0_data          (rsp_xbar_demux_src0_data),                     //          .data
		.src0_channel       (rsp_xbar_demux_src0_channel),                  //          .channel
		.src0_startofpacket (rsp_xbar_demux_src0_startofpacket),            //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_src0_endofpacket)               //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_demux_002 rsp_xbar_demux_001 (
		.clk                (avl_clk_out_clk_clk),                          //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (id_router_001_src_ready),                      //      sink.ready
		.sink_channel       (id_router_001_src_channel),                    //          .channel
		.sink_data          (id_router_001_src_data),                       //          .data
		.sink_startofpacket (id_router_001_src_startofpacket),              //          .startofpacket
		.sink_endofpacket   (id_router_001_src_endofpacket),                //          .endofpacket
		.sink_valid         (id_router_001_src_valid),                      //          .valid
		.src0_ready         (rsp_xbar_demux_001_src0_ready),                //      src0.ready
		.src0_valid         (rsp_xbar_demux_001_src0_valid),                //          .valid
		.src0_data          (rsp_xbar_demux_001_src0_data),                 //          .data
		.src0_channel       (rsp_xbar_demux_001_src0_channel),              //          .channel
		.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_001_src0_endofpacket)           //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_demux_002 rsp_xbar_demux_002 (
		.clk                (avl_clk_out_clk_clk),                          //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (id_router_002_src_ready),                      //      sink.ready
		.sink_channel       (id_router_002_src_channel),                    //          .channel
		.sink_data          (id_router_002_src_data),                       //          .data
		.sink_startofpacket (id_router_002_src_startofpacket),              //          .startofpacket
		.sink_endofpacket   (id_router_002_src_endofpacket),                //          .endofpacket
		.sink_valid         (id_router_002_src_valid),                      //          .valid
		.src0_ready         (rsp_xbar_demux_002_src0_ready),                //      src0.ready
		.src0_valid         (rsp_xbar_demux_002_src0_valid),                //          .valid
		.src0_data          (rsp_xbar_demux_002_src0_data),                 //          .data
		.src0_channel       (rsp_xbar_demux_002_src0_channel),              //          .channel
		.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_002_src0_endofpacket)           //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_rsp_xbar_demux_003 rsp_xbar_demux_003 (
		.clk                (avl_clk_out_clk_clk),                          //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (id_router_003_src_ready),                      //      sink.ready
		.sink_channel       (id_router_003_src_channel),                    //          .channel
		.sink_data          (id_router_003_src_data),                       //          .data
		.sink_startofpacket (id_router_003_src_startofpacket),              //          .startofpacket
		.sink_endofpacket   (id_router_003_src_endofpacket),                //          .endofpacket
		.sink_valid         (id_router_003_src_valid),                      //          .valid
		.src0_ready         (rsp_xbar_demux_003_src0_ready),                //      src0.ready
		.src0_valid         (rsp_xbar_demux_003_src0_valid),                //          .valid
		.src0_data          (rsp_xbar_demux_003_src0_data),                 //          .data
		.src0_channel       (rsp_xbar_demux_003_src0_channel),              //          .channel
		.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_003_src0_endofpacket),          //          .endofpacket
		.src1_ready         (rsp_xbar_demux_003_src1_ready),                //      src1.ready
		.src1_valid         (rsp_xbar_demux_003_src1_valid),                //          .valid
		.src1_data          (rsp_xbar_demux_003_src1_data),                 //          .data
		.src1_channel       (rsp_xbar_demux_003_src1_channel),              //          .channel
		.src1_startofpacket (rsp_xbar_demux_003_src1_startofpacket),        //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_003_src1_endofpacket),          //          .endofpacket
		.src2_ready         (rsp_xbar_demux_003_src2_ready),                //      src2.ready
		.src2_valid         (rsp_xbar_demux_003_src2_valid),                //          .valid
		.src2_data          (rsp_xbar_demux_003_src2_data),                 //          .data
		.src2_channel       (rsp_xbar_demux_003_src2_channel),              //          .channel
		.src2_startofpacket (rsp_xbar_demux_003_src2_startofpacket),        //          .startofpacket
		.src2_endofpacket   (rsp_xbar_demux_003_src2_endofpacket)           //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_cmd_xbar_demux_002 rsp_xbar_demux_004 (
		.clk                (avl_clk_out_clk_clk),                          //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (id_router_004_src_ready),                      //      sink.ready
		.sink_channel       (id_router_004_src_channel),                    //          .channel
		.sink_data          (id_router_004_src_data),                       //          .data
		.sink_startofpacket (id_router_004_src_startofpacket),              //          .startofpacket
		.sink_endofpacket   (id_router_004_src_endofpacket),                //          .endofpacket
		.sink_valid         (id_router_004_src_valid),                      //          .valid
		.src0_ready         (rsp_xbar_demux_004_src0_ready),                //      src0.ready
		.src0_valid         (rsp_xbar_demux_004_src0_valid),                //          .valid
		.src0_data          (rsp_xbar_demux_004_src0_data),                 //          .data
		.src0_channel       (rsp_xbar_demux_004_src0_channel),              //          .channel
		.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_004_src0_endofpacket)           //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_rsp_xbar_demux_005 rsp_xbar_demux_005 (
		.clk                (avl_clk_out_clk_clk),                          //       clk.clk
		.reset              (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (id_router_005_src_ready),                      //      sink.ready
		.sink_channel       (id_router_005_src_channel),                    //          .channel
		.sink_data          (id_router_005_src_data),                       //          .data
		.sink_startofpacket (id_router_005_src_startofpacket),              //          .startofpacket
		.sink_endofpacket   (id_router_005_src_endofpacket),                //          .endofpacket
		.sink_valid         (id_router_005_src_valid),                      //          .valid
		.src0_ready         (rsp_xbar_demux_005_src0_ready),                //      src0.ready
		.src0_valid         (rsp_xbar_demux_005_src0_valid),                //          .valid
		.src0_data          (rsp_xbar_demux_005_src0_data),                 //          .data
		.src0_channel       (rsp_xbar_demux_005_src0_channel),              //          .channel
		.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_005_src0_endofpacket),          //          .endofpacket
		.src1_ready         (rsp_xbar_demux_005_src1_ready),                //      src1.ready
		.src1_valid         (rsp_xbar_demux_005_src1_valid),                //          .valid
		.src1_data          (rsp_xbar_demux_005_src1_data),                 //          .data
		.src1_channel       (rsp_xbar_demux_005_src1_channel),              //          .channel
		.src1_startofpacket (rsp_xbar_demux_005_src1_startofpacket),        //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_005_src1_endofpacket)           //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux (
		.clk                 (avl_clk_out_clk_clk),                          //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_xbar_mux_src_ready),                       //       src.ready
		.src_valid           (rsp_xbar_mux_src_valid),                       //          .valid
		.src_data            (rsp_xbar_mux_src_data),                        //          .data
		.src_channel         (rsp_xbar_mux_src_channel),                     //          .channel
		.src_startofpacket   (rsp_xbar_mux_src_startofpacket),               //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_src_endofpacket),                 //          .endofpacket
		.sink0_ready         (rsp_xbar_demux_src0_ready),                    //     sink0.ready
		.sink0_valid         (rsp_xbar_demux_src0_valid),                    //          .valid
		.sink0_channel       (rsp_xbar_demux_src0_channel),                  //          .channel
		.sink0_data          (rsp_xbar_demux_src0_data),                     //          .data
		.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (rsp_xbar_demux_src0_endofpacket),              //          .endofpacket
		.sink1_ready         (rsp_xbar_demux_001_src0_ready),                //     sink1.ready
		.sink1_valid         (rsp_xbar_demux_001_src0_valid),                //          .valid
		.sink1_channel       (rsp_xbar_demux_001_src0_channel),              //          .channel
		.sink1_data          (rsp_xbar_demux_001_src0_data),                 //          .data
		.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket),        //          .startofpacket
		.sink1_endofpacket   (rsp_xbar_demux_001_src0_endofpacket),          //          .endofpacket
		.sink2_ready         (rsp_xbar_demux_002_src0_ready),                //     sink2.ready
		.sink2_valid         (rsp_xbar_demux_002_src0_valid),                //          .valid
		.sink2_channel       (rsp_xbar_demux_002_src0_channel),              //          .channel
		.sink2_data          (rsp_xbar_demux_002_src0_data),                 //          .data
		.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket),        //          .startofpacket
		.sink2_endofpacket   (rsp_xbar_demux_002_src0_endofpacket),          //          .endofpacket
		.sink3_ready         (rsp_xbar_demux_003_src0_ready),                //     sink3.ready
		.sink3_valid         (rsp_xbar_demux_003_src0_valid),                //          .valid
		.sink3_channel       (rsp_xbar_demux_003_src0_channel),              //          .channel
		.sink3_data          (rsp_xbar_demux_003_src0_data),                 //          .data
		.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket),        //          .startofpacket
		.sink3_endofpacket   (rsp_xbar_demux_003_src0_endofpacket),          //          .endofpacket
		.sink4_ready         (rsp_xbar_demux_004_src0_ready),                //     sink4.ready
		.sink4_valid         (rsp_xbar_demux_004_src0_valid),                //          .valid
		.sink4_channel       (rsp_xbar_demux_004_src0_channel),              //          .channel
		.sink4_data          (rsp_xbar_demux_004_src0_data),                 //          .data
		.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket),        //          .startofpacket
		.sink4_endofpacket   (rsp_xbar_demux_004_src0_endofpacket),          //          .endofpacket
		.sink5_ready         (rsp_xbar_demux_005_src0_ready),                //     sink5.ready
		.sink5_valid         (rsp_xbar_demux_005_src0_valid),                //          .valid
		.sink5_channel       (rsp_xbar_demux_005_src0_channel),              //          .channel
		.sink5_data          (rsp_xbar_demux_005_src0_data),                 //          .data
		.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket),        //          .startofpacket
		.sink5_endofpacket   (rsp_xbar_demux_005_src0_endofpacket)           //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_rsp_xbar_mux_001 rsp_xbar_mux_001 (
		.clk                 (avl_clk_out_clk_clk),                          //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_xbar_mux_001_src_ready),                   //       src.ready
		.src_valid           (rsp_xbar_mux_001_src_valid),                   //          .valid
		.src_data            (rsp_xbar_mux_001_src_data),                    //          .data
		.src_channel         (rsp_xbar_mux_001_src_channel),                 //          .channel
		.src_startofpacket   (rsp_xbar_mux_001_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_001_src_endofpacket),             //          .endofpacket
		.sink0_ready         (rsp_xbar_demux_003_src1_ready),                //     sink0.ready
		.sink0_valid         (rsp_xbar_demux_003_src1_valid),                //          .valid
		.sink0_channel       (rsp_xbar_demux_003_src1_channel),              //          .channel
		.sink0_data          (rsp_xbar_demux_003_src1_data),                 //          .data
		.sink0_startofpacket (rsp_xbar_demux_003_src1_startofpacket),        //          .startofpacket
		.sink0_endofpacket   (rsp_xbar_demux_003_src1_endofpacket),          //          .endofpacket
		.sink1_ready         (rsp_xbar_demux_005_src1_ready),                //     sink1.ready
		.sink1_valid         (rsp_xbar_demux_005_src1_valid),                //          .valid
		.sink1_channel       (rsp_xbar_demux_005_src1_channel),              //          .channel
		.sink1_data          (rsp_xbar_demux_005_src1_data),                 //          .data
		.sink1_startofpacket (rsp_xbar_demux_005_src1_startofpacket),        //          .startofpacket
		.sink1_endofpacket   (rsp_xbar_demux_005_src1_endofpacket)           //          .endofpacket
	);

	DDR3_test_s0_mm_interconnect_0_rsp_xbar_mux_002 rsp_xbar_mux_002 (
		.clk                 (avl_clk_out_clk_clk),                          //       clk.clk
		.reset               (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_xbar_mux_002_src_ready),                   //       src.ready
		.src_valid           (rsp_xbar_mux_002_src_valid),                   //          .valid
		.src_data            (rsp_xbar_mux_002_src_data),                    //          .data
		.src_channel         (rsp_xbar_mux_002_src_channel),                 //          .channel
		.src_startofpacket   (rsp_xbar_mux_002_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_002_src_endofpacket),             //          .endofpacket
		.sink0_ready         (rsp_xbar_demux_003_src2_ready),                //     sink0.ready
		.sink0_valid         (rsp_xbar_demux_003_src2_valid),                //          .valid
		.sink0_channel       (rsp_xbar_demux_003_src2_channel),              //          .channel
		.sink0_data          (rsp_xbar_demux_003_src2_data),                 //          .data
		.sink0_startofpacket (rsp_xbar_demux_003_src2_startofpacket),        //          .startofpacket
		.sink0_endofpacket   (rsp_xbar_demux_003_src2_endofpacket)           //          .endofpacket
	);

endmodule
