# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
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# applicable agreement for further details.
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# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.1.1 Build 166 11/26/2013 SJ Full Version
# Date created = 21:20:49  April 03, 2014
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		DDR3_test_example_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY CYCLONEV
set_global_assignment -name DEVICE AUTO
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:20:49  APRIL 03, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name TOP_LEVEL_ENTITY DDR3_test_example
set_global_assignment -name TEXT_FILE ../params.txt
set_global_assignment -name QIP_FILE DDR3_test_example.qip
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME uniphy_rtl_simulation -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME dut -section_id uniphy_rtl_simulation
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME DDR3_test_example_tb -section_id uniphy_rtl_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH uniphy_rtl_simulation -section_id eda_simulation
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING ON -section_id eda_simulation
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation
# Enable the following line when using Modelsim in order to add some useful UniPHY signals to the wave viewer automatically
#set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT DDR3_test_example_wave.do -section_id eda_simulation
