# system info DDR3_test_example on 2014.04.03.21:20:46
system_info:
name,value
DEVICE,
DEVICE_FAMILY,Cyclone V
GENERATION_ID,
#
#
# Files generated for DDR3_test_example on 2014.04.03.21:20:46
files:
filepath,kind,attributes,module,is_top
DDR3_test_example/DDR3_test_example.v,VERILOG,,DDR3_test_example,true
DDR3_test_example/submodules/DDR3_test_example_if0.v,VERILOG,,DDR3_test_example_if0,false
DDR3_test_example/submodules/DDR3_test_example_d0.v,VERILOG,,DDR3_test_example_d0,false
DDR3_test_example/submodules/DDR3_test_example_mm_interconnect_0.v,VERILOG,,DDR3_test_example_mm_interconnect_0,false
DDR3_test_example/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
DDR3_test_example/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
DDR3_test_example/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
DDR3_test_example/submodules/DDR3_test_example_if0_pll0.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_pll0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_clock_pair_generator.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_read_valid_selector.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_addr_cmd_datapath.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_reset.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_acv_ldc.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_memphy.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_reset_sync.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_new_io_pads.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_fr_cycle_shifter.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_fr_cycle_extender.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_read_datapath.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_write_datapath.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_core_shadow_registers.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_simple_ddio_out.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_phy_csr.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_iss_probe.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_addr_cmd_pads.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_flop_mem.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_altdqdqs.v,VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/altdq_dqs2_acv_cyclonev.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0.ppf,OTHER,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0.sdc,SDC,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_timing.tcl,OTHER,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_report_timing.tcl,OTHER,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_report_timing_core.tcl,OTHER,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_pin_map.tcl,OTHER,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_pin_assignments.tcl,OTHER,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/DDR3_test_example_if0_p0_parameters.tcl,OTHER,,DDR3_test_example_if0_p0,false
DDR3_test_example/submodules/afi_mux_ddr3_ddrx.v,VERILOG,,afi_mux_ddr3_ddrx,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_software/sequencer.c,OTHER,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_software/sequencer.h,OTHER,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_software/sequencer_defines.h,OTHER,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_make_qsys_seq.tcl,OTHER,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_addr_router_002.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/sequencer_scc_acv_phase_decode.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_data_decoder.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_datamux.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/altera_merlin_traffic_limiter.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_cmd_xbar_mux_003.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/sequencer_scc_mgr.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_inst_ROM_reg.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_ram_csr.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_jumplogic.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/altera_merlin_reorder_memory.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_lfsr12.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/sequencer_scc_siii_phase_decode.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_irq_mapper.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_pattern_fifo.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_generic.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_cmd_xbar_mux_005.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/altera_avalon_mm_bridge.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_cmd_xbar_demux_002.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_ac_ROM_reg.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_addr_router.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_lfsr36.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_read_datapath.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_rsp_xbar_demux_005.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/sequencer_scc_acv_wrapper.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_core.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_ddr3.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_addr_router_001.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_rsp_xbar_mux.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_cmd_xbar_demux.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_inst_ROM_no_ifdef_params.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/sequencer_scc_sv_phase_decode.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_cmd_xbar_demux_001.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/sequencer_reg_file.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_ac_ROM_no_ifdef_params.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_bitcheck.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/sequencer_data_mgr.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_write_decoder.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_ram.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/sequencer_scc_sv_wrapper.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/altera_mem_if_sequencer_rst.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/sequencer_phy_mgr.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_rsp_xbar_mux_001.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_id_router_003.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_di_buffer.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_cmd_xbar_mux.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_lfsr72.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_id_router_005.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_id_router.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_di_buffer_wrap.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/sequencer_scc_siii_wrapper.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_data_broadcast.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_rsp_xbar_mux_002.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/sequencer_scc_reg_file.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/rw_manager_dm_decoder.v,VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_mm_interconnect_0_rsp_xbar_demux_003.sv,SYSTEM_VERILOG,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_sequencer_mem.hex,HEX,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_AC_ROM.hex,HEX,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_s0_inst_ROM.hex,HEX,,DDR3_test_example_if0_s0,false
DDR3_test_example/submodules/DDR3_test_example_if0_dmaster.v,VERILOG,,DDR3_test_example_if0_dmaster,false
DDR3_test_example/submodules/DDR3_test_example_if0_c0.v,VERILOG,,DDR3_test_example_if0_c0,false
DDR3_test_example/submodules/altera_mem_if_oct_cyclonev.sv,SYSTEM_VERILOG,,altera_mem_if_oct_cyclonev,false
DDR3_test_example/submodules/altera_mem_if_dll_cyclonev.sv,SYSTEM_VERILOG,,altera_mem_if_dll_cyclonev,false
DDR3_test_example/submodules/DDR3_test_example_if0_mm_interconnect_0.v,VERILOG,,DDR3_test_example_if0_mm_interconnect_0,false
DDR3_test_example/submodules/driver_definitions.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/burst_boundary_addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/lfsr.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/lfsr_wrapper.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/rand_addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/rand_burstcount_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/rand_num_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/rand_seq_addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/reset_sync.v,VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/scfifo_wrapper.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/seq_addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/template_addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/template_stage.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/driver_csr.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/avalon_traffic_gen_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/block_rw_stage_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/driver_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/driver_fsm_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/read_compare_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/single_rw_stage_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
DDR3_test_example/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
DDR3_test_example/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
DDR3_test_example/submodules/altera_avalon_st_jtag_interface.v,VERILOG,,altera_avalon_st_jtag_interface,false
DDR3_test_example/submodules/altera_jtag_dc_streaming.v,VERILOG,,altera_avalon_st_jtag_interface,false
DDR3_test_example/submodules/altera_jtag_sld_node.v,VERILOG,,altera_avalon_st_jtag_interface,false
DDR3_test_example/submodules/altera_jtag_streaming.v,VERILOG,,altera_avalon_st_jtag_interface,false
DDR3_test_example/submodules/altera_pli_streaming.v,VERILOG,,altera_avalon_st_jtag_interface,false
DDR3_test_example/submodules/altera_avalon_st_clock_crosser.v,VERILOG,,altera_avalon_st_jtag_interface,false
DDR3_test_example/submodules/altera_avalon_st_pipeline_base.v,VERILOG,,altera_avalon_st_jtag_interface,false
DDR3_test_example/submodules/altera_avalon_st_idle_remover.v,VERILOG,,altera_avalon_st_jtag_interface,false
DDR3_test_example/submodules/altera_avalon_st_idle_inserter.v,VERILOG,,altera_avalon_st_jtag_interface,false
DDR3_test_example/submodules/altera_avalon_st_jtag_interface.sdc,SDC,,altera_avalon_st_jtag_interface,false
DDR3_test_example/submodules/DDR3_test_example_if0_dmaster_timing_adt.v,VERILOG,,DDR3_test_example_if0_dmaster_timing_adt,false
DDR3_test_example/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
DDR3_test_example/submodules/altera_avalon_st_bytes_to_packets.v,VERILOG,,altera_avalon_st_bytes_to_packets,false
DDR3_test_example/submodules/altera_avalon_st_packets_to_bytes.v,VERILOG,,altera_avalon_st_packets_to_bytes,false
DDR3_test_example/submodules/altera_avalon_packets_to_master.v,VERILOG,,altera_avalon_packets_to_master,false
DDR3_test_example/submodules/DDR3_test_example_if0_dmaster_b2p_adapter.v,VERILOG,,DDR3_test_example_if0_dmaster_b2p_adapter,false
DDR3_test_example/submodules/DDR3_test_example_if0_dmaster_p2b_adapter.v,VERILOG,,DDR3_test_example_if0_dmaster_p2b_adapter,false
DDR3_test_example/submodules/alt_mem_ddrx_addr_cmd.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_addr_cmd_wrap.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_ddr2_odt_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_ddr3_odt_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_odt_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_rdwr_data_tmg.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_arbiter.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_burst_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_cmd_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_csr.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_buffer.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_buffer_manager.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_burst_tracking.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_dataid_manager.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_fifo.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_list.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_rdata_path.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_wdata_path.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_define.iv,VERILOG_INCLUDE,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_ecc_decoder.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_ecc_encoder.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_axi_st_converter.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_input_if.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_rank_timer.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_sideband.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_tbp.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_timing_param.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_controller.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_controller_st_top.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv,SYSTEM_VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
DDR3_test_example/submodules/alt_mem_ddrx_mm_st_converter.v,VERILOG,,alt_mem_ddrx_mm_st_converter,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
DDR3_test_example.if0,DDR3_test_example_if0
DDR3_test_example.if0.pll0,DDR3_test_example_if0_pll0
DDR3_test_example.if0.p0,DDR3_test_example_if0_p0
DDR3_test_example.if0.m0,afi_mux_ddr3_ddrx
DDR3_test_example.if0.s0,DDR3_test_example_if0_s0
DDR3_test_example.if0.dmaster,DDR3_test_example_if0_dmaster
DDR3_test_example.if0.dmaster.jtag_phy_embedded_in_jtag_master,altera_avalon_st_jtag_interface
DDR3_test_example.if0.dmaster.timing_adt,DDR3_test_example_if0_dmaster_timing_adt
DDR3_test_example.if0.dmaster.fifo,altera_avalon_sc_fifo
DDR3_test_example.if0.dmaster.b2p,altera_avalon_st_bytes_to_packets
DDR3_test_example.if0.dmaster.p2b,altera_avalon_st_packets_to_bytes
DDR3_test_example.if0.dmaster.transacto,altera_avalon_packets_to_master
DDR3_test_example.if0.dmaster.b2p_adapter,DDR3_test_example_if0_dmaster_b2p_adapter
DDR3_test_example.if0.dmaster.p2b_adapter,DDR3_test_example_if0_dmaster_p2b_adapter
DDR3_test_example.if0.dmaster.rst_controller,altera_reset_controller
DDR3_test_example.if0.c0,DDR3_test_example_if0_c0
DDR3_test_example.if0.c0.ng0,alt_mem_if_nextgen_ddr3_controller_core
DDR3_test_example.if0.c0.a0,alt_mem_ddrx_mm_st_converter
DDR3_test_example.if0.oct0,altera_mem_if_oct_cyclonev
DDR3_test_example.if0.dll0,altera_mem_if_dll_cyclonev
DDR3_test_example.if0.mm_interconnect_0,DDR3_test_example_if0_mm_interconnect_0
DDR3_test_example.if0.mm_interconnect_0.dmaster_master_translator,altera_merlin_master_translator
DDR3_test_example.if0.mm_interconnect_0.s0_seq_debug_translator,altera_merlin_slave_translator
DDR3_test_example.d0,DDR3_test_example_d0
DDR3_test_example.d0.traffic_generator_0,driver_avl_use_be_avl_use_burstbegin
DDR3_test_example.mm_interconnect_0,DDR3_test_example_mm_interconnect_0
DDR3_test_example.mm_interconnect_0.d0_avl_translator,altera_merlin_master_translator
DDR3_test_example.mm_interconnect_0.if0_avl_translator,altera_merlin_slave_translator
DDR3_test_example.rst_controller,altera_reset_controller
