module register(clk,rst,en,din,dout);
   input clk,rst,en;
   input [7:0] din;
   output [7:0] dout;

   always_ff@(posedge clk)
     begin
	if(rst)
	  dout<=0;
	else if(en)
	  dout<=din;
	else
	  dout<=dout;
     end
endmodule // register
