// lab3_mm_interconnect_0.v

// This file was auto-generated from altera_merlin_interconnect_wrapper_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 13.1.1 166 at 2014.05.01.20:23:37

`timescale 1 ps / 1 ps
module lab3_mm_interconnect_0 (
		input  wire [11:0] hps_0_h2f_lw_axi_master_awid,                                        //                                       hps_0_h2f_lw_axi_master.awid
		input  wire [20:0] hps_0_h2f_lw_axi_master_awaddr,                                      //                                                              .awaddr
		input  wire [3:0]  hps_0_h2f_lw_axi_master_awlen,                                       //                                                              .awlen
		input  wire [2:0]  hps_0_h2f_lw_axi_master_awsize,                                      //                                                              .awsize
		input  wire [1:0]  hps_0_h2f_lw_axi_master_awburst,                                     //                                                              .awburst
		input  wire [1:0]  hps_0_h2f_lw_axi_master_awlock,                                      //                                                              .awlock
		input  wire [3:0]  hps_0_h2f_lw_axi_master_awcache,                                     //                                                              .awcache
		input  wire [2:0]  hps_0_h2f_lw_axi_master_awprot,                                      //                                                              .awprot
		input  wire        hps_0_h2f_lw_axi_master_awvalid,                                     //                                                              .awvalid
		output wire        hps_0_h2f_lw_axi_master_awready,                                     //                                                              .awready
		input  wire [11:0] hps_0_h2f_lw_axi_master_wid,                                         //                                                              .wid
		input  wire [31:0] hps_0_h2f_lw_axi_master_wdata,                                       //                                                              .wdata
		input  wire [3:0]  hps_0_h2f_lw_axi_master_wstrb,                                       //                                                              .wstrb
		input  wire        hps_0_h2f_lw_axi_master_wlast,                                       //                                                              .wlast
		input  wire        hps_0_h2f_lw_axi_master_wvalid,                                      //                                                              .wvalid
		output wire        hps_0_h2f_lw_axi_master_wready,                                      //                                                              .wready
		output wire [11:0] hps_0_h2f_lw_axi_master_bid,                                         //                                                              .bid
		output wire [1:0]  hps_0_h2f_lw_axi_master_bresp,                                       //                                                              .bresp
		output wire        hps_0_h2f_lw_axi_master_bvalid,                                      //                                                              .bvalid
		input  wire        hps_0_h2f_lw_axi_master_bready,                                      //                                                              .bready
		input  wire [11:0] hps_0_h2f_lw_axi_master_arid,                                        //                                                              .arid
		input  wire [20:0] hps_0_h2f_lw_axi_master_araddr,                                      //                                                              .araddr
		input  wire [3:0]  hps_0_h2f_lw_axi_master_arlen,                                       //                                                              .arlen
		input  wire [2:0]  hps_0_h2f_lw_axi_master_arsize,                                      //                                                              .arsize
		input  wire [1:0]  hps_0_h2f_lw_axi_master_arburst,                                     //                                                              .arburst
		input  wire [1:0]  hps_0_h2f_lw_axi_master_arlock,                                      //                                                              .arlock
		input  wire [3:0]  hps_0_h2f_lw_axi_master_arcache,                                     //                                                              .arcache
		input  wire [2:0]  hps_0_h2f_lw_axi_master_arprot,                                      //                                                              .arprot
		input  wire        hps_0_h2f_lw_axi_master_arvalid,                                     //                                                              .arvalid
		output wire        hps_0_h2f_lw_axi_master_arready,                                     //                                                              .arready
		output wire [11:0] hps_0_h2f_lw_axi_master_rid,                                         //                                                              .rid
		output wire [31:0] hps_0_h2f_lw_axi_master_rdata,                                       //                                                              .rdata
		output wire [1:0]  hps_0_h2f_lw_axi_master_rresp,                                       //                                                              .rresp
		output wire        hps_0_h2f_lw_axi_master_rlast,                                       //                                                              .rlast
		output wire        hps_0_h2f_lw_axi_master_rvalid,                                      //                                                              .rvalid
		input  wire        hps_0_h2f_lw_axi_master_rready,                                      //                                                              .rready
		input  wire        clk_0_clk_clk,                                                       //                                                     clk_0_clk.clk
		input  wire        hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
		input  wire        master_0_clk_reset_reset_bridge_in_reset_reset,                      //                      master_0_clk_reset_reset_bridge_in_reset.reset
		input  wire        vga_led_0_reset_sink_reset_bridge_in_reset_reset,                    //                    vga_led_0_reset_sink_reset_bridge_in_reset.reset
		input  wire [31:0] master_0_master_address,                                             //                                               master_0_master.address
		output wire        master_0_master_waitrequest,                                         //                                                              .waitrequest
		input  wire [3:0]  master_0_master_byteenable,                                          //                                                              .byteenable
		input  wire        master_0_master_read,                                                //                                                              .read
		output wire [31:0] master_0_master_readdata,                                            //                                                              .readdata
		output wire        master_0_master_readdatavalid,                                       //                                                              .readdatavalid
		input  wire        master_0_master_write,                                               //                                                              .write
		input  wire [31:0] master_0_master_writedata,                                           //                                                              .writedata
		output wire [3:0]  vga_led_0_avalon_slave_0_address,                                    //                                      vga_led_0_avalon_slave_0.address
		output wire        vga_led_0_avalon_slave_0_write,                                      //                                                              .write
		output wire [7:0]  vga_led_0_avalon_slave_0_writedata,                                  //                                                              .writedata
		output wire        vga_led_0_avalon_slave_0_chipselect                                  //                                                              .chipselect
	);

	wire          rsp_xbar_mux_src_endofpacket;                                                                  // rsp_xbar_mux:src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
	wire          rsp_xbar_mux_src_valid;                                                                        // rsp_xbar_mux:src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
	wire          rsp_xbar_mux_src_startofpacket;                                                                // rsp_xbar_mux:src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
	wire  [122:0] rsp_xbar_mux_src_data;                                                                         // rsp_xbar_mux:src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
	wire    [2:0] rsp_xbar_mux_src_channel;                                                                      // rsp_xbar_mux:src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
	wire          rsp_xbar_mux_src_ready;                                                                        // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> rsp_xbar_mux:src_ready
	wire          rsp_xbar_mux_001_src_endofpacket;                                                              // rsp_xbar_mux_001:src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
	wire          rsp_xbar_mux_001_src_valid;                                                                    // rsp_xbar_mux_001:src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
	wire          rsp_xbar_mux_001_src_startofpacket;                                                            // rsp_xbar_mux_001:src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
	wire  [122:0] rsp_xbar_mux_001_src_data;                                                                     // rsp_xbar_mux_001:src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
	wire    [2:0] rsp_xbar_mux_001_src_channel;                                                                  // rsp_xbar_mux_001:src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
	wire          rsp_xbar_mux_001_src_ready;                                                                    // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> rsp_xbar_mux_001:src_ready
	wire          master_0_master_translator_avalon_universal_master_0_waitrequest;                              // master_0_master_translator_avalon_universal_master_0_agent:av_waitrequest -> master_0_master_translator:uav_waitrequest
	wire    [2:0] master_0_master_translator_avalon_universal_master_0_burstcount;                               // master_0_master_translator:uav_burstcount -> master_0_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [31:0] master_0_master_translator_avalon_universal_master_0_writedata;                                // master_0_master_translator:uav_writedata -> master_0_master_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] master_0_master_translator_avalon_universal_master_0_address;                                  // master_0_master_translator:uav_address -> master_0_master_translator_avalon_universal_master_0_agent:av_address
	wire          master_0_master_translator_avalon_universal_master_0_lock;                                     // master_0_master_translator:uav_lock -> master_0_master_translator_avalon_universal_master_0_agent:av_lock
	wire          master_0_master_translator_avalon_universal_master_0_write;                                    // master_0_master_translator:uav_write -> master_0_master_translator_avalon_universal_master_0_agent:av_write
	wire          master_0_master_translator_avalon_universal_master_0_read;                                     // master_0_master_translator:uav_read -> master_0_master_translator_avalon_universal_master_0_agent:av_read
	wire   [31:0] master_0_master_translator_avalon_universal_master_0_readdata;                                 // master_0_master_translator_avalon_universal_master_0_agent:av_readdata -> master_0_master_translator:uav_readdata
	wire          master_0_master_translator_avalon_universal_master_0_debugaccess;                              // master_0_master_translator:uav_debugaccess -> master_0_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [3:0] master_0_master_translator_avalon_universal_master_0_byteenable;                               // master_0_master_translator:uav_byteenable -> master_0_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire          master_0_master_translator_avalon_universal_master_0_readdatavalid;                            // master_0_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> master_0_master_translator:uav_readdatavalid
	wire          rsp_xbar_mux_002_src_endofpacket;                                                              // rsp_xbar_mux_002:src_endofpacket -> master_0_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          rsp_xbar_mux_002_src_valid;                                                                    // rsp_xbar_mux_002:src_valid -> master_0_master_translator_avalon_universal_master_0_agent:rp_valid
	wire          rsp_xbar_mux_002_src_startofpacket;                                                            // rsp_xbar_mux_002:src_startofpacket -> master_0_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [122:0] rsp_xbar_mux_002_src_data;                                                                     // rsp_xbar_mux_002:src_data -> master_0_master_translator_avalon_universal_master_0_agent:rp_data
	wire    [2:0] rsp_xbar_mux_002_src_channel;                                                                  // rsp_xbar_mux_002:src_channel -> master_0_master_translator_avalon_universal_master_0_agent:rp_channel
	wire          rsp_xbar_mux_002_src_ready;                                                                    // master_0_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_002:src_ready
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest;             // vga_led_0_avalon_slave_0_translator:uav_waitrequest -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [0:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount;              // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> vga_led_0_avalon_slave_0_translator:uav_burstcount
	wire    [7:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata;               // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> vga_led_0_avalon_slave_0_translator:uav_writedata
	wire   [31:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address;                 // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> vga_led_0_avalon_slave_0_translator:uav_address
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write;                   // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> vga_led_0_avalon_slave_0_translator:uav_write
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock;                    // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> vga_led_0_avalon_slave_0_translator:uav_lock
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read;                    // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> vga_led_0_avalon_slave_0_translator:uav_read
	wire    [7:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata;                // vga_led_0_avalon_slave_0_translator:uav_readdata -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid;           // vga_led_0_avalon_slave_0_translator:uav_readdatavalid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess;             // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> vga_led_0_avalon_slave_0_translator:uav_debugaccess
	wire    [0:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable;              // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> vga_led_0_avalon_slave_0_translator:uav_byteenable
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;      // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid;            // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;    // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire   [96:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data;             // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready;            // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;   // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;         // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire   [96:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;          // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;         // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;       // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
	wire    [9:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;        // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;       // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid;       // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire    [9:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data;        // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready;       // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket;                                            // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> addr_router:sink_endofpacket
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_valid;                                                  // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> addr_router:sink_valid
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket;                                          // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> addr_router:sink_startofpacket
	wire  [122:0] hps_0_h2f_lw_axi_master_agent_write_cp_data;                                                   // hps_0_h2f_lw_axi_master_agent:write_cp_data -> addr_router:sink_data
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_ready;                                                  // addr_router:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
	wire          addr_router_src_endofpacket;                                                                   // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
	wire          addr_router_src_valid;                                                                         // addr_router:src_valid -> cmd_xbar_demux:sink_valid
	wire          addr_router_src_startofpacket;                                                                 // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
	wire  [122:0] addr_router_src_data;                                                                          // addr_router:src_data -> cmd_xbar_demux:sink_data
	wire    [2:0] addr_router_src_channel;                                                                       // addr_router:src_channel -> cmd_xbar_demux:sink_channel
	wire          addr_router_src_ready;                                                                         // cmd_xbar_demux:sink_ready -> addr_router:src_ready
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket;                                             // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> addr_router_001:sink_endofpacket
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_valid;                                                   // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> addr_router_001:sink_valid
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket;                                           // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> addr_router_001:sink_startofpacket
	wire  [122:0] hps_0_h2f_lw_axi_master_agent_read_cp_data;                                                    // hps_0_h2f_lw_axi_master_agent:read_cp_data -> addr_router_001:sink_data
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_ready;                                                   // addr_router_001:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
	wire          addr_router_001_src_endofpacket;                                                               // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
	wire          addr_router_001_src_valid;                                                                     // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
	wire          addr_router_001_src_startofpacket;                                                             // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
	wire  [122:0] addr_router_001_src_data;                                                                      // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
	wire    [2:0] addr_router_001_src_channel;                                                                   // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
	wire          addr_router_001_src_ready;                                                                     // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
	wire          master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket;                     // master_0_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
	wire          master_0_master_translator_avalon_universal_master_0_agent_cp_valid;                           // master_0_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
	wire          master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket;                   // master_0_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
	wire  [122:0] master_0_master_translator_avalon_universal_master_0_agent_cp_data;                            // master_0_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
	wire          master_0_master_translator_avalon_universal_master_0_agent_cp_ready;                           // addr_router_002:sink_ready -> master_0_master_translator_avalon_universal_master_0_agent:cp_ready
	wire          addr_router_002_src_endofpacket;                                                               // addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
	wire          addr_router_002_src_valid;                                                                     // addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
	wire          addr_router_002_src_startofpacket;                                                             // addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
	wire  [122:0] addr_router_002_src_data;                                                                      // addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
	wire    [2:0] addr_router_002_src_channel;                                                                   // addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
	wire          addr_router_002_src_ready;                                                                     // cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket;             // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid;                   // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket;           // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
	wire   [95:0] vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data;                    // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
	wire          vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready;                   // id_router:sink_ready -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
	wire          burst_adapter_source0_endofpacket;                                                             // burst_adapter:source0_endofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          burst_adapter_source0_valid;                                                                   // burst_adapter:source0_valid -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
	wire          burst_adapter_source0_startofpacket;                                                           // burst_adapter:source0_startofpacket -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire   [95:0] burst_adapter_source0_data;                                                                    // burst_adapter:source0_data -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
	wire          burst_adapter_source0_ready;                                                                   // vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
	wire    [2:0] burst_adapter_source0_channel;                                                                 // burst_adapter:source0_channel -> vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_xbar_demux_src0_endofpacket;                                                               // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
	wire          cmd_xbar_demux_src0_valid;                                                                     // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
	wire          cmd_xbar_demux_src0_startofpacket;                                                             // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
	wire  [122:0] cmd_xbar_demux_src0_data;                                                                      // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
	wire    [2:0] cmd_xbar_demux_src0_channel;                                                                   // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
	wire          cmd_xbar_demux_src0_ready;                                                                     // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
	wire          cmd_xbar_demux_001_src0_endofpacket;                                                           // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
	wire          cmd_xbar_demux_001_src0_valid;                                                                 // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
	wire          cmd_xbar_demux_001_src0_startofpacket;                                                         // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
	wire  [122:0] cmd_xbar_demux_001_src0_data;                                                                  // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
	wire    [2:0] cmd_xbar_demux_001_src0_channel;                                                               // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
	wire          cmd_xbar_demux_001_src0_ready;                                                                 // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
	wire          cmd_xbar_demux_002_src0_endofpacket;                                                           // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux:sink2_endofpacket
	wire          cmd_xbar_demux_002_src0_valid;                                                                 // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux:sink2_valid
	wire          cmd_xbar_demux_002_src0_startofpacket;                                                         // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux:sink2_startofpacket
	wire  [122:0] cmd_xbar_demux_002_src0_data;                                                                  // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux:sink2_data
	wire    [2:0] cmd_xbar_demux_002_src0_channel;                                                               // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux:sink2_channel
	wire          cmd_xbar_demux_002_src0_ready;                                                                 // cmd_xbar_mux:sink2_ready -> cmd_xbar_demux_002:src0_ready
	wire          rsp_xbar_demux_src0_endofpacket;                                                               // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
	wire          rsp_xbar_demux_src0_valid;                                                                     // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
	wire          rsp_xbar_demux_src0_startofpacket;                                                             // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
	wire  [122:0] rsp_xbar_demux_src0_data;                                                                      // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
	wire    [2:0] rsp_xbar_demux_src0_channel;                                                                   // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
	wire          rsp_xbar_demux_src0_ready;                                                                     // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
	wire          rsp_xbar_demux_src1_endofpacket;                                                               // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
	wire          rsp_xbar_demux_src1_valid;                                                                     // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
	wire          rsp_xbar_demux_src1_startofpacket;                                                             // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
	wire  [122:0] rsp_xbar_demux_src1_data;                                                                      // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
	wire    [2:0] rsp_xbar_demux_src1_channel;                                                                   // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
	wire          rsp_xbar_demux_src1_ready;                                                                     // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
	wire          rsp_xbar_demux_src2_endofpacket;                                                               // rsp_xbar_demux:src2_endofpacket -> rsp_xbar_mux_002:sink0_endofpacket
	wire          rsp_xbar_demux_src2_valid;                                                                     // rsp_xbar_demux:src2_valid -> rsp_xbar_mux_002:sink0_valid
	wire          rsp_xbar_demux_src2_startofpacket;                                                             // rsp_xbar_demux:src2_startofpacket -> rsp_xbar_mux_002:sink0_startofpacket
	wire  [122:0] rsp_xbar_demux_src2_data;                                                                      // rsp_xbar_demux:src2_data -> rsp_xbar_mux_002:sink0_data
	wire    [2:0] rsp_xbar_demux_src2_channel;                                                                   // rsp_xbar_demux:src2_channel -> rsp_xbar_mux_002:sink0_channel
	wire          rsp_xbar_demux_src2_ready;                                                                     // rsp_xbar_mux_002:sink0_ready -> rsp_xbar_demux:src2_ready
	wire          id_router_src_endofpacket;                                                                     // id_router:src_endofpacket -> width_adapter:in_endofpacket
	wire          id_router_src_valid;                                                                           // id_router:src_valid -> width_adapter:in_valid
	wire          id_router_src_startofpacket;                                                                   // id_router:src_startofpacket -> width_adapter:in_startofpacket
	wire   [95:0] id_router_src_data;                                                                            // id_router:src_data -> width_adapter:in_data
	wire    [2:0] id_router_src_channel;                                                                         // id_router:src_channel -> width_adapter:in_channel
	wire          id_router_src_ready;                                                                           // width_adapter:in_ready -> id_router:src_ready
	wire          width_adapter_src_endofpacket;                                                                 // width_adapter:out_endofpacket -> rsp_xbar_demux:sink_endofpacket
	wire          width_adapter_src_valid;                                                                       // width_adapter:out_valid -> rsp_xbar_demux:sink_valid
	wire          width_adapter_src_startofpacket;                                                               // width_adapter:out_startofpacket -> rsp_xbar_demux:sink_startofpacket
	wire  [122:0] width_adapter_src_data;                                                                        // width_adapter:out_data -> rsp_xbar_demux:sink_data
	wire          width_adapter_src_ready;                                                                       // rsp_xbar_demux:sink_ready -> width_adapter:out_ready
	wire    [2:0] width_adapter_src_channel;                                                                     // width_adapter:out_channel -> rsp_xbar_demux:sink_channel
	wire          cmd_xbar_mux_src_endofpacket;                                                                  // cmd_xbar_mux:src_endofpacket -> width_adapter_001:in_endofpacket
	wire          cmd_xbar_mux_src_valid;                                                                        // cmd_xbar_mux:src_valid -> width_adapter_001:in_valid
	wire          cmd_xbar_mux_src_startofpacket;                                                                // cmd_xbar_mux:src_startofpacket -> width_adapter_001:in_startofpacket
	wire  [122:0] cmd_xbar_mux_src_data;                                                                         // cmd_xbar_mux:src_data -> width_adapter_001:in_data
	wire    [2:0] cmd_xbar_mux_src_channel;                                                                      // cmd_xbar_mux:src_channel -> width_adapter_001:in_channel
	wire          cmd_xbar_mux_src_ready;                                                                        // width_adapter_001:in_ready -> cmd_xbar_mux:src_ready
	wire          width_adapter_001_src_endofpacket;                                                             // width_adapter_001:out_endofpacket -> burst_adapter:sink0_endofpacket
	wire          width_adapter_001_src_valid;                                                                   // width_adapter_001:out_valid -> burst_adapter:sink0_valid
	wire          width_adapter_001_src_startofpacket;                                                           // width_adapter_001:out_startofpacket -> burst_adapter:sink0_startofpacket
	wire   [95:0] width_adapter_001_src_data;                                                                    // width_adapter_001:out_data -> burst_adapter:sink0_data
	wire          width_adapter_001_src_ready;                                                                   // burst_adapter:sink0_ready -> width_adapter_001:out_ready
	wire    [2:0] width_adapter_001_src_channel;                                                                 // width_adapter_001:out_channel -> burst_adapter:sink0_channel

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) master_0_master_translator (
		.clk                      (clk_0_clk_clk),                                                      //                       clk.clk
		.reset                    (vga_led_0_reset_sink_reset_bridge_in_reset_reset),                   //                     reset.reset
		.uav_address              (master_0_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount           (master_0_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read                 (master_0_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write                (master_0_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest          (master_0_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid        (master_0_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable           (master_0_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata             (master_0_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata            (master_0_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock                 (master_0_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess          (master_0_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address               (master_0_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest           (master_0_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable            (master_0_master_byteenable),                                         //                          .byteenable
		.av_read                  (master_0_master_read),                                               //                          .read
		.av_readdata              (master_0_master_readdata),                                           //                          .readdata
		.av_readdatavalid         (master_0_master_readdatavalid),                                      //                          .readdatavalid
		.av_write                 (master_0_master_write),                                              //                          .write
		.av_writedata             (master_0_master_writedata),                                          //                          .writedata
		.av_burstcount            (1'b1),                                                               //               (terminated)
		.av_beginbursttransfer    (1'b0),                                                               //               (terminated)
		.av_begintransfer         (1'b0),                                                               //               (terminated)
		.av_chipselect            (1'b0),                                                               //               (terminated)
		.av_lock                  (1'b0),                                                               //               (terminated)
		.av_debugaccess           (1'b0),                                                               //               (terminated)
		.uav_clken                (),                                                                   //               (terminated)
		.av_clken                 (1'b1),                                                               //               (terminated)
		.uav_response             (2'b00),                                                              //               (terminated)
		.av_response              (),                                                                   //               (terminated)
		.uav_writeresponserequest (),                                                                   //               (terminated)
		.uav_writeresponsevalid   (1'b0),                                                               //               (terminated)
		.av_writeresponserequest  (1'b0),                                                               //               (terminated)
		.av_writeresponsevalid    ()                                                                    //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (4),
		.AV_DATA_W                      (8),
		.UAV_DATA_W                     (8),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (1),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (1),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (1),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) vga_led_0_avalon_slave_0_translator (
		.clk                      (clk_0_clk_clk),                                                                       //                      clk.clk
		.reset                    (vga_led_0_reset_sink_reset_bridge_in_reset_reset),                                    //                    reset.reset
		.uav_address              (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount           (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read                 (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write                (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid        (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable           (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata             (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata            (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock                 (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address               (vga_led_0_avalon_slave_0_address),                                                    //      avalon_anti_slave_0.address
		.av_write                 (vga_led_0_avalon_slave_0_write),                                                      //                         .write
		.av_writedata             (vga_led_0_avalon_slave_0_writedata),                                                  //                         .writedata
		.av_chipselect            (vga_led_0_avalon_slave_0_chipselect),                                                 //                         .chipselect
		.av_read                  (),                                                                                    //              (terminated)
		.av_readdata              (8'b10101101),                                                                         //              (terminated)
		.av_begintransfer         (),                                                                                    //              (terminated)
		.av_beginbursttransfer    (),                                                                                    //              (terminated)
		.av_burstcount            (),                                                                                    //              (terminated)
		.av_byteenable            (),                                                                                    //              (terminated)
		.av_readdatavalid         (1'b0),                                                                                //              (terminated)
		.av_waitrequest           (1'b0),                                                                                //              (terminated)
		.av_writebyteenable       (),                                                                                    //              (terminated)
		.av_lock                  (),                                                                                    //              (terminated)
		.av_clken                 (),                                                                                    //              (terminated)
		.uav_clken                (1'b0),                                                                                //              (terminated)
		.av_debugaccess           (),                                                                                    //              (terminated)
		.av_outputenable          (),                                                                                    //              (terminated)
		.uav_response             (),                                                                                    //              (terminated)
		.av_response              (2'b00),                                                                               //              (terminated)
		.uav_writeresponserequest (1'b0),                                                                                //              (terminated)
		.uav_writeresponsevalid   (),                                                                                    //              (terminated)
		.av_writeresponserequest  (),                                                                                    //              (terminated)
		.av_writeresponsevalid    (1'b0)                                                                                 //              (terminated)
	);

	altera_merlin_axi_master_ni #(
		.ID_WIDTH                  (12),
		.ADDR_WIDTH                (21),
		.RDATA_WIDTH               (32),
		.WDATA_WIDTH               (32),
		.ADDR_USER_WIDTH           (1),
		.DATA_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (4),
		.AXI_LOCK_WIDTH            (2),
		.AXI_VERSION               ("AXI3"),
		.WRITE_ISSUING_CAPABILITY  (8),
		.READ_ISSUING_CAPABILITY   (8),
		.PKT_BEGIN_BURST           (95),
		.PKT_CACHE_H               (117),
		.PKT_CACHE_L               (114),
		.PKT_ADDR_SIDEBAND_H       (93),
		.PKT_ADDR_SIDEBAND_L       (93),
		.PKT_PROTECTION_H          (113),
		.PKT_PROTECTION_L          (111),
		.PKT_BURST_SIZE_H          (90),
		.PKT_BURST_SIZE_L          (88),
		.PKT_BURST_TYPE_H          (92),
		.PKT_BURST_TYPE_L          (91),
		.PKT_RESPONSE_STATUS_L     (118),
		.PKT_RESPONSE_STATUS_H     (119),
		.PKT_BURSTWRAP_H           (87),
		.PKT_BURSTWRAP_L           (81),
		.PKT_BYTE_CNT_H            (80),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (97),
		.PKT_SRC_ID_L              (97),
		.PKT_DEST_ID_H             (98),
		.PKT_DEST_ID_L             (98),
		.PKT_THREAD_ID_H           (110),
		.PKT_THREAD_ID_L           (99),
		.PKT_QOS_L                 (96),
		.PKT_QOS_H                 (96),
		.PKT_ORI_BURST_SIZE_L      (120),
		.PKT_ORI_BURST_SIZE_H      (122),
		.PKT_DATA_SIDEBAND_H       (94),
		.PKT_DATA_SIDEBAND_L       (94),
		.ST_DATA_W                 (123),
		.ST_CHANNEL_W              (3),
		.ID                        (0)
	) hps_0_h2f_lw_axi_master_agent (
		.aclk                   (clk_0_clk_clk),                                                        //              clk.clk
		.aresetn                (~hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //        clk_reset.reset_n
		.write_cp_valid         (hps_0_h2f_lw_axi_master_agent_write_cp_valid),                         //         write_cp.valid
		.write_cp_data          (hps_0_h2f_lw_axi_master_agent_write_cp_data),                          //                 .data
		.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket),                 //                 .startofpacket
		.write_cp_endofpacket   (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket),                   //                 .endofpacket
		.write_cp_ready         (hps_0_h2f_lw_axi_master_agent_write_cp_ready),                         //                 .ready
		.write_rp_valid         (rsp_xbar_mux_src_valid),                                               //         write_rp.valid
		.write_rp_data          (rsp_xbar_mux_src_data),                                                //                 .data
		.write_rp_channel       (rsp_xbar_mux_src_channel),                                             //                 .channel
		.write_rp_startofpacket (rsp_xbar_mux_src_startofpacket),                                       //                 .startofpacket
		.write_rp_endofpacket   (rsp_xbar_mux_src_endofpacket),                                         //                 .endofpacket
		.write_rp_ready         (rsp_xbar_mux_src_ready),                                               //                 .ready
		.read_cp_valid          (hps_0_h2f_lw_axi_master_agent_read_cp_valid),                          //          read_cp.valid
		.read_cp_data           (hps_0_h2f_lw_axi_master_agent_read_cp_data),                           //                 .data
		.read_cp_startofpacket  (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket),                  //                 .startofpacket
		.read_cp_endofpacket    (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket),                    //                 .endofpacket
		.read_cp_ready          (hps_0_h2f_lw_axi_master_agent_read_cp_ready),                          //                 .ready
		.read_rp_valid          (rsp_xbar_mux_001_src_valid),                                           //          read_rp.valid
		.read_rp_data           (rsp_xbar_mux_001_src_data),                                            //                 .data
		.read_rp_channel        (rsp_xbar_mux_001_src_channel),                                         //                 .channel
		.read_rp_startofpacket  (rsp_xbar_mux_001_src_startofpacket),                                   //                 .startofpacket
		.read_rp_endofpacket    (rsp_xbar_mux_001_src_endofpacket),                                     //                 .endofpacket
		.read_rp_ready          (rsp_xbar_mux_001_src_ready),                                           //                 .ready
		.awid                   (hps_0_h2f_lw_axi_master_awid),                                         // altera_axi_slave.awid
		.awaddr                 (hps_0_h2f_lw_axi_master_awaddr),                                       //                 .awaddr
		.awlen                  (hps_0_h2f_lw_axi_master_awlen),                                        //                 .awlen
		.awsize                 (hps_0_h2f_lw_axi_master_awsize),                                       //                 .awsize
		.awburst                (hps_0_h2f_lw_axi_master_awburst),                                      //                 .awburst
		.awlock                 (hps_0_h2f_lw_axi_master_awlock),                                       //                 .awlock
		.awcache                (hps_0_h2f_lw_axi_master_awcache),                                      //                 .awcache
		.awprot                 (hps_0_h2f_lw_axi_master_awprot),                                       //                 .awprot
		.awvalid                (hps_0_h2f_lw_axi_master_awvalid),                                      //                 .awvalid
		.awready                (hps_0_h2f_lw_axi_master_awready),                                      //                 .awready
		.wid                    (hps_0_h2f_lw_axi_master_wid),                                          //                 .wid
		.wdata                  (hps_0_h2f_lw_axi_master_wdata),                                        //                 .wdata
		.wstrb                  (hps_0_h2f_lw_axi_master_wstrb),                                        //                 .wstrb
		.wlast                  (hps_0_h2f_lw_axi_master_wlast),                                        //                 .wlast
		.wvalid                 (hps_0_h2f_lw_axi_master_wvalid),                                       //                 .wvalid
		.wready                 (hps_0_h2f_lw_axi_master_wready),                                       //                 .wready
		.bid                    (hps_0_h2f_lw_axi_master_bid),                                          //                 .bid
		.bresp                  (hps_0_h2f_lw_axi_master_bresp),                                        //                 .bresp
		.bvalid                 (hps_0_h2f_lw_axi_master_bvalid),                                       //                 .bvalid
		.bready                 (hps_0_h2f_lw_axi_master_bready),                                       //                 .bready
		.arid                   (hps_0_h2f_lw_axi_master_arid),                                         //                 .arid
		.araddr                 (hps_0_h2f_lw_axi_master_araddr),                                       //                 .araddr
		.arlen                  (hps_0_h2f_lw_axi_master_arlen),                                        //                 .arlen
		.arsize                 (hps_0_h2f_lw_axi_master_arsize),                                       //                 .arsize
		.arburst                (hps_0_h2f_lw_axi_master_arburst),                                      //                 .arburst
		.arlock                 (hps_0_h2f_lw_axi_master_arlock),                                       //                 .arlock
		.arcache                (hps_0_h2f_lw_axi_master_arcache),                                      //                 .arcache
		.arprot                 (hps_0_h2f_lw_axi_master_arprot),                                       //                 .arprot
		.arvalid                (hps_0_h2f_lw_axi_master_arvalid),                                      //                 .arvalid
		.arready                (hps_0_h2f_lw_axi_master_arready),                                      //                 .arready
		.rid                    (hps_0_h2f_lw_axi_master_rid),                                          //                 .rid
		.rdata                  (hps_0_h2f_lw_axi_master_rdata),                                        //                 .rdata
		.rresp                  (hps_0_h2f_lw_axi_master_rresp),                                        //                 .rresp
		.rlast                  (hps_0_h2f_lw_axi_master_rlast),                                        //                 .rlast
		.rvalid                 (hps_0_h2f_lw_axi_master_rvalid),                                       //                 .rvalid
		.rready                 (hps_0_h2f_lw_axi_master_rready),                                       //                 .rready
		.awuser                 (1'b0),                                                                 //      (terminated)
		.aruser                 (1'b0),                                                                 //      (terminated)
		.awqos                  (4'b0000),                                                              //      (terminated)
		.arqos                  (4'b0000),                                                              //      (terminated)
		.awregion               (4'b0000),                                                              //      (terminated)
		.arregion               (4'b0000),                                                              //      (terminated)
		.wuser                  (8'b00000000),                                                          //      (terminated)
		.ruser                  (),                                                                     //      (terminated)
		.buser                  ()                                                                      //      (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (113),
		.PKT_PROTECTION_L          (111),
		.PKT_BEGIN_BURST           (95),
		.PKT_BURSTWRAP_H           (87),
		.PKT_BURSTWRAP_L           (81),
		.PKT_BURST_SIZE_H          (90),
		.PKT_BURST_SIZE_L          (88),
		.PKT_BURST_TYPE_H          (92),
		.PKT_BURST_TYPE_L          (91),
		.PKT_BYTE_CNT_H            (80),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (97),
		.PKT_SRC_ID_L              (97),
		.PKT_DEST_ID_H             (98),
		.PKT_DEST_ID_L             (98),
		.PKT_THREAD_ID_H           (110),
		.PKT_THREAD_ID_L           (99),
		.PKT_CACHE_H               (117),
		.PKT_CACHE_L               (114),
		.PKT_DATA_SIDEBAND_H       (94),
		.PKT_DATA_SIDEBAND_L       (94),
		.PKT_QOS_H                 (96),
		.PKT_QOS_L                 (96),
		.PKT_ADDR_SIDEBAND_H       (93),
		.PKT_ADDR_SIDEBAND_L       (93),
		.PKT_RESPONSE_STATUS_H     (119),
		.PKT_RESPONSE_STATUS_L     (118),
		.PKT_ORI_BURST_SIZE_L      (120),
		.PKT_ORI_BURST_SIZE_H      (122),
		.ST_DATA_W                 (123),
		.ST_CHANNEL_W              (3),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (127),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) master_0_master_translator_avalon_universal_master_0_agent (
		.clk                     (clk_0_clk_clk),                                                               //       clk.clk
		.reset                   (vga_led_0_reset_sink_reset_bridge_in_reset_reset),                            // clk_reset.reset
		.av_address              (master_0_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write                (master_0_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read                 (master_0_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata            (master_0_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata             (master_0_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest          (master_0_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid        (master_0_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable           (master_0_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount           (master_0_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess          (master_0_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock                 (master_0_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid                (master_0_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data                 (master_0_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket        (master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket          (master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready                (master_0_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid                (rsp_xbar_mux_002_src_valid),                                                  //        rp.valid
		.rp_data                 (rsp_xbar_mux_002_src_data),                                                   //          .data
		.rp_channel              (rsp_xbar_mux_002_src_channel),                                                //          .channel
		.rp_startofpacket        (rsp_xbar_mux_002_src_startofpacket),                                          //          .startofpacket
		.rp_endofpacket          (rsp_xbar_mux_002_src_endofpacket),                                            //          .endofpacket
		.rp_ready                (rsp_xbar_mux_002_src_ready),                                                  //          .ready
		.av_response             (),                                                                            // (terminated)
		.av_writeresponserequest (1'b0),                                                                        // (terminated)
		.av_writeresponsevalid   ()                                                                             // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (7),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (68),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (8),
		.PKT_BYTEEN_L              (8),
		.PKT_ADDR_H                (40),
		.PKT_ADDR_L                (9),
		.PKT_TRANS_COMPRESSED_READ (41),
		.PKT_TRANS_POSTED          (42),
		.PKT_TRANS_WRITE           (43),
		.PKT_TRANS_READ            (44),
		.PKT_TRANS_LOCK            (45),
		.PKT_SRC_ID_H              (70),
		.PKT_SRC_ID_L              (70),
		.PKT_DEST_ID_H             (71),
		.PKT_DEST_ID_L             (71),
		.PKT_BURSTWRAP_H           (60),
		.PKT_BURSTWRAP_L           (54),
		.PKT_BYTE_CNT_H            (53),
		.PKT_BYTE_CNT_L            (47),
		.PKT_PROTECTION_H          (86),
		.PKT_PROTECTION_L          (84),
		.PKT_RESPONSE_STATUS_H     (92),
		.PKT_RESPONSE_STATUS_L     (91),
		.PKT_BURST_SIZE_H          (63),
		.PKT_BURST_SIZE_L          (61),
		.PKT_ORI_BURST_SIZE_L      (93),
		.PKT_ORI_BURST_SIZE_H      (95),
		.ST_CHANNEL_W              (3),
		.ST_DATA_W                 (96),
		.AVS_BURSTCOUNT_W          (1),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
		.clk                     (clk_0_clk_clk),                                                                                 //             clk.clk
		.reset                   (vga_led_0_reset_sink_reset_bridge_in_reset_reset),                                              //       clk_reset.reset
		.m0_address              (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (burst_adapter_source0_ready),                                                                   //              cp.ready
		.cp_valid                (burst_adapter_source0_valid),                                                                   //                .valid
		.cp_data                 (burst_adapter_source0_data),                                                                    //                .data
		.cp_startofpacket        (burst_adapter_source0_startofpacket),                                                           //                .startofpacket
		.cp_endofpacket          (burst_adapter_source0_endofpacket),                                                             //                .endofpacket
		.cp_channel              (burst_adapter_source0_channel),                                                                 //                .channel
		.rf_sink_ready           (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid),       //                .valid
		.rdata_fifo_sink_data    (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),        //                .data
		.rdata_fifo_src_ready    (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                                                         //     (terminated)
		.m0_writeresponserequest (),                                                                                              //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                                           //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (97),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (clk_0_clk_clk),                                                                                 //       clk.clk
		.reset             (vga_led_0_reset_sink_reset_bridge_in_reset_reset),                                              // clk_reset.reset
		.in_data           (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                         // (terminated)
		.csr_read          (1'b0),                                                                                          // (terminated)
		.csr_write         (1'b0),                                                                                          // (terminated)
		.csr_readdata      (),                                                                                              // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                          // (terminated)
		.almost_full_data  (),                                                                                              // (terminated)
		.almost_empty_data (),                                                                                              // (terminated)
		.in_empty          (1'b0),                                                                                          // (terminated)
		.out_empty         (),                                                                                              // (terminated)
		.in_error          (1'b0),                                                                                          // (terminated)
		.out_error         (),                                                                                              // (terminated)
		.in_channel        (1'b0),                                                                                          // (terminated)
		.out_channel       ()                                                                                               // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (10),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo (
		.clk               (clk_0_clk_clk),                                                                           //       clk.clk
		.reset             (vga_led_0_reset_sink_reset_bridge_in_reset_reset),                                        // clk_reset.reset
		.in_data           (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_startofpacket  (1'b0),                                                                                    // (terminated)
		.in_endofpacket    (1'b0),                                                                                    // (terminated)
		.out_startofpacket (),                                                                                        // (terminated)
		.out_endofpacket   (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	lab3_mm_interconnect_0_addr_router addr_router (
		.sink_ready         (hps_0_h2f_lw_axi_master_agent_write_cp_ready),                        //      sink.ready
		.sink_valid         (hps_0_h2f_lw_axi_master_agent_write_cp_valid),                        //          .valid
		.sink_data          (hps_0_h2f_lw_axi_master_agent_write_cp_data),                         //          .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket),                //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket),                  //          .endofpacket
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (addr_router_src_ready),                                               //       src.ready
		.src_valid          (addr_router_src_valid),                                               //          .valid
		.src_data           (addr_router_src_data),                                                //          .data
		.src_channel        (addr_router_src_channel),                                             //          .channel
		.src_startofpacket  (addr_router_src_startofpacket),                                       //          .startofpacket
		.src_endofpacket    (addr_router_src_endofpacket)                                          //          .endofpacket
	);

	lab3_mm_interconnect_0_addr_router addr_router_001 (
		.sink_ready         (hps_0_h2f_lw_axi_master_agent_read_cp_ready),                         //      sink.ready
		.sink_valid         (hps_0_h2f_lw_axi_master_agent_read_cp_valid),                         //          .valid
		.sink_data          (hps_0_h2f_lw_axi_master_agent_read_cp_data),                          //          .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket),                   //          .endofpacket
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (addr_router_001_src_ready),                                           //       src.ready
		.src_valid          (addr_router_001_src_valid),                                           //          .valid
		.src_data           (addr_router_001_src_data),                                            //          .data
		.src_channel        (addr_router_001_src_channel),                                         //          .channel
		.src_startofpacket  (addr_router_001_src_startofpacket),                                   //          .startofpacket
		.src_endofpacket    (addr_router_001_src_endofpacket)                                      //          .endofpacket
	);

	lab3_mm_interconnect_0_addr_router addr_router_002 (
		.sink_ready         (master_0_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (master_0_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (master_0_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (master_0_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (master_0_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (clk_0_clk_clk),                                                               //       clk.clk
		.reset              (vga_led_0_reset_sink_reset_bridge_in_reset_reset),                            // clk_reset.reset
		.src_ready          (addr_router_002_src_ready),                                                   //       src.ready
		.src_valid          (addr_router_002_src_valid),                                                   //          .valid
		.src_data           (addr_router_002_src_data),                                                    //          .data
		.src_channel        (addr_router_002_src_channel),                                                 //          .channel
		.src_startofpacket  (addr_router_002_src_startofpacket),                                           //          .startofpacket
		.src_endofpacket    (addr_router_002_src_endofpacket)                                              //          .endofpacket
	);

	lab3_mm_interconnect_0_id_router id_router (
		.sink_ready         (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (vga_led_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_0_clk_clk),                                                                       //       clk.clk
		.reset              (vga_led_0_reset_sink_reset_bridge_in_reset_reset),                                    // clk_reset.reset
		.src_ready          (id_router_src_ready),                                                                 //       src.ready
		.src_valid          (id_router_src_valid),                                                                 //          .valid
		.src_data           (id_router_src_data),                                                                  //          .data
		.src_channel        (id_router_src_channel),                                                               //          .channel
		.src_startofpacket  (id_router_src_startofpacket),                                                         //          .startofpacket
		.src_endofpacket    (id_router_src_endofpacket)                                                            //          .endofpacket
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (40),
		.PKT_ADDR_L                (9),
		.PKT_BEGIN_BURST           (68),
		.PKT_BYTE_CNT_H            (53),
		.PKT_BYTE_CNT_L            (47),
		.PKT_BYTEEN_H              (8),
		.PKT_BYTEEN_L              (8),
		.PKT_BURST_SIZE_H          (63),
		.PKT_BURST_SIZE_L          (61),
		.PKT_BURST_TYPE_H          (65),
		.PKT_BURST_TYPE_L          (64),
		.PKT_BURSTWRAP_H           (60),
		.PKT_BURSTWRAP_L           (54),
		.PKT_TRANS_COMPRESSED_READ (41),
		.PKT_TRANS_WRITE           (43),
		.PKT_TRANS_READ            (44),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (96),
		.ST_CHANNEL_W              (3),
		.OUT_BYTE_CNT_H            (47),
		.OUT_BURSTWRAP_H           (60),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0)
	) burst_adapter (
		.clk                   (clk_0_clk_clk),                                    //       cr0.clk
		.reset                 (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // cr0_reset.reset
		.sink0_valid           (width_adapter_001_src_valid),                      //     sink0.valid
		.sink0_data            (width_adapter_001_src_data),                       //          .data
		.sink0_channel         (width_adapter_001_src_channel),                    //          .channel
		.sink0_startofpacket   (width_adapter_001_src_startofpacket),              //          .startofpacket
		.sink0_endofpacket     (width_adapter_001_src_endofpacket),                //          .endofpacket
		.sink0_ready           (width_adapter_001_src_ready),                      //          .ready
		.source0_valid         (burst_adapter_source0_valid),                      //   source0.valid
		.source0_data          (burst_adapter_source0_data),                       //          .data
		.source0_channel       (burst_adapter_source0_channel),                    //          .channel
		.source0_startofpacket (burst_adapter_source0_startofpacket),              //          .startofpacket
		.source0_endofpacket   (burst_adapter_source0_endofpacket),                //          .endofpacket
		.source0_ready         (burst_adapter_source0_ready)                       //          .ready
	);

	lab3_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux (
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (addr_router_src_ready),                                               //      sink.ready
		.sink_channel       (addr_router_src_channel),                                             //          .channel
		.sink_data          (addr_router_src_data),                                                //          .data
		.sink_startofpacket (addr_router_src_startofpacket),                                       //          .startofpacket
		.sink_endofpacket   (addr_router_src_endofpacket),                                         //          .endofpacket
		.sink_valid         (addr_router_src_valid),                                               //          .valid
		.src0_ready         (cmd_xbar_demux_src0_ready),                                           //      src0.ready
		.src0_valid         (cmd_xbar_demux_src0_valid),                                           //          .valid
		.src0_data          (cmd_xbar_demux_src0_data),                                            //          .data
		.src0_channel       (cmd_xbar_demux_src0_channel),                                         //          .channel
		.src0_startofpacket (cmd_xbar_demux_src0_startofpacket),                                   //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_src0_endofpacket)                                      //          .endofpacket
	);

	lab3_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux_001 (
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (addr_router_001_src_ready),                                           //      sink.ready
		.sink_channel       (addr_router_001_src_channel),                                         //          .channel
		.sink_data          (addr_router_001_src_data),                                            //          .data
		.sink_startofpacket (addr_router_001_src_startofpacket),                                   //          .startofpacket
		.sink_endofpacket   (addr_router_001_src_endofpacket),                                     //          .endofpacket
		.sink_valid         (addr_router_001_src_valid),                                           //          .valid
		.src0_ready         (cmd_xbar_demux_001_src0_ready),                                       //      src0.ready
		.src0_valid         (cmd_xbar_demux_001_src0_valid),                                       //          .valid
		.src0_data          (cmd_xbar_demux_001_src0_data),                                        //          .data
		.src0_channel       (cmd_xbar_demux_001_src0_channel),                                     //          .channel
		.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket),                               //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_001_src0_endofpacket)                                  //          .endofpacket
	);

	lab3_mm_interconnect_0_cmd_xbar_demux cmd_xbar_demux_002 (
		.clk                (clk_0_clk_clk),                                    //       clk.clk
		.reset              (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (addr_router_002_src_ready),                        //      sink.ready
		.sink_channel       (addr_router_002_src_channel),                      //          .channel
		.sink_data          (addr_router_002_src_data),                         //          .data
		.sink_startofpacket (addr_router_002_src_startofpacket),                //          .startofpacket
		.sink_endofpacket   (addr_router_002_src_endofpacket),                  //          .endofpacket
		.sink_valid         (addr_router_002_src_valid),                        //          .valid
		.src0_ready         (cmd_xbar_demux_002_src0_ready),                    //      src0.ready
		.src0_valid         (cmd_xbar_demux_002_src0_valid),                    //          .valid
		.src0_data          (cmd_xbar_demux_002_src0_data),                     //          .data
		.src0_channel       (cmd_xbar_demux_002_src0_channel),                  //          .channel
		.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket),            //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_002_src0_endofpacket)               //          .endofpacket
	);

	lab3_mm_interconnect_0_cmd_xbar_mux cmd_xbar_mux (
		.clk                 (clk_0_clk_clk),                                    //       clk.clk
		.reset               (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_src_ready),                           //       src.ready
		.src_valid           (cmd_xbar_mux_src_valid),                           //          .valid
		.src_data            (cmd_xbar_mux_src_data),                            //          .data
		.src_channel         (cmd_xbar_mux_src_channel),                         //          .channel
		.src_startofpacket   (cmd_xbar_mux_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (cmd_xbar_demux_src0_ready),                        //     sink0.ready
		.sink0_valid         (cmd_xbar_demux_src0_valid),                        //          .valid
		.sink0_channel       (cmd_xbar_demux_src0_channel),                      //          .channel
		.sink0_data          (cmd_xbar_demux_src0_data),                         //          .data
		.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket),                //          .startofpacket
		.sink0_endofpacket   (cmd_xbar_demux_src0_endofpacket),                  //          .endofpacket
		.sink1_ready         (cmd_xbar_demux_001_src0_ready),                    //     sink1.ready
		.sink1_valid         (cmd_xbar_demux_001_src0_valid),                    //          .valid
		.sink1_channel       (cmd_xbar_demux_001_src0_channel),                  //          .channel
		.sink1_data          (cmd_xbar_demux_001_src0_data),                     //          .data
		.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket),            //          .startofpacket
		.sink1_endofpacket   (cmd_xbar_demux_001_src0_endofpacket),              //          .endofpacket
		.sink2_ready         (cmd_xbar_demux_002_src0_ready),                    //     sink2.ready
		.sink2_valid         (cmd_xbar_demux_002_src0_valid),                    //          .valid
		.sink2_channel       (cmd_xbar_demux_002_src0_channel),                  //          .channel
		.sink2_data          (cmd_xbar_demux_002_src0_data),                     //          .data
		.sink2_startofpacket (cmd_xbar_demux_002_src0_startofpacket),            //          .startofpacket
		.sink2_endofpacket   (cmd_xbar_demux_002_src0_endofpacket)               //          .endofpacket
	);

	lab3_mm_interconnect_0_rsp_xbar_demux rsp_xbar_demux (
		.clk                (clk_0_clk_clk),                                    //       clk.clk
		.reset              (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (width_adapter_src_ready),                          //      sink.ready
		.sink_channel       (width_adapter_src_channel),                        //          .channel
		.sink_data          (width_adapter_src_data),                           //          .data
		.sink_startofpacket (width_adapter_src_startofpacket),                  //          .startofpacket
		.sink_endofpacket   (width_adapter_src_endofpacket),                    //          .endofpacket
		.sink_valid         (width_adapter_src_valid),                          //          .valid
		.src0_ready         (rsp_xbar_demux_src0_ready),                        //      src0.ready
		.src0_valid         (rsp_xbar_demux_src0_valid),                        //          .valid
		.src0_data          (rsp_xbar_demux_src0_data),                         //          .data
		.src0_channel       (rsp_xbar_demux_src0_channel),                      //          .channel
		.src0_startofpacket (rsp_xbar_demux_src0_startofpacket),                //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_src0_endofpacket),                  //          .endofpacket
		.src1_ready         (rsp_xbar_demux_src1_ready),                        //      src1.ready
		.src1_valid         (rsp_xbar_demux_src1_valid),                        //          .valid
		.src1_data          (rsp_xbar_demux_src1_data),                         //          .data
		.src1_channel       (rsp_xbar_demux_src1_channel),                      //          .channel
		.src1_startofpacket (rsp_xbar_demux_src1_startofpacket),                //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_src1_endofpacket),                  //          .endofpacket
		.src2_ready         (rsp_xbar_demux_src2_ready),                        //      src2.ready
		.src2_valid         (rsp_xbar_demux_src2_valid),                        //          .valid
		.src2_data          (rsp_xbar_demux_src2_data),                         //          .data
		.src2_channel       (rsp_xbar_demux_src2_channel),                      //          .channel
		.src2_startofpacket (rsp_xbar_demux_src2_startofpacket),                //          .startofpacket
		.src2_endofpacket   (rsp_xbar_demux_src2_endofpacket)                   //          .endofpacket
	);

	lab3_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux (
		.clk                 (clk_0_clk_clk),                                                       //       clk.clk
		.reset               (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_xbar_mux_src_ready),                                              //       src.ready
		.src_valid           (rsp_xbar_mux_src_valid),                                              //          .valid
		.src_data            (rsp_xbar_mux_src_data),                                               //          .data
		.src_channel         (rsp_xbar_mux_src_channel),                                            //          .channel
		.src_startofpacket   (rsp_xbar_mux_src_startofpacket),                                      //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_src_endofpacket),                                        //          .endofpacket
		.sink0_ready         (rsp_xbar_demux_src0_ready),                                           //     sink0.ready
		.sink0_valid         (rsp_xbar_demux_src0_valid),                                           //          .valid
		.sink0_channel       (rsp_xbar_demux_src0_channel),                                         //          .channel
		.sink0_data          (rsp_xbar_demux_src0_data),                                            //          .data
		.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket),                                   //          .startofpacket
		.sink0_endofpacket   (rsp_xbar_demux_src0_endofpacket)                                      //          .endofpacket
	);

	lab3_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux_001 (
		.clk                 (clk_0_clk_clk),                                                       //       clk.clk
		.reset               (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_xbar_mux_001_src_ready),                                          //       src.ready
		.src_valid           (rsp_xbar_mux_001_src_valid),                                          //          .valid
		.src_data            (rsp_xbar_mux_001_src_data),                                           //          .data
		.src_channel         (rsp_xbar_mux_001_src_channel),                                        //          .channel
		.src_startofpacket   (rsp_xbar_mux_001_src_startofpacket),                                  //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_001_src_endofpacket),                                    //          .endofpacket
		.sink0_ready         (rsp_xbar_demux_src1_ready),                                           //     sink0.ready
		.sink0_valid         (rsp_xbar_demux_src1_valid),                                           //          .valid
		.sink0_channel       (rsp_xbar_demux_src1_channel),                                         //          .channel
		.sink0_data          (rsp_xbar_demux_src1_data),                                            //          .data
		.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket),                                   //          .startofpacket
		.sink0_endofpacket   (rsp_xbar_demux_src1_endofpacket)                                      //          .endofpacket
	);

	lab3_mm_interconnect_0_rsp_xbar_mux rsp_xbar_mux_002 (
		.clk                 (clk_0_clk_clk),                                    //       clk.clk
		.reset               (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_xbar_mux_002_src_ready),                       //       src.ready
		.src_valid           (rsp_xbar_mux_002_src_valid),                       //          .valid
		.src_data            (rsp_xbar_mux_002_src_data),                        //          .data
		.src_channel         (rsp_xbar_mux_002_src_channel),                     //          .channel
		.src_startofpacket   (rsp_xbar_mux_002_src_startofpacket),               //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_002_src_endofpacket),                 //          .endofpacket
		.sink0_ready         (rsp_xbar_demux_src2_ready),                        //     sink0.ready
		.sink0_valid         (rsp_xbar_demux_src2_valid),                        //          .valid
		.sink0_channel       (rsp_xbar_demux_src2_channel),                      //          .channel
		.sink0_data          (rsp_xbar_demux_src2_data),                         //          .data
		.sink0_startofpacket (rsp_xbar_demux_src2_startofpacket),                //          .startofpacket
		.sink0_endofpacket   (rsp_xbar_demux_src2_endofpacket)                   //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (40),
		.IN_PKT_ADDR_L                 (9),
		.IN_PKT_DATA_H                 (7),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (8),
		.IN_PKT_BYTEEN_L               (8),
		.IN_PKT_BYTE_CNT_H             (53),
		.IN_PKT_BYTE_CNT_L             (47),
		.IN_PKT_TRANS_COMPRESSED_READ  (41),
		.IN_PKT_BURSTWRAP_H            (60),
		.IN_PKT_BURSTWRAP_L            (54),
		.IN_PKT_BURST_SIZE_H           (63),
		.IN_PKT_BURST_SIZE_L           (61),
		.IN_PKT_RESPONSE_STATUS_H      (92),
		.IN_PKT_RESPONSE_STATUS_L      (91),
		.IN_PKT_TRANS_EXCLUSIVE        (46),
		.IN_PKT_BURST_TYPE_H           (65),
		.IN_PKT_BURST_TYPE_L           (64),
		.IN_PKT_ORI_BURST_SIZE_L       (93),
		.IN_PKT_ORI_BURST_SIZE_H       (95),
		.IN_ST_DATA_W                  (96),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (80),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (90),
		.OUT_PKT_BURST_SIZE_L          (88),
		.OUT_PKT_RESPONSE_STATUS_H     (119),
		.OUT_PKT_RESPONSE_STATUS_L     (118),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (92),
		.OUT_PKT_BURST_TYPE_L          (91),
		.OUT_PKT_ORI_BURST_SIZE_L      (120),
		.OUT_PKT_ORI_BURST_SIZE_H      (122),
		.OUT_ST_DATA_W                 (123),
		.ST_CHANNEL_W                  (3),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1)
	) width_adapter (
		.clk                  (clk_0_clk_clk),                                    //       clk.clk
		.reset                (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (id_router_src_valid),                              //      sink.valid
		.in_channel           (id_router_src_channel),                            //          .channel
		.in_startofpacket     (id_router_src_startofpacket),                      //          .startofpacket
		.in_endofpacket       (id_router_src_endofpacket),                        //          .endofpacket
		.in_ready             (id_router_src_ready),                              //          .ready
		.in_data              (id_router_src_data),                               //          .data
		.out_endofpacket      (width_adapter_src_endofpacket),                    //       src.endofpacket
		.out_data             (width_adapter_src_data),                           //          .data
		.out_channel          (width_adapter_src_channel),                        //          .channel
		.out_valid            (width_adapter_src_valid),                          //          .valid
		.out_ready            (width_adapter_src_ready),                          //          .ready
		.out_startofpacket    (width_adapter_src_startofpacket),                  //          .startofpacket
		.in_command_size_data (3'b000)                                            // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (80),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_BURSTWRAP_H            (87),
		.IN_PKT_BURSTWRAP_L            (81),
		.IN_PKT_BURST_SIZE_H           (90),
		.IN_PKT_BURST_SIZE_L           (88),
		.IN_PKT_RESPONSE_STATUS_H      (119),
		.IN_PKT_RESPONSE_STATUS_L      (118),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (92),
		.IN_PKT_BURST_TYPE_L           (91),
		.IN_PKT_ORI_BURST_SIZE_L       (120),
		.IN_PKT_ORI_BURST_SIZE_H       (122),
		.IN_ST_DATA_W                  (123),
		.OUT_PKT_ADDR_H                (40),
		.OUT_PKT_ADDR_L                (9),
		.OUT_PKT_DATA_H                (7),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (8),
		.OUT_PKT_BYTEEN_L              (8),
		.OUT_PKT_BYTE_CNT_H            (53),
		.OUT_PKT_BYTE_CNT_L            (47),
		.OUT_PKT_TRANS_COMPRESSED_READ (41),
		.OUT_PKT_BURST_SIZE_H          (63),
		.OUT_PKT_BURST_SIZE_L          (61),
		.OUT_PKT_RESPONSE_STATUS_H     (92),
		.OUT_PKT_RESPONSE_STATUS_L     (91),
		.OUT_PKT_TRANS_EXCLUSIVE       (46),
		.OUT_PKT_BURST_TYPE_H          (65),
		.OUT_PKT_BURST_TYPE_L          (64),
		.OUT_PKT_ORI_BURST_SIZE_L      (93),
		.OUT_PKT_ORI_BURST_SIZE_H      (95),
		.OUT_ST_DATA_W                 (96),
		.ST_CHANNEL_W                  (3),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0)
	) width_adapter_001 (
		.clk                  (clk_0_clk_clk),                                    //       clk.clk
		.reset                (vga_led_0_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (cmd_xbar_mux_src_valid),                           //      sink.valid
		.in_channel           (cmd_xbar_mux_src_channel),                         //          .channel
		.in_startofpacket     (cmd_xbar_mux_src_startofpacket),                   //          .startofpacket
		.in_endofpacket       (cmd_xbar_mux_src_endofpacket),                     //          .endofpacket
		.in_ready             (cmd_xbar_mux_src_ready),                           //          .ready
		.in_data              (cmd_xbar_mux_src_data),                            //          .data
		.out_endofpacket      (width_adapter_001_src_endofpacket),                //       src.endofpacket
		.out_data             (width_adapter_001_src_data),                       //          .data
		.out_channel          (width_adapter_001_src_channel),                    //          .channel
		.out_valid            (width_adapter_001_src_valid),                      //          .valid
		.out_ready            (width_adapter_001_src_ready),                      //          .ready
		.out_startofpacket    (width_adapter_001_src_startofpacket),              //          .startofpacket
		.in_command_size_data (3'b000)                                            // (terminated)
	);

endmodule
