# TCL File Generated by Component Editor 13.1.1
# Thu May 01 20:09:09 EDT 2014
# DO NOT MODIFY


# 
# vga_led "VGA LED Emulator" v1.0
#  2014.05.01.20:09:09
# 
# 

# 
# request TCL package from ACDS 13.1
# 
package require -exact qsys 13.1


# 
# module vga_led
# 
set_module_property DESCRIPTION ""
set_module_property NAME vga_led
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "VGA LED Emulator"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL VGA_LED
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file decoder.sv SYSTEM_VERILOG PATH decoder.sv
add_fileset_file ellipse_draw.sv SYSTEM_VERILOG PATH ellipse_draw.sv
add_fileset_file inter_face.sv SYSTEM_VERILOG PATH inter_face.sv
add_fileset_file inter_face_top.sv SYSTEM_VERILOG PATH inter_face_top.sv
add_fileset_file mux140.sv SYSTEM_VERILOG PATH mux140.sv
add_fileset_file ram_control_new.v VERILOG PATH ram_control_new.v
add_fileset_file ram_win.v VERILOG PATH ram_win.v
add_fileset_file register_file.sv SYSTEM_VERILOG PATH register_file.sv
add_fileset_file regsiter.sv SYSTEM_VERILOG PATH regsiter.sv
add_fileset_file rom150back.v VERILOG PATH rom150back.v
add_fileset_file rom_bg.v VERILOG PATH rom_bg.v
add_fileset_file rom_front_gs.v VERILOG PATH rom_front_gs.v
add_fileset_file rom_xin.v VERILOG PATH rom_xin.v
add_fileset_file romheight.v VERILOG PATH romheight.v
add_fileset_file VGA_LED.sv SYSTEM_VERILOG PATH VGA_LED.sv TOP_LEVEL_FILE
add_fileset_file VGA_LED_Emulator.sv SYSTEM_VERILOG PATH VGA_LED_Emulator.sv


# 
# parameters
# 
add_parameter y_in_st INTEGER 100
set_parameter_property y_in_st DEFAULT_VALUE 100
set_parameter_property y_in_st DISPLAY_NAME y_in_st
set_parameter_property y_in_st TYPE INTEGER
set_parameter_property y_in_st UNITS None
set_parameter_property y_in_st HDL_PARAMETER true


# 
# display items
# 


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1


# 
# connection point avalon_slave_0
# 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock
set_interface_property avalon_slave_0 associatedReset reset_sink
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
set_interface_property avalon_slave_0 EXPORT_OF ""
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""

add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 chipselect chipselect Input 1
add_interface_port avalon_slave_0 address address Input 4
add_interface_port avalon_slave_0 writedata writedata Input 8
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0


# 
# connection point reset_sink
# 
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""

add_interface_port reset_sink reset reset Input 1


# 
# connection point conduit_end
# 
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock clock
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""

add_interface_port conduit_end VGA_R export Output 8
add_interface_port conduit_end VGA_G export Output 8
add_interface_port conduit_end VGA_B export Output 8
add_interface_port conduit_end VGA_CLK export Output 1
add_interface_port conduit_end VGA_HS export Output 1
add_interface_port conduit_end VGA_VS export Output 1
add_interface_port conduit_end VGA_BLANK_n export Output 1
add_interface_port conduit_end VGA_SYNC_n export Output 1

