module counter_en_gen(in_hex,in_reg,en1_out,en2_out);
   input [7:0]in_hex,in_reg;
   output reg en1_out,en2_out;

   always@*
     if(in_hex==0)
       begin
	  en1_out=0;
	  en2_out=1;
       end
     else if(in_reg==0)
       begin
	  en1_out=0;
	  en2_out=1;
       end
     else
       begin
	  en1_out=1;
	  en2_out=0;
       end
endmodule // counter_en_gen
