typedef logic [7:0] dataout[0:139];
module register_file(clk,rst,en,din0,din1,din2,din3,din4,din5,din6,dout);
   input clk,rst;
   input [139:0] en;
   input [7:0] 	 din0,din1,din2,din3,din4,din5,din6;
   output 	 dataout dout;
   
	genvar 	 n0;
   generate
      for (n0=0;n0<=139;n0=n0+7)begin:reg_file0
	 register register(clk,rst,en[n0],din0,dout[n0]);
      end
      endgenerate
   genvar 	 n1;
   
	generate
      for (n1=1;n1<=139;n1=n1+7)begin:reg_file1
	 register register(clk,rst,en[n1],din1,dout[n1]);
      end
      endgenerate
   
	genvar 	 n2;
   generate
      for (n2=2;n2<=139;n2=n2+7)begin:reg_file2
	 register register(clk,rst,en[n2],din2,dout[n2]);
      end
      endgenerate
  
   genvar 	 n3;
   generate
      for (n3=3;n3<=139;n3=n3+7)begin:reg_file3
	 register register(clk,rst,en[n3],din3,dout[n3]);
      end
      endgenerate
  
   genvar 	 n4;
   generate
      for (n4=4;n4<=139;n4=n4+7)begin:reg_file4
	 register register(clk,rst,en[n4],din4,dout[n4]);
      end
      endgenerate
   
	genvar 	 n5;
   generate
      for (n5=5;n5<=139;n5=n5+7)begin:reg_file5
	 register register(clk,rst,en[n5],din5,dout[n5]);
      end
      endgenerate
   
	genvar 	 n6;
   generate
      for (n6=6;n6<=139;n6=n6+7)begin:reg_file6
	 register register(clk,rst,en[n6],din6,dout[n6]);
      end
      endgenerate
endmodule // register_file
