module delay_mouse_count(clk,rst,en1,en2,ctrl_out_en,ctrl_out_set0);
   input clk,rst,en1,en2;//en1 is true data in reg>0,en2 is true when hex now is 0(that's to say, displacement now went back to 0)
   output reg ctrl_out_en,ctrl_out_set0;
   reg [31:0] counter;
   always@(posedge clk)
     if(rst)
       begin
	  counter<=0;
	  ctrl_out_en<=1;
	  ctrl_out_set0<=0;
       end
     else if(counter==32'd19000000)
       begin
	  counter<=0;
	  ctrl_out_en<=1;
	  ctrl_out_set0<=0;
       end
     else if(en1 && !en2)
       begin
	  counter<=counter+1;
	  ctrl_out_en<=0;
	  ctrl_out_set0<=1;
       end
     else if(en2 && !en1)
       begin
	  counter<=0;
	  ctrl_out_en<=1;
	  ctrl_out_set0<=0;
       end // else: !if(en && counter<=32'd19000000)
     else
       begin
	  counter<=counter;
	  ctrl_out_en<=0;
	  ctrl_out_set0<=1;
       end // else: !if(en2)
endmodule // delay_mouse_count

	  