typedef logic [7:0] dataout[0:139];
module inter_face(clk,rst,ctrl_in,din0,din1,din2,din3,din4,din5,din6,dout);
   input 				clk,rst;
   input 	[4:0] 	ctrl_in;
   input 	[7:0] 	din0,din1,din2,din3,din4,din5,din6;
   output      		dataout dout;
   wire 		[139:0] 	ctrl_out;
   
	decoder decoder(clk,rst,ctrl_in,ctrl_out);
   
	register_file register_file(clk,rst,ctrl_out,din0,din1,din2,din3,din4,din5,din6,dout);

endmodule // inter_face
