lab3 |

2014.05.02.09:57:57 | Datasheet

Overview

clk_0 | lab3

All Components
vga_led_0 vga_led 1.0
Memory Map

| hps_0 | hps_0_arm_a9_0 | hps_0_arm_a9_1 | master_0
h2f_axi_master | h2f_lw_axi_master | altera_axi_master | altera_axi_master | master
hps_0 |  |  |  |  |
f2h_axi_slave |  |  |  |  |
hps_0_arm_gic_0 |  |  |  |  |
axi_slave0 |  |  | 0xfffed000 | 0xfffed000 |
axi_slave1 |  |  | 0xfffec100 | 0xfffec100 |
hps_0_L2 |  |  |  |  |
axi_slave0 |  |  | 0xfffef000 | 0xfffef000 |
hps_0_dma |  |  |  |  |
axi_slave0 |  |  | 0xffe01000 | 0xffe01000 |
hps_0_sysmgr |  |  |  |  |
axi_slave0 |  |  | 0xffd08000 | 0xffd08000 |
hps_0_clkmgr |  |  |  |  |
axi_slave0 |  |  | 0xffd04000 | 0xffd04000 |
hps_0_rstmgr |  |  |  |  |
axi_slave0 |  |  | 0xffd05000 | 0xffd05000 |
hps_0_fpgamgr |  |  |  |  |
axi_slave0 |  |  | 0xff706000 | 0xff706000 |
axi_slave1 |  |  | 0xffb90000 | 0xffb90000 |
hps_0_uart0 |  |  |  |  |
axi_slave0 |  |  | 0xffc02000 | 0xffc02000 |
hps_0_uart1 |  |  |  |  |
axi_slave0 |  |  | 0xffc03000 | 0xffc03000 |
hps_0_timer0 |  |  |  |  |
axi_slave0 |  |  | 0xffc08000 | 0xffc08000 |
hps_0_timer1 |  |  |  |  |
axi_slave0 |  |  | 0xffc09000 | 0xffc09000 |
hps_0_timer2 |  |  |  |  |
axi_slave0 |  |  | 0xffd00000 | 0xffd00000 |
hps_0_timer3 |  |  |  |  |
axi_slave0 |  |  | 0xffd01000 | 0xffd01000 |
hps_0_gpio0 |  |  |  |  |
axi_slave0 |  |  | 0xff708000 | 0xff708000 |
hps_0_gpio1 |  |  |  |  |
axi_slave0 |  |  | 0xff709000 | 0xff709000 |
hps_0_gpio2 |  |  |  |  |
axi_slave0 |  |  | 0xff70a000 | 0xff70a000 |
hps_0_i2c0 |  |  |  |  |
axi_slave0 |  |  | 0xffc04000 | 0xffc04000 |
hps_0_i2c1 |  |  |  |  |
axi_slave0 |  |  | 0xffc05000 | 0xffc05000 |
hps_0_i2c2 |  |  |  |  |
axi_slave0 |  |  | 0xffc06000 | 0xffc06000 |
hps_0_i2c3 |  |  |  |  |
axi_slave0 |  |  | 0xffc07000 | 0xffc07000 |
hps_0_nand0 |  |  |  |  |
axi_slave0 |  |  | 0xff900000 | 0xff900000 |
axi_slave1 |  |  | 0xffb80000 | 0xffb80000 |
hps_0_spi0 |  |  |  |  |
axi_slave0 |  |  | 0xffe02000 | 0xffe02000 |
hps_0_spi1 |  |  |  |  |
axi_slave0 |  |  | 0xffe03000 | 0xffe03000 |
hps_0_qspi |  |  |  |  |
axi_slave0 |  |  | 0xff705000 | 0xff705000 |
axi_slave1 |  |  | 0xffa00000 | 0xffa00000 |
hps_0_sdmmc |  |  |  |  |
axi_slave0 |  |  | 0xff704000 | 0xff704000 |
hps_0_usb0 |  |  |  |  |
axi_slave0 |  |  | 0xffb00000 | 0xffb00000 |
hps_0_usb1 |  |  |  |  |
axi_slave0 |  |  | 0xffb40000 | 0xffb40000 |
hps_0_gmac0 |  |  |  |  |
axi_slave0 |  |  | 0xff700000 | 0xff700000 |
hps_0_gmac1 |  |  |  |  |
axi_slave0 |  |  | 0xff702000 | 0xff702000 |
hps_0_axi_ocram |  |  |  |  |
axi_slave0 |  |  | 0xffff0000 | 0xffff0000 |
hps_0_timer |  |  |  |  |
axi_slave0 |  |  | 0xfffec600 | 0xfffec600 |
vga_led_0 |  |  |  |  |
avalon_slave_0 |  | 0x00000000 | 0xff200000 | 0xff200000 | 0x00000000

## clk_0

clock_source v13.1

## Parameters
clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0

altera_hps v13.1.1

## Parameters
AC_ROM_MR0 | 0010001110001
AC_ROM_MR0_MIRR | 0010001101001
AC_ROM_MR0_CALIB |
AC_ROM_MR0_DLL_RESET | 0010101110000
AC_ROM_MR0_DLL_RESET_MIRR | 0010011101000
AC_ROM_MR1 | 0000000000110
AC_ROM_MR1_MIRR | 0000000000110
AC_ROM_MR1_CALIB |
AC_ROM_MR1_OCD_ENABLE |
AC_ROM_MR2 | 0001000011000
AC_ROM_MR2_MIRR | 0001000011000
AC_ROM_MR3 | 0000000000000
AC_ROM_MR3_MIRR | 0000000000000
USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY | true
MR0_BL | 1
MR0_BT | 0
MR0_CAS_LATENCY | 7
MR0_DLL | 1
MR0_WR | 2
MR0_PD | 0
MR1_DLL | 0
MR1_ODS | 1
MR1_RTT | 1
MR1_AL | 0
MR1_WL | 0
MR1_TDQS | 0
MR1_QOFF | 0
MR1_DQS | 0
MR1_RDQS | 0
MR2_CWL | 3
MR2_ASR | 0
MR2_SRT | 0
MR2_SRF | 0
MR2_RTT_WR | 1
MR3_MPR_RF | 0
MR3_MPR | 0
MR3_MPR_AA | 0
MR1_BL | 2
MR1_BT | 0
MR1_WC | 0
MR1_WR | 1
MR2_RLWL | 1
MR3_DS | 2
MR1_DS | 0
MR1_PASR | 0
MEM_IF_READ_DQS_WIDTH | 4
MEM_IF_WRITE_DQS_WIDTH | 4
SCC_DATA_WIDTH | 1
MEM_IF_ADDR_WIDTH | 15
MEM_IF_ADDR_WIDTH_MIN | 13
MEM_IF_ROW_ADDR_WIDTH | 15
MEM_IF_COL_ADDR_WIDTH | 10
MEM_IF_DM_WIDTH | 4
MEM_IF_CS_PER_RANK | 1
MEM_IF_NUMBER_OF_RANKS | 1
MEM_IF_CS_PER_DIMM | 1
MEM_IF_CONTROL_WIDTH | 1
MEM_BURST_LENGTH | 8
MEM_LEVELING | false
MEM_IF_DQS_WIDTH | 4
MEM_IF_CS_WIDTH | 1
MEM_IF_CHIP_BITS | 1
MEM_IF_BANKADDR_WIDTH | 3
MEM_IF_DQ_WIDTH | 32
MEM_IF_CK_WIDTH | 1
MEM_IF_CLK_EN_WIDTH | 1
MEM_IF_CLK_PAIR_COUNT | 1
DEVICE_WIDTH | 1
MEM_CLK_MAX_NS | 1.25
MEM_CLK_MAX_PS | 1250.0
MEM_TRC | 20
MEM_TRAS | 14
MEM_TRCD | 6
MEM_TRP | 6
MEM_TREFI | 3120
MEM_TRFC | 104
CFG_TCCD | 1
MEM_TWR | 6
MEM_TFAW | 12
MEM_TRRD | 3
MEM_TRTP | 3
MEM_DQS_TO_CLK_CAPTURE_DELAY | 450
MEM_CLK_TO_DQS_CAPTURE_DELAY | 100000
MEM_IF_ODT_WIDTH | 1
MEM_WTCL_INT | 8
FLY_BY | true
RDIMM | false
LRDIMM | false
RDIMM_INT | 0
LRDIMM_INT | 0
MEM_IF_RD_TO_WR_TURNAROUND_OCT | 2
MEM_IF_WR_TO_RD_TURNAROUND_OCT | 3
CTL_RD_TO_PCH_EXTRA_CLK | 0
CTL_RD_TO_RD_EXTRA_CLK | 0
CTL_WR_TO_WR_EXTRA_CLK | 0
CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK | 1
CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK | 2
MEM_TYPE | DDR3
MEM_MIRROR_ADDRESSING_DEC | 0
MEM_ATCL_INT | 0
MEM_REGDIMM_ENABLED | false
MEM_LRDIMM_ENABLED | false
MEM_VENDOR | Micron
MEM_FORMAT | DISCRETE
AC_PARITY | false
RDIMM_CONFIG | 0000000000000000
LRDIMM_EXTENDED_CONFIG | 0x000000000000000000
DISCRETE_FLY_BY | true
DEVICE_DEPTH | 1
MEM_MIRROR_ADDRESSING | 0
MEM_CLK_FREQ_MAX | 800.0
MEM_ROW_ADDR_WIDTH | 15
MEM_COL_ADDR_WIDTH | 10
MEM_DQ_WIDTH | 32
MEM_DQ_PER_DQS | 8
MEM_BANKADDR_WIDTH | 3
MEM_IF_DM_PINS_EN | true
MEM_IF_DQSN_EN | true
MEM_NUMBER_OF_DIMMS | 1
MEM_NUMBER_OF_RANKS_PER_DIMM | 1
MEM_NUMBER_OF_RANKS_PER_DEVICE | 1
MEM_RANK_MULTIPLICATION_FACTOR | 1
MEM_CK_WIDTH | 1
MEM_CS_WIDTH | 1
MEM_CLK_EN_WIDTH | 1
ALTMEMPHY_COMPATIBLE_MODE | false
NEXTGEN | true
MEM_IF_BOARD_BASE_DELAY | 10
MEM_IF_SIM_VALID_WINDOW | 0
MEM_GUARANTEED_WRITE_INIT | false
MEM_VERBOSE | true
PINGPONGPHY_EN | false
REFRESH_BURST_VALIDATION | false
MEM_BL | OTF
MEM_BT | Sequential
MEM_ASR | Manual
MEM_SRT | Normal
MEM_PD | DLL off
MEM_DRV_STR | RZQ/7
MEM_DLL_EN | true
MEM_RTT_NOM | RZQ/4
MEM_RTT_WR | RZQ/4
MEM_WTCL | 8
MEM_ATCL | Disabled
MEM_TCL | 11
MEM_AUTO_LEVELING_MODE | true
MEM_USER_LEVELING_MODE | Leveling
MEM_INIT_EN | false
MEM_INIT_FILE |
DAT_DATA_WIDTH | 32
TIMING_TIS | 180
TIMING_TIH | 140
TIMING_TDS | 30
TIMING_TDH | 65
TIMING_TDQSQ | 125
TIMING_TQHS | 300
TIMING_TQH | 0.38
TIMING_TDQSCK | 255
TIMING_TDQSCKDS | 450
TIMING_TDQSCKDM | 900
TIMING_TDQSCKDL | 1200
TIMING_TDQSS | 0.25
TIMING_TDQSH | 0.35
TIMING_TQSH | 0.4
TIMING_TDSH | 0.2
TIMING_TDSS | 0.2
MEM_TINIT_US | 500
MEM_TINIT_CK | 200000
MEM_TDQSCK | 1
MEM_TMRD_CK | 4
MEM_TRAS_NS | 35.0
MEM_TRCD_NS | 13.75
MEM_TRP_NS | 13.75
MEM_TREFI_US | 7.8
MEM_TRFC_NS | 260.0
CFG_TCCD_NS | 2.5
MEM_TWR_NS | 15.0
MEM_TWTR | 4
MEM_TFAW_NS | 30.0
MEM_TRRD_NS | 7.5
MEM_TRTP_NS | 7.5
EXPORT_CSR_PORT | false
CSR_ADDR_WIDTH | 10
CSR_DATA_WIDTH | 8
CSR_BE_WIDTH | 1
CTL_CS_WIDTH | 1
AVL_ADDR_WIDTH | 27
AVL_BE_WIDTH | 8
AVL_DATA_WIDTH | 64
AVL_SYMBOL_WIDTH | 8
AVL_NUM_SYMBOLS | 8
AVL_SIZE_WIDTH | 3
HR_DDIO_OUT_HAS_THREE_REGS | false
CTL_ECC_CSR_ENABLED | false
DWIDTH_RATIO | 2
CTL_ODT_ENABLED | true
CTL_OUTPUT_REGD | false
CTL_ECC_MULTIPLES_40_72 | 1
CTL_ECC_MULTIPLES_16_24_40_72 | 1
CTL_REGDIMM_ENABLED | false
LOW_LATENCY | false
CONTROLLER_TYPE | nextgen_v110
CTL_TBP_NUM | 4
CTL_USR_REFRESH | 0
CTL_SELF_REFRESH | 0
CFG_TYPE | 2
CFG_INTERFACE_WIDTH | 32
CFG_BURST_LENGTH | 8
CFG_ADDR_ORDER | 0
CFG_PDN_EXIT_CYCLES | 10
CFG_POWER_SAVING_EXIT_CYCLES | 5
CFG_MEM_CLK_ENTRY_CYCLES | 10
CFG_SELF_RFSH_EXIT_CYCLES | 512
CFG_PORT_WIDTH_WRITE_ODT_CHIP | 1
CFG_PORT_WIDTH_READ_ODT_CHIP | 1
CFG_WRITE_ODT_CHIP | 1
CFG_READ_ODT_CHIP | 0
LOCAL_CS_WIDTH | 0
CFG_CLR_INTR | 0
CFG_ENABLE_NO_DM | 0
MEM_ADD_LAT | 0
CTL_ENABLE_BURST_INTERRUPT_INT | false
CTL_ENABLE_BURST_TERMINATE_INT | false
CFG_ERRCMD_FIFO_REG | 0
CFG_ECC_DECODER_REG | 0
CTL_ENABLE_WDATA_PATH_LATENCY | false
CFG_STARVE_LIMIT | 10
MEM_AUTO_PD_CYCLES | 0
AVL_PORT | Port 0
AVL_DATA_WIDTH_PORT_0 | 1
AVL_ADDR_WIDTH_PORT_0 | 1
PRIORITY_PORT_0 | 1
WEIGHT_PORT_0 | 0
CPORT_TYPE_PORT_0 | 0
AVL_NUM_SYMBOLS_PORT_0 | 1
LSB_WFIFO_PORT_0 | 5
MSB_WFIFO_PORT_0 | 5
LSB_RFIFO_PORT_0 | 5
MSB_RFIFO_PORT_0 | 5
AVL_DATA_WIDTH_PORT_1 | 1
AVL_ADDR_WIDTH_PORT_1 | 1
PRIORITY_PORT_1 | 1
WEIGHT_PORT_1 | 0
CPORT_TYPE_PORT_1 | 0
AVL_NUM_SYMBOLS_PORT_1 | 1
LSB_WFIFO_PORT_1 | 5
MSB_WFIFO_PORT_1 | 5
LSB_RFIFO_PORT_1 | 5
MSB_RFIFO_PORT_1 | 5
AVL_DATA_WIDTH_PORT_2 | 1
AVL_ADDR_WIDTH_PORT_2 | 1
PRIORITY_PORT_2 | 1
WEIGHT_PORT_2 | 0
CPORT_TYPE_PORT_2 | 0
AVL_NUM_SYMBOLS_PORT_2 | 1
LSB_WFIFO_PORT_2 | 5
MSB_WFIFO_PORT_2 | 5
LSB_RFIFO_PORT_2 | 5
MSB_RFIFO_PORT_2 | 5
AVL_DATA_WIDTH_PORT_3 | 1
AVL_ADDR_WIDTH_PORT_3 | 1
PRIORITY_PORT_3 | 1
WEIGHT_PORT_3 | 0
CPORT_TYPE_PORT_3 | 0
AVL_NUM_SYMBOLS_PORT_3 | 1
LSB_WFIFO_PORT_3 | 5
MSB_WFIFO_PORT_3 | 5
LSB_RFIFO_PORT_3 | 5
MSB_RFIFO_PORT_3 | 5
AVL_DATA_WIDTH_PORT_4 | 1
AVL_ADDR_WIDTH_PORT_4 | 1
PRIORITY_PORT_4 | 1
WEIGHT_PORT_4 | 0
CPORT_TYPE_PORT_4 | 0
AVL_NUM_SYMBOLS_PORT_4 | 1
LSB_WFIFO_PORT_4 | 5
MSB_WFIFO_PORT_4 | 5
LSB_RFIFO_PORT_4 | 5
MSB_RFIFO_PORT_4 | 5
AVL_DATA_WIDTH_PORT_5 | 1
AVL_ADDR_WIDTH_PORT_5 | 1
PRIORITY_PORT_5 | 1
WEIGHT_PORT_5 | 0
CPORT_TYPE_PORT_5 | 0
AVL_NUM_SYMBOLS_PORT_5 | 1
LSB_WFIFO_PORT_5 | 5
MSB_WFIFO_PORT_5 | 5
LSB_RFIFO_PORT_5 | 5
MSB_RFIFO_PORT_5 | 5
ALLOCATED_RFIFO_PORT | None,None,None,None,None,None
ALLOCATED_WFIFO_PORT | None,None,None,None,None,None
ENUM_ATTR_COUNTER_ONE_RESET | DISABLED
ENUM_ATTR_COUNTER_ZERO_RESET | DISABLED
ENUM_ATTR_STATIC_CONFIG_VALID | DISABLED
ENUM_AUTO_PCH_ENABLE_0 | DISABLED
ENUM_AUTO_PCH_ENABLE_1 | DISABLED
ENUM_AUTO_PCH_ENABLE_2 | DISABLED
ENUM_AUTO_PCH_ENABLE_3 | DISABLED
ENUM_AUTO_PCH_ENABLE_4 | DISABLED
ENUM_AUTO_PCH_ENABLE_5 | DISABLED
ENUM_CAL_REQ | DISABLED
ENUM_CFG_BURST_LENGTH | BL_8
ENUM_CFG_INTERFACE_WIDTH | DWIDTH_32
ENUM_CFG_SELF_RFSH_EXIT_CYCLES | SELF_RFSH_EXIT_CYCLES_512
ENUM_CFG_STARVE_LIMIT | STARVE_LIMIT_10
ENUM_CFG_TYPE | DDR3
ENUM_CLOCK_OFF_0 | DISABLED
ENUM_CLOCK_OFF_1 | DISABLED
ENUM_CLOCK_OFF_2 | DISABLED
ENUM_CLOCK_OFF_3 | DISABLED
ENUM_CLOCK_OFF_4 | DISABLED
ENUM_CLOCK_OFF_5 | DISABLED
ENUM_CLR_INTR | NO_CLR_INTR
ENUM_CMD_PORT_IN_USE_0 | FALSE
ENUM_CMD_PORT_IN_USE_1 | FALSE
ENUM_CMD_PORT_IN_USE_2 | FALSE
ENUM_CMD_PORT_IN_USE_3 | FALSE
ENUM_CMD_PORT_IN_USE_4 | FALSE
ENUM_CMD_PORT_IN_USE_5 | FALSE
ENUM_CPORT0_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT0_RFIFO_MAP | FIFO_0
ENUM_CPORT0_TYPE | DISABLE
ENUM_CPORT0_WFIFO_MAP | FIFO_0
ENUM_CPORT1_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT1_RFIFO_MAP | FIFO_0
ENUM_CPORT1_TYPE | DISABLE
ENUM_CPORT1_WFIFO_MAP | FIFO_0
ENUM_CPORT2_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT2_RFIFO_MAP | FIFO_0
ENUM_CPORT2_TYPE | DISABLE
ENUM_CPORT2_WFIFO_MAP | FIFO_0
ENUM_CPORT3_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT3_RFIFO_MAP | FIFO_0
ENUM_CPORT3_TYPE | DISABLE
ENUM_CPORT3_WFIFO_MAP | FIFO_0
ENUM_CPORT4_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT4_RFIFO_MAP | FIFO_0
ENUM_CPORT4_TYPE | DISABLE
ENUM_CPORT4_WFIFO_MAP | FIFO_0
ENUM_CPORT5_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT5_RFIFO_MAP | FIFO_0
ENUM_CPORT5_TYPE | DISABLE
ENUM_CPORT5_WFIFO_MAP | FIFO_0
ENUM_CTL_ADDR_ORDER | CHIP_ROW_BANK_COL
ENUM_CTL_ECC_ENABLED | CTL_ECC_DISABLED
ENUM_CTL_ECC_RMW_ENABLED | CTL_ECC_RMW_DISABLED
ENUM_CTL_REGDIMM_ENABLED | REGDIMM_DISABLED
ENUM_CTL_USR_REFRESH | CTL_USR_REFRESH_DISABLED
ENUM_CTRL_WIDTH | DATA_WIDTH_64_BIT
ENUM_DELAY_BONDING | BONDING_LATENCY_0
ENUM_DFX_BYPASS_ENABLE | DFX_BYPASS_DISABLED
ENUM_DISABLE_MERGING | MERGING_ENABLED
ENUM_ECC_DQ_WIDTH | ECC_DQ_WIDTH_0
ENUM_ENABLE_ATPG | DISABLED
ENUM_ENABLE_BONDING_0 | DISABLED
ENUM_ENABLE_BONDING_1 | DISABLED
ENUM_ENABLE_BONDING_2 | DISABLED
ENUM_ENABLE_BONDING_3 | DISABLED
ENUM_ENABLE_BONDING_4 | DISABLED
ENUM_ENABLE_BONDING_5 | DISABLED
ENUM_ENABLE_BONDING_WRAPBACK | DISABLED
ENUM_ENABLE_DQS_TRACKING | ENABLED
ENUM_ENABLE_ECC_CODE_OVERWRITES | DISABLED
ENUM_ENABLE_FAST_EXIT_PPD | DISABLED
ENUM_ENABLE_INTR | DISABLED
ENUM_ENABLE_NO_DM | DISABLED
ENUM_ENABLE_PIPELINEGLOBAL | DISABLED
ENUM_GANGED_ARF | DISABLED
ENUM_GEN_DBE | GEN_DBE_DISABLED
ENUM_GEN_SBE | GEN_SBE_DISABLED
ENUM_INC_SYNC | FIFO_SET_2
ENUM_LOCAL_IF_CS_WIDTH | ADDR_WIDTH_0
ENUM_MASK_CORR_DROPPED_INTR | DISABLED
ENUM_MASK_DBE_INTR | DISABLED
ENUM_MASK_SBE_INTR | DISABLED
ENUM_MEM_IF_AL | AL_0
ENUM_MEM_IF_BANKADDR_WIDTH | ADDR_WIDTH_3
ENUM_MEM_IF_BURSTLENGTH | MEM_IF_BURSTLENGTH_8
ENUM_MEM_IF_COLADDR_WIDTH | ADDR_WIDTH_10
ENUM_MEM_IF_CS_PER_RANK | MEM_IF_CS_PER_RANK_1
ENUM_MEM_IF_CS_WIDTH | MEM_IF_CS_WIDTH_1
ENUM_MEM_IF_DQ_PER_CHIP | MEM_IF_DQ_PER_CHIP_8
ENUM_MEM_IF_DQS_WIDTH | DQS_WIDTH_4
ENUM_MEM_IF_DWIDTH | MEM_IF_DWIDTH_32
ENUM_MEM_IF_MEMTYPE | DDR3_SDRAM
ENUM_MEM_IF_ROWADDR_WIDTH | ADDR_WIDTH_15
ENUM_MEM_IF_SPEEDBIN | DDR3_1600_8_8_8
ENUM_MEM_IF_TCCD | TCCD_4
ENUM_MEM_IF_TCL | TCL_11
ENUM_MEM_IF_TCWL | TCWL_8
ENUM_MEM_IF_TFAW | TFAW_12
ENUM_MEM_IF_TMRD | TMRD_4
ENUM_MEM_IF_TRAS | TRAS_14
ENUM_MEM_IF_TRC | TRC_20
ENUM_MEM_IF_TRCD | TRCD_6
ENUM_MEM_IF_TRP | TRP_6
ENUM_MEM_IF_TRRD | TRRD_3
ENUM_MEM_IF_TRTP | TRTP_3
ENUM_MEM_IF_TWR | TWR_6
ENUM_MEM_IF_TWTR | TWTR_4
ENUM_MMR_CFG_MEM_BL | MP_BL_8
ENUM_OUTPUT_REGD | DISABLED
ENUM_PDN_EXIT_CYCLES | SLOW_EXIT
ENUM_PORT0_WIDTH | PORT_32_BIT
ENUM_PORT1_WIDTH | PORT_32_BIT
ENUM_PORT2_WIDTH | PORT_32_BIT
ENUM_PORT3_WIDTH | PORT_32_BIT
ENUM_PORT4_WIDTH | PORT_32_BIT
ENUM_PORT5_WIDTH | PORT_32_BIT
ENUM_PRIORITY_0_0 | WEIGHT_0
ENUM_PRIORITY_0_1 | WEIGHT_0
ENUM_PRIORITY_0_2 | WEIGHT_0
ENUM_PRIORITY_0_3 | WEIGHT_0
ENUM_PRIORITY_0_4 | WEIGHT_0
ENUM_PRIORITY_0_5 | WEIGHT_0
ENUM_PRIORITY_1_0 | WEIGHT_0
ENUM_PRIORITY_1_1 | WEIGHT_0
ENUM_PRIORITY_1_2 | WEIGHT_0
ENUM_PRIORITY_1_3 | WEIGHT_0
ENUM_PRIORITY_1_4 | WEIGHT_0
ENUM_PRIORITY_1_5 | WEIGHT_0
ENUM_PRIORITY_2_0 | WEIGHT_0
ENUM_PRIORITY_2_1 | WEIGHT_0
ENUM_PRIORITY_2_2 | WEIGHT_0
ENUM_PRIORITY_2_3 | WEIGHT_0
ENUM_PRIORITY_2_4 | WEIGHT_0
ENUM_PRIORITY_2_5 | WEIGHT_0
ENUM_PRIORITY_3_0 | WEIGHT_0
ENUM_PRIORITY_3_1 | WEIGHT_0
ENUM_PRIORITY_3_2 | WEIGHT_0
ENUM_PRIORITY_3_3 | WEIGHT_0
ENUM_PRIORITY_3_4 | WEIGHT_0
ENUM_PRIORITY_3_5 | WEIGHT_0
ENUM_PRIORITY_4_0 | WEIGHT_0
ENUM_PRIORITY_4_1 | WEIGHT_0
ENUM_PRIORITY_4_2 | WEIGHT_0
ENUM_PRIORITY_4_3 | WEIGHT_0
ENUM_PRIORITY_4_4 | WEIGHT_0
ENUM_PRIORITY_4_5 | WEIGHT_0
ENUM_PRIORITY_5_0 | WEIGHT_0
ENUM_PRIORITY_5_1 | WEIGHT_0
ENUM_PRIORITY_5_2 | WEIGHT_0
ENUM_PRIORITY_5_3 | WEIGHT_0
ENUM_PRIORITY_5_4 | WEIGHT_0
ENUM_PRIORITY_5_5 | WEIGHT_0
ENUM_PRIORITY_6_0 | WEIGHT_0
ENUM_PRIORITY_6_1 | WEIGHT_0
ENUM_PRIORITY_6_2 | WEIGHT_0
ENUM_PRIORITY_6_3 | WEIGHT_0
ENUM_PRIORITY_6_4 | WEIGHT_0
ENUM_PRIORITY_6_5 | WEIGHT_0
ENUM_PRIORITY_7_0 | WEIGHT_0
ENUM_PRIORITY_7_1 | WEIGHT_0
ENUM_PRIORITY_7_2 | WEIGHT_0
ENUM_PRIORITY_7_3 | WEIGHT_0
ENUM_PRIORITY_7_4 | WEIGHT_0
ENUM_PRIORITY_7_5 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_0 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_1 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_2 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_3 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_4 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_5 | WEIGHT_0
ENUM_RCFG_USER_PRIORITY_0 | PRIORITY_1
ENUM_RCFG_USER_PRIORITY_1 | PRIORITY_1
ENUM_RCFG_USER_PRIORITY_2 | PRIORITY_1
ENUM_RCFG_USER_PRIORITY_3 | PRIORITY_1
ENUM_RCFG_USER_PRIORITY_4 | PRIORITY_1
ENUM_RCFG_USER_PRIORITY_5 | PRIORITY_1
ENUM_RD_DWIDTH_0 | DWIDTH_0
ENUM_RD_DWIDTH_1 | DWIDTH_0
ENUM_RD_DWIDTH_2 | DWIDTH_0
ENUM_RD_DWIDTH_3 | DWIDTH_0
ENUM_RD_DWIDTH_4 | DWIDTH_0
ENUM_RD_DWIDTH_5 | DWIDTH_0
ENUM_RD_FIFO_IN_USE_0 | FALSE
ENUM_RD_FIFO_IN_USE_1 | FALSE
ENUM_RD_FIFO_IN_USE_2 | FALSE
ENUM_RD_FIFO_IN_USE_3 | FALSE
ENUM_RD_PORT_INFO_0 | USE_NO
ENUM_RD_PORT_INFO_1 | USE_NO
ENUM_RD_PORT_INFO_2 | USE_NO
ENUM_RD_PORT_INFO_3 | USE_NO
ENUM_RD_PORT_INFO_4 | USE_NO
ENUM_RD_PORT_INFO_5 | USE_NO
ENUM_READ_ODT_CHIP | ODT_DISABLED
ENUM_REORDER_DATA | DATA_REORDERING
ENUM_RFIFO0_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO1_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO2_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO3_CPORT_MAP | CMD_PORT_0
ENUM_SINGLE_READY_0 | CONCATENATE_RDY
ENUM_SINGLE_READY_1 | CONCATENATE_RDY
ENUM_SINGLE_READY_2 | CONCATENATE_RDY
ENUM_SINGLE_READY_3 | CONCATENATE_RDY
ENUM_STATIC_WEIGHT_0 | WEIGHT_0
ENUM_STATIC_WEIGHT_1 | WEIGHT_0
ENUM_STATIC_WEIGHT_2 | WEIGHT_0
ENUM_STATIC_WEIGHT_3 | WEIGHT_0
ENUM_STATIC_WEIGHT_4 | WEIGHT_0
ENUM_STATIC_WEIGHT_5 | WEIGHT_0
ENUM_SYNC_MODE_0 | ASYNCHRONOUS
ENUM_SYNC_MODE_1 | ASYNCHRONOUS
ENUM_SYNC_MODE_2 | ASYNCHRONOUS
ENUM_SYNC_MODE_3 | ASYNCHRONOUS
ENUM_SYNC_MODE_4 | ASYNCHRONOUS
ENUM_SYNC_MODE_5 | ASYNCHRONOUS
ENUM_TEST_MODE | NORMAL_MODE
ENUM_THLD_JAR1_0 | THRESHOLD_32
ENUM_THLD_JAR1_1 | THRESHOLD_32
ENUM_THLD_JAR1_2 | THRESHOLD_32
ENUM_THLD_JAR1_3 | THRESHOLD_32
ENUM_THLD_JAR1_4 | THRESHOLD_32
ENUM_THLD_JAR1_5 | THRESHOLD_32
ENUM_THLD_JAR2_0 | THRESHOLD_16
ENUM_THLD_JAR2_1 | THRESHOLD_16
ENUM_THLD_JAR2_2 | THRESHOLD_16
ENUM_THLD_JAR2_3 | THRESHOLD_16
ENUM_THLD_JAR2_4 | THRESHOLD_16
ENUM_THLD_JAR2_5 | THRESHOLD_16
ENUM_USE_ALMOST_EMPTY_0 | EMPTY
ENUM_USE_ALMOST_EMPTY_1 | EMPTY
ENUM_USE_ALMOST_EMPTY_2 | EMPTY
ENUM_USE_ALMOST_EMPTY_3 | EMPTY
ENUM_USER_ECC_EN | DISABLE
ENUM_USER_PRIORITY_0 | PRIORITY_1
ENUM_USER_PRIORITY_1 | PRIORITY_1
ENUM_USER_PRIORITY_2 | PRIORITY_1
ENUM_USER_PRIORITY_3 | PRIORITY_1
ENUM_USER_PRIORITY_4 | PRIORITY_1
ENUM_USER_PRIORITY_5 | PRIORITY_1
ENUM_WFIFO0_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO0_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO1_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO1_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO2_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO2_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO3_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO3_RDY_ALMOST_FULL | NOT_FULL
ENUM_WR_DWIDTH_0 | DWIDTH_0
ENUM_WR_DWIDTH_1 | DWIDTH_0
ENUM_WR_DWIDTH_2 | DWIDTH_0
ENUM_WR_DWIDTH_3 | DWIDTH_0
ENUM_WR_DWIDTH_4 | DWIDTH_0
ENUM_WR_DWIDTH_5 | DWIDTH_0
ENUM_WR_FIFO_IN_USE_0 | FALSE
ENUM_WR_FIFO_IN_USE_1 | FALSE
ENUM_WR_FIFO_IN_USE_2 | FALSE
ENUM_WR_FIFO_IN_USE_3 | FALSE
ENUM_WR_PORT_INFO_0 | USE_NO
ENUM_WR_PORT_INFO_1 | USE_NO
ENUM_WR_PORT_INFO_2 | USE_NO
ENUM_WR_PORT_INFO_3 | USE_NO
ENUM_WR_PORT_INFO_4 | USE_NO
ENUM_WR_PORT_INFO_5 | USE_NO
ENUM_WRITE_ODT_CHIP | WRITE_CHIP0_ODT0_CHIP1
INTG_MEM_AUTO_PD_CYCLES | 0
INTG_CYC_TO_RLD_JARS_0 | 1
INTG_CYC_TO_RLD_JARS_1 | 1
INTG_CYC_TO_RLD_JARS_2 | 1
INTG_CYC_TO_RLD_JARS_3 | 1
INTG_CYC_TO_RLD_JARS_4 | 1
INTG_CYC_TO_RLD_JARS_5 | 1
INTG_EXTRA_CTL_CLK_ACT_TO_ACT | 0
INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK | 0
INTG_EXTRA_CTL_CLK_ACT_TO_PCH | 0
INTG_EXTRA_CTL_CLK_ACT_TO_RDWR | 0
INTG_EXTRA_CTL_CLK_ARF_PERIOD | 0
INTG_EXTRA_CTL_CLK_ARF_TO_VALID | 0
INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT | 0
INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID | 0
INTG_EXTRA_CTL_CLK_PCH_TO_VALID | 0
INTG_EXTRA_CTL_CLK_PDN_PERIOD | 0
INTG_EXTRA_CTL_CLK_PDN_TO_VALID | 0
INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID | 0
INTG_EXTRA_CTL_CLK_RD_TO_PCH | 0
INTG_EXTRA_CTL_CLK_RD_TO_RD | 0
INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP | 0
INTG_EXTRA_CTL_CLK_RD_TO_WR | 2
INTG_EXTRA_CTL_CLK_RD_TO_WR_BC | 2
INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP | 2
INTG_EXTRA_CTL_CLK_SRF_TO_VALID | 0
INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL | 0
INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID | 0
INTG_EXTRA_CTL_CLK_WR_TO_PCH | 0
INTG_EXTRA_CTL_CLK_WR_TO_RD | 3
INTG_EXTRA_CTL_CLK_WR_TO_RD_BC | 3
INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP | 3
INTG_EXTRA_CTL_CLK_WR_TO_WR | 0
INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP | 0
INTG_MEM_IF_TREFI | 3120
INTG_MEM_IF_TRFC | 104
INTG_RCFG_SUM_WT_PRIORITY_0 | 0
INTG_RCFG_SUM_WT_PRIORITY_1 | 0
INTG_RCFG_SUM_WT_PRIORITY_2 | 0
INTG_RCFG_SUM_WT_PRIORITY_3 | 0
INTG_RCFG_SUM_WT_PRIORITY_4 | 0
INTG_RCFG_SUM_WT_PRIORITY_5 | 0
INTG_RCFG_SUM_WT_PRIORITY_6 | 0
INTG_RCFG_SUM_WT_PRIORITY_7 | 0
INTG_SUM_WT_PRIORITY_0 | 0
INTG_SUM_WT_PRIORITY_1 | 0
INTG_SUM_WT_PRIORITY_2 | 0
INTG_SUM_WT_PRIORITY_3 | 0
INTG_SUM_WT_PRIORITY_4 | 0
INTG_SUM_WT_PRIORITY_5 | 0
INTG_SUM_WT_PRIORITY_6 | 0
INTG_SUM_WT_PRIORITY_7 | 0
VECT_ATTR_COUNTER_ONE_MASK | 0
VECT_ATTR_COUNTER_ONE_MATCH | 0
VECT_ATTR_COUNTER_ZERO_MASK | 0
VECT_ATTR_COUNTER_ZERO_MATCH | 0
VECT_ATTR_DEBUG_SELECT_BYTE | 0
INTG_POWER_SAVING_EXIT_CYCLES | 5
INTG_MEM_CLK_ENTRY_CYCLES | 10
ENUM_ENABLE_BURST_INTERRUPT | DISABLED
ENUM_ENABLE_BURST_TERMINATE | DISABLED
AV_PORT_0_CONNECT_TO_CV_PORT | 0
CV_PORT_0_CONNECT_TO_AV_PORT | 0
CV_AVL_DATA_WIDTH_PORT_0 | 1
CV_AVL_ADDR_WIDTH_PORT_0 | 1
CV_CPORT_TYPE_PORT_0 | 0
CV_AVL_NUM_SYMBOLS_PORT_0 | 1
CV_LSB_WFIFO_PORT_0 | 5
CV_MSB_WFIFO_PORT_0 | 5
CV_LSB_RFIFO_PORT_0 | 5
CV_MSB_RFIFO_PORT_0 | 5
CV_ENUM_AUTO_PCH_ENABLE_0 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_0 | FALSE
CV_ENUM_CPORT0_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT0_TYPE | DISABLE
CV_ENUM_CPORT0_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_0 | DISABLED
CV_ENUM_PORT0_WIDTH | PORT_32_BIT
CV_ENUM_PRIORITY_0_0 | WEIGHT_0
CV_ENUM_PRIORITY_1_0 | WEIGHT_0
CV_ENUM_PRIORITY_2_0 | WEIGHT_0
CV_ENUM_PRIORITY_3_0 | WEIGHT_0
CV_ENUM_PRIORITY_4_0 | WEIGHT_0
CV_ENUM_PRIORITY_5_0 | WEIGHT_0
CV_ENUM_PRIORITY_6_0 | WEIGHT_0
CV_ENUM_PRIORITY_7_0 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_0 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_0 | PRIORITY_1
CV_ENUM_RD_DWIDTH_0 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_0 | USE_NO
CV_ENUM_STATIC_WEIGHT_0 | WEIGHT_0
CV_ENUM_USER_PRIORITY_0 | PRIORITY_1
CV_ENUM_WR_DWIDTH_0 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_0 | USE_NO
TG_TEMP_PORT_0 | 0
AV_PORT_1_CONNECT_TO_CV_PORT | 1
CV_PORT_1_CONNECT_TO_AV_PORT | 1
CV_AVL_DATA_WIDTH_PORT_1 | 1
CV_AVL_ADDR_WIDTH_PORT_1 | 1
CV_CPORT_TYPE_PORT_1 | 0
CV_AVL_NUM_SYMBOLS_PORT_1 | 1
CV_LSB_WFIFO_PORT_1 | 5
CV_MSB_WFIFO_PORT_1 | 5
CV_LSB_RFIFO_PORT_1 | 5
CV_MSB_RFIFO_PORT_1 | 5
CV_ENUM_AUTO_PCH_ENABLE_1 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_1 | FALSE
CV_ENUM_CPORT1_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT1_TYPE | DISABLE
CV_ENUM_CPORT1_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_1 | DISABLED
CV_ENUM_PORT1_WIDTH | PORT_32_BIT
CV_ENUM_PRIORITY_0_1 | WEIGHT_0
CV_ENUM_PRIORITY_1_1 | WEIGHT_0
CV_ENUM_PRIORITY_2_1 | WEIGHT_0
CV_ENUM_PRIORITY_3_1 | WEIGHT_0
CV_ENUM_PRIORITY_4_1 | WEIGHT_0
CV_ENUM_PRIORITY_5_1 | WEIGHT_0
CV_ENUM_PRIORITY_6_1 | WEIGHT_0
CV_ENUM_PRIORITY_7_1 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_1 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_1 | PRIORITY_1
CV_ENUM_RD_DWIDTH_1 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_1 | USE_NO
CV_ENUM_STATIC_WEIGHT_1 | WEIGHT_0
CV_ENUM_USER_PRIORITY_1 | PRIORITY_1
CV_ENUM_WR_DWIDTH_1 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_1 | USE_NO
TG_TEMP_PORT_1 | 0
AV_PORT_2_CONNECT_TO_CV_PORT | 2
CV_PORT_2_CONNECT_TO_AV_PORT | 2
CV_AVL_DATA_WIDTH_PORT_2 | 1
CV_AVL_ADDR_WIDTH_PORT_2 | 1
CV_CPORT_TYPE_PORT_2 | 0
CV_AVL_NUM_SYMBOLS_PORT_2 | 1
CV_LSB_WFIFO_PORT_2 | 5
CV_MSB_WFIFO_PORT_2 | 5
CV_LSB_RFIFO_PORT_2 | 5
CV_MSB_RFIFO_PORT_2 | 5
CV_ENUM_AUTO_PCH_ENABLE_2 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_2 | FALSE
CV_ENUM_CPORT2_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT2_TYPE | DISABLE
CV_ENUM_CPORT2_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_2 | DISABLED
CV_ENUM_PORT2_WIDTH | PORT_32_BIT
CV_ENUM_PRIORITY_0_2 | WEIGHT_0
CV_ENUM_PRIORITY_1_2 | WEIGHT_0
CV_ENUM_PRIORITY_2_2 | WEIGHT_0
CV_ENUM_PRIORITY_3_2 | WEIGHT_0
CV_ENUM_PRIORITY_4_2 | WEIGHT_0
CV_ENUM_PRIORITY_5_2 | WEIGHT_0
CV_ENUM_PRIORITY_6_2 | WEIGHT_0
CV_ENUM_PRIORITY_7_2 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_2 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_2 | PRIORITY_1
CV_ENUM_RD_DWIDTH_2 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_2 | USE_NO
CV_ENUM_STATIC_WEIGHT_2 | WEIGHT_0
CV_ENUM_USER_PRIORITY_2 | PRIORITY_1
CV_ENUM_WR_DWIDTH_2 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_2 | USE_NO
TG_TEMP_PORT_2 | 0
AV_PORT_3_CONNECT_TO_CV_PORT | 3
CV_PORT_3_CONNECT_TO_AV_PORT | 3
CV_AVL_DATA_WIDTH_PORT_3 | 1
CV_AVL_ADDR_WIDTH_PORT_3 | 1
CV_CPORT_TYPE_PORT_3 | 0
CV_AVL_NUM_SYMBOLS_PORT_3 | 1
CV_LSB_WFIFO_PORT_3 | 5
CV_MSB_WFIFO_PORT_3 | 5
CV_LSB_RFIFO_PORT_3 | 5
CV_MSB_RFIFO_PORT_3 | 5
CV_ENUM_AUTO_PCH_ENABLE_3 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_3 | FALSE
CV_ENUM_CPORT3_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT3_TYPE | DISABLE
CV_ENUM_CPORT3_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_3 | DISABLED
CV_ENUM_PORT3_WIDTH | PORT_32_BIT
CV_ENUM_PRIORITY_0_3 | WEIGHT_0
CV_ENUM_PRIORITY_1_3 | WEIGHT_0
CV_ENUM_PRIORITY_2_3 | WEIGHT_0
CV_ENUM_PRIORITY_3_3 | WEIGHT_0
CV_ENUM_PRIORITY_4_3 | WEIGHT_0
CV_ENUM_PRIORITY_5_3 | WEIGHT_0
CV_ENUM_PRIORITY_6_3 | WEIGHT_0
CV_ENUM_PRIORITY_7_3 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_3 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_3 | PRIORITY_1
CV_ENUM_RD_DWIDTH_3 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_3 | USE_NO
CV_ENUM_STATIC_WEIGHT_3 | WEIGHT_0
CV_ENUM_USER_PRIORITY_3 | PRIORITY_1
CV_ENUM_WR_DWIDTH_3 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_3 | USE_NO
TG_TEMP_PORT_3 | 0
AV_PORT_4_CONNECT_TO_CV_PORT | 4
CV_PORT_4_CONNECT_TO_AV_PORT | 4
CV_AVL_DATA_WIDTH_PORT_4 | 1
CV_AVL_ADDR_WIDTH_PORT_4 | 1
CV_CPORT_TYPE_PORT_4 | 0
CV_AVL_NUM_SYMBOLS_PORT_4 | 1
CV_LSB_WFIFO_PORT_4 | 5
CV_MSB_WFIFO_PORT_4 | 5
CV_LSB_RFIFO_PORT_4 | 5
CV_MSB_RFIFO_PORT_4 | 5
CV_ENUM_AUTO_PCH_ENABLE_4 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_4 | FALSE
CV_ENUM_CPORT4_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT4_TYPE | DISABLE
CV_ENUM_CPORT4_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_4 | DISABLED
CV_ENUM_PORT4_WIDTH | PORT_32_BIT
CV_ENUM_PRIORITY_0_4 | WEIGHT_0
CV_ENUM_PRIORITY_1_4 | WEIGHT_0
CV_ENUM_PRIORITY_2_4 | WEIGHT_0
CV_ENUM_PRIORITY_3_4 | WEIGHT_0
CV_ENUM_PRIORITY_4_4 | WEIGHT_0
CV_ENUM_PRIORITY_5_4 | WEIGHT_0
CV_ENUM_PRIORITY_6_4 | WEIGHT_0
CV_ENUM_PRIORITY_7_4 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_4 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_4 | PRIORITY_1
CV_ENUM_RD_DWIDTH_4 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_4 | USE_NO
CV_ENUM_STATIC_WEIGHT_4 | WEIGHT_0
CV_ENUM_USER_PRIORITY_4 | PRIORITY_1
CV_ENUM_WR_DWIDTH_4 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_4 | USE_NO
TG_TEMP_PORT_4 | 0
AV_PORT_5_CONNECT_TO_CV_PORT | 5
CV_PORT_5_CONNECT_TO_AV_PORT | 5
CV_AVL_DATA_WIDTH_PORT_5 | 1
CV_AVL_ADDR_WIDTH_PORT_5 | 1
CV_CPORT_TYPE_PORT_5 | 0
CV_AVL_NUM_SYMBOLS_PORT_5 | 1
CV_LSB_WFIFO_PORT_5 | 5
CV_MSB_WFIFO_PORT_5 | 5
CV_LSB_RFIFO_PORT_5 | 5
CV_MSB_RFIFO_PORT_5 | 5
CV_ENUM_AUTO_PCH_ENABLE_5 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_5 | FALSE
CV_ENUM_CPORT5_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT5_TYPE | DISABLE
CV_ENUM_CPORT5_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_5 | DISABLED
CV_ENUM_PORT5_WIDTH | PORT_32_BIT
CV_ENUM_PRIORITY_0_5 | WEIGHT_0
CV_ENUM_PRIORITY_1_5 | WEIGHT_0
CV_ENUM_PRIORITY_2_5 | WEIGHT_0
CV_ENUM_PRIORITY_3_5 | WEIGHT_0
CV_ENUM_PRIORITY_4_5 | WEIGHT_0
CV_ENUM_PRIORITY_5_5 | WEIGHT_0
CV_ENUM_PRIORITY_6_5 | WEIGHT_0
CV_ENUM_PRIORITY_7_5 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_5 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_5 | PRIORITY_1
CV_ENUM_RD_DWIDTH_5 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_5 | USE_NO
CV_ENUM_STATIC_WEIGHT_5 | WEIGHT_0
CV_ENUM_USER_PRIORITY_5 | PRIORITY_1
CV_ENUM_WR_DWIDTH_5 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_5 | USE_NO
TG_TEMP_PORT_5 | 0
CV_ENUM_RFIFO0_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO0_CPORT_MAP | CMD_PORT_0
CV_ENUM_RFIFO1_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO1_CPORT_MAP | CMD_PORT_0
CV_ENUM_RFIFO2_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO2_CPORT_MAP | CMD_PORT_0
CV_ENUM_RFIFO3_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO3_CPORT_MAP | CMD_PORT_0
CV_INTG_RCFG_SUM_WT_PRIORITY_0 | 0
CV_INTG_SUM_WT_PRIORITY_0 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_1 | 0
CV_INTG_SUM_WT_PRIORITY_1 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_2 | 0
CV_INTG_SUM_WT_PRIORITY_2 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_3 | 0
CV_INTG_SUM_WT_PRIORITY_3 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_4 | 0
CV_INTG_SUM_WT_PRIORITY_4 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_5 | 0
CV_INTG_SUM_WT_PRIORITY_5 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_6 | 0
CV_INTG_SUM_WT_PRIORITY_6 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_7 | 0
CV_INTG_SUM_WT_PRIORITY_7 | 0
POWER_OF_TWO_BUS | false
SOPC_COMPAT_RESET | false
AVL_MAX_SIZE | 4
BYTE_ENABLE | true
ENABLE_CTRL_AVALON_INTERFACE | true
CTL_DEEP_POWERDN_EN | false
CTL_SELF_REFRESH_EN | false
AUTO_POWERDN_EN | false
AUTO_PD_CYCLES | 0
CTL_USR_REFRESH_EN | false
CTL_AUTOPCH_EN | false
CTL_ZQCAL_EN | false
ADDR_ORDER | 0
CTL_LOOK_AHEAD_DEPTH | 4
CONTROLLER_LATENCY | 5
CFG_REORDER_DATA | true
STARVE_LIMIT | 10
CTL_CSR_ENABLED | false
CTL_CSR_CONNECTION | INTERNAL_JTAG
CTL_ECC_ENABLED | false
CTL_HRB_ENABLED | false
CTL_ECC_AUTO_CORRECTION_ENABLED | false
MULTICAST_EN | false
CTL_DYNAMIC_BANK_ALLOCATION | false
CTL_DYNAMIC_BANK_NUM | 4
DEBUG_MODE | false
ENABLE_BURST_MERGE | false
CTL_ENABLE_BURST_INTERRUPT | false
CTL_ENABLE_BURST_TERMINATE | false
LOCAL_ID_WIDTH | 8
RDBUFFER_ADDR_WIDTH | 8
WRBUFFER_ADDR_WIDTH | 6
MAX_PENDING_WR_CMD | 16
MAX_PENDING_RD_CMD | 32
USE_MM_ADAPTOR | true
USE_AXI_ADAPTOR | false
HCX_COMPAT_MODE | false
CTL_CMD_QUEUE_DEPTH | 8
CTL_CSR_READ_ONLY | 1
CFG_DATA_REORDERING_TYPE | INTER_BANK
NUM_OF_PORTS | 1
ENABLE_BONDING | false
ENABLE_USER_ECC | false
AVL_DATA_WIDTH_PORT | 32,32,32,32,32,32
PRIORITY_PORT | 1,1,1,1,1,1
WEIGHT_PORT | 0,0,0,0,0,0
CPORT_TYPE_PORT | Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional
CORE_PERIPHERY_DUAL_CLOCK | false
USE_DR_CLK | false
DLL_USE_DR_CLK | false
USE_2X_FF | false
DUAL_WRITE_CLOCK | false
GENERIC_PLL | true
USE_HARD_READ_FIFO | false
READ_FIFO_HALF_RATE | false
PLL_MASTER | true
DLL_MASTER | true
PHY_VERSION_NUMBER | 131
ENABLE_NIOS_OCI | false
ENABLE_EMIT_JTAG_MASTER | true
ENABLE_NIOS_JTAG_UART | false
ENABLE_NIOS_PRINTF_OUTPUT | false
ENABLE_LARGE_RW_MGR_DI_BUFFER | false
ENABLE_EMIT_BFM_MASTER | false
FORCE_SEQUENCER_TCL_DEBUG_MODE | false
ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT | false
ENABLE_MAX_SIZE_SEQ_MEM | false
MAKE_INTERNAL_NIOS_VISIBLE | false
DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG | false
ENABLE_CSR_SOFT_RESET_REQ | true
DUPLICATE_PLL_FOR_PHY_CLK | true
MAX_LATENCY_COUNT_WIDTH | 5
READ_VALID_FIFO_SIZE | 16
EXTRA_VFIFO_SHIFT | 0
TB_MEM_CLK_FREQ | 400.0
TB_RATE | FULL
TB_MEM_IF_DQ_WIDTH | 32
TB_MEM_IF_READ_DQS_WIDTH | 4
TB_PLL_DLL_MASTER | true
FAST_SIM_CALIBRATION | false
REF_CLK_FREQ | 25.0
REF_CLK_FREQ_STR | 25.0 MHz
REF_CLK_NS | 40.0
REF_CLK_PS | 40000.0
PLL_DR_CLK_FREQ | 0.0
PLL_DR_CLK_FREQ_STR |
PLL_DR_CLK_FREQ_SIM_STR | 0 ps
PLL_DR_CLK_PHASE_PS | 0
PLL_DR_CLK_PHASE_PS_STR |
PLL_DR_CLK_PHASE_DEG | 0.0
PLL_DR_CLK_PHASE_PS_SIM | 0
PLL_DR_CLK_PHASE_PS_SIM_STR |
PLL_DR_CLK_PHASE_DEG_SIM | 0.0
PLL_DR_CLK_MULT | 0
PLL_DR_CLK_DIV | 0
PLL_MEM_CLK_FREQ | 400.0
PLL_MEM_CLK_FREQ_STR | 400.0 MHz
PLL_MEM_CLK_FREQ_SIM_STR | 2500 ps
PLL_MEM_CLK_PHASE_PS | 0
PLL_MEM_CLK_PHASE_PS_STR | 0 ps
PLL_MEM_CLK_PHASE_DEG | 0.0
PLL_MEM_CLK_PHASE_PS_SIM | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR | 0 ps
PLL_MEM_CLK_PHASE_DEG_SIM | 0.0
PLL_MEM_CLK_MULT | 32
PLL_MEM_CLK_DIV | 2
PLL_AFI_CLK_FREQ | 400.0
PLL_AFI_CLK_FREQ_STR | 400.0 MHz
PLL_AFI_CLK_FREQ_SIM_STR | 2500 ps
PLL_AFI_CLK_PHASE_PS | 0
PLL_AFI_CLK_PHASE_PS_STR | 0 ps
PLL_AFI_CLK_PHASE_DEG | 0.0
PLL_AFI_CLK_PHASE_PS_SIM | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR | 0 ps
PLL_AFI_CLK_PHASE_DEG_SIM | 0.0
PLL_AFI_CLK_MULT | 32
PLL_AFI_CLK_DIV | 2
PLL_WRITE_CLK_FREQ | 400.0
PLL_WRITE_CLK_FREQ_STR | 400.0 MHz
PLL_WRITE_CLK_FREQ_SIM_STR | 2500 ps
PLL_WRITE_CLK_PHASE_PS | 1875
PLL_WRITE_CLK_PHASE_PS_STR | 1875 ps
PLL_WRITE_CLK_PHASE_DEG | 270.0
PLL_WRITE_CLK_PHASE_PS_SIM | 1875
PLL_WRITE_CLK_PHASE_PS_SIM_STR | 1875 ps
PLL_WRITE_CLK_PHASE_DEG_SIM | 270.0
PLL_WRITE_CLK_MULT | 32
PLL_WRITE_CLK_DIV | 2
PLL_ADDR_CMD_CLK_FREQ | 400.0
PLL_ADDR_CMD_CLK_FREQ_STR | 400.0 MHz
PLL_ADDR_CMD_CLK_FREQ_SIM_STR | 2500 ps
PLL_ADDR_CMD_CLK_PHASE_PS | 1875
PLL_ADDR_CMD_CLK_PHASE_PS_STR | 1875 ps
PLL_ADDR_CMD_CLK_PHASE_DEG | 270.0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM | 1875
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR | 1875 ps
PLL_ADDR_CMD_CLK_PHASE_DEG_SIM | 270.0
PLL_ADDR_CMD_CLK_MULT | 32
PLL_ADDR_CMD_CLK_DIV | 2
PLL_AFI_HALF_CLK_FREQ | 400.0
PLL_AFI_HALF_CLK_FREQ_STR | 400.0 MHz
PLL_AFI_HALF_CLK_FREQ_SIM_STR | 5000 ps
PLL_AFI_HALF_CLK_PHASE_PS | 0
PLL_AFI_HALF_CLK_PHASE_PS_STR | 0 ps
PLL_AFI_HALF_CLK_PHASE_DEG | 0.0
PLL_AFI_HALF_CLK_PHASE_PS_SIM | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR | 0 ps
PLL_AFI_HALF_CLK_PHASE_DEG_SIM | 0.0
PLL_AFI_HALF_CLK_MULT | 32
PLL_AFI_HALF_CLK_DIV | 2
PLL_NIOS_CLK_FREQ | 66.6666666667
PLL_NIOS_CLK_FREQ_STR |
PLL_NIOS_CLK_FREQ_SIM_STR | 15000 ps
PLL_NIOS_CLK_PHASE_PS | 0
PLL_NIOS_CLK_PHASE_PS_STR |
PLL_NIOS_CLK_PHASE_DEG | 10.0
PLL_NIOS_CLK_PHASE_PS_SIM | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR |
PLL_NIOS_CLK_PHASE_DEG_SIM | 10.0
PLL_NIOS_CLK_MULT | 0
PLL_NIOS_CLK_DIV | 6000000
PLL_CONFIG_CLK_FREQ | 22.2222222222
PLL_CONFIG_CLK_FREQ_STR |
PLL_CONFIG_CLK_FREQ_SIM_STR | 45000 ps
PLL_CONFIG_CLK_PHASE_PS | 0
PLL_CONFIG_CLK_PHASE_PS_STR |
PLL_CONFIG_CLK_PHASE_DEG | 0.0
PLL_CONFIG_CLK_PHASE_PS_SIM | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR |
PLL_CONFIG_CLK_PHASE_DEG_SIM | 0.0
PLL_CONFIG_CLK_MULT | 0
PLL_CONFIG_CLK_DIV | 18000000
PLL_P2C_READ_CLK_FREQ | 0.0
PLL_P2C_READ_CLK_FREQ_STR |
PLL_P2C_READ_CLK_FREQ_SIM_STR | 0 ps
PLL_P2C_READ_CLK_PHASE_PS | 0
PLL_P2C_READ_CLK_PHASE_PS_STR |
PLL_P2C_READ_CLK_PHASE_DEG | 0.0
PLL_P2C_READ_CLK_PHASE_PS_SIM | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR |
PLL_P2C_READ_CLK_PHASE_DEG_SIM | 0.0
PLL_P2C_READ_CLK_MULT | 0
PLL_P2C_READ_CLK_DIV | 0
PLL_C2P_WRITE_CLK_FREQ | 0.0
PLL_C2P_WRITE_CLK_FREQ_STR |
PLL_C2P_WRITE_CLK_FREQ_SIM_STR | 0 ps
PLL_C2P_WRITE_CLK_PHASE_PS | 0
PLL_C2P_WRITE_CLK_PHASE_PS_STR |
PLL_C2P_WRITE_CLK_PHASE_DEG | 0.0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR |
PLL_C2P_WRITE_CLK_PHASE_DEG_SIM | 0.0
PLL_C2P_WRITE_CLK_MULT | 0
PLL_C2P_WRITE_CLK_DIV | 0
PLL_HR_CLK_FREQ | 0.0
PLL_HR_CLK_FREQ_STR |
PLL_HR_CLK_FREQ_SIM_STR | 0 ps
PLL_HR_CLK_PHASE_PS | 0
PLL_HR_CLK_PHASE_PS_STR |
PLL_HR_CLK_PHASE_DEG | 0.0
PLL_HR_CLK_PHASE_PS_SIM | 0
PLL_HR_CLK_PHASE_PS_SIM_STR |
PLL_HR_CLK_PHASE_DEG_SIM | 0.0
PLL_HR_CLK_MULT | 0
PLL_HR_CLK_DIV | 0
PLL_AFI_PHY_CLK_FREQ | 400.0
PLL_AFI_PHY_CLK_FREQ_STR |
PLL_AFI_PHY_CLK_FREQ_SIM_STR | 2500 ps
PLL_AFI_PHY_CLK_PHASE_PS | 0
PLL_AFI_PHY_CLK_PHASE_PS_STR |
PLL_AFI_PHY_CLK_PHASE_DEG | 0.0
PLL_AFI_PHY_CLK_PHASE_PS_SIM | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR |
PLL_AFI_PHY_CLK_PHASE_DEG_SIM | 0.0
PLL_AFI_PHY_CLK_MULT | 0
PLL_AFI_PHY_CLK_DIV | 1000000
REF_CLK_FREQ_CACHE_VALID | true
REF_CLK_FREQ_PARAM_VALID | false
REF_CLK_FREQ_MIN_PARAM | 0.0
REF_CLK_FREQ_MAX_PARAM | 0.0
REF_CLK_FREQ_MIN_CACHE | 10.0
REF_CLK_FREQ_MAX_CACHE | 500.0
PLL_DR_CLK_FREQ_PARAM | 0.0
PLL_DR_CLK_FREQ_SIM_STR_PARAM |
PLL_DR_CLK_PHASE_PS_PARAM | 0
PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_DR_CLK_MULT_PARAM | 0
PLL_DR_CLK_DIV_PARAM | 0
PLL_DR_CLK_FREQ_CACHE | 0.0
PLL_DR_CLK_FREQ_SIM_STR_CACHE |
PLL_DR_CLK_PHASE_PS_CACHE | 0
PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_DR_CLK_MULT_CACHE | 0
PLL_DR_CLK_DIV_CACHE | 0
PLL_MEM_CLK_FREQ_PARAM | 0.0
PLL_MEM_CLK_FREQ_SIM_STR_PARAM |
PLL_MEM_CLK_PHASE_PS_PARAM | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_MEM_CLK_MULT_PARAM | 0
PLL_MEM_CLK_DIV_PARAM | 0
PLL_MEM_CLK_FREQ_CACHE | 400.0
PLL_MEM_CLK_FREQ_SIM_STR_CACHE | 2500 ps
PLL_MEM_CLK_PHASE_PS_CACHE | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE | 0 ps
PLL_MEM_CLK_MULT_CACHE | 32
PLL_MEM_CLK_DIV_CACHE | 2
PLL_AFI_CLK_FREQ_PARAM | 0.0
PLL_AFI_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_CLK_PHASE_PS_PARAM | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_CLK_MULT_PARAM | 0
PLL_AFI_CLK_DIV_PARAM | 0
PLL_AFI_CLK_FREQ_CACHE | 400.0
PLL_AFI_CLK_FREQ_SIM_STR_CACHE | 2500 ps
PLL_AFI_CLK_PHASE_PS_CACHE | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE | 0 ps
PLL_AFI_CLK_MULT_CACHE | 32
PLL_AFI_CLK_DIV_CACHE | 2
PLL_WRITE_CLK_FREQ_PARAM | 0.0
PLL_WRITE_CLK_FREQ_SIM_STR_PARAM |
PLL_WRITE_CLK_PHASE_PS_PARAM | 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_WRITE_CLK_MULT_PARAM | 0
PLL_WRITE_CLK_DIV_PARAM | 0
PLL_WRITE_CLK_FREQ_CACHE | 400.0
PLL_WRITE_CLK_FREQ_SIM_STR_CACHE | 2500 ps
PLL_WRITE_CLK_PHASE_PS_CACHE | 1875
PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE | 1875 ps
PLL_WRITE_CLK_MULT_CACHE | 32
PLL_WRITE_CLK_DIV_CACHE | 2
PLL_ADDR_CMD_CLK_FREQ_PARAM | 0.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM |
PLL_ADDR_CMD_CLK_PHASE_PS_PARAM | 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_ADDR_CMD_CLK_MULT_PARAM | 0
PLL_ADDR_CMD_CLK_DIV_PARAM | 0
PLL_ADDR_CMD_CLK_FREQ_CACHE | 400.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE | 2500 ps
PLL_ADDR_CMD_CLK_PHASE_PS_CACHE | 1875
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE | 1875 ps
PLL_ADDR_CMD_CLK_MULT_CACHE | 32
PLL_ADDR_CMD_CLK_DIV_CACHE | 2
PLL_AFI_HALF_CLK_FREQ_PARAM | 0.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_HALF_CLK_PHASE_PS_PARAM | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_HALF_CLK_MULT_PARAM | 0
PLL_AFI_HALF_CLK_DIV_PARAM | 0
PLL_AFI_HALF_CLK_FREQ_CACHE | 400.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE | 5000 ps
PLL_AFI_HALF_CLK_PHASE_PS_CACHE | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE | 0 ps
PLL_AFI_HALF_CLK_MULT_CACHE | 32
PLL_AFI_HALF_CLK_DIV_CACHE | 2
PLL_NIOS_CLK_FREQ_PARAM | 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_PARAM |
PLL_NIOS_CLK_PHASE_PS_PARAM | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_NIOS_CLK_MULT_PARAM | 0
PLL_NIOS_CLK_DIV_PARAM | 0
PLL_NIOS_CLK_FREQ_CACHE | 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_CACHE |
PLL_NIOS_CLK_PHASE_PS_CACHE | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_NIOS_CLK_MULT_CACHE | 0
PLL_NIOS_CLK_DIV_CACHE | 0
PLL_CONFIG_CLK_FREQ_PARAM | 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM |
PLL_CONFIG_CLK_PHASE_PS_PARAM | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_CONFIG_CLK_MULT_PARAM | 0
PLL_CONFIG_CLK_DIV_PARAM | 0
PLL_CONFIG_CLK_FREQ_CACHE | 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE |
PLL_CONFIG_CLK_PHASE_PS_CACHE | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_CONFIG_CLK_MULT_CACHE | 0
PLL_CONFIG_CLK_DIV_CACHE | 0
PLL_P2C_READ_CLK_FREQ_PARAM | 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM |
PLL_P2C_READ_CLK_PHASE_PS_PARAM | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_P2C_READ_CLK_MULT_PARAM | 0
PLL_P2C_READ_CLK_DIV_PARAM | 0
PLL_P2C_READ_CLK_FREQ_CACHE | 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE |
PLL_P2C_READ_CLK_PHASE_PS_CACHE | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_P2C_READ_CLK_MULT_CACHE | 0
PLL_P2C_READ_CLK_DIV_CACHE | 0
PLL_C2P_WRITE_CLK_FREQ_PARAM | 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM |
PLL_C2P_WRITE_CLK_PHASE_PS_PARAM | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_C2P_WRITE_CLK_MULT_PARAM | 0
PLL_C2P_WRITE_CLK_DIV_PARAM | 0
PLL_C2P_WRITE_CLK_FREQ_CACHE | 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE |
PLL_C2P_WRITE_CLK_PHASE_PS_CACHE | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_C2P_WRITE_CLK_MULT_CACHE | 0
PLL_C2P_WRITE_CLK_DIV_CACHE | 0
PLL_HR_CLK_FREQ_PARAM | 0.0
PLL_HR_CLK_FREQ_SIM_STR_PARAM |
PLL_HR_CLK_PHASE_PS_PARAM | 0
PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_HR_CLK_MULT_PARAM | 0
PLL_HR_CLK_DIV_PARAM | 0
PLL_HR_CLK_FREQ_CACHE | 0.0
PLL_HR_CLK_FREQ_SIM_STR_CACHE |
PLL_HR_CLK_PHASE_PS_CACHE | 0
PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_HR_CLK_MULT_CACHE | 0
PLL_HR_CLK_DIV_CACHE | 0
PLL_AFI_PHY_CLK_FREQ_PARAM | 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_PHY_CLK_PHASE_PS_PARAM | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_PHY_CLK_MULT_PARAM | 0
PLL_AFI_PHY_CLK_DIV_PARAM | 0
PLL_AFI_PHY_CLK_FREQ_CACHE | 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE |
PLL_AFI_PHY_CLK_PHASE_PS_CACHE | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_AFI_PHY_CLK_MULT_CACHE | 0
PLL_AFI_PHY_CLK_DIV_CACHE | 0
SPEED_GRADE_CACHE | 7
IS_ES_DEVICE_CACHE | false
MEM_CLK_FREQ_CACHE | 400.0
REF_CLK_FREQ_CACHE | 25.0
RATE_CACHE | Full
HCX_COMPAT_MODE_CACHE | false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE | CYCLONEV
COMMAND_PHASE_CACHE | 0.0
MEM_CK_PHASE_CACHE | 0.0
P2C_READ_CLOCK_ADD_PHASE_CACHE | 0.0
C2P_WRITE_CLOCK_ADD_PHASE_CACHE | 0.0
ACV_PHY_CLK_ADD_FR_PHASE_CACHE | 0.0
SEQUENCER_TYPE_CACHE | NIOS
USE_MEM_CLK_FREQ_CACHE | false
PLL_CLK_CACHE_VALID | true
PLL_CLK_PARAM_VALID | false
ENABLE_EXTRA_REPORTING | false
NUM_EXTRA_REPORT_PATH | 10
ENABLE_ISS_PROBES | false
CALIB_REG_WIDTH | 8
USE_SEQUENCER_BFM | false
DEFAULT_FAST_SIM_MODEL | true
PLL_SHARING_MODE | None
NUM_PLL_SHARING_INTERFACES | 1
EXPORT_AFI_HALF_CLK | false
ABSTRACT_REAL_COMPARE_TEST | false
INCLUDE_BOARD_DELAY_MODEL | false
INCLUDE_MULTIRANK_BOARD_DELAY_MODEL | false
USE_FAKE_PHY_INTERNAL | false
USE_FAKE_PHY | false
FORCE_MAX_LATENCY_COUNT_WIDTH | 0
USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE | false
ENABLE_NON_DESTRUCTIVE_CALIB | false
TRACKING_ERROR_TEST | false
TRACKING_WATCH_TEST | false
MARGIN_VARIATION_TEST | false
EXTRA_SETTINGS |
MEM_DEVICE | MISSING_MODEL
FORCE_SYNTHESIS_LANGUAGE |
NUM_SUBGROUP_PER_READ_DQS | 1
QVLD_EXTRA_FLOP_STAGES | 5
QVLD_WR_ADDRESS_OFFSET | 5
MAX_WRITE_LATENCY_COUNT_WIDTH | 4
NUM_WRITE_PATH_FLOP_STAGES | 1
NUM_AC_FR_CYCLE_SHIFTS | 0
FORCED_NUM_WRITE_FR_CYCLE_SHIFTS | 0
NUM_WRITE_FR_CYCLE_SHIFTS | 0
PERFORM_READ_AFTER_WRITE_CALIBRATION | true
SEQ_BURST_COUNT_WIDTH | 2
VCALIB_COUNT_WIDTH | 2
PLL_PHASE_COUNTER_WIDTH | 4
DQS_DELAY_CHAIN_PHASE_SETTING | 0
DQS_PHASE_SHIFT | 0
DELAYED_CLOCK_PHASE_SETTING | 2
IO_DQS_IN_RESERVE | 4
IO_DQS_OUT_RESERVE | 4
IO_DQ_OUT_RESERVE | 0
IO_DM_OUT_RESERVE | 0
IO_DQS_EN_DELAY_OFFSET | 0
IO_DQS_EN_PHASE_MAX | 7
IO_DQDQS_OUT_PHASE_MAX | 0
IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS | false
MEM_CLK_NS | 2.5
MEM_CLK_PS | 2500.0
CALIB_LFIFO_OFFSET | 12
CALIB_VFIFO_OFFSET | 10
DELAY_PER_OPA_TAP | 312
DELAY_PER_DCHAIN_TAP | 25
DELAY_PER_DQS_EN_DCHAIN_TAP | 25
DQS_EN_DELAY_MAX | 31
DQS_IN_DELAY_MAX | 31
IO_IN_DELAY_MAX | 31
IO_OUT1_DELAY_MAX | 31
IO_OUT2_DELAY_MAX | 0
IO_STANDARD | SSTL-15
VFIFO_AS_SHIFT_REG | true
SEQUENCER_TYPE | NIOS
NIOS_HEX_FILE_LOCATION | ../
ADVERTIZE_SEQUENCER_SW_BUILD_FILES | false
NEGATIVE_WRITE_CK_PHASE | true
MEM_T_WL | 8
MEM_T_RL | 11
PHY_CLKBUF | false
USE_LDC_AS_LOW_SKEW_CLOCK | false
USE_LDC_FOR_ADDR_CMD | false
ENABLE_LDC_MEM_CK_ADJUSTMENT | false
MEM_CK_LDC_ADJUSTMENT_THRESHOLD | 0
LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT | true
LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE | 0
FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT | false
NON_LDC_ADDR_CMD_MEM_CK_INVERT | false
REGISTER_C2P | false
EARLY_ADDR_CMD_CLK_TRANSFER | true
PHY_ONLY | false
SEQ_MODE | 0
ADVANCED_CK_PHASES | false
COMMAND_PHASE | 0.0
MEM_CK_PHASE | 0.0
P2C_READ_CLOCK_ADD_PHASE | 0.0
C2P_WRITE_CLOCK_ADD_PHASE | 0.0
ACV_PHY_CLK_ADD_FR_PHASE | 0.0
MEM_VOLTAGE | 1.5V DDR3
PLL_LOCATION | Top_Bottom
SKIP_MEM_INIT | true
READ_DQ_DQS_CLOCK_SOURCE | INVERTED_DQS_BUS
DQ_INPUT_REG_USE_CLKN | false
DQS_DQSN_MODE | DIFFERENTIAL
AFI_DEBUG_INFO_WIDTH | 32
CALIBRATION_MODE | Skip
NIOS_ROM_DATA_WIDTH | 32
NIOS_ROM_ADDRESS_WIDTH | 13
READ_FIFO_SIZE | 8
PHY_CSR_ENABLED | false
PHY_CSR_CONNECTION | INTERNAL_JTAG
USER_DEBUG_LEVEL | 1
TIMING_BOARD_DERATE_METHOD | AUTO
TIMING_BOARD_CK_CKN_SLEW_RATE | 2.0
TIMING_BOARD_AC_SLEW_RATE | 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE | 2.0
TIMING_BOARD_DQ_SLEW_RATE | 1.0
TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED | 2.0
TIMING_BOARD_AC_SLEW_RATE_APPLIED | 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED | 2.0
TIMING_BOARD_DQ_SLEW_RATE_APPLIED | 1.0
TIMING_BOARD_TIS | 0.0
TIMING_BOARD_TIH | 0.0
TIMING_BOARD_TDS | 0.0
TIMING_BOARD_TDH | 0.0
TIMING_BOARD_TIS_APPLIED | 0.33
TIMING_BOARD_TIH_APPLIED | 0.24
TIMING_BOARD_TDS_APPLIED | 0.18
TIMING_BOARD_TDH_APPLIED | 0.165
TIMING_BOARD_ISI_METHOD | AUTO
TIMING_BOARD_AC_EYE_REDUCTION_SU | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H | 0.0
TIMING_BOARD_DQ_EYE_REDUCTION | 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME | 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION | 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED | 0.0
TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED | 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED | 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED | 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED | 0.0
PACKAGE_DESKEW | false
AC_PACKAGE_DESKEW | false
TIMING_BOARD_MAX_CK_DELAY | 0.03
TIMING_BOARD_MAX_DQS_DELAY | 0.02
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN | 0.09
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED | 0.09
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX | 0.16
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED | 0.16
TIMING_BOARD_SKEW_BETWEEN_DIMMS | 0.05
TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED | 0.0
TIMING_BOARD_SKEW_WITHIN_DQS | 0.01
TIMING_BOARD_SKEW_BETWEEN_DQS | 0.08
TIMING_BOARD_DQ_TO_DQS_SKEW | 0.0
TIMING_BOARD_AC_SKEW | 0.03
TIMING_BOARD_AC_TO_CK_SKEW | 0.0
RATE | Full
MEM_CLK_FREQ | 400.0
USE_MEM_CLK_FREQ | false
USE_DQS_TRACKING | true
FORCE_DQS_TRACKING | AUTO
USE_HPS_DQS_TRACKING | false
TRK_PARALLEL_SCC_LOAD | false
USE_SHADOW_REGS | false
FORCE_SHADOW_REGS | AUTO
DQ_DDR | 1
ADDR_CMD_DDR | 1
AFI_RATE_RATIO | 1
DATA_RATE_RATIO | 2
ADDR_RATE_RATIO | 2
AFI_ADDR_WIDTH | 30
AFI_BANKADDR_WIDTH | 6
AFI_CONTROL_WIDTH | 2
AFI_CS_WIDTH | 1
AFI_CLK_EN_WIDTH | 1
AFI_DM_WIDTH | 8
AFI_DQ_WIDTH | 64
AFI_ODT_WIDTH | 1
AFI_WRITE_DQS_WIDTH | 4
AFI_RLAT_WIDTH | 6
AFI_WLAT_WIDTH | 6
AFI_RRANK_WIDTH | 0
AFI_WRANK_WIDTH | 0
AFI_CLK_PAIR_COUNT | 1
MRS_MIRROR_PING_PONG_ATSO | false
SYS_INFO_DEVICE_FAMILY | CYCLONEV
PARSE_FRIENDLY_DEVICE_FAMILY | CYCLONEV
DEVICE_FAMILY | Cyclone V
PRE_V_SERIES_FAMILY | false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID | true
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID | false
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM |
DEVICE_FAMILY_PARAM |
SPEED_GRADE | 7
IS_ES_DEVICE | false
DISABLE_CHILD_MESSAGING | false
HARD_PHY | true
HARD_EMIF | true
HHP_HPS | true
HHP_HPS_VERIFICATION | false
HHP_HPS_SIMULATION | false
HPS_PROTOCOL | DDR3
CUT_NEW_FAMILY_TIMING | true
ENABLE_EXPORT_SEQ_DEBUG_BRIDGE | false
CORE_DEBUG_CONNECTION | EXPORT
ADD_EXTERNAL_SEQ_DEBUG_NIOS | false
ED_EXPORT_SEQ_DEBUG | false
ADD_EFFICIENCY_MONITOR | false
ENABLE_ABS_RAM_MEM_INIT | false
ENABLE_ABS_RAM_INTERNAL | false
ENABLE_ABSTRACT_RAM | false
ABS_RAM_MEM_INIT_FILENAME | meminit
DLL_DELAY_CTRL_WIDTH | 7
DLL_OFFSET_CTRL_WIDTH | 6
DELAY_BUFFER_MODE | HIGH
DELAY_CHAIN_LENGTH | 8
DLL_SHARING_MODE | None
NUM_DLL_SHARING_INTERFACES | 1
OCT_TERM_CONTROL_WIDTH | 16
OCT_SHARING_MODE | None
NUM_OCT_SHARING_INTERFACES | 1
MPU_EVENTS_Enable | false
GP_Enable | false
DEBUGAPB_Enable | false
STM_Enable | false
CTI_Enable | false
TPIUFPGA_Enable | false
BOOTFROMFPGA_Enable | false
TEST_Enable | false
HLGPI_Enable | false
BSEL_EN | false
BSEL | 1
CSEL_EN | false
CSEL | 0
F2S_Width | 2
S2F_Width | 2
LWH2F_Enable | true
F2SDRAM_Name_DERIVED |
F2SDRAM_Type |
F2SDRAM_Width |
F2SDRAM_Width_Last_Size | 0
F2SDRAM_CMD_PORT_USED | 0x0
F2SDRAM_WR_PORT_USED | 0x0
F2SDRAM_RD_PORT_USED | 0x0
F2SDRAM_RST_PORT_USED | 0x0
BONDING_OUT_ENABLED | false
S2FCLK_COLDRST_Enable | false
S2FCLK_PENDINGRST_Enable | false
F2SCLK_DBGRST_Enable | false
F2SCLK_WARMRST_Enable | false
F2SCLK_COLDRST_Enable | false
DMA_PeriphId_DERIVED | 0,1,2,3,4,5,6,7
DMA_Enable | No,No,No,No,No,No,No,No
F2SINTERRUPT_Enable | true
S2FINTERRUPT_CAN_Enable | false
S2FINTERRUPT_CLOCKPERIPHERAL_Enable | false
S2FINTERRUPT_CTI_Enable | false
S2FINTERRUPT_DMA_Enable | false
S2FINTERRUPT_EMAC_Enable | false
S2FINTERRUPT_FPGAMANAGER_Enable | false
S2FINTERRUPT_GPIO_Enable | false
S2FINTERRUPT_I2CEMAC_Enable | false
S2FINTERRUPT_I2CPERIPHERAL_Enable | false
S2FINTERRUPT_L4TIMER_Enable | false
S2FINTERRUPT_NAND_Enable | false
S2FINTERRUPT_OSCTIMER_Enable | false
S2FINTERRUPT_QSPI_Enable | false
S2FINTERRUPT_SDMMC_Enable | false
S2FINTERRUPT_SPIMASTER_Enable | false
S2FINTERRUPT_SPISLAVE_Enable | false
S2FINTERRUPT_UART_Enable | false
S2FINTERRUPT_USB_Enable | false
S2FINTERRUPT_WATCHDOG_Enable | false
EMAC0_PinMuxing | Unused
EMAC0_Mode | N/A
EMAC1_PinMuxing | HPS I/O Set 0
EMAC1_Mode | RGMII
NAND_PinMuxing | Unused
NAND_Mode | N/A
QSPI_PinMuxing | HPS I/O Set 0
QSPI_Mode | 1 SS
SDIO_PinMuxing | HPS I/O Set 0
SDIO_Mode | 4-bit Data
USB0_PinMuxing | Unused
USB0_Mode | N/A
USB1_PinMuxing | HPS I/O Set 0
USB1_Mode | SDR
SPIM0_PinMuxing | HPS I/O Set 0
SPIM0_Mode | Single Slave Select
SPIM1_PinMuxing | HPS I/O Set 0
SPIM1_Mode | Single Slave Select
SPIS0_PinMuxing | Unused
SPIS0_Mode | N/A
SPIS1_PinMuxing | Unused
SPIS1_Mode | N/A
UART0_PinMuxing | HPS I/O Set 0
UART0_Mode | No Flow Control
UART1_PinMuxing | Unused
UART1_Mode | N/A
I2C0_PinMuxing | Unused
I2C0_Mode | N/A
I2C1_PinMuxing | HPS I/O Set 0
I2C1_Mode | I2C
I2C2_PinMuxing | Unused
I2C2_Mode | N/A
I2C3_PinMuxing | Unused
I2C3_Mode | N/A
CAN0_PinMuxing | Unused
CAN0_Mode | N/A
CAN1_PinMuxing | Unused
CAN1_Mode | N/A
TRACE_PinMuxing | Unused
TRACE_Mode | N/A
Customer_Pin_Name_DERIVED | RGMII0_TX_CLK,RGMII0_TXD0,RGMII0_TXD1,RGMII0_TXD2,RGMII0_TXD3,RGMII0_RXD0,RGMII0_MDIO,RGMII0_MDC ,RGMII0_RX_CTL,RGMII0_TX_CTL,RGMII0_RX_CLK,RGMII0_RXD1,RGMII0_RXD2,RGMII0_RXD3,NAND_ALE,NAND_CE,NAND_CLE,NAND_RE,NAND_RB,NAND_DQ0,NAND_DQ1,NAND_DQ2,NAND_DQ3,NAND_DQ4,NAND_DQ5,NAND_DQ6,NAND_DQ7,NAND_WP,NAND_WE,QSPI_IO0,QSPI_IO1,QSPI_IO2,QSPI_IO3,QSPI_SS0,QSPI_CLK,QSPI_SS1,SDMMC_CMD,SDMMC_PWREN,SDMMC_D0,SDMMC_D1,SDMMC_D4,SDMMC_D5,SDMMC_D6,SDMMC_D7,SDMMC_FB_CLK_IN,SDMMC_CCLK_OUT,SDMMC_D2,SDMMC_D3,TRACE_CLK,TRACE_D0,TRACE_D1,TRACE_D2,TRACE_D3,TRACE_D4,TRACE_D5,TRACE_D6,TRACE_D7,SPIM0_CLK,SPIM0_MOSI,SPIM0_MISO,SPIM0_SS0,UART0_RX,UART0_TX,I2C0_SDA,I2C0_SCL,CAN0_RX,CAN0_TX
GPIO_Conflict_DERIVED | ,USB1.D0,USB1.D1,USB1.D2,USB1.D3,USB1.D4,USB1.D5,USB1.D6,USB1.D7,,USB1.CLK,USB1.STP,USB1.DIR,USB1.NXT,EMAC1.TX_CLK,EMAC1.TXD0,EMAC1.TXD1,EMAC1.TXD2,EMAC1.TXD3,EMAC1.RXD0,EMAC1.MDIO,EMAC1.MDC,EMAC1.RX_CTL,EMAC1.TX_CTL,EMAC1.RX_CLK,EMAC1.RXD1,EMAC1.RXD2,EMAC1.RXD3,,QSPI.IO0,QSPI.IO1,QSPI.IO2,QSPI.IO3,QSPI.SS0,QSPI.CLK,,SDIO.CMD,,SDIO.D0,SDIO.D1,,,,,,SDIO.CLK,SDIO.D2,SDIO.D3,,UART0.RX,UART0.TX,I2C1.SDA,I2C1.SCL,,,,,SPIM0.CLK,SPIM0.MOSI,SPIM0.MISO,SPIM0.SS0,,,SPIM1.CLK,SPIM1.MOSI,SPIM1.MISO,SPIM1.SS0
GPIO_Name_DERIVED | GPIO00,GPIO01,GPIO02,GPIO03,GPIO04,GPIO05,GPIO06,GPIO07,GPIO08,GPIO09,GPIO10,GPIO11,GPIO12,GPIO13,GPIO14,GPIO15,GPIO16,GPIO17,GPIO18,GPIO19,GPIO20,GPIO21,GPIO22,GPIO23,GPIO24,GPIO25,GPIO26,GPIO27,GPIO28,GPIO29,GPIO30,GPIO31,GPIO32,GPIO33,GPIO34,GPIO35,GPIO36,GPIO37,GPIO38,GPIO39,GPIO40,GPIO41,GPIO42,GPIO43,GPIO44,GPIO45,GPIO46,GPIO47,GPIO48,GPIO49,GPIO50,GPIO51,GPIO52,GPIO53,GPIO54,GPIO55,GPIO56,GPIO57,GPIO58,GPIO59,GPIO60,GPIO61,GPIO62,GPIO63,GPIO64,GPIO65,GPIO66
GPIO_Enable | No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No
LOANIO_Name_DERIVED | LOANIO00,LOANIO01,LOANIO02,LOANIO03,LOANIO04,LOANIO05,LOANIO06,LOANIO07,LOANIO08,LOANIO09,LOANIO10,LOANIO11,LOANIO12,LOANIO13,LOANIO14,LOANIO15,LOANIO16,LOANIO17,LOANIO18,LOANIO19,LOANIO20,LOANIO21,LOANIO22,LOANIO23,LOANIO24,LOANIO25,LOANIO26,LOANIO27,LOANIO28,LOANIO29,LOANIO30,LOANIO31,LOANIO32,LOANIO33,LOANIO34,LOANIO35,LOANIO36,LOANIO37,LOANIO38,LOANIO39,LOANIO40,LOANIO41,LOANIO42,LOANIO43,LOANIO44,LOANIO45,LOANIO46,LOANIO47,LOANIO48,LOANIO49,LOANIO50,LOANIO51,LOANIO52,LOANIO53,LOANIO54,LOANIO55,LOANIO56,LOANIO57,LOANIO58,LOANIO59,LOANIO60,LOANIO61,LOANIO62,LOANIO63,LOANIO64,LOANIO65,LOANIO66
LOANIO_Enable | No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No
JAVA_CONFLICT_PIN | No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No
JAVA_GUI_PIN_LIST | EMACIO0,EMACIO1,EMACIO2,EMACIO3,EMACIO4,EMACIO5,EMACIO6,EMACIO7,EMACIO8,EMACIO9,EMACIO10,EMACIO11,EMACIO12,EMACIO13,MIXED1IO0,MIXED1IO1,MIXED1IO2,MIXED1IO3,MIXED1IO4,MIXED1IO5,MIXED1IO6,MIXED1IO7,MIXED1IO8,MIXED1IO9,MIXED1IO10,MIXED1IO11,MIXED1IO12,MIXED1IO13,MIXED1IO14,MIXED1IO15,MIXED1IO16,MIXED1IO17,MIXED1IO18,MIXED1IO19,MIXED1IO20,MIXED1IO21,FLASHIO0,FLASHIO1,FLASHIO2,FLASHIO3,FLASHIO4,FLASHIO5,FLASHIO6,FLASHIO7,FLASHIO8,FLASHIO9,FLASHIO10,FLASHIO11,GENERALIO0,GENERALIO1,GENERALIO2,GENERALIO3,GENERALIO4,GENERALIO5,GENERALIO6,GENERALIO7,GENERALIO8,GENERALIO9,GENERALIO10,GENERALIO11,GENERALIO12,GENERALIO13,GENERALIO14,GENERALIO15,GENERALIO16,GENERALIO17,GENERALIO18
JAVA_EMAC0_DATA | EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}
JAVA_EMAC1_DATA | EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}
JAVA_NAND_DATA | NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}
JAVA_QSPI_DATA | QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}
JAVA_SDIO_DATA | SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 CLK_IN CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} {SDMMC_FB_CLK(0:0) {} {}} {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}
JAVA_USB0_DATA | USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes SDR pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}
JAVA_USB1_DATA | USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes SDR pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes SDR pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}
JAVA_SPIM0_DATA | SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}
JAVA_SPIM1_DATA | SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}
JAVA_SPIS0_DATA | SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}
JAVA_SPIS1_DATA | SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}
JAVA_UART0_DATA | UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}
JAVA_UART1_DATA | UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}
JAVA_I2C0_DATA | I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}
JAVA_I2C1_DATA | I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}
JAVA_I2C2_DATA | I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}
JAVA_I2C3_DATA | I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}
JAVA_CAN0_DATA | CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}
JAVA_CAN1_DATA | CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}
JAVA_TRACE_DATA | TRACE {signals_by_mode {HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes HPS pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}
S2FCLK_USER0CLK_Enable | false
S2FCLK_USER0CLK_FREQ | 100
S2FCLK_USER1CLK_Enable | false
S2FCLK_USER1CLK_FREQ | 100
S2FCLK_USER2CLK_Enable | false
S2FCLK_USER2CLK_FREQ | 100
F2SCLK_PERIPHCLK_Enable | false
F2SCLK_PERIPHCLK_FREQ | 100
F2SCLK_SDRAMCLK_Enable | false
F2SCLK_SDRAMCLK_FREQ | 100
F2H_AXI_CLOCK_FREQ | 50000000
H2F_AXI_CLOCK_FREQ | 50000000
H2F_LW_AXI_CLOCK_FREQ | 50000000
F2H_SDRAM0_CLOCK_FREQ | 100
F2H_SDRAM1_CLOCK_FREQ | 100
F2H_SDRAM2_CLOCK_FREQ | 100
F2H_SDRAM3_CLOCK_FREQ | 100
F2H_SDRAM4_CLOCK_FREQ | 100
F2H_SDRAM5_CLOCK_FREQ | 100
H2F_CTI_CLOCK_FREQ | 100
H2F_TPIU_CLOCK_IN_FREQ | 100
H2F_DEBUG_APB_CLOCK_FREQ | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDIO_CLK_IN | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK | 100
FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN | 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK | 100
hps_device_family | Cyclone V
device_name | 5CSXFC6D6F31C8ES
quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces | false
quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface | false
quartus_ini_hps_ip_enable_test_interface | false
quartus_ini_hps_ip_fast_f2sdram_sim_model | false
quartus_ini_hps_ip_suppress_sdram_synth | false
quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces | false
quartus_ini_hps_ip_enable_bsel_csel | false
quartus_ini_hps_ip_f2sdram_bonding_out | false
test_iface_definition | DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output
DB_periph_ifaces | USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output} @orderednames {sdio sdio_reset sdio_clk_in sdio_cclk} sdio_clk_in {@no_export 0 properties {} type clock direction Input}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}
DB_iface_ports | can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} sdio_clk_in {sdmmc_clk_in {atom_signal_name clk_in direction Input role clk} @orderednames sdmmc_clk_in} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}
DB_port_pins | i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} sdmmc_clk_in {0 clk_in} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}
DB_bfm_types |
pin_muxing | {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes SDR pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 CLK_IN CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} {SDMMC_FB_CLK(0:0) {} {}} {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes HPS pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes SDR pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes SDR pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 SDMMC_FB_CLK_IN SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}
pin_muxing_check | Cyclone V+5CSXFC6D6F31C8ES
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_fpga_interfaces

altera_interface_generator v13.1.1

## Parameters
AC_ROM_MR0 |
AC_ROM_MR0_MIRR |
AC_ROM_MR0_CALIB |
AC_ROM_MR0_DLL_RESET |
AC_ROM_MR0_DLL_RESET_MIRR |
AC_ROM_MR1 |
AC_ROM_MR1_MIRR |
AC_ROM_MR1_CALIB |
AC_ROM_MR1_OCD_ENABLE |
AC_ROM_MR2 |
AC_ROM_MR2_MIRR |
AC_ROM_MR3 |
AC_ROM_MR3_MIRR |
USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY | false
MR0_BL | 2
MR0_BT | 0
MR0_CAS_LATENCY | 3
MR0_DLL | 1
MR0_WR | 4
MR0_PD | 0
MR1_DLL | 0
MR1_ODS | 1
MR1_RTT | 1
MR1_AL | 0
MR1_WL | 0
MR1_TDQS | 0
MR1_QOFF | 0
MR1_DQS | 0
MR1_RDQS | 0
MR2_CWL | 1
MR2_ASR | 0
MR2_SRT | 0
MR2_SRF | 0
MR2_RTT_WR | 1
MR3_MPR_RF | 0
MR3_MPR | 0
MR3_MPR_AA | 0
MR1_BL | 2
MR1_BT | 0
MR1_WC | 0
MR1_WR | 1
MR2_RLWL | 1
MR3_DS | 2
MR1_DS | 0
MR1_PASR | 0
MEM_IF_READ_DQS_WIDTH | 0
MEM_IF_WRITE_DQS_WIDTH | 0
SCC_DATA_WIDTH | 0
MEM_IF_ADDR_WIDTH | 0
MEM_IF_ADDR_WIDTH_MIN | 10
MEM_IF_ROW_ADDR_WIDTH | 0
MEM_IF_COL_ADDR_WIDTH | 0
MEM_IF_DM_WIDTH | 0
MEM_IF_CS_PER_RANK | 0
MEM_IF_NUMBER_OF_RANKS | 0
MEM_IF_CS_PER_DIMM | 0
MEM_IF_CONTROL_WIDTH | 0
MEM_BURST_LENGTH | 8
MEM_LEVELING | true
MEM_IF_DQS_WIDTH | 0
MEM_IF_CS_WIDTH | 0
MEM_IF_CHIP_BITS | -1
MEM_IF_BANKADDR_WIDTH | 0
MEM_IF_DQ_WIDTH | 0
MEM_IF_CK_WIDTH | 0
MEM_IF_CLK_EN_WIDTH | 0
MEM_IF_CLK_PAIR_COUNT | 1
DEVICE_WIDTH | 1
MEM_CLK_MAX_NS | 2.5
MEM_CLK_MAX_PS | 2500.0
MEM_TRC | 0
MEM_TRAS | 0
MEM_TRCD | 0
MEM_TRP | 0
MEM_TREFI | 0
MEM_TRFC | 0
CFG_TCCD | 0
MEM_TWR | 0
MEM_TFAW | 0
MEM_TRRD | 0
MEM_TRTP | 0
MEM_DQS_TO_CLK_CAPTURE_DELAY | 0
MEM_CLK_TO_DQS_CAPTURE_DELAY | 0
MEM_IF_ODT_WIDTH | 0
MEM_WTCL_INT | 6
FLY_BY | true
RDIMM | false
LRDIMM | false
RDIMM_INT | 0
LRDIMM_INT | 0
MEM_IF_RD_TO_WR_TURNAROUND_OCT | 0
MEM_IF_WR_TO_RD_TURNAROUND_OCT | 3
CTL_RD_TO_PCH_EXTRA_CLK | 0
CTL_RD_TO_RD_EXTRA_CLK | 0
CTL_WR_TO_WR_EXTRA_CLK | 0
CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK | 0
CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK | 0
MEM_TYPE |
MEM_MIRROR_ADDRESSING_DEC | 0
MEM_ATCL_INT | 0
MEM_REGDIMM_ENABLED | false
MEM_LRDIMM_ENABLED | false
MEM_VENDOR | Micron
MEM_FORMAT | DISCRETE
AC_PARITY | false
RDIMM_CONFIG | 0000000000000000
LRDIMM_EXTENDED_CONFIG | 0x000000000000000000
DISCRETE_FLY_BY | true
DEVICE_DEPTH | 1
MEM_MIRROR_ADDRESSING | 0
MEM_CLK_FREQ_MAX | 800.0
MEM_ROW_ADDR_WIDTH | 15
MEM_COL_ADDR_WIDTH | 10
MEM_DQ_WIDTH | 32
MEM_DQ_PER_DQS | 8
MEM_BANKADDR_WIDTH | 3
MEM_IF_DM_PINS_EN | true
MEM_IF_DQSN_EN | true
MEM_NUMBER_OF_DIMMS | 1
MEM_NUMBER_OF_RANKS_PER_DIMM | 1
MEM_NUMBER_OF_RANKS_PER_DEVICE | 1
MEM_RANK_MULTIPLICATION_FACTOR | 1
MEM_CK_WIDTH | 1
MEM_CS_WIDTH | 1
MEM_CLK_EN_WIDTH | 1
ALTMEMPHY_COMPATIBLE_MODE | false
NEXTGEN | true
MEM_IF_BOARD_BASE_DELAY | 10
MEM_IF_SIM_VALID_WINDOW | 0
MEM_GUARANTEED_WRITE_INIT | false
MEM_VERBOSE | true
PINGPONGPHY_EN | false
REFRESH_BURST_VALIDATION | false
MEM_BL | OTF
MEM_BT | Sequential
MEM_ASR | Manual
MEM_SRT | Normal
MEM_PD | DLL off
MEM_DRV_STR | RZQ/7
MEM_DLL_EN | true
MEM_RTT_NOM | RZQ/4
MEM_RTT_WR | RZQ/4
MEM_WTCL | 8
MEM_ATCL | Disabled
MEM_TCL | 11
MEM_AUTO_LEVELING_MODE | true
MEM_USER_LEVELING_MODE | Leveling
MEM_INIT_EN | false
MEM_INIT_FILE |
DAT_DATA_WIDTH | 32
TIMING_TIS | 180
TIMING_TIH | 140
TIMING_TDS | 30
TIMING_TDH | 65
TIMING_TDQSQ | 125
TIMING_TQHS | 300
TIMING_TQH | 0.38
TIMING_TDQSCK | 255
TIMING_TDQSCKDS | 450
TIMING_TDQSCKDM | 900
TIMING_TDQSCKDL | 1200
TIMING_TDQSS | 0.25
TIMING_TDQSH | 0.35
TIMING_TQSH | 0.4
TIMING_TDSH | 0.2
TIMING_TDSS | 0.2
MEM_TINIT_US | 500
MEM_TINIT_CK | 499
MEM_TDQSCK | 2
MEM_TMRD_CK | 4
MEM_TRAS_NS | 35.0
MEM_TRCD_NS | 13.75
MEM_TRP_NS | 13.75
MEM_TREFI_US | 7.8
MEM_TRFC_NS | 260.0
CFG_TCCD_NS | 2.5
MEM_TWR_NS | 15.0
MEM_TWTR | 4
MEM_TFAW_NS | 30.0
MEM_TRRD_NS | 7.5
MEM_TRTP_NS | 7.5
EXPORT_CSR_PORT | false
CSR_ADDR_WIDTH | 8
CSR_DATA_WIDTH | 32
CSR_BE_WIDTH | 4
CTL_CS_WIDTH | 0
AVL_ADDR_WIDTH | 0
AVL_BE_WIDTH | 0
AVL_DATA_WIDTH | 0
AVL_SYMBOL_WIDTH | 8
AVL_NUM_SYMBOLS | 2
AVL_SIZE_WIDTH | 0
HR_DDIO_OUT_HAS_THREE_REGS | false
CTL_ECC_CSR_ENABLED | false
DWIDTH_RATIO | 4
CTL_ODT_ENABLED | false
CTL_OUTPUT_REGD | false
CTL_ECC_MULTIPLES_40_72 | 0
CTL_ECC_MULTIPLES_16_24_40_72 | 0
CTL_REGDIMM_ENABLED | false
LOW_LATENCY | false
CONTROLLER_TYPE | nextgen_v110
CTL_TBP_NUM | 4
CTL_USR_REFRESH | 0
CTL_SELF_REFRESH | 0
CFG_TYPE | 0
CFG_INTERFACE_WIDTH | 0
CFG_BURST_LENGTH | 0
CFG_ADDR_ORDER | 0
CFG_PDN_EXIT_CYCLES | 0
CFG_POWER_SAVING_EXIT_CYCLES | 0
CFG_MEM_CLK_ENTRY_CYCLES | 0
CFG_SELF_RFSH_EXIT_CYCLES | 0
CFG_PORT_WIDTH_WRITE_ODT_CHIP | 0
CFG_PORT_WIDTH_READ_ODT_CHIP | 0
CFG_WRITE_ODT_CHIP | 0
CFG_READ_ODT_CHIP | 0
LOCAL_CS_WIDTH | 0
CFG_CLR_INTR | 0
CFG_ENABLE_NO_DM | 0
MEM_ADD_LAT | 0
CTL_ENABLE_BURST_INTERRUPT_INT | false
CTL_ENABLE_BURST_TERMINATE_INT | false
CFG_ERRCMD_FIFO_REG | 0
CFG_ECC_DECODER_REG | 0
CTL_ENABLE_WDATA_PATH_LATENCY | false
CFG_STARVE_LIMIT | 0
MEM_AUTO_PD_CYCLES | 0
AVL_PORT |
AVL_DATA_WIDTH_PORT_0 | 0
AVL_ADDR_WIDTH_PORT_0 | 0
PRIORITY_PORT_0 | 0
WEIGHT_PORT_0 | 0
CPORT_TYPE_PORT_0 | 0
AVL_NUM_SYMBOLS_PORT_0 | 2
LSB_WFIFO_PORT_0 | 5
MSB_WFIFO_PORT_0 | 5
LSB_RFIFO_PORT_0 | 5
MSB_RFIFO_PORT_0 | 5
AVL_DATA_WIDTH_PORT_1 | 0
AVL_ADDR_WIDTH_PORT_1 | 0
PRIORITY_PORT_1 | 0
WEIGHT_PORT_1 | 0
CPORT_TYPE_PORT_1 | 0
AVL_NUM_SYMBOLS_PORT_1 | 2
LSB_WFIFO_PORT_1 | 5
MSB_WFIFO_PORT_1 | 5
LSB_RFIFO_PORT_1 | 5
MSB_RFIFO_PORT_1 | 5
AVL_DATA_WIDTH_PORT_2 | 0
AVL_ADDR_WIDTH_PORT_2 | 0
PRIORITY_PORT_2 | 0
WEIGHT_PORT_2 | 0
CPORT_TYPE_PORT_2 | 0
AVL_NUM_SYMBOLS_PORT_2 | 2
LSB_WFIFO_PORT_2 | 5
MSB_WFIFO_PORT_2 | 5
LSB_RFIFO_PORT_2 | 5
MSB_RFIFO_PORT_2 | 5
AVL_DATA_WIDTH_PORT_3 | 0
AVL_ADDR_WIDTH_PORT_3 | 0
PRIORITY_PORT_3 | 0
WEIGHT_PORT_3 | 0
CPORT_TYPE_PORT_3 | 0
AVL_NUM_SYMBOLS_PORT_3 | 2
LSB_WFIFO_PORT_3 | 5
MSB_WFIFO_PORT_3 | 5
LSB_RFIFO_PORT_3 | 5
MSB_RFIFO_PORT_3 | 5
AVL_DATA_WIDTH_PORT_4 | 0
AVL_ADDR_WIDTH_PORT_4 | 0
PRIORITY_PORT_4 | 0
WEIGHT_PORT_4 | 0
CPORT_TYPE_PORT_4 | 0
AVL_NUM_SYMBOLS_PORT_4 | 2
LSB_WFIFO_PORT_4 | 5
MSB_WFIFO_PORT_4 | 5
LSB_RFIFO_PORT_4 | 5
MSB_RFIFO_PORT_4 | 5
AVL_DATA_WIDTH_PORT_5 | 0
AVL_ADDR_WIDTH_PORT_5 | 0
PRIORITY_PORT_5 | 0
WEIGHT_PORT_5 | 0
CPORT_TYPE_PORT_5 | 0
AVL_NUM_SYMBOLS_PORT_5 | 2
LSB_WFIFO_PORT_5 | 5
MSB_WFIFO_PORT_5 | 5
LSB_RFIFO_PORT_5 | 5
MSB_RFIFO_PORT_5 | 5
ALLOCATED_RFIFO_PORT | 0,None,None,None,None,None
ALLOCATED_WFIFO_PORT | 0,None,None,None,None,None
ENUM_ATTR_COUNTER_ONE_RESET | DISABLED
ENUM_ATTR_COUNTER_ZERO_RESET | DISABLED
ENUM_ATTR_STATIC_CONFIG_VALID | DISABLED
ENUM_AUTO_PCH_ENABLE_0 | DISABLED
ENUM_AUTO_PCH_ENABLE_1 | DISABLED
ENUM_AUTO_PCH_ENABLE_2 | DISABLED
ENUM_AUTO_PCH_ENABLE_3 | DISABLED
ENUM_AUTO_PCH_ENABLE_4 | DISABLED
ENUM_AUTO_PCH_ENABLE_5 | DISABLED
ENUM_CAL_REQ | DISABLED
ENUM_CFG_BURST_LENGTH | BL_8
ENUM_CFG_INTERFACE_WIDTH | DWIDTH_32
ENUM_CFG_SELF_RFSH_EXIT_CYCLES |
ENUM_CFG_STARVE_LIMIT | STARVE_LIMIT_32
ENUM_CFG_TYPE | DDR3
ENUM_CLOCK_OFF_0 | DISABLED
ENUM_CLOCK_OFF_1 | DISABLED
ENUM_CLOCK_OFF_2 | DISABLED
ENUM_CLOCK_OFF_3 | DISABLED
ENUM_CLOCK_OFF_4 | DISABLED
ENUM_CLOCK_OFF_5 | DISABLED
ENUM_CLR_INTR | NO_CLR_INTR
ENUM_CMD_PORT_IN_USE_0 | FALSE
ENUM_CMD_PORT_IN_USE_1 | FALSE
ENUM_CMD_PORT_IN_USE_2 | FALSE
ENUM_CMD_PORT_IN_USE_3 | FALSE
ENUM_CMD_PORT_IN_USE_4 | FALSE
ENUM_CMD_PORT_IN_USE_5 | FALSE
ENUM_CPORT0_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT0_RFIFO_MAP | FIFO_0
ENUM_CPORT0_TYPE | DISABLE
ENUM_CPORT0_WFIFO_MAP | FIFO_0
ENUM_CPORT1_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT1_RFIFO_MAP | FIFO_0
ENUM_CPORT1_TYPE | DISABLE
ENUM_CPORT1_WFIFO_MAP | FIFO_0
ENUM_CPORT2_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT2_RFIFO_MAP | FIFO_0
ENUM_CPORT2_TYPE | DISABLE
ENUM_CPORT2_WFIFO_MAP | FIFO_0
ENUM_CPORT3_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT3_RFIFO_MAP | FIFO_0
ENUM_CPORT3_TYPE | DISABLE
ENUM_CPORT3_WFIFO_MAP | FIFO_0
ENUM_CPORT4_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT4_RFIFO_MAP | FIFO_0
ENUM_CPORT4_TYPE | DISABLE
ENUM_CPORT4_WFIFO_MAP | FIFO_0
ENUM_CPORT5_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT5_RFIFO_MAP | FIFO_0
ENUM_CPORT5_TYPE | DISABLE
ENUM_CPORT5_WFIFO_MAP | FIFO_0
ENUM_CTL_ADDR_ORDER | CHIP_BANK_ROW_COL
ENUM_CTL_ECC_ENABLED | CTL_ECC_DISABLED
ENUM_CTL_ECC_RMW_ENABLED | CTL_ECC_RMW_DISABLED
ENUM_CTL_REGDIMM_ENABLED | REGDIMM_DISABLED
ENUM_CTL_USR_REFRESH | CTL_USR_REFRESH_DISABLED
ENUM_CTRL_WIDTH | DATA_WIDTH_64_BIT
ENUM_DELAY_BONDING | BONDING_LATENCY_0
ENUM_DFX_BYPASS_ENABLE | DFX_BYPASS_DISABLED
ENUM_DISABLE_MERGING | MERGING_ENABLED
ENUM_ECC_DQ_WIDTH | ECC_DQ_WIDTH_0
ENUM_ENABLE_ATPG | DISABLED
ENUM_ENABLE_BONDING_0 | DISABLED
ENUM_ENABLE_BONDING_1 | DISABLED
ENUM_ENABLE_BONDING_2 | DISABLED
ENUM_ENABLE_BONDING_3 | DISABLED
ENUM_ENABLE_BONDING_4 | DISABLED
ENUM_ENABLE_BONDING_5 | DISABLED
ENUM_ENABLE_BONDING_WRAPBACK | DISABLED
ENUM_ENABLE_DQS_TRACKING | DISABLED
ENUM_ENABLE_ECC_CODE_OVERWRITES | DISABLED
ENUM_ENABLE_FAST_EXIT_PPD | DISABLED
ENUM_ENABLE_INTR | DISABLED
ENUM_ENABLE_NO_DM | DISABLED
ENUM_ENABLE_PIPELINEGLOBAL | DISABLED
ENUM_GANGED_ARF | DISABLED
ENUM_GEN_DBE | GEN_DBE_DISABLED
ENUM_GEN_SBE | GEN_SBE_DISABLED
ENUM_INC_SYNC | FIFO_SET_2
ENUM_LOCAL_IF_CS_WIDTH | ADDR_WIDTH_2
ENUM_MASK_CORR_DROPPED_INTR | DISABLED
ENUM_MASK_DBE_INTR | DISABLED
ENUM_MASK_SBE_INTR | DISABLED
ENUM_MEM_IF_AL | AL_0
ENUM_MEM_IF_BANKADDR_WIDTH | ADDR_WIDTH_3
ENUM_MEM_IF_BURSTLENGTH | MEM_IF_BURSTLENGTH_8
ENUM_MEM_IF_COLADDR_WIDTH | ADDR_WIDTH_12
ENUM_MEM_IF_CS_PER_RANK | MEM_IF_CS_PER_RANK_1
ENUM_MEM_IF_CS_WIDTH | MEM_IF_CS_WIDTH_1
ENUM_MEM_IF_DQ_PER_CHIP | MEM_IF_DQ_PER_CHIP_8
ENUM_MEM_IF_DQS_WIDTH | DQS_WIDTH_4
ENUM_MEM_IF_DWIDTH | MEM_IF_DWIDTH_32
ENUM_MEM_IF_MEMTYPE | DDR3_SDRAM
ENUM_MEM_IF_ROWADDR_WIDTH | ADDR_WIDTH_16
ENUM_MEM_IF_SPEEDBIN | DDR3_1066_6_6_6
ENUM_MEM_IF_TCCD | TCCD_4
ENUM_MEM_IF_TCL | TCL_6
ENUM_MEM_IF_TCWL | TCWL_5
ENUM_MEM_IF_TFAW | TFAW_16
ENUM_MEM_IF_TMRD |
ENUM_MEM_IF_TRAS | TRAS_16
ENUM_MEM_IF_TRC | TRC_22
ENUM_MEM_IF_TRCD | TRCD_6
ENUM_MEM_IF_TRP | TRP_6
ENUM_MEM_IF_TRRD | TRRD_4
ENUM_MEM_IF_TRTP | TRTP_4
ENUM_MEM_IF_TWR | TWR_6
ENUM_MEM_IF_TWTR | TWTR_4
ENUM_MMR_CFG_MEM_BL | MP_BL_8
ENUM_OUTPUT_REGD | DISABLED
ENUM_PDN_EXIT_CYCLES | SLOW_EXIT
ENUM_PORT0_WIDTH | PORT_64_BIT
ENUM_PORT1_WIDTH | PORT_64_BIT
ENUM_PORT2_WIDTH | PORT_64_BIT
ENUM_PORT3_WIDTH | PORT_64_BIT
ENUM_PORT4_WIDTH | PORT_64_BIT
ENUM_PORT5_WIDTH | PORT_64_BIT
ENUM_PRIORITY_0_0 | WEIGHT_0
ENUM_PRIORITY_0_1 | WEIGHT_0
ENUM_PRIORITY_0_2 | WEIGHT_0
ENUM_PRIORITY_0_3 | WEIGHT_0
ENUM_PRIORITY_0_4 | WEIGHT_0
ENUM_PRIORITY_0_5 | WEIGHT_0
ENUM_PRIORITY_1_0 | WEIGHT_0
ENUM_PRIORITY_1_1 | WEIGHT_0
ENUM_PRIORITY_1_2 | WEIGHT_0
ENUM_PRIORITY_1_3 | WEIGHT_0
ENUM_PRIORITY_1_4 | WEIGHT_0
ENUM_PRIORITY_1_5 | WEIGHT_0
ENUM_PRIORITY_2_0 | WEIGHT_0
ENUM_PRIORITY_2_1 | WEIGHT_0
ENUM_PRIORITY_2_2 | WEIGHT_0
ENUM_PRIORITY_2_3 | WEIGHT_0
ENUM_PRIORITY_2_4 | WEIGHT_0
ENUM_PRIORITY_2_5 | WEIGHT_0
ENUM_PRIORITY_3_0 | WEIGHT_0
ENUM_PRIORITY_3_1 | WEIGHT_0
ENUM_PRIORITY_3_2 | WEIGHT_0
ENUM_PRIORITY_3_3 | WEIGHT_0
ENUM_PRIORITY_3_4 | WEIGHT_0
ENUM_PRIORITY_3_5 | WEIGHT_0
ENUM_PRIORITY_4_0 | WEIGHT_0
ENUM_PRIORITY_4_1 | WEIGHT_0
ENUM_PRIORITY_4_2 | WEIGHT_0
ENUM_PRIORITY_4_3 | WEIGHT_0
ENUM_PRIORITY_4_4 | WEIGHT_0
ENUM_PRIORITY_4_5 | WEIGHT_0
ENUM_PRIORITY_5_0 | WEIGHT_0
ENUM_PRIORITY_5_1 | WEIGHT_0
ENUM_PRIORITY_5_2 | WEIGHT_0
ENUM_PRIORITY_5_3 | WEIGHT_0
ENUM_PRIORITY_5_4 | WEIGHT_0
ENUM_PRIORITY_5_5 | WEIGHT_0
ENUM_PRIORITY_6_0 | WEIGHT_0
ENUM_PRIORITY_6_1 | WEIGHT_0
ENUM_PRIORITY_6_2 | WEIGHT_0
ENUM_PRIORITY_6_3 | WEIGHT_0
ENUM_PRIORITY_6_4 | WEIGHT_0
ENUM_PRIORITY_6_5 | WEIGHT_0
ENUM_PRIORITY_7_0 | WEIGHT_0
ENUM_PRIORITY_7_1 | WEIGHT_0
ENUM_PRIORITY_7_2 | WEIGHT_0
ENUM_PRIORITY_7_3 | WEIGHT_0
ENUM_PRIORITY_7_4 | WEIGHT_0
ENUM_PRIORITY_7_5 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_0 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_1 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_2 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_3 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_4 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_5 | WEIGHT_0
ENUM_RCFG_USER_PRIORITY_0 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_1 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_2 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_3 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_4 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_5 | PRIORITY_0
ENUM_RD_DWIDTH_0 | DWIDTH_0
ENUM_RD_DWIDTH_1 | DWIDTH_0
ENUM_RD_DWIDTH_2 | DWIDTH_0
ENUM_RD_DWIDTH_3 | DWIDTH_0
ENUM_RD_DWIDTH_4 | DWIDTH_0
ENUM_RD_DWIDTH_5 | DWIDTH_0
ENUM_RD_FIFO_IN_USE_0 | FALSE
ENUM_RD_FIFO_IN_USE_1 | FALSE
ENUM_RD_FIFO_IN_USE_2 | FALSE
ENUM_RD_FIFO_IN_USE_3 | FALSE
ENUM_RD_PORT_INFO_0 | USE_NO
ENUM_RD_PORT_INFO_1 | USE_NO
ENUM_RD_PORT_INFO_2 | USE_NO
ENUM_RD_PORT_INFO_3 | USE_NO
ENUM_RD_PORT_INFO_4 | USE_NO
ENUM_RD_PORT_INFO_5 | USE_NO
ENUM_READ_ODT_CHIP | ODT_DISABLED
ENUM_REORDER_DATA | DATA_REORDERING
ENUM_RFIFO0_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO1_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO2_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO3_CPORT_MAP | CMD_PORT_0
ENUM_SINGLE_READY_0 | CONCATENATE_RDY
ENUM_SINGLE_READY_1 | CONCATENATE_RDY
ENUM_SINGLE_READY_2 | CONCATENATE_RDY
ENUM_SINGLE_READY_3 | CONCATENATE_RDY
ENUM_STATIC_WEIGHT_0 | WEIGHT_0
ENUM_STATIC_WEIGHT_1 | WEIGHT_0
ENUM_STATIC_WEIGHT_2 | WEIGHT_0
ENUM_STATIC_WEIGHT_3 | WEIGHT_0
ENUM_STATIC_WEIGHT_4 | WEIGHT_0
ENUM_STATIC_WEIGHT_5 | WEIGHT_0
ENUM_SYNC_MODE_0 | ASYNCHRONOUS
ENUM_SYNC_MODE_1 | ASYNCHRONOUS
ENUM_SYNC_MODE_2 | ASYNCHRONOUS
ENUM_SYNC_MODE_3 | ASYNCHRONOUS
ENUM_SYNC_MODE_4 | ASYNCHRONOUS
ENUM_SYNC_MODE_5 | ASYNCHRONOUS
ENUM_TEST_MODE | NORMAL_MODE
ENUM_THLD_JAR1_0 | THRESHOLD_32
ENUM_THLD_JAR1_1 | THRESHOLD_32
ENUM_THLD_JAR1_2 | THRESHOLD_32
ENUM_THLD_JAR1_3 | THRESHOLD_32
ENUM_THLD_JAR1_4 | THRESHOLD_32
ENUM_THLD_JAR1_5 | THRESHOLD_32
ENUM_THLD_JAR2_0 | THRESHOLD_16
ENUM_THLD_JAR2_1 | THRESHOLD_16
ENUM_THLD_JAR2_2 | THRESHOLD_16
ENUM_THLD_JAR2_3 | THRESHOLD_16
ENUM_THLD_JAR2_4 | THRESHOLD_16
ENUM_THLD_JAR2_5 | THRESHOLD_16
ENUM_USE_ALMOST_EMPTY_0 | EMPTY
ENUM_USE_ALMOST_EMPTY_1 | EMPTY
ENUM_USE_ALMOST_EMPTY_2 | EMPTY
ENUM_USE_ALMOST_EMPTY_3 | EMPTY
ENUM_USER_ECC_EN | DISABLE
ENUM_USER_PRIORITY_0 | PRIORITY_0
ENUM_USER_PRIORITY_1 | PRIORITY_0
ENUM_USER_PRIORITY_2 | PRIORITY_0
ENUM_USER_PRIORITY_3 | PRIORITY_0
ENUM_USER_PRIORITY_4 | PRIORITY_0
ENUM_USER_PRIORITY_5 | PRIORITY_0
ENUM_WFIFO0_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO0_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO1_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO1_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO2_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO2_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO3_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO3_RDY_ALMOST_FULL | NOT_FULL
ENUM_WR_DWIDTH_0 | DWIDTH_0
ENUM_WR_DWIDTH_1 | DWIDTH_0
ENUM_WR_DWIDTH_2 | DWIDTH_0
ENUM_WR_DWIDTH_3 | DWIDTH_0
ENUM_WR_DWIDTH_4 | DWIDTH_0
ENUM_WR_DWIDTH_5 | DWIDTH_0
ENUM_WR_FIFO_IN_USE_0 | FALSE
ENUM_WR_FIFO_IN_USE_1 | FALSE
ENUM_WR_FIFO_IN_USE_2 | FALSE
ENUM_WR_FIFO_IN_USE_3 | FALSE
ENUM_WR_PORT_INFO_0 | USE_NO
ENUM_WR_PORT_INFO_1 | USE_NO
ENUM_WR_PORT_INFO_2 | USE_NO
ENUM_WR_PORT_INFO_3 | USE_NO
ENUM_WR_PORT_INFO_4 | USE_NO
ENUM_WR_PORT_INFO_5 | USE_NO
ENUM_WRITE_ODT_CHIP | ODT_DISABLED
INTG_MEM_AUTO_PD_CYCLES | 0
INTG_CYC_TO_RLD_JARS_0 | 1
INTG_CYC_TO_RLD_JARS_1 | 1
INTG_CYC_TO_RLD_JARS_2 | 1
INTG_CYC_TO_RLD_JARS_3 | 1
INTG_CYC_TO_RLD_JARS_4 | 1
INTG_CYC_TO_RLD_JARS_5 | 1
INTG_EXTRA_CTL_CLK_ACT_TO_ACT | 0
INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK | 0
INTG_EXTRA_CTL_CLK_ACT_TO_PCH | 0
INTG_EXTRA_CTL_CLK_ACT_TO_RDWR | 0
INTG_EXTRA_CTL_CLK_ARF_PERIOD | 0
INTG_EXTRA_CTL_CLK_ARF_TO_VALID | 0
INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT | 0
INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID | 0
INTG_EXTRA_CTL_CLK_PCH_TO_VALID | 0
INTG_EXTRA_CTL_CLK_PDN_PERIOD | 0
INTG_EXTRA_CTL_CLK_PDN_TO_VALID | 0
INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID | 0
INTG_EXTRA_CTL_CLK_RD_TO_PCH | 0
INTG_EXTRA_CTL_CLK_RD_TO_RD | 0
INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP | 0
INTG_EXTRA_CTL_CLK_RD_TO_WR | 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_BC | 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP | 0
INTG_EXTRA_CTL_CLK_SRF_TO_VALID | 0
INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL | 0
INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID | 0
INTG_EXTRA_CTL_CLK_WR_TO_PCH | 0
INTG_EXTRA_CTL_CLK_WR_TO_RD | 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_BC | 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP | 0
INTG_EXTRA_CTL_CLK_WR_TO_WR | 0
INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP | 0
INTG_MEM_IF_TREFI | 3120
INTG_MEM_IF_TRFC | 34
INTG_RCFG_SUM_WT_PRIORITY_0 | 0
INTG_RCFG_SUM_WT_PRIORITY_1 | 0
INTG_RCFG_SUM_WT_PRIORITY_2 | 0
INTG_RCFG_SUM_WT_PRIORITY_3 | 0
INTG_RCFG_SUM_WT_PRIORITY_4 | 0
INTG_RCFG_SUM_WT_PRIORITY_5 | 0
INTG_RCFG_SUM_WT_PRIORITY_6 | 0
INTG_RCFG_SUM_WT_PRIORITY_7 | 0
INTG_SUM_WT_PRIORITY_0 | 0
INTG_SUM_WT_PRIORITY_1 | 0
INTG_SUM_WT_PRIORITY_2 | 0
INTG_SUM_WT_PRIORITY_3 | 0
INTG_SUM_WT_PRIORITY_4 | 0
INTG_SUM_WT_PRIORITY_5 | 0
INTG_SUM_WT_PRIORITY_6 | 0
INTG_SUM_WT_PRIORITY_7 | 0
VECT_ATTR_COUNTER_ONE_MASK | 0
VECT_ATTR_COUNTER_ONE_MATCH | 0
VECT_ATTR_COUNTER_ZERO_MASK | 0
VECT_ATTR_COUNTER_ZERO_MATCH | 0
VECT_ATTR_DEBUG_SELECT_BYTE | 0
INTG_POWER_SAVING_EXIT_CYCLES | 5
INTG_MEM_CLK_ENTRY_CYCLES | 10
ENUM_ENABLE_BURST_INTERRUPT | DISABLED
ENUM_ENABLE_BURST_TERMINATE | DISABLED
AV_PORT_0_CONNECT_TO_CV_PORT | 0
CV_PORT_0_CONNECT_TO_AV_PORT | 0
CV_AVL_DATA_WIDTH_PORT_0 | 0
CV_AVL_ADDR_WIDTH_PORT_0 | 0
CV_CPORT_TYPE_PORT_0 | 0
CV_AVL_NUM_SYMBOLS_PORT_0 | 2
CV_LSB_WFIFO_PORT_0 | 5
CV_MSB_WFIFO_PORT_0 | 5
CV_LSB_RFIFO_PORT_0 | 5
CV_MSB_RFIFO_PORT_0 | 5
CV_ENUM_AUTO_PCH_ENABLE_0 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_0 | FALSE
CV_ENUM_CPORT0_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT0_TYPE | DISABLE
CV_ENUM_CPORT0_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_0 | DISABLED
CV_ENUM_PORT0_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_0 | WEIGHT_0
CV_ENUM_PRIORITY_1_0 | WEIGHT_0
CV_ENUM_PRIORITY_2_0 | WEIGHT_0
CV_ENUM_PRIORITY_3_0 | WEIGHT_0
CV_ENUM_PRIORITY_4_0 | WEIGHT_0
CV_ENUM_PRIORITY_5_0 | WEIGHT_0
CV_ENUM_PRIORITY_6_0 | WEIGHT_0
CV_ENUM_PRIORITY_7_0 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_0 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_0 | PRIORITY_0
CV_ENUM_RD_DWIDTH_0 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_0 | USE_NO
CV_ENUM_STATIC_WEIGHT_0 | WEIGHT_0
CV_ENUM_USER_PRIORITY_0 | PRIORITY_0
CV_ENUM_WR_DWIDTH_0 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_0 | USE_NO
TG_TEMP_PORT_0 | 0
AV_PORT_1_CONNECT_TO_CV_PORT | 1
CV_PORT_1_CONNECT_TO_AV_PORT | 1
CV_AVL_DATA_WIDTH_PORT_1 | 0
CV_AVL_ADDR_WIDTH_PORT_1 | 0
CV_CPORT_TYPE_PORT_1 | 0
CV_AVL_NUM_SYMBOLS_PORT_1 | 2
CV_LSB_WFIFO_PORT_1 | 5
CV_MSB_WFIFO_PORT_1 | 5
CV_LSB_RFIFO_PORT_1 | 5
CV_MSB_RFIFO_PORT_1 | 5
CV_ENUM_AUTO_PCH_ENABLE_1 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_1 | FALSE
CV_ENUM_CPORT1_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT1_TYPE | DISABLE
CV_ENUM_CPORT1_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_1 | DISABLED
CV_ENUM_PORT1_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_1 | WEIGHT_0
CV_ENUM_PRIORITY_1_1 | WEIGHT_0
CV_ENUM_PRIORITY_2_1 | WEIGHT_0
CV_ENUM_PRIORITY_3_1 | WEIGHT_0
CV_ENUM_PRIORITY_4_1 | WEIGHT_0
CV_ENUM_PRIORITY_5_1 | WEIGHT_0
CV_ENUM_PRIORITY_6_1 | WEIGHT_0
CV_ENUM_PRIORITY_7_1 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_1 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_1 | PRIORITY_0
CV_ENUM_RD_DWIDTH_1 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_1 | USE_NO
CV_ENUM_STATIC_WEIGHT_1 | WEIGHT_0
CV_ENUM_USER_PRIORITY_1 | PRIORITY_0
CV_ENUM_WR_DWIDTH_1 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_1 | USE_NO
TG_TEMP_PORT_1 | 0
AV_PORT_2_CONNECT_TO_CV_PORT | 2
CV_PORT_2_CONNECT_TO_AV_PORT | 2
CV_AVL_DATA_WIDTH_PORT_2 | 0
CV_AVL_ADDR_WIDTH_PORT_2 | 0
CV_CPORT_TYPE_PORT_2 | 0
CV_AVL_NUM_SYMBOLS_PORT_2 | 2
CV_LSB_WFIFO_PORT_2 | 5
CV_MSB_WFIFO_PORT_2 | 5
CV_LSB_RFIFO_PORT_2 | 5
CV_MSB_RFIFO_PORT_2 | 5
CV_ENUM_AUTO_PCH_ENABLE_2 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_2 | FALSE
CV_ENUM_CPORT2_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT2_TYPE | DISABLE
CV_ENUM_CPORT2_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_2 | DISABLED
CV_ENUM_PORT2_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_2 | WEIGHT_0
CV_ENUM_PRIORITY_1_2 | WEIGHT_0
CV_ENUM_PRIORITY_2_2 | WEIGHT_0
CV_ENUM_PRIORITY_3_2 | WEIGHT_0
CV_ENUM_PRIORITY_4_2 | WEIGHT_0
CV_ENUM_PRIORITY_5_2 | WEIGHT_0
CV_ENUM_PRIORITY_6_2 | WEIGHT_0
CV_ENUM_PRIORITY_7_2 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_2 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_2 | PRIORITY_0
CV_ENUM_RD_DWIDTH_2 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_2 | USE_NO
CV_ENUM_STATIC_WEIGHT_2 | WEIGHT_0
CV_ENUM_USER_PRIORITY_2 | PRIORITY_0
CV_ENUM_WR_DWIDTH_2 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_2 | USE_NO
TG_TEMP_PORT_2 | 0
AV_PORT_3_CONNECT_TO_CV_PORT | 3
CV_PORT_3_CONNECT_TO_AV_PORT | 3
CV_AVL_DATA_WIDTH_PORT_3 | 0
CV_AVL_ADDR_WIDTH_PORT_3 | 0
CV_CPORT_TYPE_PORT_3 | 0
CV_AVL_NUM_SYMBOLS_PORT_3 | 2
CV_LSB_WFIFO_PORT_3 | 5
CV_MSB_WFIFO_PORT_3 | 5
CV_LSB_RFIFO_PORT_3 | 5
CV_MSB_RFIFO_PORT_3 | 5
CV_ENUM_AUTO_PCH_ENABLE_3 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_3 | FALSE
CV_ENUM_CPORT3_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT3_TYPE | DISABLE
CV_ENUM_CPORT3_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_3 | DISABLED
CV_ENUM_PORT3_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_3 | WEIGHT_0
CV_ENUM_PRIORITY_1_3 | WEIGHT_0
CV_ENUM_PRIORITY_2_3 | WEIGHT_0
CV_ENUM_PRIORITY_3_3 | WEIGHT_0
CV_ENUM_PRIORITY_4_3 | WEIGHT_0
CV_ENUM_PRIORITY_5_3 | WEIGHT_0
CV_ENUM_PRIORITY_6_3 | WEIGHT_0
CV_ENUM_PRIORITY_7_3 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_3 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_3 | PRIORITY_0
CV_ENUM_RD_DWIDTH_3 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_3 | USE_NO
CV_ENUM_STATIC_WEIGHT_3 | WEIGHT_0
CV_ENUM_USER_PRIORITY_3 | PRIORITY_0
CV_ENUM_WR_DWIDTH_3 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_3 | USE_NO
TG_TEMP_PORT_3 | 0
AV_PORT_4_CONNECT_TO_CV_PORT | 4
CV_PORT_4_CONNECT_TO_AV_PORT | 4
CV_AVL_DATA_WIDTH_PORT_4 | 0
CV_AVL_ADDR_WIDTH_PORT_4 | 0
CV_CPORT_TYPE_PORT_4 | 0
CV_AVL_NUM_SYMBOLS_PORT_4 | 2
CV_LSB_WFIFO_PORT_4 | 5
CV_MSB_WFIFO_PORT_4 | 5
CV_LSB_RFIFO_PORT_4 | 5
CV_MSB_RFIFO_PORT_4 | 5
CV_ENUM_AUTO_PCH_ENABLE_4 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_4 | FALSE
CV_ENUM_CPORT4_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT4_TYPE | DISABLE
CV_ENUM_CPORT4_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_4 | DISABLED
CV_ENUM_PORT4_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_4 | WEIGHT_0
CV_ENUM_PRIORITY_1_4 | WEIGHT_0
CV_ENUM_PRIORITY_2_4 | WEIGHT_0
CV_ENUM_PRIORITY_3_4 | WEIGHT_0
CV_ENUM_PRIORITY_4_4 | WEIGHT_0
CV_ENUM_PRIORITY_5_4 | WEIGHT_0
CV_ENUM_PRIORITY_6_4 | WEIGHT_0
CV_ENUM_PRIORITY_7_4 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_4 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_4 | PRIORITY_0
CV_ENUM_RD_DWIDTH_4 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_4 | USE_NO
CV_ENUM_STATIC_WEIGHT_4 | WEIGHT_0
CV_ENUM_USER_PRIORITY_4 | PRIORITY_0
CV_ENUM_WR_DWIDTH_4 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_4 | USE_NO
TG_TEMP_PORT_4 | 0
AV_PORT_5_CONNECT_TO_CV_PORT | 5
CV_PORT_5_CONNECT_TO_AV_PORT | 5
CV_AVL_DATA_WIDTH_PORT_5 | 0
CV_AVL_ADDR_WIDTH_PORT_5 | 0
CV_CPORT_TYPE_PORT_5 | 0
CV_AVL_NUM_SYMBOLS_PORT_5 | 2
CV_LSB_WFIFO_PORT_5 | 5
CV_MSB_WFIFO_PORT_5 | 5
CV_LSB_RFIFO_PORT_5 | 5
CV_MSB_RFIFO_PORT_5 | 5
CV_ENUM_AUTO_PCH_ENABLE_5 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_5 | FALSE
CV_ENUM_CPORT5_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT5_TYPE | DISABLE
CV_ENUM_CPORT5_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_5 | DISABLED
CV_ENUM_PORT5_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_5 | WEIGHT_0
CV_ENUM_PRIORITY_1_5 | WEIGHT_0
CV_ENUM_PRIORITY_2_5 | WEIGHT_0
CV_ENUM_PRIORITY_3_5 | WEIGHT_0
CV_ENUM_PRIORITY_4_5 | WEIGHT_0
CV_ENUM_PRIORITY_5_5 | WEIGHT_0
CV_ENUM_PRIORITY_6_5 | WEIGHT_0
CV_ENUM_PRIORITY_7_5 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_5 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_5 | PRIORITY_0
CV_ENUM_RD_DWIDTH_5 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_5 | USE_NO
CV_ENUM_STATIC_WEIGHT_5 | WEIGHT_0
CV_ENUM_USER_PRIORITY_5 | PRIORITY_0
CV_ENUM_WR_DWIDTH_5 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_5 | USE_NO
TG_TEMP_PORT_5 | 0
CV_ENUM_RFIFO0_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO0_CPORT_MAP | CMD_PORT_0
CV_ENUM_RFIFO1_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO1_CPORT_MAP | CMD_PORT_0
CV_ENUM_RFIFO2_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO2_CPORT_MAP | CMD_PORT_0
CV_ENUM_RFIFO3_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO3_CPORT_MAP | CMD_PORT_0
CV_INTG_RCFG_SUM_WT_PRIORITY_0 | 0
CV_INTG_SUM_WT_PRIORITY_0 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_1 | 0
CV_INTG_SUM_WT_PRIORITY_1 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_2 | 0
CV_INTG_SUM_WT_PRIORITY_2 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_3 | 0
CV_INTG_SUM_WT_PRIORITY_3 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_4 | 0
CV_INTG_SUM_WT_PRIORITY_4 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_5 | 0
CV_INTG_SUM_WT_PRIORITY_5 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_6 | 0
CV_INTG_SUM_WT_PRIORITY_6 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_7 | 0
CV_INTG_SUM_WT_PRIORITY_7 | 0
POWER_OF_TWO_BUS | false
SOPC_COMPAT_RESET | false
AVL_MAX_SIZE | 4
BYTE_ENABLE | true
ENABLE_CTRL_AVALON_INTERFACE | true
CTL_DEEP_POWERDN_EN | false
CTL_SELF_REFRESH_EN | false
AUTO_POWERDN_EN | false
AUTO_PD_CYCLES | 0
CTL_USR_REFRESH_EN | false
CTL_AUTOPCH_EN | false
CTL_ZQCAL_EN | false
ADDR_ORDER | 0
CTL_LOOK_AHEAD_DEPTH | 4
CONTROLLER_LATENCY | 5
CFG_REORDER_DATA | true
STARVE_LIMIT | 10
CTL_CSR_ENABLED | false
CTL_CSR_CONNECTION | INTERNAL_JTAG
CTL_ECC_ENABLED | false
CTL_HRB_ENABLED | false
CTL_ECC_AUTO_CORRECTION_ENABLED | false
MULTICAST_EN | false
CTL_DYNAMIC_BANK_ALLOCATION | false
CTL_DYNAMIC_BANK_NUM | 4
DEBUG_MODE | false
ENABLE_BURST_MERGE | false
CTL_ENABLE_BURST_INTERRUPT | false
CTL_ENABLE_BURST_TERMINATE | false
LOCAL_ID_WIDTH | 8
RDBUFFER_ADDR_WIDTH | 6
WRBUFFER_ADDR_WIDTH | 6
MAX_PENDING_WR_CMD | 16
MAX_PENDING_RD_CMD | 32
USE_MM_ADAPTOR | true
USE_AXI_ADAPTOR | false
HCX_COMPAT_MODE | false
CTL_CMD_QUEUE_DEPTH | 8
CTL_CSR_READ_ONLY | 1
CFG_DATA_REORDERING_TYPE | INTER_BANK
NUM_OF_PORTS | 1
ENABLE_BONDING | false
ENABLE_USER_ECC | false
AVL_DATA_WIDTH_PORT | 32,32,32,32,32,32
PRIORITY_PORT | 1,1,1,1,1,1
WEIGHT_PORT | 0,0,0,0,0,0
CPORT_TYPE_PORT | Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional
CORE_PERIPHERY_DUAL_CLOCK | false
USE_DR_CLK | false
DLL_USE_DR_CLK | false
USE_2X_FF | false
DUAL_WRITE_CLOCK | false
GENERIC_PLL | false
USE_HARD_READ_FIFO | false
READ_FIFO_HALF_RATE | false
PLL_MASTER | false
DLL_MASTER | false
PHY_VERSION_NUMBER | 0
ENABLE_NIOS_OCI | false
ENABLE_EMIT_JTAG_MASTER | false
ENABLE_NIOS_JTAG_UART | false
ENABLE_NIOS_PRINTF_OUTPUT | false
ENABLE_LARGE_RW_MGR_DI_BUFFER | false
ENABLE_EMIT_BFM_MASTER | false
FORCE_SEQUENCER_TCL_DEBUG_MODE | false
ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT | false
ENABLE_MAX_SIZE_SEQ_MEM | false
MAKE_INTERNAL_NIOS_VISIBLE | false
DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG | false
ENABLE_CSR_SOFT_RESET_REQ | false
DUPLICATE_PLL_FOR_PHY_CLK | false
MAX_LATENCY_COUNT_WIDTH | 6
READ_VALID_FIFO_SIZE | 16
EXTRA_VFIFO_SHIFT | 0
TB_MEM_CLK_FREQ | 0.0
TB_RATE |
TB_MEM_IF_DQ_WIDTH | 0
TB_MEM_IF_READ_DQS_WIDTH | 0
TB_PLL_DLL_MASTER | true
FAST_SIM_CALIBRATION | false
REF_CLK_FREQ | 25.0
REF_CLK_FREQ_STR |
REF_CLK_NS | 0.0
REF_CLK_PS | 0.0
PLL_DR_CLK_FREQ | 0.0
PLL_DR_CLK_FREQ_STR |
PLL_DR_CLK_FREQ_SIM_STR |
PLL_DR_CLK_PHASE_PS | 0
PLL_DR_CLK_PHASE_PS_STR |
PLL_DR_CLK_PHASE_DEG | 0.0
PLL_DR_CLK_PHASE_PS_SIM | 0
PLL_DR_CLK_PHASE_PS_SIM_STR |
PLL_DR_CLK_PHASE_DEG_SIM | 0.0
PLL_DR_CLK_MULT | 0
PLL_DR_CLK_DIV | 0
PLL_MEM_CLK_FREQ | 0.0
PLL_MEM_CLK_FREQ_STR |
PLL_MEM_CLK_FREQ_SIM_STR |
PLL_MEM_CLK_PHASE_PS | 0
PLL_MEM_CLK_PHASE_PS_STR |
PLL_MEM_CLK_PHASE_DEG | 0.0
PLL_MEM_CLK_PHASE_PS_SIM | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR |
PLL_MEM_CLK_PHASE_DEG_SIM | 0.0
PLL_MEM_CLK_MULT | 0
PLL_MEM_CLK_DIV | 0
PLL_AFI_CLK_FREQ | 0.0
PLL_AFI_CLK_FREQ_STR |
PLL_AFI_CLK_FREQ_SIM_STR |
PLL_AFI_CLK_PHASE_PS | 0
PLL_AFI_CLK_PHASE_PS_STR |
PLL_AFI_CLK_PHASE_DEG | 0.0
PLL_AFI_CLK_PHASE_PS_SIM | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR |
PLL_AFI_CLK_PHASE_DEG_SIM | 0.0
PLL_AFI_CLK_MULT | 0
PLL_AFI_CLK_DIV | 0
PLL_WRITE_CLK_FREQ | 0.0
PLL_WRITE_CLK_FREQ_STR |
PLL_WRITE_CLK_FREQ_SIM_STR |
PLL_WRITE_CLK_PHASE_PS | 0
PLL_WRITE_CLK_PHASE_PS_STR |
PLL_WRITE_CLK_PHASE_DEG | 0.0
PLL_WRITE_CLK_PHASE_PS_SIM | 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR |
PLL_WRITE_CLK_PHASE_DEG_SIM | 0.0
PLL_WRITE_CLK_MULT | 0
PLL_WRITE_CLK_DIV | 0
PLL_ADDR_CMD_CLK_FREQ | 0.0
PLL_ADDR_CMD_CLK_FREQ_STR |
PLL_ADDR_CMD_CLK_FREQ_SIM_STR |
PLL_ADDR_CMD_CLK_PHASE_PS | 0
PLL_ADDR_CMD_CLK_PHASE_PS_STR |
PLL_ADDR_CMD_CLK_PHASE_DEG | 0.0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM | 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR |
PLL_ADDR_CMD_CLK_PHASE_DEG_SIM | 0.0
PLL_ADDR_CMD_CLK_MULT | 0
PLL_ADDR_CMD_CLK_DIV | 0
PLL_AFI_HALF_CLK_FREQ | 0.0
PLL_AFI_HALF_CLK_FREQ_STR |
PLL_AFI_HALF_CLK_FREQ_SIM_STR |
PLL_AFI_HALF_CLK_PHASE_PS | 0
PLL_AFI_HALF_CLK_PHASE_PS_STR |
PLL_AFI_HALF_CLK_PHASE_DEG | 0.0
PLL_AFI_HALF_CLK_PHASE_PS_SIM | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR |
PLL_AFI_HALF_CLK_PHASE_DEG_SIM | 0.0
PLL_AFI_HALF_CLK_MULT | 0
PLL_AFI_HALF_CLK_DIV | 0
PLL_NIOS_CLK_FREQ | 0.0
PLL_NIOS_CLK_FREQ_STR |
PLL_NIOS_CLK_FREQ_SIM_STR |
PLL_NIOS_CLK_PHASE_PS | 0
PLL_NIOS_CLK_PHASE_PS_STR |
PLL_NIOS_CLK_PHASE_DEG | 0.0
PLL_NIOS_CLK_PHASE_PS_SIM | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR |
PLL_NIOS_CLK_PHASE_DEG_SIM | 0.0
PLL_NIOS_CLK_MULT | 0
PLL_NIOS_CLK_DIV | 0
PLL_CONFIG_CLK_FREQ | 0.0
PLL_CONFIG_CLK_FREQ_STR |
PLL_CONFIG_CLK_FREQ_SIM_STR |
PLL_CONFIG_CLK_PHASE_PS | 0
PLL_CONFIG_CLK_PHASE_PS_STR |
PLL_CONFIG_CLK_PHASE_DEG | 0.0
PLL_CONFIG_CLK_PHASE_PS_SIM | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR |
PLL_CONFIG_CLK_PHASE_DEG_SIM | 0.0
PLL_CONFIG_CLK_MULT | 0
PLL_CONFIG_CLK_DIV | 0
PLL_P2C_READ_CLK_FREQ | 0.0
PLL_P2C_READ_CLK_FREQ_STR |
PLL_P2C_READ_CLK_FREQ_SIM_STR |
PLL_P2C_READ_CLK_PHASE_PS | 0
PLL_P2C_READ_CLK_PHASE_PS_STR |
PLL_P2C_READ_CLK_PHASE_DEG | 0.0
PLL_P2C_READ_CLK_PHASE_PS_SIM | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR |
PLL_P2C_READ_CLK_PHASE_DEG_SIM | 0.0
PLL_P2C_READ_CLK_MULT | 0
PLL_P2C_READ_CLK_DIV | 0
PLL_C2P_WRITE_CLK_FREQ | 0.0
PLL_C2P_WRITE_CLK_FREQ_STR |
PLL_C2P_WRITE_CLK_FREQ_SIM_STR |
PLL_C2P_WRITE_CLK_PHASE_PS | 0
PLL_C2P_WRITE_CLK_PHASE_PS_STR |
PLL_C2P_WRITE_CLK_PHASE_DEG | 0.0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR |
PLL_C2P_WRITE_CLK_PHASE_DEG_SIM | 0.0
PLL_C2P_WRITE_CLK_MULT | 0
PLL_C2P_WRITE_CLK_DIV | 0
PLL_HR_CLK_FREQ | 0.0
PLL_HR_CLK_FREQ_STR |
PLL_HR_CLK_FREQ_SIM_STR |
PLL_HR_CLK_PHASE_PS | 0
PLL_HR_CLK_PHASE_PS_STR |
PLL_HR_CLK_PHASE_DEG | 0.0
PLL_HR_CLK_PHASE_PS_SIM | 0
PLL_HR_CLK_PHASE_PS_SIM_STR |
PLL_HR_CLK_PHASE_DEG_SIM | 0.0
PLL_HR_CLK_MULT | 0
PLL_HR_CLK_DIV | 0
PLL_AFI_PHY_CLK_FREQ | 0.0
PLL_AFI_PHY_CLK_FREQ_STR |
PLL_AFI_PHY_CLK_FREQ_SIM_STR |
PLL_AFI_PHY_CLK_PHASE_PS | 0
PLL_AFI_PHY_CLK_PHASE_PS_STR |
PLL_AFI_PHY_CLK_PHASE_DEG | 0.0
PLL_AFI_PHY_CLK_PHASE_PS_SIM | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR |
PLL_AFI_PHY_CLK_PHASE_DEG_SIM | 0.0
PLL_AFI_PHY_CLK_MULT | 0
PLL_AFI_PHY_CLK_DIV | 0
REF_CLK_FREQ_CACHE_VALID | false
REF_CLK_FREQ_PARAM_VALID | false
REF_CLK_FREQ_MIN_PARAM | 0.0
REF_CLK_FREQ_MAX_PARAM | 0.0
REF_CLK_FREQ_MIN_CACHE | 0.0
REF_CLK_FREQ_MAX_CACHE | 0.0
PLL_DR_CLK_FREQ_PARAM | 0.0
PLL_DR_CLK_FREQ_SIM_STR_PARAM |
PLL_DR_CLK_PHASE_PS_PARAM | 0
PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_DR_CLK_MULT_PARAM | 0
PLL_DR_CLK_DIV_PARAM | 0
PLL_DR_CLK_FREQ_CACHE | 0.0
PLL_DR_CLK_FREQ_SIM_STR_CACHE |
PLL_DR_CLK_PHASE_PS_CACHE | 0
PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_DR_CLK_MULT_CACHE | 0
PLL_DR_CLK_DIV_CACHE | 0
PLL_MEM_CLK_FREQ_PARAM | 0.0
PLL_MEM_CLK_FREQ_SIM_STR_PARAM |
PLL_MEM_CLK_PHASE_PS_PARAM | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_MEM_CLK_MULT_PARAM | 0
PLL_MEM_CLK_DIV_PARAM | 0
PLL_MEM_CLK_FREQ_CACHE | 0.0
PLL_MEM_CLK_FREQ_SIM_STR_CACHE |
PLL_MEM_CLK_PHASE_PS_CACHE | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_MEM_CLK_MULT_CACHE | 0
PLL_MEM_CLK_DIV_CACHE | 0
PLL_AFI_CLK_FREQ_PARAM | 0.0
PLL_AFI_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_CLK_PHASE_PS_PARAM | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_CLK_MULT_PARAM | 0
PLL_AFI_CLK_DIV_PARAM | 0
PLL_AFI_CLK_FREQ_CACHE | 0.0
PLL_AFI_CLK_FREQ_SIM_STR_CACHE |
PLL_AFI_CLK_PHASE_PS_CACHE | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_AFI_CLK_MULT_CACHE | 0
PLL_AFI_CLK_DIV_CACHE | 0
PLL_WRITE_CLK_FREQ_PARAM | 0.0
PLL_WRITE_CLK_FREQ_SIM_STR_PARAM |
PLL_WRITE_CLK_PHASE_PS_PARAM | 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_WRITE_CLK_MULT_PARAM | 0
PLL_WRITE_CLK_DIV_PARAM | 0
PLL_WRITE_CLK_FREQ_CACHE | 0.0
PLL_WRITE_CLK_FREQ_SIM_STR_CACHE |
PLL_WRITE_CLK_PHASE_PS_CACHE | 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_WRITE_CLK_MULT_CACHE | 0
PLL_WRITE_CLK_DIV_CACHE | 0
PLL_ADDR_CMD_CLK_FREQ_PARAM | 0.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM |
PLL_ADDR_CMD_CLK_PHASE_PS_PARAM | 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_ADDR_CMD_CLK_MULT_PARAM | 0
PLL_ADDR_CMD_CLK_DIV_PARAM | 0
PLL_ADDR_CMD_CLK_FREQ_CACHE | 0.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE |
PLL_ADDR_CMD_CLK_PHASE_PS_CACHE | 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_ADDR_CMD_CLK_MULT_CACHE | 0
PLL_ADDR_CMD_CLK_DIV_CACHE | 0
PLL_AFI_HALF_CLK_FREQ_PARAM | 0.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_HALF_CLK_PHASE_PS_PARAM | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_HALF_CLK_MULT_PARAM | 0
PLL_AFI_HALF_CLK_DIV_PARAM | 0
PLL_AFI_HALF_CLK_FREQ_CACHE | 0.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE |
PLL_AFI_HALF_CLK_PHASE_PS_CACHE | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_AFI_HALF_CLK_MULT_CACHE | 0
PLL_AFI_HALF_CLK_DIV_CACHE | 0
PLL_NIOS_CLK_FREQ_PARAM | 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_PARAM |
PLL_NIOS_CLK_PHASE_PS_PARAM | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_NIOS_CLK_MULT_PARAM | 0
PLL_NIOS_CLK_DIV_PARAM | 0
PLL_NIOS_CLK_FREQ_CACHE | 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_CACHE |
PLL_NIOS_CLK_PHASE_PS_CACHE | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_NIOS_CLK_MULT_CACHE | 0
PLL_NIOS_CLK_DIV_CACHE | 0
PLL_CONFIG_CLK_FREQ_PARAM | 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM |
PLL_CONFIG_CLK_PHASE_PS_PARAM | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_CONFIG_CLK_MULT_PARAM | 0
PLL_CONFIG_CLK_DIV_PARAM | 0
PLL_CONFIG_CLK_FREQ_CACHE | 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE |
PLL_CONFIG_CLK_PHASE_PS_CACHE | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_CONFIG_CLK_MULT_CACHE | 0
PLL_CONFIG_CLK_DIV_CACHE | 0
PLL_P2C_READ_CLK_FREQ_PARAM | 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM |
PLL_P2C_READ_CLK_PHASE_PS_PARAM | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_P2C_READ_CLK_MULT_PARAM | 0
PLL_P2C_READ_CLK_DIV_PARAM | 0
PLL_P2C_READ_CLK_FREQ_CACHE | 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE |
PLL_P2C_READ_CLK_PHASE_PS_CACHE | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_P2C_READ_CLK_MULT_CACHE | 0
PLL_P2C_READ_CLK_DIV_CACHE | 0
PLL_C2P_WRITE_CLK_FREQ_PARAM | 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM |
PLL_C2P_WRITE_CLK_PHASE_PS_PARAM | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_C2P_WRITE_CLK_MULT_PARAM | 0
PLL_C2P_WRITE_CLK_DIV_PARAM | 0
PLL_C2P_WRITE_CLK_FREQ_CACHE | 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE |
PLL_C2P_WRITE_CLK_PHASE_PS_CACHE | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_C2P_WRITE_CLK_MULT_CACHE | 0
PLL_C2P_WRITE_CLK_DIV_CACHE | 0
PLL_HR_CLK_FREQ_PARAM | 0.0
PLL_HR_CLK_FREQ_SIM_STR_PARAM |
PLL_HR_CLK_PHASE_PS_PARAM | 0
PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_HR_CLK_MULT_PARAM | 0
PLL_HR_CLK_DIV_PARAM | 0
PLL_HR_CLK_FREQ_CACHE | 0.0
PLL_HR_CLK_FREQ_SIM_STR_CACHE |
PLL_HR_CLK_PHASE_PS_CACHE | 0
PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_HR_CLK_MULT_CACHE | 0
PLL_HR_CLK_DIV_CACHE | 0
PLL_AFI_PHY_CLK_FREQ_PARAM | 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_PHY_CLK_PHASE_PS_PARAM | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_PHY_CLK_MULT_PARAM | 0
PLL_AFI_PHY_CLK_DIV_PARAM | 0
PLL_AFI_PHY_CLK_FREQ_CACHE | 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE |
PLL_AFI_PHY_CLK_PHASE_PS_CACHE | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_AFI_PHY_CLK_MULT_CACHE | 0
PLL_AFI_PHY_CLK_DIV_CACHE | 0
SPEED_GRADE_CACHE |
IS_ES_DEVICE_CACHE | false
MEM_CLK_FREQ_CACHE | 0.0
REF_CLK_FREQ_CACHE | 0.0
RATE_CACHE | Unknown
HCX_COMPAT_MODE_CACHE | false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE | Unknown
COMMAND_PHASE_CACHE | 0.0
MEM_CK_PHASE_CACHE | 0.0
P2C_READ_CLOCK_ADD_PHASE_CACHE | 0.0
C2P_WRITE_CLOCK_ADD_PHASE_CACHE | 0.0
ACV_PHY_CLK_ADD_FR_PHASE_CACHE | 0.0
SEQUENCER_TYPE_CACHE | Unknown
USE_MEM_CLK_FREQ_CACHE | false
PLL_CLK_CACHE_VALID | false
PLL_CLK_PARAM_VALID | false
ENABLE_EXTRA_REPORTING | false
NUM_EXTRA_REPORT_PATH | 10
ENABLE_ISS_PROBES | false
CALIB_REG_WIDTH | 8
USE_SEQUENCER_BFM | false
DEFAULT_FAST_SIM_MODEL | true
PLL_SHARING_MODE | None
NUM_PLL_SHARING_INTERFACES | 1
EXPORT_AFI_HALF_CLK | false
ABSTRACT_REAL_COMPARE_TEST | false
INCLUDE_BOARD_DELAY_MODEL | false
INCLUDE_MULTIRANK_BOARD_DELAY_MODEL | false
USE_FAKE_PHY_INTERNAL | false
USE_FAKE_PHY | false
FORCE_MAX_LATENCY_COUNT_WIDTH | 0
USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE | false
ENABLE_NON_DESTRUCTIVE_CALIB | false
TRACKING_ERROR_TEST | false
TRACKING_WATCH_TEST | false
MARGIN_VARIATION_TEST | false
EXTRA_SETTINGS |
MEM_DEVICE | MISSING_MODEL
FORCE_SYNTHESIS_LANGUAGE |
NUM_SUBGROUP_PER_READ_DQS | 0
QVLD_EXTRA_FLOP_STAGES | 0
QVLD_WR_ADDRESS_OFFSET | 0
MAX_WRITE_LATENCY_COUNT_WIDTH | 4
NUM_WRITE_PATH_FLOP_STAGES | 0
NUM_AC_FR_CYCLE_SHIFTS | 0
FORCED_NUM_WRITE_FR_CYCLE_SHIFTS | 0
NUM_WRITE_FR_CYCLE_SHIFTS | 0
PERFORM_READ_AFTER_WRITE_CALIBRATION | false
SEQ_BURST_COUNT_WIDTH | 0
VCALIB_COUNT_WIDTH | 0
PLL_PHASE_COUNTER_WIDTH | 0
DQS_DELAY_CHAIN_PHASE_SETTING | 2
DQS_PHASE_SHIFT | 9000
DELAYED_CLOCK_PHASE_SETTING | 2
IO_DQS_IN_RESERVE | 3
IO_DQS_OUT_RESERVE | 3
IO_DQ_OUT_RESERVE | 0
IO_DM_OUT_RESERVE | 0
IO_DQS_EN_DELAY_OFFSET | 0
IO_DQS_EN_PHASE_MAX | 0
IO_DQDQS_OUT_PHASE_MAX | 0
IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS | false
MEM_CLK_NS | 0.0
MEM_CLK_PS | 0.0
CALIB_LFIFO_OFFSET | -1
CALIB_VFIFO_OFFSET | -1
DELAY_PER_OPA_TAP | -1
DELAY_PER_DCHAIN_TAP | -1
DELAY_PER_DQS_EN_DCHAIN_TAP | -1
DQS_EN_DELAY_MAX | -1
DQS_IN_DELAY_MAX | -1
IO_IN_DELAY_MAX | -1
IO_OUT1_DELAY_MAX | -1
IO_OUT2_DELAY_MAX | -1
IO_STANDARD |
VFIFO_AS_SHIFT_REG | false
SEQUENCER_TYPE | NIOS
NIOS_HEX_FILE_LOCATION |
ADVERTIZE_SEQUENCER_SW_BUILD_FILES | false
NEGATIVE_WRITE_CK_PHASE | false
MEM_T_WL | 0
MEM_T_RL | 0
PHY_CLKBUF | false
USE_LDC_AS_LOW_SKEW_CLOCK | false
USE_LDC_FOR_ADDR_CMD | false
ENABLE_LDC_MEM_CK_ADJUSTMENT | false
MEM_CK_LDC_ADJUSTMENT_THRESHOLD | 0
LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT | true
LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE | 0
FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT | false
NON_LDC_ADDR_CMD_MEM_CK_INVERT | false
REGISTER_C2P | false
EARLY_ADDR_CMD_CLK_TRANSFER | false
PHY_ONLY | false
SEQ_MODE | 0
ADVANCED_CK_PHASES | false
COMMAND_PHASE | 0.0
MEM_CK_PHASE | 0.0
P2C_READ_CLOCK_ADD_PHASE | 0.0
C2P_WRITE_CLOCK_ADD_PHASE | 0.0
ACV_PHY_CLK_ADD_FR_PHASE | 0.0
MEM_VOLTAGE | 1.5V DDR3
PLL_LOCATION | Top_Bottom
SKIP_MEM_INIT | true
READ_DQ_DQS_CLOCK_SOURCE | INVERTED_DQS_BUS
DQ_INPUT_REG_USE_CLKN | false
DQS_DQSN_MODE | DIFFERENTIAL
AFI_DEBUG_INFO_WIDTH | 32
CALIBRATION_MODE | Skip
NIOS_ROM_DATA_WIDTH | 32
NIOS_ROM_ADDRESS_WIDTH | 13
READ_FIFO_SIZE | 8
PHY_CSR_ENABLED | false
PHY_CSR_CONNECTION | INTERNAL_JTAG
USER_DEBUG_LEVEL | 1
TIMING_BOARD_DERATE_METHOD | AUTO
TIMING_BOARD_CK_CKN_SLEW_RATE | 2.0
TIMING_BOARD_AC_SLEW_RATE | 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE | 2.0
TIMING_BOARD_DQ_SLEW_RATE | 1.0
TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED | 2.0
TIMING_BOARD_AC_SLEW_RATE_APPLIED | 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED | 2.0
TIMING_BOARD_DQ_SLEW_RATE_APPLIED | 1.0
TIMING_BOARD_TIS | 0.0
TIMING_BOARD_TIH | 0.0
TIMING_BOARD_TDS | 0.0
TIMING_BOARD_TDH | 0.0
TIMING_BOARD_TIS_APPLIED | 0.0
TIMING_BOARD_TIH_APPLIED | 0.0
TIMING_BOARD_TDS_APPLIED | 0.0
TIMING_BOARD_TDH_APPLIED | 0.0
TIMING_BOARD_ISI_METHOD | AUTO
TIMING_BOARD_AC_EYE_REDUCTION_SU | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H | 0.0
TIMING_BOARD_DQ_EYE_REDUCTION | 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME | 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION | 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED | 0.0
TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED | 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED | 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED | 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED | 0.0
PACKAGE_DESKEW | false
AC_PACKAGE_DESKEW | false
TIMING_BOARD_MAX_CK_DELAY | 0.03
TIMING_BOARD_MAX_DQS_DELAY | 0.02
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN | 0.09
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED | -0.01
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX | 0.16
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED | 0.01
TIMING_BOARD_SKEW_BETWEEN_DIMMS | 0.05
TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED | 0.05
TIMING_BOARD_SKEW_WITHIN_DQS | 0.01
TIMING_BOARD_SKEW_BETWEEN_DQS | 0.08
TIMING_BOARD_DQ_TO_DQS_SKEW | 0.0
TIMING_BOARD_AC_SKEW | 0.03
TIMING_BOARD_AC_TO_CK_SKEW | 0.0
RATE | Full
MEM_CLK_FREQ | 400.0
USE_MEM_CLK_FREQ | false
USE_DQS_TRACKING | false
FORCE_DQS_TRACKING | AUTO
USE_HPS_DQS_TRACKING | false
TRK_PARALLEL_SCC_LOAD | false
USE_SHADOW_REGS | false
FORCE_SHADOW_REGS | AUTO
DQ_DDR | 0
ADDR_CMD_DDR | 0
AFI_RATE_RATIO | 0
DATA_RATE_RATIO | 0
ADDR_RATE_RATIO | 0
AFI_ADDR_WIDTH | 0
AFI_BANKADDR_WIDTH | 0
AFI_CONTROL_WIDTH | 0
AFI_CS_WIDTH | 0
AFI_CLK_EN_WIDTH | 0
AFI_DM_WIDTH | 0
AFI_DQ_WIDTH | 0
AFI_ODT_WIDTH | 0
AFI_WRITE_DQS_WIDTH | 0
AFI_RLAT_WIDTH | 0
AFI_WLAT_WIDTH | 0
AFI_RRANK_WIDTH | 0
AFI_WRANK_WIDTH | 0
AFI_CLK_PAIR_COUNT | 0
MRS_MIRROR_PING_PONG_ATSO | false
SYS_INFO_DEVICE_FAMILY | CYCLONEV
PARSE_FRIENDLY_DEVICE_FAMILY |
DEVICE_FAMILY |
PRE_V_SERIES_FAMILY | false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID | false
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID | false
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM |
DEVICE_FAMILY_PARAM |
SPEED_GRADE | 7
IS_ES_DEVICE | false
DISABLE_CHILD_MESSAGING | false
HARD_PHY | false
HARD_EMIF | true
HHP_HPS | true
HHP_HPS_VERIFICATION | false
HHP_HPS_SIMULATION | true
HPS_PROTOCOL | DDR3
CUT_NEW_FAMILY_TIMING | true
ENABLE_EXPORT_SEQ_DEBUG_BRIDGE | false
CORE_DEBUG_CONNECTION | EXPORT
ADD_EXTERNAL_SEQ_DEBUG_NIOS | false
ED_EXPORT_SEQ_DEBUG | false
ADD_EFFICIENCY_MONITOR | false
ENABLE_ABS_RAM_MEM_INIT | false
ENABLE_ABS_RAM_INTERNAL | false
ENABLE_ABSTRACT_RAM | false
ABS_RAM_MEM_INIT_FILENAME | meminit
DLL_DELAY_CTRL_WIDTH | 6
DLL_OFFSET_CTRL_WIDTH | 6
DELAY_BUFFER_MODE | HIGH
DELAY_CHAIN_LENGTH | 8
DLL_SHARING_MODE | None
NUM_DLL_SHARING_INTERFACES | 1
OCT_TERM_CONTROL_WIDTH | 14
OCT_SHARING_MODE | None
NUM_OCT_SHARING_INTERFACES | 1
interfaceDefinition | instances {boot_from_fpga {entity_name cyclonev_hps_interface_boot_from_fpga location HPSINTERFACEBOOTFROMFPGA_X52_Y74_N111 signal_widths {boot_from_fpga_ready 1 boot_from_fpga_on_failure 1 bsel_en 1 csel_en 1 csel 2 bsel 3} signal_terminations {boot_from_fpga_ready {0:0 0} boot_from_fpga_on_failure {0:0 0} bsel_en {0:0 0} csel_en {0:0 0} csel {1:0 1} bsel {2:0 1}} parameters {} signal_default_terminations {boot_from_fpga_ready 0 boot_from_fpga_on_failure 0 bsel_en 0 csel_en 0 csel 0 bsel 0}} tpiu {entity_name cyclonev_hps_interface_tpiu_trace location HPSINTERFACETPIUTRACE_X52_Y39_N111 signal_widths {traceclk_ctl 1} parameters {} signal_terminations {traceclk_ctl {0:0 1}} signal_default_terminations {traceclk_ctl 1}} clocks_resets {entity_name cyclonev_hps_interface_clocks_resets location HPSINTERFACECLOCKSRESETS_X52_Y78_N111 signal_widths {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 1 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 1} signal_terminations {f2h_warm_rst_req_n {0:0 1} f2h_pending_rst_ack {0:0 1} f2h_sdram_ref_clk {} f2h_dbg_rst_req_n {0:0 1} f2h_cold_rst_req_n {0:0 1} f2h_periph_ref_clk {}} parameters {} signal_default_terminations {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 0 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 0}} @orderednames {clocks_resets debug_apb tpiu boot_from_fpga interrupts} debug_apb {entity_name cyclonev_hps_interface_dbg_apb location HPSINTERFACEDBGAPB_X52_Y80_N111 signal_widths {DBG_APB_DISABLE 1 P_CLK_EN 1} signal_terminations {DBG_APB_DISABLE {0:0 0} P_CLK_EN {0:0 0}} parameters {} signal_default_terminations {DBG_APB_DISABLE 0 P_CLK_EN 0}} interrupts {entity_name cyclonev_hps_interface_interrupts location HPSINTERFACEINTERRUPTS_X52_Y40_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {} properties {} bfm_types {} intermediate_wire_count 0 wires_to_fragments {} interfaces {@orderednames h2f_reset h2f_reset {properties {associatedResetSinks none synchronousEdges none} type reset direction Output signals {@orderednames h2f_rst_n h2f_rst_n {fragments {} properties {} internal_name h2f_rst_n width 1 instance_name clocks_resets direction Output role reset_n}}}} raw_assign_sim_style {}
qipEntries |
ignoreSimulation | false
hps_parameter_map |
device | 5CSXFC6D6F31C8ES
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_hps_io

altera_hps_io v13.1.1

## Parameters
border_description | instances {sdio_inst {entity_name cyclonev_hps_peripheral_sdmmc location HPSPERIPHERALSDMMC_X87_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} emac1_inst {entity_name cyclonev_hps_peripheral_emac location HPSPERIPHERALEMAC_X77_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c1_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y65_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} spim1_inst {entity_name cyclonev_hps_peripheral_spi_master location HPSPERIPHERALSPIMASTER_X87_Y53_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} qspi_inst {entity_name cyclonev_hps_peripheral_qspi location HPSPERIPHERALQSPI_X87_Y58_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} uart0_inst {entity_name cyclonev_hps_peripheral_uart location HPSPERIPHERALUART_X87_Y45_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} @orderednames {emac1_inst qspi_inst sdio_inst usb1_inst spim0_inst spim1_inst uart0_inst i2c1_inst hps_sdram_inst} usb1_inst {entity_name cyclonev_hps_peripheral_usb location HPSPERIPHERALUSB_X55_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps_sdram_inst {entity_name hps_sdram location {} signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} spim0_inst {entity_name cyclonev_hps_peripheral_spi_master location HPSPERIPHERALSPIMASTER_X87_Y55_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {} properties {SUPPRESS_SDRAM_SYNTH 0 GENERATE_ISW 1} bfm_types {} intermediate_wire_count 42 wires_to_fragments {{intermediate 9} {output qspi_inst:QSPI_MO_EN_N(3:3)} {intermediate 8} {output qspi_inst:QSPI_MO3(0:0)} {intermediate 7} {output qspi_inst:QSPI_MO_EN_N(2:2)} {intermediate 6} {output qspi_inst:QSPI_MO2(0:0)} {intermediate 5} {output qspi_inst:QSPI_MO_EN_N(1:1)} {intermediate 4} {output qspi_inst:QSPI_MO1(0:0)} {intermediate 3} {output qspi_inst:QSPI_MO_EN_N(0:0)} {intermediate 2} {output qspi_inst:QSPI_MO0(0:0)} {intermediate 1} {output emac1_inst:EMAC_GMII_MDO_OE(0:0)} {intermediate 0} {output emac1_inst:EMAC_GMII_MDO_O(0:0)} {intermediate 19} {output sdio_inst:SDMMC_DATA_OE(3:3)} {intermediate 18} {output sdio_inst:SDMMC_DATA_O(3:3)} {intermediate 17} {output sdio_inst:SDMMC_DATA_OE(2:2)} {intermediate 16} {output sdio_inst:SDMMC_DATA_O(2:2)} {intermediate 15} {output sdio_inst:SDMMC_DATA_OE(1:1)} {intermediate 14} {output sdio_inst:SDMMC_DATA_O(1:1)} {intermediate 13} {output sdio_inst:SDMMC_DATA_OE(0:0)} {intermediate 12} {output sdio_inst:SDMMC_DATA_O(0:0)} {intermediate 11} {output sdio_inst:SDMMC_CMD_OE(0:0)} {intermediate 10} {output sdio_inst:SDMMC_CMD_O(0:0)} {intermediate 41} {output i2c1_inst:I2C_CLK_OE(0:0)} {intermediate 40} {output i2c1_inst:I2C_DATA_OE(0:0)} {intermediate 39} {output spim1_inst:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 38} {output spim1_inst:SPI_MASTER_TXD(0:0)} {intermediate 37} {output spim0_inst:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 36} {output spim0_inst:SPI_MASTER_TXD(0:0)} {intermediate 35} {output usb1_inst:USB_ULPI_DATA_OE(7:7)} {intermediate 34} {output usb1_inst:USB_ULPI_DATA_O(7:7)} {intermediate 33} {output usb1_inst:USB_ULPI_DATA_OE(6:6)} {intermediate 32} {output usb1_inst:USB_ULPI_DATA_O(6:6)} {intermediate 31} {output usb1_inst:USB_ULPI_DATA_OE(5:5)} {intermediate 30} {output usb1_inst:USB_ULPI_DATA_O(5:5)} {intermediate 29} {output usb1_inst:USB_ULPI_DATA_OE(4:4)} {intermediate 28} {output usb1_inst:USB_ULPI_DATA_O(4:4)} {intermediate 27} {output usb1_inst:USB_ULPI_DATA_OE(3:3)} {intermediate 26} {output usb1_inst:USB_ULPI_DATA_O(3:3)} {intermediate 25} {output usb1_inst:USB_ULPI_DATA_OE(2:2)} {intermediate 24} {output usb1_inst:USB_ULPI_DATA_O(2:2)} {intermediate 23} {output usb1_inst:USB_ULPI_DATA_OE(1:1)} {intermediate 22} {output usb1_inst:USB_ULPI_DATA_O(1:1)} {intermediate 21} {output usb1_inst:USB_ULPI_DATA_OE(0:0)} {intermediate 20} {output usb1_inst:USB_ULPI_DATA_O(0:0)}} interfaces {@orderednames {memory hps_io} memory {properties {} type conduit direction end signals {@orderednames {mem_a mem_ba mem_ck mem_ck_n mem_cke mem_cs_n mem_ras_n mem_cas_n mem_we_n mem_reset_n mem_dq mem_dqs mem_dqs_n mem_odt mem_dm oct_rzqin} mem_a {fragments {} properties {} internal_name mem_a width 15 instance_name hps_sdram_inst direction Output role mem_a} mem_ba {fragments {} properties {} internal_name mem_ba width 3 instance_name hps_sdram_inst direction Output role mem_ba} mem_ck {fragments {} properties {} internal_name mem_ck width 1 instance_name hps_sdram_inst direction Output role mem_ck} mem_ck_n {fragments {} properties {} internal_name mem_ck_n width 1 instance_name hps_sdram_inst direction Output role mem_ck_n} mem_cke {fragments {} properties {} internal_name mem_cke width 1 instance_name hps_sdram_inst direction Output role mem_cke} mem_cs_n {fragments {} properties {} internal_name mem_cs_n width 1 instance_name hps_sdram_inst direction Output role mem_cs_n} mem_ras_n {fragments {} properties {} internal_name mem_ras_n width 1 instance_name hps_sdram_inst direction Output role mem_ras_n} mem_cas_n {fragments {} properties {} internal_name mem_cas_n width 1 instance_name hps_sdram_inst direction Output role mem_cas_n} mem_we_n {fragments {} properties {} internal_name mem_we_n width 1 instance_name hps_sdram_inst direction Output role mem_we_n} mem_reset_n {fragments {} properties {} internal_name mem_reset_n width 1 instance_name hps_sdram_inst direction Output role mem_reset_n} mem_dq {fragments {} properties {} internal_name mem_dq width 32 instance_name hps_sdram_inst direction Bidir role mem_dq} mem_dqs {fragments {} properties {} internal_name mem_dqs width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs} mem_dqs_n {fragments {} properties {} internal_name mem_dqs_n width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs_n} mem_odt {fragments {} properties {} internal_name mem_odt width 1 instance_name hps_sdram_inst direction Output role mem_odt} mem_dm {fragments {} properties {} internal_name mem_dm width 4 instance_name hps_sdram_inst direction Output role mem_dm} oct_rzqin {fragments {} properties {} internal_name oct_rzqin width 1 instance_name hps_sdram_inst direction Input role oct_rzqin}}} hps_io {properties {} type conduit direction input signals {@orderednames {hps_io_emac1_inst_TX_CLK hps_io_emac1_inst_TXD0 hps_io_emac1_inst_TXD1 hps_io_emac1_inst_TXD2 hps_io_emac1_inst_TXD3 hps_io_emac1_inst_RXD0 hps_io_emac1_inst_MDIO hps_io_emac1_inst_MDC hps_io_emac1_inst_RX_CTL hps_io_emac1_inst_TX_CTL hps_io_emac1_inst_RX_CLK hps_io_emac1_inst_RXD1 hps_io_emac1_inst_RXD2 hps_io_emac1_inst_RXD3 hps_io_qspi_inst_IO0 hps_io_qspi_inst_IO1 hps_io_qspi_inst_IO2 hps_io_qspi_inst_IO3 hps_io_qspi_inst_SS0 hps_io_qspi_inst_CLK hps_io_sdio_inst_CMD hps_io_sdio_inst_D0 hps_io_sdio_inst_D1 hps_io_sdio_inst_CLK hps_io_sdio_inst_D2 hps_io_sdio_inst_D3 hps_io_usb1_inst_D0 hps_io_usb1_inst_D1 hps_io_usb1_inst_D2 hps_io_usb1_inst_D3 hps_io_usb1_inst_D4 hps_io_usb1_inst_D5 hps_io_usb1_inst_D6 hps_io_usb1_inst_D7 hps_io_usb1_inst_CLK hps_io_usb1_inst_STP hps_io_usb1_inst_DIR hps_io_usb1_inst_NXT hps_io_spim0_inst_CLK hps_io_spim0_inst_MOSI hps_io_spim0_inst_MISO hps_io_spim0_inst_SS0 hps_io_spim1_inst_CLK hps_io_spim1_inst_MOSI hps_io_spim1_inst_MISO hps_io_spim1_inst_SS0 hps_io_uart0_inst_RX hps_io_uart0_inst_TX hps_io_i2c1_inst_SDA hps_io_i2c1_inst_SCL} hps_io_emac1_inst_TX_CLK {fragments emac1_inst:EMAC_CLK_TX(0:0) properties {} internal_name hps_io_emac1_inst_TX_CLK width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CLK} hps_io_emac1_inst_TXD0 {fragments emac1_inst:EMAC_PHY_TXD(0:0) properties {} internal_name hps_io_emac1_inst_TXD0 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD0} hps_io_emac1_inst_TXD1 {fragments emac1_inst:EMAC_PHY_TXD(1:1) properties {} internal_name hps_io_emac1_inst_TXD1 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD1} hps_io_emac1_inst_TXD2 {fragments emac1_inst:EMAC_PHY_TXD(2:2) properties {} internal_name hps_io_emac1_inst_TXD2 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD2} hps_io_emac1_inst_TXD3 {fragments emac1_inst:EMAC_PHY_TXD(3:3) properties {} internal_name hps_io_emac1_inst_TXD3 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD3} hps_io_emac1_inst_RXD0 {fragments emac1_inst:EMAC_PHY_RXD(0:0) properties {} internal_name hps_io_emac1_inst_RXD0 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD0} hps_io_emac1_inst_MDIO {fragments emac1_inst:EMAC_GMII_MDO_I(0:0) properties {} internal_name hps_io_emac1_inst_MDIO width 1 instance_name hps_io tristate_output {{intermediate 1} {intermediate 0}} direction bidir role hps_io_emac1_inst_MDIO} hps_io_emac1_inst_MDC {fragments emac1_inst:EMAC_GMII_MDC(0:0) properties {} internal_name hps_io_emac1_inst_MDC width 1 instance_name hps_io direction output role hps_io_emac1_inst_MDC} hps_io_emac1_inst_RX_CTL {fragments emac1_inst:EMAC_PHY_RXDV(0:0) properties {} internal_name hps_io_emac1_inst_RX_CTL width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CTL} hps_io_emac1_inst_TX_CTL {fragments emac1_inst:EMAC_PHY_TX_OE(0:0) properties {} internal_name hps_io_emac1_inst_TX_CTL width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CTL} hps_io_emac1_inst_RX_CLK {fragments emac1_inst:EMAC_CLK_RX(0:0) properties {} internal_name hps_io_emac1_inst_RX_CLK width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CLK} hps_io_emac1_inst_RXD1 {fragments emac1_inst:EMAC_PHY_RXD(1:1) properties {} internal_name hps_io_emac1_inst_RXD1 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD1} hps_io_emac1_inst_RXD2 {fragments emac1_inst:EMAC_PHY_RXD(2:2) properties {} internal_name hps_io_emac1_inst_RXD2 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD2} hps_io_emac1_inst_RXD3 {fragments emac1_inst:EMAC_PHY_RXD(3:3) properties {} internal_name hps_io_emac1_inst_RXD3 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD3} hps_io_qspi_inst_IO0 {fragments qspi_inst:QSPI_MI0(0:0) properties {} internal_name hps_io_qspi_inst_IO0 width 1 instance_name hps_io tristate_output {{intermediate 3} {intermediate 2}} direction bidir role hps_io_qspi_inst_IO0} hps_io_qspi_inst_IO1 {fragments qspi_inst:QSPI_MI1(0:0) properties {} internal_name hps_io_qspi_inst_IO1 width 1 instance_name hps_io tristate_output {{intermediate 5} {intermediate 4}} direction bidir role hps_io_qspi_inst_IO1} hps_io_qspi_inst_IO2 {fragments qspi_inst:QSPI_MI2(0:0) properties {} internal_name hps_io_qspi_inst_IO2 width 1 instance_name hps_io tristate_output {{intermediate 7} {intermediate 6}} direction bidir role hps_io_qspi_inst_IO2} hps_io_qspi_inst_IO3 {fragments qspi_inst:QSPI_MI3(0:0) properties {} internal_name hps_io_qspi_inst_IO3 width 1 instance_name hps_io tristate_output {{intermediate 9} {intermediate 8}} direction bidir role hps_io_qspi_inst_IO3} hps_io_qspi_inst_SS0 {fragments qspi_inst:QSPI_SS_N(0:0) properties {} internal_name hps_io_qspi_inst_SS0 width 1 instance_name hps_io direction output role hps_io_qspi_inst_SS0} hps_io_qspi_inst_CLK {fragments qspi_inst:QSPI_SCLK(0:0) properties {} internal_name hps_io_qspi_inst_CLK width 1 instance_name hps_io direction output role hps_io_qspi_inst_CLK} hps_io_sdio_inst_CMD {fragments sdio_inst:SDMMC_CMD_I(0:0) properties {} internal_name hps_io_sdio_inst_CMD width 1 instance_name hps_io tristate_output {{intermediate 11} {intermediate 10}} direction bidir role hps_io_sdio_inst_CMD} hps_io_sdio_inst_D0 {fragments sdio_inst:SDMMC_DATA_I(0:0) properties {} internal_name hps_io_sdio_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 13} {intermediate 12}} direction bidir role hps_io_sdio_inst_D0} hps_io_sdio_inst_D1 {fragments sdio_inst:SDMMC_DATA_I(1:1) properties {} internal_name hps_io_sdio_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 15} {intermediate 14}} direction bidir role hps_io_sdio_inst_D1} hps_io_sdio_inst_CLK {fragments sdio_inst:SDMMC_CCLK(0:0) properties {} internal_name hps_io_sdio_inst_CLK width 1 instance_name hps_io direction output role hps_io_sdio_inst_CLK} hps_io_sdio_inst_D2 {fragments sdio_inst:SDMMC_DATA_I(2:2) properties {} internal_name hps_io_sdio_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 17} {intermediate 16}} direction bidir role hps_io_sdio_inst_D2} hps_io_sdio_inst_D3 {fragments sdio_inst:SDMMC_DATA_I(3:3) properties {} internal_name hps_io_sdio_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 19} {intermediate 18}} direction bidir role hps_io_sdio_inst_D3} hps_io_usb1_inst_D0 {fragments usb1_inst:USB_ULPI_DATA_I(0:0) properties {} internal_name hps_io_usb1_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 21} {intermediate 20}} direction bidir role hps_io_usb1_inst_D0} hps_io_usb1_inst_D1 {fragments usb1_inst:USB_ULPI_DATA_I(1:1) properties {} internal_name hps_io_usb1_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 23} {intermediate 22}} direction bidir role hps_io_usb1_inst_D1} hps_io_usb1_inst_D2 {fragments usb1_inst:USB_ULPI_DATA_I(2:2) properties {} internal_name hps_io_usb1_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 25} {intermediate 24}} direction bidir role hps_io_usb1_inst_D2} hps_io_usb1_inst_D3 {fragments usb1_inst:USB_ULPI_DATA_I(3:3) properties {} internal_name hps_io_usb1_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 27} {intermediate 26}} direction bidir role hps_io_usb1_inst_D3} hps_io_usb1_inst_D4 {fragments usb1_inst:USB_ULPI_DATA_I(4:4) properties {} internal_name hps_io_usb1_inst_D4 width 1 instance_name hps_io tristate_output {{intermediate 29} {intermediate 28}} direction bidir role hps_io_usb1_inst_D4} hps_io_usb1_inst_D5 {fragments usb1_inst:USB_ULPI_DATA_I(5:5) properties {} internal_name hps_io_usb1_inst_D5 width 1 instance_name hps_io tristate_output {{intermediate 31} {intermediate 30}} direction bidir role hps_io_usb1_inst_D5} hps_io_usb1_inst_D6 {fragments usb1_inst:USB_ULPI_DATA_I(6:6) properties {} internal_name hps_io_usb1_inst_D6 width 1 instance_name hps_io tristate_output {{intermediate 33} {intermediate 32}} direction bidir role hps_io_usb1_inst_D6} hps_io_usb1_inst_D7 {fragments usb1_inst:USB_ULPI_DATA_I(7:7) properties {} internal_name hps_io_usb1_inst_D7 width 1 instance_name hps_io tristate_output {{intermediate 35} {intermediate 34}} direction bidir role hps_io_usb1_inst_D7} hps_io_usb1_inst_CLK {fragments usb1_inst:USB_ULPI_CLK(0:0) properties {} internal_name hps_io_usb1_inst_CLK width 1 instance_name hps_io direction input role hps_io_usb1_inst_CLK} hps_io_usb1_inst_STP {fragments usb1_inst:USB_ULPI_STP(0:0) properties {} internal_name hps_io_usb1_inst_STP width 1 instance_name hps_io direction output role hps_io_usb1_inst_STP} hps_io_usb1_inst_DIR {fragments usb1_inst:USB_ULPI_DIR(0:0) properties {} internal_name hps_io_usb1_inst_DIR width 1 instance_name hps_io direction input role hps_io_usb1_inst_DIR} hps_io_usb1_inst_NXT {fragments usb1_inst:USB_ULPI_NXT(0:0) properties {} internal_name hps_io_usb1_inst_NXT width 1 instance_name hps_io direction input role hps_io_usb1_inst_NXT} hps_io_spim0_inst_CLK {fragments spim0_inst:SPI_MASTER_SCLK(0:0) properties {} internal_name hps_io_spim0_inst_CLK width 1 instance_name hps_io direction output role hps_io_spim0_inst_CLK} hps_io_spim0_inst_MOSI {fragments {} properties {} internal_name hps_io_spim0_inst_MOSI width 1 instance_name hps_io tristate_output {{intermediate 37} {intermediate 36}} direction output role hps_io_spim0_inst_MOSI} hps_io_spim0_inst_MISO {fragments spim0_inst:SPI_MASTER_RXD(0:0) properties {} internal_name hps_io_spim0_inst_MISO width 1 instance_name hps_io direction input role hps_io_spim0_inst_MISO} hps_io_spim0_inst_SS0 {fragments spim0_inst:SPI_MASTER_SS_0_N(0:0) properties {} internal_name hps_io_spim0_inst_SS0 width 1 instance_name hps_io direction output role hps_io_spim0_inst_SS0} hps_io_spim1_inst_CLK {fragments spim1_inst:SPI_MASTER_SCLK(0:0) properties {} internal_name hps_io_spim1_inst_CLK width 1 instance_name hps_io direction output role hps_io_spim1_inst_CLK} hps_io_spim1_inst_MOSI {fragments {} properties {} internal_name hps_io_spim1_inst_MOSI width 1 instance_name hps_io tristate_output {{intermediate 39} {intermediate 38}} direction output role hps_io_spim1_inst_MOSI} hps_io_spim1_inst_MISO {fragments spim1_inst:SPI_MASTER_RXD(0:0) properties {} internal_name hps_io_spim1_inst_MISO width 1 instance_name hps_io direction input role hps_io_spim1_inst_MISO} hps_io_spim1_inst_SS0 {fragments spim1_inst:SPI_MASTER_SS_0_N(0:0) properties {} internal_name hps_io_spim1_inst_SS0 width 1 instance_name hps_io direction output role hps_io_spim1_inst_SS0} hps_io_uart0_inst_RX {fragments uart0_inst:UART_RXD(0:0) properties {} internal_name hps_io_uart0_inst_RX width 1 instance_name hps_io direction input role hps_io_uart0_inst_RX} hps_io_uart0_inst_TX {fragments uart0_inst:UART_TXD(0:0) properties {} internal_name hps_io_uart0_inst_TX width 1 instance_name hps_io direction output role hps_io_uart0_inst_TX} hps_io_i2c1_inst_SDA {fragments i2c1_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c1_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 40} {}} direction bidir role hps_io_i2c1_inst_SDA} hps_io_i2c1_inst_SCL {fragments i2c1_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c1_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 41} {}} direction bidir role hps_io_i2c1_inst_SCL}}}} raw_assign_sim_style {}
hps_parameter_map | AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes HPS pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 1.25 QSPI_Mode {1 SS} CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 32 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 4 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false MEM_TRCD 6 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSXFC6D6F31C8ES HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 14 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 64 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} sdmmc_clk_in {0 clk_in} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 125 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.02 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 32 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 SDMMC_FB_CLK_IN SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 100 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 2500.0 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 30 PLL_WRITE_CLK_PHASE_PS_CACHE 1875 UART0_PinMuxing {HPS I/O Set 0} F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 MEM_IF_CLK_EN_WIDTH 1 QSPI_PinMuxing {HPS I/O Set 0} INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode RGMII NIOS_ROM_ADDRESS_WIDTH 13 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 2.5 PLL_AFI_CLK_MULT_CACHE 32 PLL_ADDR_CMD_CLK_DIV 2 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 32 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes SDR pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes SDR pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {45000 ps} PLL_AFI_CLK_DIV 2 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 13.75 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 400.0 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 2 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 CLK_IN CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} {SDMMC_FB_CLK(0:0) {} {}} {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.8 PLL_DR_CLK_FREQ_SIM_STR {0 ps} PLL_HR_CLK_DIV_PARAM 0 TIMING_BOARD_SKEW_BETWEEN_DQS 0.08 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 100 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 TIMING_TIS 180 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {25.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.03 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 6 TIMING_TIH 140 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing {HPS I/O Set 0} BYTE_ENABLE true TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_8 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 1875 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 30 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 6 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 65 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {2500 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 20 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 32 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} AVL_DATA_WIDTH 64 PLL_AFI_PHY_CLK_FREQ 400.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000110 GPIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 4 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {400.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode N/A IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} VECT_ATTR_DEBUG_SELECT_BYTE 0 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.09 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 CV_LSB_RFIFO_PORT_2 5 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 35.0 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 2 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false PLL_MEM_CLK_FREQ_SIM_STR {2500 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED true TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode {No Flow Control} S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 800.0 CV_LSB_WFIFO_PORT_3 5 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 1875 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 100 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 8 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 10 TRK_PARALLEL_SCC_LOAD false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode {Single Slave Select} hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM RZQ/4 AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 40000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_6 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 13.75 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 8 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED CV_ENUM_PORT5_WIDTH PORT_32_BIT CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.16 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 40.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 2 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 400.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable true ENUM_MEM_IF_TRP TRP_6 MR2_RTT_WR 1 MEM_TCL 11 JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 104 USE_2X_FF false ENUM_MEM_IF_TRC TRC_20 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 AVL_ADDR_WIDTH 27 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable true USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 2 F2SDRAM_Width {} PLL_AFI_CLK_FREQ 400.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.18 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 400.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 66.6666666667 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {2500 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {1875 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 15 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} PLL_AFI_HALF_CLK_MULT_CACHE 32 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 32 AV_PORT_4_CONNECT_TO_CV_PORT 4 PLL_AFI_HALF_CLK_FREQ_CACHE 400.0 AFI_WRITE_DQS_WIDTH 4 ENUM_OUTPUT_REGD DISABLED PLL_MEM_CLK_PHASE_DEG_SIM 0.0 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.16 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 10 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 TIMING_BOARD_TIS_APPLIED 0.33 CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {1875 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {2500 ps} PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 15 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {1875 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0010011101000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/7 MEM_IF_DM_WIDTH 4 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.5 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDIO_CLK_IN 100 MEM_DQ_WIDTH 32 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 32 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 30.0 DELAY_PER_OPA_TAP 312 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing {HPS I/O Set 0} MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {2500 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 6000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 2 ENUM_MEM_IF_TCL TCL_11 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 MEM_VENDOR Micron FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes SDR pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing {HPS I/O Set 0} CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_3 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 2 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 AVL_NUM_SYMBOLS_PORT_1 1 AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} S2FCLK_USER0CLK_FREQ 100 MR2_CWL 3 PLL_P2C_READ_CLK_DIV_PARAM 0 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 131 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875 MEM_MIRROR_ADDRESSING 0 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 400.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 15 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 MR0_BT 0 PLL_CONFIG_CLK_FREQ 22.2222222222 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 1 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {400.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} PLL_MEM_CLK_MULT_CACHE 32 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR RZQ/4 TIMING_TDQSCK 255 REF_CLK_FREQ_CACHE 25.0 AC_ROM_MR0_DLL_RESET 0010101110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {15000 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0010001101001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 100 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 12 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 100 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {400.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing Unused MEM_TREFI 3120 VFIFO_AS_SHIFT_REG true PLL_WRITE_CLK_MULT 32 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.09 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {2500 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 4 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 10 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_6 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 50000000 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.165 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 500 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 32 TIMING_BOARD_SKEW_WITHIN_DQS 0.01 ENUM_MEM_IF_TRAS TRAS_14 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 1 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode {Single Slave Select} AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.03 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 7 H2F_LW_AXI_CLOCK_FREQ 50000000 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {400.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 2 PHY_CLKBUF false PLL_WRITE_CLK_PHASE_PS_STR {1875 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false CV_PORT_0_CONNECT_TO_AV_PORT 0 PLL_MEM_CLK_DIV_CACHE 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_32 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 8 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.24 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing {HPS I/O Set 0} INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 MEM_CLK_FREQ_CACHE 400.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 25.0 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 2 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output} @orderednames {sdio sdio_reset sdio_clk_in sdio_cclk} sdio_clk_in {@no_export 0 properties {} type clock direction Input}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 4 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {5000 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 8 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 11 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0001000011000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 DEFAULT_FAST_SIM_MODEL true ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode I2C quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 3120 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 1875 PLL_SHARING_MODE None ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {400.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 260.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY true ENUM_PRIORITY_5_1 WEIGHT_0 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} sdio_clk_in {sdmmc_clk_in {atom_signal_name clk_in direction Input role clk} @orderednames sdmmc_clk_in} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 3 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE pin_muxing_check {Cyclone V+5CSXFC6D6F31C8ES} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 2 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 200000 PLL_WRITE_CLK_MULT_CACHE 32 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 400.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 4 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing {HPS I/O Set 0} PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} USB1.D0 USB1.D1 USB1.D2 USB1.D3 USB1.D4 USB1.D5 USB1.D6 USB1.D7 {} USB1.CLK USB1.STP USB1.DIR USB1.NXT EMAC1.TX_CLK EMAC1.TXD0 EMAC1.TXD1 EMAC1.TXD2 EMAC1.TXD3 EMAC1.RXD0 EMAC1.MDIO EMAC1.MDC EMAC1.RX_CTL EMAC1.TX_CTL EMAC1.RX_CLK EMAC1.RXD1 EMAC1.RXD2 EMAC1.RXD3 {} QSPI.IO0 QSPI.IO1 QSPI.IO2 QSPI.IO3 QSPI.SS0 QSPI.CLK {} SDIO.CMD {} SDIO.D0 SDIO.D1 {} {} {} {} {} SDIO.CLK SDIO.D2 SDIO.D3 {} UART0.RX UART0.TX I2C1.SDA I2C1.SCL {} {} {} {} SPIM0.CLK SPIM0.MOSI SPIM0.MISO SPIM0.SS0 {} {} SPIM1.CLK SPIM1.MOSI SPIM1.MISO SPIM1.SS0} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 8 MR1_AL 0 PLL_MEM_CLK_FREQ_CACHE 400.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 8 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 32 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0001000011000 S2FCLK_USER1CLK_FREQ 100 AC_ROM_MR1 0000000000110 TB_MEM_CLK_FREQ 400.0 AC_ROM_MR0 0010001110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 18000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 400.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {2500 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 100 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 5 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_4 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing {HPS I/O Set 0} CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 ENUM_THLD_JAR1_2 THRESHOLD_32 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {5000 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode SDR ENUM_CLOCK_OFF_1 DISABLED ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.4 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 400.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes SDR pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 CLK_IN CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} {SDMMC_FB_CLK(0:0) {} {}} {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes HPS pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes SDR pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes SDR pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 SDMMC_FB_CLK_IN SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 2 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 1250.0 S2FCLK_USER1CLK_Enable false SDIO_Mode {4-bit Data} MEM_TRFC 104 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2
AC_ROM_MR0 |
AC_ROM_MR0_MIRR |
AC_ROM_MR0_CALIB |
AC_ROM_MR0_DLL_RESET |
AC_ROM_MR0_DLL_RESET_MIRR |
AC_ROM_MR1 |
AC_ROM_MR1_MIRR |
AC_ROM_MR1_CALIB |
AC_ROM_MR1_OCD_ENABLE |
AC_ROM_MR2 |
AC_ROM_MR2_MIRR |
AC_ROM_MR3 |
AC_ROM_MR3_MIRR |
USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY | false
MR0_BL | 2
MR0_BT | 0
MR0_CAS_LATENCY | 3
MR0_DLL | 1
MR0_WR | 4
MR0_PD | 0
MR1_DLL | 0
MR1_ODS | 1
MR1_RTT | 1
MR1_AL | 0
MR1_WL | 0
MR1_TDQS | 0
MR1_QOFF | 0
MR1_DQS | 0
MR1_RDQS | 0
MR2_CWL | 1
MR2_ASR | 0
MR2_SRT | 0
MR2_SRF | 0
MR2_RTT_WR | 1
MR3_MPR_RF | 0
MR3_MPR | 0
MR3_MPR_AA | 0
MR1_BL | 2
MR1_BT | 0
MR1_WC | 0
MR1_WR | 1
MR2_RLWL | 1
MR3_DS | 2
MR1_DS | 0
MR1_PASR | 0
MEM_IF_READ_DQS_WIDTH | 0
MEM_IF_WRITE_DQS_WIDTH | 0
SCC_DATA_WIDTH | 0
MEM_IF_ADDR_WIDTH | 0
MEM_IF_ADDR_WIDTH_MIN | 10
MEM_IF_ROW_ADDR_WIDTH | 0
MEM_IF_COL_ADDR_WIDTH | 0
MEM_IF_DM_WIDTH | 0
MEM_IF_CS_PER_RANK | 0
MEM_IF_NUMBER_OF_RANKS | 0
MEM_IF_CS_PER_DIMM | 0
MEM_IF_CONTROL_WIDTH | 0
MEM_BURST_LENGTH | 8
MEM_LEVELING | true
MEM_IF_DQS_WIDTH | 0
MEM_IF_CS_WIDTH | 0
MEM_IF_CHIP_BITS | -1
MEM_IF_BANKADDR_WIDTH | 0
MEM_IF_DQ_WIDTH | 0
MEM_IF_CK_WIDTH | 0
MEM_IF_CLK_EN_WIDTH | 0
MEM_IF_CLK_PAIR_COUNT | 1
DEVICE_WIDTH | 1
MEM_CLK_MAX_NS | 2.5
MEM_CLK_MAX_PS | 2500.0
MEM_TRC | 0
MEM_TRAS | 0
MEM_TRCD | 0
MEM_TRP | 0
MEM_TREFI | 0
MEM_TRFC | 0
CFG_TCCD | 0
MEM_TWR | 0
MEM_TFAW | 0
MEM_TRRD | 0
MEM_TRTP | 0
MEM_DQS_TO_CLK_CAPTURE_DELAY | 0
MEM_CLK_TO_DQS_CAPTURE_DELAY | 0
MEM_IF_ODT_WIDTH | 0
MEM_WTCL_INT | 6
FLY_BY | true
RDIMM | false
LRDIMM | false
RDIMM_INT | 0
LRDIMM_INT | 0
MEM_IF_RD_TO_WR_TURNAROUND_OCT | 0
MEM_IF_WR_TO_RD_TURNAROUND_OCT | 3
CTL_RD_TO_PCH_EXTRA_CLK | 0
CTL_RD_TO_RD_EXTRA_CLK | 0
CTL_WR_TO_WR_EXTRA_CLK | 0
CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK | 0
CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK | 0
MEM_TYPE |
MEM_MIRROR_ADDRESSING_DEC | 0
MEM_ATCL_INT | 0
MEM_REGDIMM_ENABLED | false
MEM_LRDIMM_ENABLED | false
MEM_VENDOR | Micron
MEM_FORMAT | DISCRETE
AC_PARITY | false
RDIMM_CONFIG | 0000000000000000
LRDIMM_EXTENDED_CONFIG | 0x000000000000000000
DISCRETE_FLY_BY | true
DEVICE_DEPTH | 1
MEM_MIRROR_ADDRESSING | 0
MEM_CLK_FREQ_MAX | 800.0
MEM_ROW_ADDR_WIDTH | 15
MEM_COL_ADDR_WIDTH | 10
MEM_DQ_WIDTH | 32
MEM_DQ_PER_DQS | 8
MEM_BANKADDR_WIDTH | 3
MEM_IF_DM_PINS_EN | true
MEM_IF_DQSN_EN | true
MEM_NUMBER_OF_DIMMS | 1
MEM_NUMBER_OF_RANKS_PER_DIMM | 1
MEM_NUMBER_OF_RANKS_PER_DEVICE | 1
MEM_RANK_MULTIPLICATION_FACTOR | 1
MEM_CK_WIDTH | 1
MEM_CS_WIDTH | 1
MEM_CLK_EN_WIDTH | 1
ALTMEMPHY_COMPATIBLE_MODE | false
NEXTGEN | true
MEM_IF_BOARD_BASE_DELAY | 10
MEM_IF_SIM_VALID_WINDOW | 0
MEM_GUARANTEED_WRITE_INIT | false
MEM_VERBOSE | true
PINGPONGPHY_EN | false
REFRESH_BURST_VALIDATION | false
MEM_BL | OTF
MEM_BT | Sequential
MEM_ASR | Manual
MEM_SRT | Normal
MEM_PD | DLL off
MEM_DRV_STR | RZQ/7
MEM_DLL_EN | true
MEM_RTT_NOM | RZQ/4
MEM_RTT_WR | RZQ/4
MEM_WTCL | 8
MEM_ATCL | Disabled
MEM_TCL | 11
MEM_AUTO_LEVELING_MODE | true
MEM_USER_LEVELING_MODE | Leveling
MEM_INIT_EN | false
MEM_INIT_FILE |
DAT_DATA_WIDTH | 32
TIMING_TIS | 180
TIMING_TIH | 140
TIMING_TDS | 30
TIMING_TDH | 65
TIMING_TDQSQ | 125
TIMING_TQHS | 300
TIMING_TQH | 0.38
TIMING_TDQSCK | 255
TIMING_TDQSCKDS | 450
TIMING_TDQSCKDM | 900
TIMING_TDQSCKDL | 1200
TIMING_TDQSS | 0.25
TIMING_TDQSH | 0.35
TIMING_TQSH | 0.4
TIMING_TDSH | 0.2
TIMING_TDSS | 0.2
MEM_TINIT_US | 500
MEM_TINIT_CK | 499
MEM_TDQSCK | 2
MEM_TMRD_CK | 4
MEM_TRAS_NS | 35.0
MEM_TRCD_NS | 13.75
MEM_TRP_NS | 13.75
MEM_TREFI_US | 7.8
MEM_TRFC_NS | 260.0
CFG_TCCD_NS | 2.5
MEM_TWR_NS | 15.0
MEM_TWTR | 4
MEM_TFAW_NS | 30.0
MEM_TRRD_NS | 7.5
MEM_TRTP_NS | 7.5
EXPORT_CSR_PORT | false
CSR_ADDR_WIDTH | 8
CSR_DATA_WIDTH | 32
CSR_BE_WIDTH | 4
CTL_CS_WIDTH | 0
AVL_ADDR_WIDTH | 0
AVL_BE_WIDTH | 0
AVL_DATA_WIDTH | 0
AVL_SYMBOL_WIDTH | 8
AVL_NUM_SYMBOLS | 2
AVL_SIZE_WIDTH | 0
HR_DDIO_OUT_HAS_THREE_REGS | false
CTL_ECC_CSR_ENABLED | false
DWIDTH_RATIO | 4
CTL_ODT_ENABLED | false
CTL_OUTPUT_REGD | false
CTL_ECC_MULTIPLES_40_72 | 0
CTL_ECC_MULTIPLES_16_24_40_72 | 0
CTL_REGDIMM_ENABLED | false
LOW_LATENCY | false
CONTROLLER_TYPE | nextgen_v110
CTL_TBP_NUM | 4
CTL_USR_REFRESH | 0
CTL_SELF_REFRESH | 0
CFG_TYPE | 0
CFG_INTERFACE_WIDTH | 0
CFG_BURST_LENGTH | 0
CFG_ADDR_ORDER | 0
CFG_PDN_EXIT_CYCLES | 0
CFG_POWER_SAVING_EXIT_CYCLES | 0
CFG_MEM_CLK_ENTRY_CYCLES | 0
CFG_SELF_RFSH_EXIT_CYCLES | 0
CFG_PORT_WIDTH_WRITE_ODT_CHIP | 0
CFG_PORT_WIDTH_READ_ODT_CHIP | 0
CFG_WRITE_ODT_CHIP | 0
CFG_READ_ODT_CHIP | 0
LOCAL_CS_WIDTH | 0
CFG_CLR_INTR | 0
CFG_ENABLE_NO_DM | 0
MEM_ADD_LAT | 0
CTL_ENABLE_BURST_INTERRUPT_INT | false
CTL_ENABLE_BURST_TERMINATE_INT | false
CFG_ERRCMD_FIFO_REG | 0
CFG_ECC_DECODER_REG | 0
CTL_ENABLE_WDATA_PATH_LATENCY | false
CFG_STARVE_LIMIT | 0
MEM_AUTO_PD_CYCLES | 0
AVL_PORT |
AVL_DATA_WIDTH_PORT_0 | 0
AVL_ADDR_WIDTH_PORT_0 | 0
PRIORITY_PORT_0 | 0
WEIGHT_PORT_0 | 0
CPORT_TYPE_PORT_0 | 0
AVL_NUM_SYMBOLS_PORT_0 | 2
LSB_WFIFO_PORT_0 | 5
MSB_WFIFO_PORT_0 | 5
LSB_RFIFO_PORT_0 | 5
MSB_RFIFO_PORT_0 | 5
AVL_DATA_WIDTH_PORT_1 | 0
AVL_ADDR_WIDTH_PORT_1 | 0
PRIORITY_PORT_1 | 0
WEIGHT_PORT_1 | 0
CPORT_TYPE_PORT_1 | 0
AVL_NUM_SYMBOLS_PORT_1 | 2
LSB_WFIFO_PORT_1 | 5
MSB_WFIFO_PORT_1 | 5
LSB_RFIFO_PORT_1 | 5
MSB_RFIFO_PORT_1 | 5
AVL_DATA_WIDTH_PORT_2 | 0
AVL_ADDR_WIDTH_PORT_2 | 0
PRIORITY_PORT_2 | 0
WEIGHT_PORT_2 | 0
CPORT_TYPE_PORT_2 | 0
AVL_NUM_SYMBOLS_PORT_2 | 2
LSB_WFIFO_PORT_2 | 5
MSB_WFIFO_PORT_2 | 5
LSB_RFIFO_PORT_2 | 5
MSB_RFIFO_PORT_2 | 5
AVL_DATA_WIDTH_PORT_3 | 0
AVL_ADDR_WIDTH_PORT_3 | 0
PRIORITY_PORT_3 | 0
WEIGHT_PORT_3 | 0
CPORT_TYPE_PORT_3 | 0
AVL_NUM_SYMBOLS_PORT_3 | 2
LSB_WFIFO_PORT_3 | 5
MSB_WFIFO_PORT_3 | 5
LSB_RFIFO_PORT_3 | 5
MSB_RFIFO_PORT_3 | 5
AVL_DATA_WIDTH_PORT_4 | 0
AVL_ADDR_WIDTH_PORT_4 | 0
PRIORITY_PORT_4 | 0
WEIGHT_PORT_4 | 0
CPORT_TYPE_PORT_4 | 0
AVL_NUM_SYMBOLS_PORT_4 | 2
LSB_WFIFO_PORT_4 | 5
MSB_WFIFO_PORT_4 | 5
LSB_RFIFO_PORT_4 | 5
MSB_RFIFO_PORT_4 | 5
AVL_DATA_WIDTH_PORT_5 | 0
AVL_ADDR_WIDTH_PORT_5 | 0
PRIORITY_PORT_5 | 0
WEIGHT_PORT_5 | 0
CPORT_TYPE_PORT_5 | 0
AVL_NUM_SYMBOLS_PORT_5 | 2
LSB_WFIFO_PORT_5 | 5
MSB_WFIFO_PORT_5 | 5
LSB_RFIFO_PORT_5 | 5
MSB_RFIFO_PORT_5 | 5
ALLOCATED_RFIFO_PORT | 0,None,None,None,None,None
ALLOCATED_WFIFO_PORT | 0,None,None,None,None,None
ENUM_ATTR_COUNTER_ONE_RESET | DISABLED
ENUM_ATTR_COUNTER_ZERO_RESET | DISABLED
ENUM_ATTR_STATIC_CONFIG_VALID | DISABLED
ENUM_AUTO_PCH_ENABLE_0 | DISABLED
ENUM_AUTO_PCH_ENABLE_1 | DISABLED
ENUM_AUTO_PCH_ENABLE_2 | DISABLED
ENUM_AUTO_PCH_ENABLE_3 | DISABLED
ENUM_AUTO_PCH_ENABLE_4 | DISABLED
ENUM_AUTO_PCH_ENABLE_5 | DISABLED
ENUM_CAL_REQ | DISABLED
ENUM_CFG_BURST_LENGTH | BL_8
ENUM_CFG_INTERFACE_WIDTH | DWIDTH_32
ENUM_CFG_SELF_RFSH_EXIT_CYCLES |
ENUM_CFG_STARVE_LIMIT | STARVE_LIMIT_32
ENUM_CFG_TYPE | DDR3
ENUM_CLOCK_OFF_0 | DISABLED
ENUM_CLOCK_OFF_1 | DISABLED
ENUM_CLOCK_OFF_2 | DISABLED
ENUM_CLOCK_OFF_3 | DISABLED
ENUM_CLOCK_OFF_4 | DISABLED
ENUM_CLOCK_OFF_5 | DISABLED
ENUM_CLR_INTR | NO_CLR_INTR
ENUM_CMD_PORT_IN_USE_0 | FALSE
ENUM_CMD_PORT_IN_USE_1 | FALSE
ENUM_CMD_PORT_IN_USE_2 | FALSE
ENUM_CMD_PORT_IN_USE_3 | FALSE
ENUM_CMD_PORT_IN_USE_4 | FALSE
ENUM_CMD_PORT_IN_USE_5 | FALSE
ENUM_CPORT0_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT0_RFIFO_MAP | FIFO_0
ENUM_CPORT0_TYPE | DISABLE
ENUM_CPORT0_WFIFO_MAP | FIFO_0
ENUM_CPORT1_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT1_RFIFO_MAP | FIFO_0
ENUM_CPORT1_TYPE | DISABLE
ENUM_CPORT1_WFIFO_MAP | FIFO_0
ENUM_CPORT2_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT2_RFIFO_MAP | FIFO_0
ENUM_CPORT2_TYPE | DISABLE
ENUM_CPORT2_WFIFO_MAP | FIFO_0
ENUM_CPORT3_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT3_RFIFO_MAP | FIFO_0
ENUM_CPORT3_TYPE | DISABLE
ENUM_CPORT3_WFIFO_MAP | FIFO_0
ENUM_CPORT4_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT4_RFIFO_MAP | FIFO_0
ENUM_CPORT4_TYPE | DISABLE
ENUM_CPORT4_WFIFO_MAP | FIFO_0
ENUM_CPORT5_RDY_ALMOST_FULL | NOT_FULL
ENUM_CPORT5_RFIFO_MAP | FIFO_0
ENUM_CPORT5_TYPE | DISABLE
ENUM_CPORT5_WFIFO_MAP | FIFO_0
ENUM_CTL_ADDR_ORDER | CHIP_BANK_ROW_COL
ENUM_CTL_ECC_ENABLED | CTL_ECC_DISABLED
ENUM_CTL_ECC_RMW_ENABLED | CTL_ECC_RMW_DISABLED
ENUM_CTL_REGDIMM_ENABLED | REGDIMM_DISABLED
ENUM_CTL_USR_REFRESH | CTL_USR_REFRESH_DISABLED
ENUM_CTRL_WIDTH | DATA_WIDTH_64_BIT
ENUM_DELAY_BONDING | BONDING_LATENCY_0
ENUM_DFX_BYPASS_ENABLE | DFX_BYPASS_DISABLED
ENUM_DISABLE_MERGING | MERGING_ENABLED
ENUM_ECC_DQ_WIDTH | ECC_DQ_WIDTH_0
ENUM_ENABLE_ATPG | DISABLED
ENUM_ENABLE_BONDING_0 | DISABLED
ENUM_ENABLE_BONDING_1 | DISABLED
ENUM_ENABLE_BONDING_2 | DISABLED
ENUM_ENABLE_BONDING_3 | DISABLED
ENUM_ENABLE_BONDING_4 | DISABLED
ENUM_ENABLE_BONDING_5 | DISABLED
ENUM_ENABLE_BONDING_WRAPBACK | DISABLED
ENUM_ENABLE_DQS_TRACKING | DISABLED
ENUM_ENABLE_ECC_CODE_OVERWRITES | DISABLED
ENUM_ENABLE_FAST_EXIT_PPD | DISABLED
ENUM_ENABLE_INTR | DISABLED
ENUM_ENABLE_NO_DM | DISABLED
ENUM_ENABLE_PIPELINEGLOBAL | DISABLED
ENUM_GANGED_ARF | DISABLED
ENUM_GEN_DBE | GEN_DBE_DISABLED
ENUM_GEN_SBE | GEN_SBE_DISABLED
ENUM_INC_SYNC | FIFO_SET_2
ENUM_LOCAL_IF_CS_WIDTH | ADDR_WIDTH_2
ENUM_MASK_CORR_DROPPED_INTR | DISABLED
ENUM_MASK_DBE_INTR | DISABLED
ENUM_MASK_SBE_INTR | DISABLED
ENUM_MEM_IF_AL | AL_0
ENUM_MEM_IF_BANKADDR_WIDTH | ADDR_WIDTH_3
ENUM_MEM_IF_BURSTLENGTH | MEM_IF_BURSTLENGTH_8
ENUM_MEM_IF_COLADDR_WIDTH | ADDR_WIDTH_12
ENUM_MEM_IF_CS_PER_RANK | MEM_IF_CS_PER_RANK_1
ENUM_MEM_IF_CS_WIDTH | MEM_IF_CS_WIDTH_1
ENUM_MEM_IF_DQ_PER_CHIP | MEM_IF_DQ_PER_CHIP_8
ENUM_MEM_IF_DQS_WIDTH | DQS_WIDTH_4
ENUM_MEM_IF_DWIDTH | MEM_IF_DWIDTH_32
ENUM_MEM_IF_MEMTYPE | DDR3_SDRAM
ENUM_MEM_IF_ROWADDR_WIDTH | ADDR_WIDTH_16
ENUM_MEM_IF_SPEEDBIN | DDR3_1066_6_6_6
ENUM_MEM_IF_TCCD | TCCD_4
ENUM_MEM_IF_TCL | TCL_6
ENUM_MEM_IF_TCWL | TCWL_5
ENUM_MEM_IF_TFAW | TFAW_16
ENUM_MEM_IF_TMRD |
ENUM_MEM_IF_TRAS | TRAS_16
ENUM_MEM_IF_TRC | TRC_22
ENUM_MEM_IF_TRCD | TRCD_6
ENUM_MEM_IF_TRP | TRP_6
ENUM_MEM_IF_TRRD | TRRD_4
ENUM_MEM_IF_TRTP | TRTP_4
ENUM_MEM_IF_TWR | TWR_6
ENUM_MEM_IF_TWTR | TWTR_4
ENUM_MMR_CFG_MEM_BL | MP_BL_8
ENUM_OUTPUT_REGD | DISABLED
ENUM_PDN_EXIT_CYCLES | SLOW_EXIT
ENUM_PORT0_WIDTH | PORT_64_BIT
ENUM_PORT1_WIDTH | PORT_64_BIT
ENUM_PORT2_WIDTH | PORT_64_BIT
ENUM_PORT3_WIDTH | PORT_64_BIT
ENUM_PORT4_WIDTH | PORT_64_BIT
ENUM_PORT5_WIDTH | PORT_64_BIT
ENUM_PRIORITY_0_0 | WEIGHT_0
ENUM_PRIORITY_0_1 | WEIGHT_0
ENUM_PRIORITY_0_2 | WEIGHT_0
ENUM_PRIORITY_0_3 | WEIGHT_0
ENUM_PRIORITY_0_4 | WEIGHT_0
ENUM_PRIORITY_0_5 | WEIGHT_0
ENUM_PRIORITY_1_0 | WEIGHT_0
ENUM_PRIORITY_1_1 | WEIGHT_0
ENUM_PRIORITY_1_2 | WEIGHT_0
ENUM_PRIORITY_1_3 | WEIGHT_0
ENUM_PRIORITY_1_4 | WEIGHT_0
ENUM_PRIORITY_1_5 | WEIGHT_0
ENUM_PRIORITY_2_0 | WEIGHT_0
ENUM_PRIORITY_2_1 | WEIGHT_0
ENUM_PRIORITY_2_2 | WEIGHT_0
ENUM_PRIORITY_2_3 | WEIGHT_0
ENUM_PRIORITY_2_4 | WEIGHT_0
ENUM_PRIORITY_2_5 | WEIGHT_0
ENUM_PRIORITY_3_0 | WEIGHT_0
ENUM_PRIORITY_3_1 | WEIGHT_0
ENUM_PRIORITY_3_2 | WEIGHT_0
ENUM_PRIORITY_3_3 | WEIGHT_0
ENUM_PRIORITY_3_4 | WEIGHT_0
ENUM_PRIORITY_3_5 | WEIGHT_0
ENUM_PRIORITY_4_0 | WEIGHT_0
ENUM_PRIORITY_4_1 | WEIGHT_0
ENUM_PRIORITY_4_2 | WEIGHT_0
ENUM_PRIORITY_4_3 | WEIGHT_0
ENUM_PRIORITY_4_4 | WEIGHT_0
ENUM_PRIORITY_4_5 | WEIGHT_0
ENUM_PRIORITY_5_0 | WEIGHT_0
ENUM_PRIORITY_5_1 | WEIGHT_0
ENUM_PRIORITY_5_2 | WEIGHT_0
ENUM_PRIORITY_5_3 | WEIGHT_0
ENUM_PRIORITY_5_4 | WEIGHT_0
ENUM_PRIORITY_5_5 | WEIGHT_0
ENUM_PRIORITY_6_0 | WEIGHT_0
ENUM_PRIORITY_6_1 | WEIGHT_0
ENUM_PRIORITY_6_2 | WEIGHT_0
ENUM_PRIORITY_6_3 | WEIGHT_0
ENUM_PRIORITY_6_4 | WEIGHT_0
ENUM_PRIORITY_6_5 | WEIGHT_0
ENUM_PRIORITY_7_0 | WEIGHT_0
ENUM_PRIORITY_7_1 | WEIGHT_0
ENUM_PRIORITY_7_2 | WEIGHT_0
ENUM_PRIORITY_7_3 | WEIGHT_0
ENUM_PRIORITY_7_4 | WEIGHT_0
ENUM_PRIORITY_7_5 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_0 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_1 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_2 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_3 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_4 | WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_5 | WEIGHT_0
ENUM_RCFG_USER_PRIORITY_0 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_1 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_2 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_3 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_4 | PRIORITY_0
ENUM_RCFG_USER_PRIORITY_5 | PRIORITY_0
ENUM_RD_DWIDTH_0 | DWIDTH_0
ENUM_RD_DWIDTH_1 | DWIDTH_0
ENUM_RD_DWIDTH_2 | DWIDTH_0
ENUM_RD_DWIDTH_3 | DWIDTH_0
ENUM_RD_DWIDTH_4 | DWIDTH_0
ENUM_RD_DWIDTH_5 | DWIDTH_0
ENUM_RD_FIFO_IN_USE_0 | FALSE
ENUM_RD_FIFO_IN_USE_1 | FALSE
ENUM_RD_FIFO_IN_USE_2 | FALSE
ENUM_RD_FIFO_IN_USE_3 | FALSE
ENUM_RD_PORT_INFO_0 | USE_NO
ENUM_RD_PORT_INFO_1 | USE_NO
ENUM_RD_PORT_INFO_2 | USE_NO
ENUM_RD_PORT_INFO_3 | USE_NO
ENUM_RD_PORT_INFO_4 | USE_NO
ENUM_RD_PORT_INFO_5 | USE_NO
ENUM_READ_ODT_CHIP | ODT_DISABLED
ENUM_REORDER_DATA | DATA_REORDERING
ENUM_RFIFO0_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO1_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO2_CPORT_MAP | CMD_PORT_0
ENUM_RFIFO3_CPORT_MAP | CMD_PORT_0
ENUM_SINGLE_READY_0 | CONCATENATE_RDY
ENUM_SINGLE_READY_1 | CONCATENATE_RDY
ENUM_SINGLE_READY_2 | CONCATENATE_RDY
ENUM_SINGLE_READY_3 | CONCATENATE_RDY
ENUM_STATIC_WEIGHT_0 | WEIGHT_0
ENUM_STATIC_WEIGHT_1 | WEIGHT_0
ENUM_STATIC_WEIGHT_2 | WEIGHT_0
ENUM_STATIC_WEIGHT_3 | WEIGHT_0
ENUM_STATIC_WEIGHT_4 | WEIGHT_0
ENUM_STATIC_WEIGHT_5 | WEIGHT_0
ENUM_SYNC_MODE_0 | ASYNCHRONOUS
ENUM_SYNC_MODE_1 | ASYNCHRONOUS
ENUM_SYNC_MODE_2 | ASYNCHRONOUS
ENUM_SYNC_MODE_3 | ASYNCHRONOUS
ENUM_SYNC_MODE_4 | ASYNCHRONOUS
ENUM_SYNC_MODE_5 | ASYNCHRONOUS
ENUM_TEST_MODE | NORMAL_MODE
ENUM_THLD_JAR1_0 | THRESHOLD_32
ENUM_THLD_JAR1_1 | THRESHOLD_32
ENUM_THLD_JAR1_2 | THRESHOLD_32
ENUM_THLD_JAR1_3 | THRESHOLD_32
ENUM_THLD_JAR1_4 | THRESHOLD_32
ENUM_THLD_JAR1_5 | THRESHOLD_32
ENUM_THLD_JAR2_0 | THRESHOLD_16
ENUM_THLD_JAR2_1 | THRESHOLD_16
ENUM_THLD_JAR2_2 | THRESHOLD_16
ENUM_THLD_JAR2_3 | THRESHOLD_16
ENUM_THLD_JAR2_4 | THRESHOLD_16
ENUM_THLD_JAR2_5 | THRESHOLD_16
ENUM_USE_ALMOST_EMPTY_0 | EMPTY
ENUM_USE_ALMOST_EMPTY_1 | EMPTY
ENUM_USE_ALMOST_EMPTY_2 | EMPTY
ENUM_USE_ALMOST_EMPTY_3 | EMPTY
ENUM_USER_ECC_EN | DISABLE
ENUM_USER_PRIORITY_0 | PRIORITY_0
ENUM_USER_PRIORITY_1 | PRIORITY_0
ENUM_USER_PRIORITY_2 | PRIORITY_0
ENUM_USER_PRIORITY_3 | PRIORITY_0
ENUM_USER_PRIORITY_4 | PRIORITY_0
ENUM_USER_PRIORITY_5 | PRIORITY_0
ENUM_WFIFO0_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO0_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO1_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO1_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO2_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO2_RDY_ALMOST_FULL | NOT_FULL
ENUM_WFIFO3_CPORT_MAP | CMD_PORT_0
ENUM_WFIFO3_RDY_ALMOST_FULL | NOT_FULL
ENUM_WR_DWIDTH_0 | DWIDTH_0
ENUM_WR_DWIDTH_1 | DWIDTH_0
ENUM_WR_DWIDTH_2 | DWIDTH_0
ENUM_WR_DWIDTH_3 | DWIDTH_0
ENUM_WR_DWIDTH_4 | DWIDTH_0
ENUM_WR_DWIDTH_5 | DWIDTH_0
ENUM_WR_FIFO_IN_USE_0 | FALSE
ENUM_WR_FIFO_IN_USE_1 | FALSE
ENUM_WR_FIFO_IN_USE_2 | FALSE
ENUM_WR_FIFO_IN_USE_3 | FALSE
ENUM_WR_PORT_INFO_0 | USE_NO
ENUM_WR_PORT_INFO_1 | USE_NO
ENUM_WR_PORT_INFO_2 | USE_NO
ENUM_WR_PORT_INFO_3 | USE_NO
ENUM_WR_PORT_INFO_4 | USE_NO
ENUM_WR_PORT_INFO_5 | USE_NO
ENUM_WRITE_ODT_CHIP | ODT_DISABLED
INTG_MEM_AUTO_PD_CYCLES | 0
INTG_CYC_TO_RLD_JARS_0 | 1
INTG_CYC_TO_RLD_JARS_1 | 1
INTG_CYC_TO_RLD_JARS_2 | 1
INTG_CYC_TO_RLD_JARS_3 | 1
INTG_CYC_TO_RLD_JARS_4 | 1
INTG_CYC_TO_RLD_JARS_5 | 1
INTG_EXTRA_CTL_CLK_ACT_TO_ACT | 0
INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK | 0
INTG_EXTRA_CTL_CLK_ACT_TO_PCH | 0
INTG_EXTRA_CTL_CLK_ACT_TO_RDWR | 0
INTG_EXTRA_CTL_CLK_ARF_PERIOD | 0
INTG_EXTRA_CTL_CLK_ARF_TO_VALID | 0
INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT | 0
INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID | 0
INTG_EXTRA_CTL_CLK_PCH_TO_VALID | 0
INTG_EXTRA_CTL_CLK_PDN_PERIOD | 0
INTG_EXTRA_CTL_CLK_PDN_TO_VALID | 0
INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID | 0
INTG_EXTRA_CTL_CLK_RD_TO_PCH | 0
INTG_EXTRA_CTL_CLK_RD_TO_RD | 0
INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP | 0
INTG_EXTRA_CTL_CLK_RD_TO_WR | 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_BC | 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP | 0
INTG_EXTRA_CTL_CLK_SRF_TO_VALID | 0
INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL | 0
INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID | 0
INTG_EXTRA_CTL_CLK_WR_TO_PCH | 0
INTG_EXTRA_CTL_CLK_WR_TO_RD | 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_BC | 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP | 0
INTG_EXTRA_CTL_CLK_WR_TO_WR | 0
INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP | 0
INTG_MEM_IF_TREFI | 3120
INTG_MEM_IF_TRFC | 34
INTG_RCFG_SUM_WT_PRIORITY_0 | 0
INTG_RCFG_SUM_WT_PRIORITY_1 | 0
INTG_RCFG_SUM_WT_PRIORITY_2 | 0
INTG_RCFG_SUM_WT_PRIORITY_3 | 0
INTG_RCFG_SUM_WT_PRIORITY_4 | 0
INTG_RCFG_SUM_WT_PRIORITY_5 | 0
INTG_RCFG_SUM_WT_PRIORITY_6 | 0
INTG_RCFG_SUM_WT_PRIORITY_7 | 0
INTG_SUM_WT_PRIORITY_0 | 0
INTG_SUM_WT_PRIORITY_1 | 0
INTG_SUM_WT_PRIORITY_2 | 0
INTG_SUM_WT_PRIORITY_3 | 0
INTG_SUM_WT_PRIORITY_4 | 0
INTG_SUM_WT_PRIORITY_5 | 0
INTG_SUM_WT_PRIORITY_6 | 0
INTG_SUM_WT_PRIORITY_7 | 0
VECT_ATTR_COUNTER_ONE_MASK | 0
VECT_ATTR_COUNTER_ONE_MATCH | 0
VECT_ATTR_COUNTER_ZERO_MASK | 0
VECT_ATTR_COUNTER_ZERO_MATCH | 0
VECT_ATTR_DEBUG_SELECT_BYTE | 0
INTG_POWER_SAVING_EXIT_CYCLES | 5
INTG_MEM_CLK_ENTRY_CYCLES | 10
ENUM_ENABLE_BURST_INTERRUPT | DISABLED
ENUM_ENABLE_BURST_TERMINATE | DISABLED
AV_PORT_0_CONNECT_TO_CV_PORT | 0
CV_PORT_0_CONNECT_TO_AV_PORT | 0
CV_AVL_DATA_WIDTH_PORT_0 | 0
CV_AVL_ADDR_WIDTH_PORT_0 | 0
CV_CPORT_TYPE_PORT_0 | 0
CV_AVL_NUM_SYMBOLS_PORT_0 | 2
CV_LSB_WFIFO_PORT_0 | 5
CV_MSB_WFIFO_PORT_0 | 5
CV_LSB_RFIFO_PORT_0 | 5
CV_MSB_RFIFO_PORT_0 | 5
CV_ENUM_AUTO_PCH_ENABLE_0 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_0 | FALSE
CV_ENUM_CPORT0_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT0_TYPE | DISABLE
CV_ENUM_CPORT0_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_0 | DISABLED
CV_ENUM_PORT0_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_0 | WEIGHT_0
CV_ENUM_PRIORITY_1_0 | WEIGHT_0
CV_ENUM_PRIORITY_2_0 | WEIGHT_0
CV_ENUM_PRIORITY_3_0 | WEIGHT_0
CV_ENUM_PRIORITY_4_0 | WEIGHT_0
CV_ENUM_PRIORITY_5_0 | WEIGHT_0
CV_ENUM_PRIORITY_6_0 | WEIGHT_0
CV_ENUM_PRIORITY_7_0 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_0 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_0 | PRIORITY_0
CV_ENUM_RD_DWIDTH_0 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_0 | USE_NO
CV_ENUM_STATIC_WEIGHT_0 | WEIGHT_0
CV_ENUM_USER_PRIORITY_0 | PRIORITY_0
CV_ENUM_WR_DWIDTH_0 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_0 | USE_NO
TG_TEMP_PORT_0 | 0
AV_PORT_1_CONNECT_TO_CV_PORT | 1
CV_PORT_1_CONNECT_TO_AV_PORT | 1
CV_AVL_DATA_WIDTH_PORT_1 | 0
CV_AVL_ADDR_WIDTH_PORT_1 | 0
CV_CPORT_TYPE_PORT_1 | 0
CV_AVL_NUM_SYMBOLS_PORT_1 | 2
CV_LSB_WFIFO_PORT_1 | 5
CV_MSB_WFIFO_PORT_1 | 5
CV_LSB_RFIFO_PORT_1 | 5
CV_MSB_RFIFO_PORT_1 | 5
CV_ENUM_AUTO_PCH_ENABLE_1 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_1 | FALSE
CV_ENUM_CPORT1_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT1_TYPE | DISABLE
CV_ENUM_CPORT1_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_1 | DISABLED
CV_ENUM_PORT1_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_1 | WEIGHT_0
CV_ENUM_PRIORITY_1_1 | WEIGHT_0
CV_ENUM_PRIORITY_2_1 | WEIGHT_0
CV_ENUM_PRIORITY_3_1 | WEIGHT_0
CV_ENUM_PRIORITY_4_1 | WEIGHT_0
CV_ENUM_PRIORITY_5_1 | WEIGHT_0
CV_ENUM_PRIORITY_6_1 | WEIGHT_0
CV_ENUM_PRIORITY_7_1 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_1 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_1 | PRIORITY_0
CV_ENUM_RD_DWIDTH_1 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_1 | USE_NO
CV_ENUM_STATIC_WEIGHT_1 | WEIGHT_0
CV_ENUM_USER_PRIORITY_1 | PRIORITY_0
CV_ENUM_WR_DWIDTH_1 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_1 | USE_NO
TG_TEMP_PORT_1 | 0
AV_PORT_2_CONNECT_TO_CV_PORT | 2
CV_PORT_2_CONNECT_TO_AV_PORT | 2
CV_AVL_DATA_WIDTH_PORT_2 | 0
CV_AVL_ADDR_WIDTH_PORT_2 | 0
CV_CPORT_TYPE_PORT_2 | 0
CV_AVL_NUM_SYMBOLS_PORT_2 | 2
CV_LSB_WFIFO_PORT_2 | 5
CV_MSB_WFIFO_PORT_2 | 5
CV_LSB_RFIFO_PORT_2 | 5
CV_MSB_RFIFO_PORT_2 | 5
CV_ENUM_AUTO_PCH_ENABLE_2 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_2 | FALSE
CV_ENUM_CPORT2_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT2_TYPE | DISABLE
CV_ENUM_CPORT2_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_2 | DISABLED
CV_ENUM_PORT2_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_2 | WEIGHT_0
CV_ENUM_PRIORITY_1_2 | WEIGHT_0
CV_ENUM_PRIORITY_2_2 | WEIGHT_0
CV_ENUM_PRIORITY_3_2 | WEIGHT_0
CV_ENUM_PRIORITY_4_2 | WEIGHT_0
CV_ENUM_PRIORITY_5_2 | WEIGHT_0
CV_ENUM_PRIORITY_6_2 | WEIGHT_0
CV_ENUM_PRIORITY_7_2 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_2 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_2 | PRIORITY_0
CV_ENUM_RD_DWIDTH_2 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_2 | USE_NO
CV_ENUM_STATIC_WEIGHT_2 | WEIGHT_0
CV_ENUM_USER_PRIORITY_2 | PRIORITY_0
CV_ENUM_WR_DWIDTH_2 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_2 | USE_NO
TG_TEMP_PORT_2 | 0
AV_PORT_3_CONNECT_TO_CV_PORT | 3
CV_PORT_3_CONNECT_TO_AV_PORT | 3
CV_AVL_DATA_WIDTH_PORT_3 | 0
CV_AVL_ADDR_WIDTH_PORT_3 | 0
CV_CPORT_TYPE_PORT_3 | 0
CV_AVL_NUM_SYMBOLS_PORT_3 | 2
CV_LSB_WFIFO_PORT_3 | 5
CV_MSB_WFIFO_PORT_3 | 5
CV_LSB_RFIFO_PORT_3 | 5
CV_MSB_RFIFO_PORT_3 | 5
CV_ENUM_AUTO_PCH_ENABLE_3 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_3 | FALSE
CV_ENUM_CPORT3_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT3_TYPE | DISABLE
CV_ENUM_CPORT3_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_3 | DISABLED
CV_ENUM_PORT3_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_3 | WEIGHT_0
CV_ENUM_PRIORITY_1_3 | WEIGHT_0
CV_ENUM_PRIORITY_2_3 | WEIGHT_0
CV_ENUM_PRIORITY_3_3 | WEIGHT_0
CV_ENUM_PRIORITY_4_3 | WEIGHT_0
CV_ENUM_PRIORITY_5_3 | WEIGHT_0
CV_ENUM_PRIORITY_6_3 | WEIGHT_0
CV_ENUM_PRIORITY_7_3 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_3 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_3 | PRIORITY_0
CV_ENUM_RD_DWIDTH_3 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_3 | USE_NO
CV_ENUM_STATIC_WEIGHT_3 | WEIGHT_0
CV_ENUM_USER_PRIORITY_3 | PRIORITY_0
CV_ENUM_WR_DWIDTH_3 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_3 | USE_NO
TG_TEMP_PORT_3 | 0
AV_PORT_4_CONNECT_TO_CV_PORT | 4
CV_PORT_4_CONNECT_TO_AV_PORT | 4
CV_AVL_DATA_WIDTH_PORT_4 | 0
CV_AVL_ADDR_WIDTH_PORT_4 | 0
CV_CPORT_TYPE_PORT_4 | 0
CV_AVL_NUM_SYMBOLS_PORT_4 | 2
CV_LSB_WFIFO_PORT_4 | 5
CV_MSB_WFIFO_PORT_4 | 5
CV_LSB_RFIFO_PORT_4 | 5
CV_MSB_RFIFO_PORT_4 | 5
CV_ENUM_AUTO_PCH_ENABLE_4 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_4 | FALSE
CV_ENUM_CPORT4_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT4_TYPE | DISABLE
CV_ENUM_CPORT4_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_4 | DISABLED
CV_ENUM_PORT4_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_4 | WEIGHT_0
CV_ENUM_PRIORITY_1_4 | WEIGHT_0
CV_ENUM_PRIORITY_2_4 | WEIGHT_0
CV_ENUM_PRIORITY_3_4 | WEIGHT_0
CV_ENUM_PRIORITY_4_4 | WEIGHT_0
CV_ENUM_PRIORITY_5_4 | WEIGHT_0
CV_ENUM_PRIORITY_6_4 | WEIGHT_0
CV_ENUM_PRIORITY_7_4 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_4 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_4 | PRIORITY_0
CV_ENUM_RD_DWIDTH_4 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_4 | USE_NO
CV_ENUM_STATIC_WEIGHT_4 | WEIGHT_0
CV_ENUM_USER_PRIORITY_4 | PRIORITY_0
CV_ENUM_WR_DWIDTH_4 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_4 | USE_NO
TG_TEMP_PORT_4 | 0
AV_PORT_5_CONNECT_TO_CV_PORT | 5
CV_PORT_5_CONNECT_TO_AV_PORT | 5
CV_AVL_DATA_WIDTH_PORT_5 | 0
CV_AVL_ADDR_WIDTH_PORT_5 | 0
CV_CPORT_TYPE_PORT_5 | 0
CV_AVL_NUM_SYMBOLS_PORT_5 | 2
CV_LSB_WFIFO_PORT_5 | 5
CV_MSB_WFIFO_PORT_5 | 5
CV_LSB_RFIFO_PORT_5 | 5
CV_MSB_RFIFO_PORT_5 | 5
CV_ENUM_AUTO_PCH_ENABLE_5 | DISABLED
CV_ENUM_CMD_PORT_IN_USE_5 | FALSE
CV_ENUM_CPORT5_RFIFO_MAP | FIFO_0
CV_ENUM_CPORT5_TYPE | DISABLE
CV_ENUM_CPORT5_WFIFO_MAP | FIFO_0
CV_ENUM_ENABLE_BONDING_5 | DISABLED
CV_ENUM_PORT5_WIDTH | PORT_64_BIT
CV_ENUM_PRIORITY_0_5 | WEIGHT_0
CV_ENUM_PRIORITY_1_5 | WEIGHT_0
CV_ENUM_PRIORITY_2_5 | WEIGHT_0
CV_ENUM_PRIORITY_3_5 | WEIGHT_0
CV_ENUM_PRIORITY_4_5 | WEIGHT_0
CV_ENUM_PRIORITY_5_5 | WEIGHT_0
CV_ENUM_PRIORITY_6_5 | WEIGHT_0
CV_ENUM_PRIORITY_7_5 | WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_5 | WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_5 | PRIORITY_0
CV_ENUM_RD_DWIDTH_5 | DWIDTH_0
CV_ENUM_RD_PORT_INFO_5 | USE_NO
CV_ENUM_STATIC_WEIGHT_5 | WEIGHT_0
CV_ENUM_USER_PRIORITY_5 | PRIORITY_0
CV_ENUM_WR_DWIDTH_5 | DWIDTH_0
CV_ENUM_WR_PORT_INFO_5 | USE_NO
TG_TEMP_PORT_5 | 0
CV_ENUM_RFIFO0_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO0_CPORT_MAP | CMD_PORT_0
CV_ENUM_RFIFO1_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO1_CPORT_MAP | CMD_PORT_0
CV_ENUM_RFIFO2_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO2_CPORT_MAP | CMD_PORT_0
CV_ENUM_RFIFO3_CPORT_MAP | CMD_PORT_0
CV_ENUM_WFIFO3_CPORT_MAP | CMD_PORT_0
CV_INTG_RCFG_SUM_WT_PRIORITY_0 | 0
CV_INTG_SUM_WT_PRIORITY_0 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_1 | 0
CV_INTG_SUM_WT_PRIORITY_1 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_2 | 0
CV_INTG_SUM_WT_PRIORITY_2 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_3 | 0
CV_INTG_SUM_WT_PRIORITY_3 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_4 | 0
CV_INTG_SUM_WT_PRIORITY_4 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_5 | 0
CV_INTG_SUM_WT_PRIORITY_5 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_6 | 0
CV_INTG_SUM_WT_PRIORITY_6 | 0
CV_INTG_RCFG_SUM_WT_PRIORITY_7 | 0
CV_INTG_SUM_WT_PRIORITY_7 | 0
POWER_OF_TWO_BUS | false
SOPC_COMPAT_RESET | false
AVL_MAX_SIZE | 4
BYTE_ENABLE | true
ENABLE_CTRL_AVALON_INTERFACE | true
CTL_DEEP_POWERDN_EN | false
CTL_SELF_REFRESH_EN | false
AUTO_POWERDN_EN | false
AUTO_PD_CYCLES | 0
CTL_USR_REFRESH_EN | false
CTL_AUTOPCH_EN | false
CTL_ZQCAL_EN | false
ADDR_ORDER | 0
CTL_LOOK_AHEAD_DEPTH | 4
CONTROLLER_LATENCY | 5
CFG_REORDER_DATA | true
STARVE_LIMIT | 10
CTL_CSR_ENABLED | false
CTL_CSR_CONNECTION | INTERNAL_JTAG
CTL_ECC_ENABLED | false
CTL_HRB_ENABLED | false
CTL_ECC_AUTO_CORRECTION_ENABLED | false
MULTICAST_EN | false
CTL_DYNAMIC_BANK_ALLOCATION | false
CTL_DYNAMIC_BANK_NUM | 4
DEBUG_MODE | false
ENABLE_BURST_MERGE | false
CTL_ENABLE_BURST_INTERRUPT | false
CTL_ENABLE_BURST_TERMINATE | false
LOCAL_ID_WIDTH | 8
RDBUFFER_ADDR_WIDTH | 6
WRBUFFER_ADDR_WIDTH | 6
MAX_PENDING_WR_CMD | 16
MAX_PENDING_RD_CMD | 32
USE_MM_ADAPTOR | true
USE_AXI_ADAPTOR | false
HCX_COMPAT_MODE | false
CTL_CMD_QUEUE_DEPTH | 8
CTL_CSR_READ_ONLY | 1
CFG_DATA_REORDERING_TYPE | INTER_BANK
NUM_OF_PORTS | 1
ENABLE_BONDING | false
ENABLE_USER_ECC | false
AVL_DATA_WIDTH_PORT | 32,32,32,32,32,32
PRIORITY_PORT | 1,1,1,1,1,1
WEIGHT_PORT | 0,0,0,0,0,0
CPORT_TYPE_PORT | Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional
CORE_PERIPHERY_DUAL_CLOCK | false
USE_DR_CLK | false
DLL_USE_DR_CLK | false
USE_2X_FF | false
DUAL_WRITE_CLOCK | false
GENERIC_PLL | false
USE_HARD_READ_FIFO | false
READ_FIFO_HALF_RATE | false
PLL_MASTER | false
DLL_MASTER | false
PHY_VERSION_NUMBER | 0
ENABLE_NIOS_OCI | false
ENABLE_EMIT_JTAG_MASTER | false
ENABLE_NIOS_JTAG_UART | false
ENABLE_NIOS_PRINTF_OUTPUT | false
ENABLE_LARGE_RW_MGR_DI_BUFFER | false
ENABLE_EMIT_BFM_MASTER | false
FORCE_SEQUENCER_TCL_DEBUG_MODE | false
ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT | false
ENABLE_MAX_SIZE_SEQ_MEM | false
MAKE_INTERNAL_NIOS_VISIBLE | false
DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG | false
ENABLE_CSR_SOFT_RESET_REQ | false
DUPLICATE_PLL_FOR_PHY_CLK | false
MAX_LATENCY_COUNT_WIDTH | 6
READ_VALID_FIFO_SIZE | 16
EXTRA_VFIFO_SHIFT | 0
TB_MEM_CLK_FREQ | 0.0
TB_RATE |
TB_MEM_IF_DQ_WIDTH | 0
TB_MEM_IF_READ_DQS_WIDTH | 0
TB_PLL_DLL_MASTER | true
FAST_SIM_CALIBRATION | false
REF_CLK_FREQ | 25.0
REF_CLK_FREQ_STR |
REF_CLK_NS | 0.0
REF_CLK_PS | 0.0
PLL_DR_CLK_FREQ | 0.0
PLL_DR_CLK_FREQ_STR |
PLL_DR_CLK_FREQ_SIM_STR |
PLL_DR_CLK_PHASE_PS | 0
PLL_DR_CLK_PHASE_PS_STR |
PLL_DR_CLK_PHASE_DEG | 0.0
PLL_DR_CLK_PHASE_PS_SIM | 0
PLL_DR_CLK_PHASE_PS_SIM_STR |
PLL_DR_CLK_PHASE_DEG_SIM | 0.0
PLL_DR_CLK_MULT | 0
PLL_DR_CLK_DIV | 0
PLL_MEM_CLK_FREQ | 0.0
PLL_MEM_CLK_FREQ_STR |
PLL_MEM_CLK_FREQ_SIM_STR |
PLL_MEM_CLK_PHASE_PS | 0
PLL_MEM_CLK_PHASE_PS_STR |
PLL_MEM_CLK_PHASE_DEG | 0.0
PLL_MEM_CLK_PHASE_PS_SIM | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR |
PLL_MEM_CLK_PHASE_DEG_SIM | 0.0
PLL_MEM_CLK_MULT | 0
PLL_MEM_CLK_DIV | 0
PLL_AFI_CLK_FREQ | 0.0
PLL_AFI_CLK_FREQ_STR |
PLL_AFI_CLK_FREQ_SIM_STR |
PLL_AFI_CLK_PHASE_PS | 0
PLL_AFI_CLK_PHASE_PS_STR |
PLL_AFI_CLK_PHASE_DEG | 0.0
PLL_AFI_CLK_PHASE_PS_SIM | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR |
PLL_AFI_CLK_PHASE_DEG_SIM | 0.0
PLL_AFI_CLK_MULT | 0
PLL_AFI_CLK_DIV | 0
PLL_WRITE_CLK_FREQ | 0.0
PLL_WRITE_CLK_FREQ_STR |
PLL_WRITE_CLK_FREQ_SIM_STR |
PLL_WRITE_CLK_PHASE_PS | 0
PLL_WRITE_CLK_PHASE_PS_STR |
PLL_WRITE_CLK_PHASE_DEG | 0.0
PLL_WRITE_CLK_PHASE_PS_SIM | 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR |
PLL_WRITE_CLK_PHASE_DEG_SIM | 0.0
PLL_WRITE_CLK_MULT | 0
PLL_WRITE_CLK_DIV | 0
PLL_ADDR_CMD_CLK_FREQ | 0.0
PLL_ADDR_CMD_CLK_FREQ_STR |
PLL_ADDR_CMD_CLK_FREQ_SIM_STR |
PLL_ADDR_CMD_CLK_PHASE_PS | 0
PLL_ADDR_CMD_CLK_PHASE_PS_STR |
PLL_ADDR_CMD_CLK_PHASE_DEG | 0.0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM | 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR |
PLL_ADDR_CMD_CLK_PHASE_DEG_SIM | 0.0
PLL_ADDR_CMD_CLK_MULT | 0
PLL_ADDR_CMD_CLK_DIV | 0
PLL_AFI_HALF_CLK_FREQ | 0.0
PLL_AFI_HALF_CLK_FREQ_STR |
PLL_AFI_HALF_CLK_FREQ_SIM_STR |
PLL_AFI_HALF_CLK_PHASE_PS | 0
PLL_AFI_HALF_CLK_PHASE_PS_STR |
PLL_AFI_HALF_CLK_PHASE_DEG | 0.0
PLL_AFI_HALF_CLK_PHASE_PS_SIM | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR |
PLL_AFI_HALF_CLK_PHASE_DEG_SIM | 0.0
PLL_AFI_HALF_CLK_MULT | 0
PLL_AFI_HALF_CLK_DIV | 0
PLL_NIOS_CLK_FREQ | 0.0
PLL_NIOS_CLK_FREQ_STR |
PLL_NIOS_CLK_FREQ_SIM_STR |
PLL_NIOS_CLK_PHASE_PS | 0
PLL_NIOS_CLK_PHASE_PS_STR |
PLL_NIOS_CLK_PHASE_DEG | 0.0
PLL_NIOS_CLK_PHASE_PS_SIM | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR |
PLL_NIOS_CLK_PHASE_DEG_SIM | 0.0
PLL_NIOS_CLK_MULT | 0
PLL_NIOS_CLK_DIV | 0
PLL_CONFIG_CLK_FREQ | 0.0
PLL_CONFIG_CLK_FREQ_STR |
PLL_CONFIG_CLK_FREQ_SIM_STR |
PLL_CONFIG_CLK_PHASE_PS | 0
PLL_CONFIG_CLK_PHASE_PS_STR |
PLL_CONFIG_CLK_PHASE_DEG | 0.0
PLL_CONFIG_CLK_PHASE_PS_SIM | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR |
PLL_CONFIG_CLK_PHASE_DEG_SIM | 0.0
PLL_CONFIG_CLK_MULT | 0
PLL_CONFIG_CLK_DIV | 0
PLL_P2C_READ_CLK_FREQ | 0.0
PLL_P2C_READ_CLK_FREQ_STR |
PLL_P2C_READ_CLK_FREQ_SIM_STR |
PLL_P2C_READ_CLK_PHASE_PS | 0
PLL_P2C_READ_CLK_PHASE_PS_STR |
PLL_P2C_READ_CLK_PHASE_DEG | 0.0
PLL_P2C_READ_CLK_PHASE_PS_SIM | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR |
PLL_P2C_READ_CLK_PHASE_DEG_SIM | 0.0
PLL_P2C_READ_CLK_MULT | 0
PLL_P2C_READ_CLK_DIV | 0
PLL_C2P_WRITE_CLK_FREQ | 0.0
PLL_C2P_WRITE_CLK_FREQ_STR |
PLL_C2P_WRITE_CLK_FREQ_SIM_STR |
PLL_C2P_WRITE_CLK_PHASE_PS | 0
PLL_C2P_WRITE_CLK_PHASE_PS_STR |
PLL_C2P_WRITE_CLK_PHASE_DEG | 0.0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR |
PLL_C2P_WRITE_CLK_PHASE_DEG_SIM | 0.0
PLL_C2P_WRITE_CLK_MULT | 0
PLL_C2P_WRITE_CLK_DIV | 0
PLL_HR_CLK_FREQ | 0.0
PLL_HR_CLK_FREQ_STR |
PLL_HR_CLK_FREQ_SIM_STR |
PLL_HR_CLK_PHASE_PS | 0
PLL_HR_CLK_PHASE_PS_STR |
PLL_HR_CLK_PHASE_DEG | 0.0
PLL_HR_CLK_PHASE_PS_SIM | 0
PLL_HR_CLK_PHASE_PS_SIM_STR |
PLL_HR_CLK_PHASE_DEG_SIM | 0.0
PLL_HR_CLK_MULT | 0
PLL_HR_CLK_DIV | 0
PLL_AFI_PHY_CLK_FREQ | 0.0
PLL_AFI_PHY_CLK_FREQ_STR |
PLL_AFI_PHY_CLK_FREQ_SIM_STR |
PLL_AFI_PHY_CLK_PHASE_PS | 0
PLL_AFI_PHY_CLK_PHASE_PS_STR |
PLL_AFI_PHY_CLK_PHASE_DEG | 0.0
PLL_AFI_PHY_CLK_PHASE_PS_SIM | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR |
PLL_AFI_PHY_CLK_PHASE_DEG_SIM | 0.0
PLL_AFI_PHY_CLK_MULT | 0
PLL_AFI_PHY_CLK_DIV | 0
REF_CLK_FREQ_CACHE_VALID | false
REF_CLK_FREQ_PARAM_VALID | false
REF_CLK_FREQ_MIN_PARAM | 0.0
REF_CLK_FREQ_MAX_PARAM | 0.0
REF_CLK_FREQ_MIN_CACHE | 0.0
REF_CLK_FREQ_MAX_CACHE | 0.0
PLL_DR_CLK_FREQ_PARAM | 0.0
PLL_DR_CLK_FREQ_SIM_STR_PARAM |
PLL_DR_CLK_PHASE_PS_PARAM | 0
PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_DR_CLK_MULT_PARAM | 0
PLL_DR_CLK_DIV_PARAM | 0
PLL_DR_CLK_FREQ_CACHE | 0.0
PLL_DR_CLK_FREQ_SIM_STR_CACHE |
PLL_DR_CLK_PHASE_PS_CACHE | 0
PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_DR_CLK_MULT_CACHE | 0
PLL_DR_CLK_DIV_CACHE | 0
PLL_MEM_CLK_FREQ_PARAM | 0.0
PLL_MEM_CLK_FREQ_SIM_STR_PARAM |
PLL_MEM_CLK_PHASE_PS_PARAM | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_MEM_CLK_MULT_PARAM | 0
PLL_MEM_CLK_DIV_PARAM | 0
PLL_MEM_CLK_FREQ_CACHE | 0.0
PLL_MEM_CLK_FREQ_SIM_STR_CACHE |
PLL_MEM_CLK_PHASE_PS_CACHE | 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_MEM_CLK_MULT_CACHE | 0
PLL_MEM_CLK_DIV_CACHE | 0
PLL_AFI_CLK_FREQ_PARAM | 0.0
PLL_AFI_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_CLK_PHASE_PS_PARAM | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_CLK_MULT_PARAM | 0
PLL_AFI_CLK_DIV_PARAM | 0
PLL_AFI_CLK_FREQ_CACHE | 0.0
PLL_AFI_CLK_FREQ_SIM_STR_CACHE |
PLL_AFI_CLK_PHASE_PS_CACHE | 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_AFI_CLK_MULT_CACHE | 0
PLL_AFI_CLK_DIV_CACHE | 0
PLL_WRITE_CLK_FREQ_PARAM | 0.0
PLL_WRITE_CLK_FREQ_SIM_STR_PARAM |
PLL_WRITE_CLK_PHASE_PS_PARAM | 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_WRITE_CLK_MULT_PARAM | 0
PLL_WRITE_CLK_DIV_PARAM | 0
PLL_WRITE_CLK_FREQ_CACHE | 0.0
PLL_WRITE_CLK_FREQ_SIM_STR_CACHE |
PLL_WRITE_CLK_PHASE_PS_CACHE | 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_WRITE_CLK_MULT_CACHE | 0
PLL_WRITE_CLK_DIV_CACHE | 0
PLL_ADDR_CMD_CLK_FREQ_PARAM | 0.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM |
PLL_ADDR_CMD_CLK_PHASE_PS_PARAM | 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_ADDR_CMD_CLK_MULT_PARAM | 0
PLL_ADDR_CMD_CLK_DIV_PARAM | 0
PLL_ADDR_CMD_CLK_FREQ_CACHE | 0.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE |
PLL_ADDR_CMD_CLK_PHASE_PS_CACHE | 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_ADDR_CMD_CLK_MULT_CACHE | 0
PLL_ADDR_CMD_CLK_DIV_CACHE | 0
PLL_AFI_HALF_CLK_FREQ_PARAM | 0.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_HALF_CLK_PHASE_PS_PARAM | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_HALF_CLK_MULT_PARAM | 0
PLL_AFI_HALF_CLK_DIV_PARAM | 0
PLL_AFI_HALF_CLK_FREQ_CACHE | 0.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE |
PLL_AFI_HALF_CLK_PHASE_PS_CACHE | 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_AFI_HALF_CLK_MULT_CACHE | 0
PLL_AFI_HALF_CLK_DIV_CACHE | 0
PLL_NIOS_CLK_FREQ_PARAM | 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_PARAM |
PLL_NIOS_CLK_PHASE_PS_PARAM | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_NIOS_CLK_MULT_PARAM | 0
PLL_NIOS_CLK_DIV_PARAM | 0
PLL_NIOS_CLK_FREQ_CACHE | 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_CACHE |
PLL_NIOS_CLK_PHASE_PS_CACHE | 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_NIOS_CLK_MULT_CACHE | 0
PLL_NIOS_CLK_DIV_CACHE | 0
PLL_CONFIG_CLK_FREQ_PARAM | 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM |
PLL_CONFIG_CLK_PHASE_PS_PARAM | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_CONFIG_CLK_MULT_PARAM | 0
PLL_CONFIG_CLK_DIV_PARAM | 0
PLL_CONFIG_CLK_FREQ_CACHE | 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE |
PLL_CONFIG_CLK_PHASE_PS_CACHE | 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_CONFIG_CLK_MULT_CACHE | 0
PLL_CONFIG_CLK_DIV_CACHE | 0
PLL_P2C_READ_CLK_FREQ_PARAM | 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM |
PLL_P2C_READ_CLK_PHASE_PS_PARAM | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_P2C_READ_CLK_MULT_PARAM | 0
PLL_P2C_READ_CLK_DIV_PARAM | 0
PLL_P2C_READ_CLK_FREQ_CACHE | 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE |
PLL_P2C_READ_CLK_PHASE_PS_CACHE | 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_P2C_READ_CLK_MULT_CACHE | 0
PLL_P2C_READ_CLK_DIV_CACHE | 0
PLL_C2P_WRITE_CLK_FREQ_PARAM | 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM |
PLL_C2P_WRITE_CLK_PHASE_PS_PARAM | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_C2P_WRITE_CLK_MULT_PARAM | 0
PLL_C2P_WRITE_CLK_DIV_PARAM | 0
PLL_C2P_WRITE_CLK_FREQ_CACHE | 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE |
PLL_C2P_WRITE_CLK_PHASE_PS_CACHE | 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_C2P_WRITE_CLK_MULT_CACHE | 0
PLL_C2P_WRITE_CLK_DIV_CACHE | 0
PLL_HR_CLK_FREQ_PARAM | 0.0
PLL_HR_CLK_FREQ_SIM_STR_PARAM |
PLL_HR_CLK_PHASE_PS_PARAM | 0
PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_HR_CLK_MULT_PARAM | 0
PLL_HR_CLK_DIV_PARAM | 0
PLL_HR_CLK_FREQ_CACHE | 0.0
PLL_HR_CLK_FREQ_SIM_STR_CACHE |
PLL_HR_CLK_PHASE_PS_CACHE | 0
PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_HR_CLK_MULT_CACHE | 0
PLL_HR_CLK_DIV_CACHE | 0
PLL_AFI_PHY_CLK_FREQ_PARAM | 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM |
PLL_AFI_PHY_CLK_PHASE_PS_PARAM | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM |
PLL_AFI_PHY_CLK_MULT_PARAM | 0
PLL_AFI_PHY_CLK_DIV_PARAM | 0
PLL_AFI_PHY_CLK_FREQ_CACHE | 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE |
PLL_AFI_PHY_CLK_PHASE_PS_CACHE | 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE |
PLL_AFI_PHY_CLK_MULT_CACHE | 0
PLL_AFI_PHY_CLK_DIV_CACHE | 0
SPEED_GRADE_CACHE |
IS_ES_DEVICE_CACHE | false
MEM_CLK_FREQ_CACHE | 0.0
REF_CLK_FREQ_CACHE | 0.0
RATE_CACHE | Unknown
HCX_COMPAT_MODE_CACHE | false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE | Unknown
COMMAND_PHASE_CACHE | 0.0
MEM_CK_PHASE_CACHE | 0.0
P2C_READ_CLOCK_ADD_PHASE_CACHE | 0.0
C2P_WRITE_CLOCK_ADD_PHASE_CACHE | 0.0
ACV_PHY_CLK_ADD_FR_PHASE_CACHE | 0.0
SEQUENCER_TYPE_CACHE | Unknown
USE_MEM_CLK_FREQ_CACHE | false
PLL_CLK_CACHE_VALID | false
PLL_CLK_PARAM_VALID | false
ENABLE_EXTRA_REPORTING | false
NUM_EXTRA_REPORT_PATH | 10
ENABLE_ISS_PROBES | false
CALIB_REG_WIDTH | 8
USE_SEQUENCER_BFM | false
DEFAULT_FAST_SIM_MODEL | true
PLL_SHARING_MODE | None
NUM_PLL_SHARING_INTERFACES | 1
EXPORT_AFI_HALF_CLK | false
ABSTRACT_REAL_COMPARE_TEST | false
INCLUDE_BOARD_DELAY_MODEL | false
INCLUDE_MULTIRANK_BOARD_DELAY_MODEL | false
USE_FAKE_PHY_INTERNAL | false
USE_FAKE_PHY | false
FORCE_MAX_LATENCY_COUNT_WIDTH | 0
USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE | false
ENABLE_NON_DESTRUCTIVE_CALIB | false
TRACKING_ERROR_TEST | false
TRACKING_WATCH_TEST | false
MARGIN_VARIATION_TEST | false
EXTRA_SETTINGS |
MEM_DEVICE | MISSING_MODEL
FORCE_SYNTHESIS_LANGUAGE |
NUM_SUBGROUP_PER_READ_DQS | 0
QVLD_EXTRA_FLOP_STAGES | 0
QVLD_WR_ADDRESS_OFFSET | 0
MAX_WRITE_LATENCY_COUNT_WIDTH | 4
NUM_WRITE_PATH_FLOP_STAGES | 0
NUM_AC_FR_CYCLE_SHIFTS | 0
FORCED_NUM_WRITE_FR_CYCLE_SHIFTS | 0
NUM_WRITE_FR_CYCLE_SHIFTS | 0
PERFORM_READ_AFTER_WRITE_CALIBRATION | false
SEQ_BURST_COUNT_WIDTH | 0
VCALIB_COUNT_WIDTH | 0
PLL_PHASE_COUNTER_WIDTH | 0
DQS_DELAY_CHAIN_PHASE_SETTING | 2
DQS_PHASE_SHIFT | 9000
DELAYED_CLOCK_PHASE_SETTING | 2
IO_DQS_IN_RESERVE | 3
IO_DQS_OUT_RESERVE | 3
IO_DQ_OUT_RESERVE | 0
IO_DM_OUT_RESERVE | 0
IO_DQS_EN_DELAY_OFFSET | 0
IO_DQS_EN_PHASE_MAX | 0
IO_DQDQS_OUT_PHASE_MAX | 0
IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS | false
MEM_CLK_NS | 0.0
MEM_CLK_PS | 0.0
CALIB_LFIFO_OFFSET | -1
CALIB_VFIFO_OFFSET | -1
DELAY_PER_OPA_TAP | -1
DELAY_PER_DCHAIN_TAP | -1
DELAY_PER_DQS_EN_DCHAIN_TAP | -1
DQS_EN_DELAY_MAX | -1
DQS_IN_DELAY_MAX | -1
IO_IN_DELAY_MAX | -1
IO_OUT1_DELAY_MAX | -1
IO_OUT2_DELAY_MAX | -1
IO_STANDARD |
VFIFO_AS_SHIFT_REG | false
SEQUENCER_TYPE | NIOS
NIOS_HEX_FILE_LOCATION |
ADVERTIZE_SEQUENCER_SW_BUILD_FILES | false
NEGATIVE_WRITE_CK_PHASE | false
MEM_T_WL | 0
MEM_T_RL | 0
PHY_CLKBUF | false
USE_LDC_AS_LOW_SKEW_CLOCK | false
USE_LDC_FOR_ADDR_CMD | false
ENABLE_LDC_MEM_CK_ADJUSTMENT | false
MEM_CK_LDC_ADJUSTMENT_THRESHOLD | 0
LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT | true
LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE | 0
FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT | false
NON_LDC_ADDR_CMD_MEM_CK_INVERT | false
REGISTER_C2P | false
EARLY_ADDR_CMD_CLK_TRANSFER | false
PHY_ONLY | false
SEQ_MODE | 0
ADVANCED_CK_PHASES | false
COMMAND_PHASE | 0.0
MEM_CK_PHASE | 0.0
P2C_READ_CLOCK_ADD_PHASE | 0.0
C2P_WRITE_CLOCK_ADD_PHASE | 0.0
ACV_PHY_CLK_ADD_FR_PHASE | 0.0
MEM_VOLTAGE | 1.5V DDR3
PLL_LOCATION | Top_Bottom
SKIP_MEM_INIT | true
READ_DQ_DQS_CLOCK_SOURCE | INVERTED_DQS_BUS
DQ_INPUT_REG_USE_CLKN | false
DQS_DQSN_MODE | DIFFERENTIAL
AFI_DEBUG_INFO_WIDTH | 32
CALIBRATION_MODE | Skip
NIOS_ROM_DATA_WIDTH | 32
NIOS_ROM_ADDRESS_WIDTH | 13
READ_FIFO_SIZE | 8
PHY_CSR_ENABLED | false
PHY_CSR_CONNECTION | INTERNAL_JTAG
USER_DEBUG_LEVEL | 1
TIMING_BOARD_DERATE_METHOD | AUTO
TIMING_BOARD_CK_CKN_SLEW_RATE | 2.0
TIMING_BOARD_AC_SLEW_RATE | 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE | 2.0
TIMING_BOARD_DQ_SLEW_RATE | 1.0
TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED | 2.0
TIMING_BOARD_AC_SLEW_RATE_APPLIED | 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED | 2.0
TIMING_BOARD_DQ_SLEW_RATE_APPLIED | 1.0
TIMING_BOARD_TIS | 0.0
TIMING_BOARD_TIH | 0.0
TIMING_BOARD_TDS | 0.0
TIMING_BOARD_TDH | 0.0
TIMING_BOARD_TIS_APPLIED | 0.0
TIMING_BOARD_TIH_APPLIED | 0.0
TIMING_BOARD_TDS_APPLIED | 0.0
TIMING_BOARD_TDH_APPLIED | 0.0
TIMING_BOARD_ISI_METHOD | AUTO
TIMING_BOARD_AC_EYE_REDUCTION_SU | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H | 0.0
TIMING_BOARD_DQ_EYE_REDUCTION | 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME | 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION | 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED | 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED | 0.0
TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED | 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED | 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED | 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED | 0.0
PACKAGE_DESKEW | false
AC_PACKAGE_DESKEW | false
TIMING_BOARD_MAX_CK_DELAY | 0.03
TIMING_BOARD_MAX_DQS_DELAY | 0.02
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN | 0.09
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED | -0.01
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX | 0.16
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED | 0.01
TIMING_BOARD_SKEW_BETWEEN_DIMMS | 0.05
TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED | 0.05
TIMING_BOARD_SKEW_WITHIN_DQS | 0.01
TIMING_BOARD_SKEW_BETWEEN_DQS | 0.08
TIMING_BOARD_DQ_TO_DQS_SKEW | 0.0
TIMING_BOARD_AC_SKEW | 0.03
TIMING_BOARD_AC_TO_CK_SKEW | 0.0
RATE | Full
MEM_CLK_FREQ | 400.0
USE_MEM_CLK_FREQ | false
USE_DQS_TRACKING | false
FORCE_DQS_TRACKING | AUTO
USE_HPS_DQS_TRACKING | false
TRK_PARALLEL_SCC_LOAD | false
USE_SHADOW_REGS | false
FORCE_SHADOW_REGS | AUTO
DQ_DDR | 0
ADDR_CMD_DDR | 0
AFI_RATE_RATIO | 0
DATA_RATE_RATIO | 0
ADDR_RATE_RATIO | 0
AFI_ADDR_WIDTH | 0
AFI_BANKADDR_WIDTH | 0
AFI_CONTROL_WIDTH | 0
AFI_CS_WIDTH | 0
AFI_CLK_EN_WIDTH | 0
AFI_DM_WIDTH | 0
AFI_DQ_WIDTH | 0
AFI_ODT_WIDTH | 0
AFI_WRITE_DQS_WIDTH | 0
AFI_RLAT_WIDTH | 0
AFI_WLAT_WIDTH | 0
AFI_RRANK_WIDTH | 0
AFI_WRANK_WIDTH | 0
AFI_CLK_PAIR_COUNT | 0
MRS_MIRROR_PING_PONG_ATSO | false
SYS_INFO_DEVICE_FAMILY | CYCLONEV
PARSE_FRIENDLY_DEVICE_FAMILY |
DEVICE_FAMILY |
PRE_V_SERIES_FAMILY | false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID | false
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID | false
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM |
DEVICE_FAMILY_PARAM |
SPEED_GRADE | 7
IS_ES_DEVICE | false
DISABLE_CHILD_MESSAGING | false
HARD_PHY | false
HARD_EMIF | true
HHP_HPS | true
HHP_HPS_VERIFICATION | false
HHP_HPS_SIMULATION | false
HPS_PROTOCOL | DDR3
CUT_NEW_FAMILY_TIMING | true
ENABLE_EXPORT_SEQ_DEBUG_BRIDGE | false
CORE_DEBUG_CONNECTION | EXPORT
ADD_EXTERNAL_SEQ_DEBUG_NIOS | false
ED_EXPORT_SEQ_DEBUG | false
ADD_EFFICIENCY_MONITOR | false
ENABLE_ABS_RAM_MEM_INIT | false
ENABLE_ABS_RAM_INTERNAL | false
ENABLE_ABSTRACT_RAM | false
ABS_RAM_MEM_INIT_FILENAME | meminit
DLL_DELAY_CTRL_WIDTH | 6
DLL_OFFSET_CTRL_WIDTH | 6
DELAY_BUFFER_MODE | HIGH
DELAY_CHAIN_LENGTH | 8
DLL_SHARING_MODE | None
NUM_DLL_SHARING_INTERFACES | 1
OCT_TERM_CONTROL_WIDTH | 14
OCT_SHARING_MODE | None
NUM_OCT_SHARING_INTERFACES | 1
AUTO_DEVICE | 5CSXFC6D6F31C8ES
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_clk_0

hps_clk_src v1.0

## Parameters
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_bridges

hps_bridge_avalon v1.0

hps_0_clk_0 | clk | hps_0_bridges
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_h2f
altera_axi_master
axi_h2f_lw
hps_0_arm_a9_1 | altera_axi_master
axi_h2f
altera_axi_master
axi_h2f_lw
clk_0 | clk
h2f_axi_clock
clk
f2h_axi_clock
clk
h2f_lw_axi_clock
|  | axi_f2h | hps_0_arm_gic_0
|  | axi_slave0
|  | axi_f2h
|  | axi_slave1
|  | axi_f2h | hps_0_L2
|  | axi_slave0
|  | axi_f2h | hps_0_dma
|  | axi_slave0
|  | axi_f2h | hps_0_sysmgr
|  | axi_slave0
|  | axi_f2h | hps_0_clkmgr
|  | axi_slave0
|  | axi_f2h | hps_0_rstmgr
|  | axi_slave0
|  | axi_f2h | hps_0_fpgamgr
|  | axi_slave0
|  | axi_f2h
|  | axi_slave1
|  | axi_f2h | hps_0_uart0
|  | axi_slave0
|  | axi_f2h | hps_0_uart1
|  | axi_slave0
|  | axi_f2h | hps_0_timer0
|  | axi_slave0
|  | axi_f2h | hps_0_timer1
|  | axi_slave0
|  | axi_f2h | hps_0_timer2
|  | axi_slave0
|  | axi_f2h | hps_0_timer3
|  | axi_slave0
|  | axi_f2h | hps_0_gpio0
|  | axi_slave0
|  | axi_f2h | hps_0_gpio1
|  | axi_slave0
|  | axi_f2h | hps_0_gpio2
|  | axi_slave0
|  | axi_f2h | hps_0_i2c0
|  | axi_slave0
|  | axi_f2h | hps_0_i2c1
|  | axi_slave0
|  | axi_f2h | hps_0_i2c2
|  | axi_slave0
|  | axi_f2h | hps_0_i2c3
|  | axi_slave0
|  | axi_f2h | hps_0_nand0
|  | axi_slave0
|  | axi_f2h
|  | axi_slave1
|  | axi_f2h | hps_0_spi0
|  | axi_slave0
|  | axi_f2h | hps_0_spi1
|  | axi_slave0
|  | axi_f2h | hps_0_qspi
|  | axi_slave0
|  | axi_f2h
|  | axi_slave1
|  | axi_f2h | hps_0_sdmmc
|  | axi_slave0
|  | axi_f2h | hps_0_usb0
|  | axi_slave0
|  | axi_f2h | hps_0_usb1
|  | axi_slave0
|  | axi_f2h | hps_0_gmac0
|  | axi_slave0
|  | axi_f2h | hps_0_gmac1
|  | axi_slave0
|  | axi_f2h | hps_0_axi_ocram
|  | axi_slave0
|  | axi_f2h | hps_0_timer
|  | axi_slave0
|  | h2f_lw | vga_led_0
|  | avalon_slave_0

## Parameters
address_map | <address-map><slave name='gmac0.axi_slave0' start='0xFF700000' end='0xFF702000' /><slave name='gmac1.axi_slave0' start='0xFF702000' end='0xFF704000' /><slave name='sdmmc.axi_slave0' start='0xFF704000' end='0xFF705000' /><slave name='qspi.axi_slave0' start='0xFF705000' end='0xFF706000' /><slave name='fpgamgr.axi_slave0' start='0xFF706000' end='0xFF707000' /><slave name='gpio0.axi_slave0' start='0xFF708000' end='0xFF709000' /><slave name='gpio1.axi_slave0' start='0xFF709000' end='0xFF70A000' /><slave name='gpio2.axi_slave0' start='0xFF70A000' end='0xFF70B000' /><slave name='nand0.axi_slave0' start='0xFF900000' end='0xFFA00000' /><slave name='qspi.axi_slave1' start='0xFFA00000' end='0xFFA01000' /><slave name='usb0.axi_slave0' start='0xFFB00000' end='0xFFB01000' /><slave name='usb1.axi_slave0' start='0xFFB40000' end='0xFFB41000' /><slave name='nand0.axi_slave1' start='0xFFB80000' end='0xFFB90000' /><slave name='fpgamgr.axi_slave1' start='0xFFB90000' end='0xFFB91000' /><slave name='uart0.axi_slave0' start='0xFFC02000' end='0xFFC03000' /><slave name='uart1.axi_slave0' start='0xFFC03000' end='0xFFC04000' /><slave name='i2c0.axi_slave0' start='0xFFC04000' end='0xFFC05000' /><slave name='i2c1.axi_slave0' start='0xFFC05000' end='0xFFC06000' /><slave name='i2c2.axi_slave0' start='0xFFC06000' end='0xFFC07000' /><slave name='i2c3.axi_slave0' start='0xFFC07000' end='0xFFC08000' /><slave name='timer0.axi_slave0' start='0xFFC08000' end='0xFFC09000' /><slave name='timer1.axi_slave0' start='0xFFC09000' end='0xFFC0A000' /><slave name='timer2.axi_slave0' start='0xFFD00000' end='0xFFD01000' /><slave name='timer3.axi_slave0' start='0xFFD01000' end='0xFFD02000' /><slave name='clkmgr.axi_slave0' start='0xFFD04000' end='0xFFD05000' /><slave name='rstmgr.axi_slave0' start='0xFFD05000' end='0xFFD06000' /><slave name='sysmgr.axi_slave0' start='0xFFD08000' end='0xFFD0C000' /><slave name='dma.axi_slave0' start='0xFFE01000' end='0xFFE02000' /><slave name='spi0.axi_slave0' start='0xFFE02000' end='0xFFE03000' /><slave name='spi1.axi_slave0' start='0xFFE03000' end='0xFFE04000' /><slave name='arm_gic_0.axi_slave1' start='0xFFFEC100' end='0xFFFEC200' /><slave name='timer.axi_slave0' start='0xFFFEC600' end='0xFFFEC700' /><slave name='arm_gic_0.axi_slave0' start='0xFFFED000' end='0xFFFEE000' /><slave name='L2.axi_slave0' start='0xFFFEF000' end='0xFFFF0000' /><slave name='axi_ocram.axi_slave0' start='0xFFFF0000' end='0x100000000' /></address-map>
F2S_Width | 2
S2F_Width | 2
LWH2F_Enable | true
F2SDRAM_Width |
F2SDRAM_Type |
BONDING_OUT_ENABLED | false
quartus_ini_hps_ip_f2sdram_bonding_out | false
F2H_SDRAM0_CLOCK_FREQ | 100
F2H_SDRAM1_CLOCK_FREQ | 100
F2H_SDRAM2_CLOCK_FREQ | 100
F2H_SDRAM3_CLOCK_FREQ | 100
F2H_SDRAM4_CLOCK_FREQ | 100
F2H_SDRAM5_CLOCK_FREQ | 100
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_arm_a9_0

arm_a9 v1.0

hps_0_clk_0 | clk | hps_0_arm_a9_0
clock_sink
clk_reset
reset_sink
|  | altera_axi_master | hps_0_bridges
|  | axi_h2f
|  | altera_axi_master
|  | axi_h2f_lw
|  | altera_axi_master | hps_0_arm_gic_0
|  | axi_slave0
|  | altera_axi_master
|  | axi_slave1
|  | altera_axi_master | hps_0_L2
|  | axi_slave0
|  | altera_axi_master | hps_0_dma
|  | axi_slave0
|  | altera_axi_master | hps_0_sysmgr
|  | axi_slave0
|  | altera_axi_master | hps_0_clkmgr
|  | axi_slave0
|  | altera_axi_master | hps_0_rstmgr
|  | axi_slave0
|  | altera_axi_master | hps_0_fpgamgr
|  | axi_slave0
|  | altera_axi_master
|  | axi_slave1
|  | altera_axi_master | hps_0_uart0
|  | axi_slave0
|  | altera_axi_master | hps_0_uart1
|  | axi_slave0
|  | altera_axi_master | hps_0_timer0
|  | axi_slave0
|  | altera_axi_master | hps_0_timer1
|  | axi_slave0
|  | altera_axi_master | hps_0_timer2
|  | axi_slave0
|  | altera_axi_master | hps_0_timer3
|  | axi_slave0
|  | altera_axi_master | hps_0_gpio0
|  | axi_slave0
|  | altera_axi_master | hps_0_gpio1
|  | axi_slave0
|  | altera_axi_master | hps_0_gpio2
|  | axi_slave0
|  | altera_axi_master | hps_0_i2c0
|  | axi_slave0
|  | altera_axi_master | hps_0_i2c1
|  | axi_slave0
|  | altera_axi_master | hps_0_i2c2
|  | axi_slave0
|  | altera_axi_master | hps_0_i2c3
|  | axi_slave0
|  | altera_axi_master | hps_0_nand0
|  | axi_slave0
|  | altera_axi_master
|  | axi_slave1
|  | altera_axi_master | hps_0_spi0
|  | axi_slave0
|  | altera_axi_master | hps_0_spi1
|  | axi_slave0
|  | altera_axi_master | hps_0_qspi
|  | axi_slave0
|  | altera_axi_master
|  | axi_slave1
|  | altera_axi_master | hps_0_sdmmc
|  | axi_slave0
|  | altera_axi_master | hps_0_usb0
|  | axi_slave0
|  | altera_axi_master | hps_0_usb1
|  | axi_slave0
|  | altera_axi_master | hps_0_gmac0
|  | axi_slave0
|  | altera_axi_master | hps_0_gmac1
|  | axi_slave0
|  | altera_axi_master | hps_0_axi_ocram
|  | axi_slave0
|  | altera_axi_master | hps_0_timer
|  | axi_slave0

## Parameters
address_map | <address-map><slave name='gmac0.axi_slave0' start='0xFF700000' end='0xFF702000' /><slave name='gmac1.axi_slave0' start='0xFF702000' end='0xFF704000' /><slave name='sdmmc.axi_slave0' start='0xFF704000' end='0xFF705000' /><slave name='qspi.axi_slave0' start='0xFF705000' end='0xFF706000' /><slave name='fpgamgr.axi_slave0' start='0xFF706000' end='0xFF707000' /><slave name='gpio0.axi_slave0' start='0xFF708000' end='0xFF709000' /><slave name='gpio1.axi_slave0' start='0xFF709000' end='0xFF70A000' /><slave name='gpio2.axi_slave0' start='0xFF70A000' end='0xFF70B000' /><slave name='nand0.axi_slave0' start='0xFF900000' end='0xFFA00000' /><slave name='qspi.axi_slave1' start='0xFFA00000' end='0xFFA01000' /><slave name='usb0.axi_slave0' start='0xFFB00000' end='0xFFB01000' /><slave name='usb1.axi_slave0' start='0xFFB40000' end='0xFFB41000' /><slave name='nand0.axi_slave1' start='0xFFB80000' end='0xFFB90000' /><slave name='fpgamgr.axi_slave1' start='0xFFB90000' end='0xFFB91000' /><slave name='uart0.axi_slave0' start='0xFFC02000' end='0xFFC03000' /><slave name='uart1.axi_slave0' start='0xFFC03000' end='0xFFC04000' /><slave name='i2c0.axi_slave0' start='0xFFC04000' end='0xFFC05000' /><slave name='i2c1.axi_slave0' start='0xFFC05000' end='0xFFC06000' /><slave name='i2c2.axi_slave0' start='0xFFC06000' end='0xFFC07000' /><slave name='i2c3.axi_slave0' start='0xFFC07000' end='0xFFC08000' /><slave name='timer0.axi_slave0' start='0xFFC08000' end='0xFFC09000' /><slave name='timer1.axi_slave0' start='0xFFC09000' end='0xFFC0A000' /><slave name='timer2.axi_slave0' start='0xFFD00000' end='0xFFD01000' /><slave name='timer3.axi_slave0' start='0xFFD01000' end='0xFFD02000' /><slave name='clkmgr.axi_slave0' start='0xFFD04000' end='0xFFD05000' /><slave name='rstmgr.axi_slave0' start='0xFFD05000' end='0xFFD06000' /><slave name='sysmgr.axi_slave0' start='0xFFD08000' end='0xFFD0C000' /><slave name='dma.axi_slave0' start='0xFFE01000' end='0xFFE02000' /><slave name='spi0.axi_slave0' start='0xFFE02000' end='0xFFE03000' /><slave name='spi1.axi_slave0' start='0xFFE03000' end='0xFFE04000' /><slave name='arm_gic_0.axi_slave1' start='0xFFFEC100' end='0xFFFEC200' /><slave name='timer.axi_slave0' start='0xFFFEC600' end='0xFFFEC700' /><slave name='arm_gic_0.axi_slave0' start='0xFFFED000' end='0xFFFEE000' /><slave name='L2.axi_slave0' start='0xFFFEF000' end='0xFFFF0000' /><slave name='axi_ocram.axi_slave0' start='0xFFFF0000' end='0x100000000' /></address-map>
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_arm_a9_1

arm_a9 v1.0

hps_0_clk_0 | clk | hps_0_arm_a9_1
clock_sink
clk_reset
reset_sink
|  | altera_axi_master | hps_0_bridges
|  | axi_h2f
|  | altera_axi_master
|  | axi_h2f_lw
|  | altera_axi_master | hps_0_arm_gic_0
|  | axi_slave0
|  | altera_axi_master
|  | axi_slave1
|  | altera_axi_master | hps_0_L2
|  | axi_slave0
|  | altera_axi_master | hps_0_dma
|  | axi_slave0
|  | altera_axi_master | hps_0_sysmgr
|  | axi_slave0
|  | altera_axi_master | hps_0_clkmgr
|  | axi_slave0
|  | altera_axi_master | hps_0_rstmgr
|  | axi_slave0
|  | altera_axi_master | hps_0_fpgamgr
|  | axi_slave0
|  | altera_axi_master
|  | axi_slave1
|  | altera_axi_master | hps_0_uart0
|  | axi_slave0
|  | altera_axi_master | hps_0_uart1
|  | axi_slave0
|  | altera_axi_master | hps_0_timer0
|  | axi_slave0
|  | altera_axi_master | hps_0_timer1
|  | axi_slave0
|  | altera_axi_master | hps_0_timer2
|  | axi_slave0
|  | altera_axi_master | hps_0_timer3
|  | axi_slave0
|  | altera_axi_master | hps_0_gpio0
|  | axi_slave0
|  | altera_axi_master | hps_0_gpio1
|  | axi_slave0
|  | altera_axi_master | hps_0_gpio2
|  | axi_slave0
|  | altera_axi_master | hps_0_i2c0
|  | axi_slave0
|  | altera_axi_master | hps_0_i2c1
|  | axi_slave0
|  | altera_axi_master | hps_0_i2c2
|  | axi_slave0
|  | altera_axi_master | hps_0_i2c3
|  | axi_slave0
|  | altera_axi_master | hps_0_nand0
|  | axi_slave0
|  | altera_axi_master
|  | axi_slave1
|  | altera_axi_master | hps_0_spi0
|  | axi_slave0
|  | altera_axi_master | hps_0_spi1
|  | axi_slave0
|  | altera_axi_master | hps_0_qspi
|  | axi_slave0
|  | altera_axi_master
|  | axi_slave1
|  | altera_axi_master | hps_0_sdmmc
|  | axi_slave0
|  | altera_axi_master | hps_0_usb0
|  | axi_slave0
|  | altera_axi_master | hps_0_usb1
|  | axi_slave0
|  | altera_axi_master | hps_0_gmac0
|  | axi_slave0
|  | altera_axi_master | hps_0_gmac1
|  | axi_slave0
|  | altera_axi_master | hps_0_axi_ocram
|  | axi_slave0
|  | altera_axi_master | hps_0_timer
|  | axi_slave0

## Parameters
address_map | <address-map><slave name='gmac0.axi_slave0' start='0xFF700000' end='0xFF702000' /><slave name='gmac1.axi_slave0' start='0xFF702000' end='0xFF704000' /><slave name='sdmmc.axi_slave0' start='0xFF704000' end='0xFF705000' /><slave name='qspi.axi_slave0' start='0xFF705000' end='0xFF706000' /><slave name='fpgamgr.axi_slave0' start='0xFF706000' end='0xFF707000' /><slave name='gpio0.axi_slave0' start='0xFF708000' end='0xFF709000' /><slave name='gpio1.axi_slave0' start='0xFF709000' end='0xFF70A000' /><slave name='gpio2.axi_slave0' start='0xFF70A000' end='0xFF70B000' /><slave name='nand0.axi_slave0' start='0xFF900000' end='0xFFA00000' /><slave name='qspi.axi_slave1' start='0xFFA00000' end='0xFFA01000' /><slave name='usb0.axi_slave0' start='0xFFB00000' end='0xFFB01000' /><slave name='usb1.axi_slave0' start='0xFFB40000' end='0xFFB41000' /><slave name='nand0.axi_slave1' start='0xFFB80000' end='0xFFB90000' /><slave name='fpgamgr.axi_slave1' start='0xFFB90000' end='0xFFB91000' /><slave name='uart0.axi_slave0' start='0xFFC02000' end='0xFFC03000' /><slave name='uart1.axi_slave0' start='0xFFC03000' end='0xFFC04000' /><slave name='i2c0.axi_slave0' start='0xFFC04000' end='0xFFC05000' /><slave name='i2c1.axi_slave0' start='0xFFC05000' end='0xFFC06000' /><slave name='i2c2.axi_slave0' start='0xFFC06000' end='0xFFC07000' /><slave name='i2c3.axi_slave0' start='0xFFC07000' end='0xFFC08000' /><slave name='timer0.axi_slave0' start='0xFFC08000' end='0xFFC09000' /><slave name='timer1.axi_slave0' start='0xFFC09000' end='0xFFC0A000' /><slave name='timer2.axi_slave0' start='0xFFD00000' end='0xFFD01000' /><slave name='timer3.axi_slave0' start='0xFFD01000' end='0xFFD02000' /><slave name='clkmgr.axi_slave0' start='0xFFD04000' end='0xFFD05000' /><slave name='rstmgr.axi_slave0' start='0xFFD05000' end='0xFFD06000' /><slave name='sysmgr.axi_slave0' start='0xFFD08000' end='0xFFD0C000' /><slave name='dma.axi_slave0' start='0xFFE01000' end='0xFFE02000' /><slave name='spi0.axi_slave0' start='0xFFE02000' end='0xFFE03000' /><slave name='spi1.axi_slave0' start='0xFFE03000' end='0xFFE04000' /><slave name='arm_gic_0.axi_slave1' start='0xFFFEC100' end='0xFFFEC200' /><slave name='timer.axi_slave0' start='0xFFFEC600' end='0xFFFEC700' /><slave name='arm_gic_0.axi_slave0' start='0xFFFED000' end='0xFFFEE000' /><slave name='L2.axi_slave0' start='0xFFFEF000' end='0xFFFF0000' /><slave name='axi_ocram.axi_slave0' start='0xFFFF0000' end='0x100000000' /></address-map>
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_arm_gic_0

arm_gic v1.0

hps_0_bridges | axi_f2h | hps_0_arm_gic_0
axi_slave0
axi_f2h
axi_slave1
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
altera_axi_master
axi_slave1
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
altera_axi_master
axi_slave1
|  | irq_rx_offset_32 | hps_0_L2
|  | interrupt_sender
|  | irq_rx_offset_104 | hps_0_dma
|  | interrupt_sender
|  | irq_rx_offset_166 | hps_0_fpgamgr
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_uart0
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_uart1
|  | interrupt_sender
|  | irq_rx_offset_166 | hps_0_timer0
|  | interrupt_sender
|  | irq_rx_offset_166 | hps_0_timer1
|  | interrupt_sender
|  | irq_rx_offset_166 | hps_0_timer2
|  | interrupt_sender
|  | irq_rx_offset_166 | hps_0_timer3
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_gpio0
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_gpio1
|  | interrupt_sender
|  | irq_rx_offset_166 | hps_0_gpio2
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_i2c0
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_i2c1
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_i2c2
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_i2c3
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_nand0
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_spi0
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_spi1
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_qspi
|  | interrupt_sender
|  | irq_rx_offset_136 | hps_0_sdmmc
|  | interrupt_sender
|  | irq_rx_offset_104 | hps_0_usb0
|  | interrupt_sender
|  | irq_rx_offset_104 | hps_0_usb1
|  | interrupt_sender
|  | irq_rx_offset_104 | hps_0_gmac0
|  | interrupt_sender
|  | irq_rx_offset_104 | hps_0_gmac1
|  | interrupt_sender
|  | arm_gic_ppi | hps_0_timer
|  | interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_L2

L2 v1.0

hps_0_bridges | axi_f2h | hps_0_L2
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_32
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_dma

dma v1.0

hps_0_bridges | axi_f2h | hps_0_dma
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_104
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_sysmgr

sysmgr v1.0

hps_0_bridges | axi_f2h | hps_0_sysmgr
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_clkmgr

clkmgr v1.0

hps_0_bridges | axi_f2h | hps_0_clkmgr
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_rstmgr

rstmgr v1.0

hps_0_bridges | axi_f2h | hps_0_rstmgr
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_fpgamgr

fpgamgr v1.0

hps_0_bridges | axi_f2h | hps_0_fpgamgr
axi_slave0
axi_f2h
axi_slave1
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
altera_axi_master
axi_slave1
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
altera_axi_master
axi_slave1
hps_0_arm_gic_0 | irq_rx_offset_166
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_uart0

snps_uart v1.0

hps_0_bridges | axi_f2h | hps_0_uart0
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_uart1

snps_uart v1.0

hps_0_bridges | axi_f2h | hps_0_uart1
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_timer0

dw-apb-timer-sp v1.0

hps_0_bridges | axi_f2h | hps_0_timer0
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_166
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_timer1

dw-apb-timer-sp v1.0

hps_0_bridges | axi_f2h | hps_0_timer1
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_166
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_timer2

dw-apb-timer-osc v1.0

hps_0_bridges | axi_f2h | hps_0_timer2
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_166
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_timer3

dw-apb-timer-osc v1.0

hps_0_bridges | axi_f2h | hps_0_timer3
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_166
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_gpio0

dw-gpio v1.0

hps_0_bridges | axi_f2h | hps_0_gpio0
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_gpio1

dw-gpio v1.0

hps_0_bridges | axi_f2h | hps_0_gpio1
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_gpio2

dw-gpio v1.0

hps_0_bridges | axi_f2h | hps_0_gpio2
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_166
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_i2c0

designware-i2c v1.0

hps_0_bridges | axi_f2h | hps_0_i2c0
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_i2c1

designware-i2c v1.0

hps_0_bridges | axi_f2h | hps_0_i2c1
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_i2c2

designware-i2c v1.0

hps_0_bridges | axi_f2h | hps_0_i2c2
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_i2c3

designware-i2c v1.0

hps_0_bridges | axi_f2h | hps_0_i2c3
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_nand0

denali_nand v1.0

hps_0_bridges | axi_f2h | hps_0_nand0
axi_slave0
axi_f2h
axi_slave1
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
altera_axi_master
axi_slave1
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
altera_axi_master
axi_slave1
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_spi0

spi v1.0

hps_0_bridges | axi_f2h | hps_0_spi0
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_spi1

spi v1.0

hps_0_bridges | axi_f2h | hps_0_spi1
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_qspi

qspi v1.0

hps_0_bridges | axi_f2h | hps_0_qspi
axi_slave0
axi_f2h
axi_slave1
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
altera_axi_master
axi_slave1
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
altera_axi_master
axi_slave1
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_sdmmc

sdmmc v1.0

hps_0_bridges | axi_f2h | hps_0_sdmmc
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_136
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_usb0

usb v1.0

hps_0_bridges | axi_f2h | hps_0_usb0
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_104
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_usb1

usb v1.0

hps_0_bridges | axi_f2h | hps_0_usb1
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_104
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_gmac0

stmmac v1.0

hps_0_bridges | axi_f2h | hps_0_gmac0
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_104
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_gmac1

stmmac v1.0

hps_0_bridges | axi_f2h | hps_0_gmac1
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | irq_rx_offset_104
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_axi_ocram

axi_ocram v1.0

hps_0_bridges | axi_f2h | hps_0_axi_ocram
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## hps_0_timer

timer v1.0

hps_0_bridges | axi_f2h | hps_0_timer
axi_slave0
hps_0_clk_0 | clk
clock_sink
clk_reset
reset_sink
hps_0_arm_a9_0 | altera_axi_master
axi_slave0
hps_0_arm_a9_1 | altera_axi_master
axi_slave0
hps_0_arm_gic_0 | arm_gic_ppi
interrupt_sender

## Parameters
AUTO_CLOCK_SINK_CLOCK_RATE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## master_0

altera_jtag_avalon_master v13.1

clk_0 | clk | master_0
clk
clk_reset
clk_reset
|  | master | vga_led_0
|  | avalon_slave_0

## Parameters
USE_PLI | 0
PLI_PORT | 50000
COMPONENT_CLOCK | 0
FAST_VER | 0
FIFO_DEPTHS | 2
AUTO_DEVICE_FAMILY | CYCLONEV
AUTO_DEVICE | 5CSXFC6D6F31C8ES
deviceFamily | Cyclone V
generateLegacySim | false

## Software Assignments (none)

## vga_led_0

vga_led v1.0

clk_0 | clk | vga_led_0
clock
clk_reset
reset_sink
hps_0_bridges | h2f_lw
avalon_slave_0
master_0 | master
avalon_slave_0

## Parameters
AUTO_CLOCK_CLOCK_RATE | 50000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

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