module RAM (
	input logic clk50,
	input logic audio_clk,
	input logic[10:0] address_w,
	input logic [10:0] address_r,
	input logic wren,
	input logic ren,
	input logic [15:0] data_input,
	output logic [15:0] data_output
);

//logic [2047:0][15:0] memory_cell;
logic [2047:0][15:0] memory_cell;
//logic [10:0] addr_w=address_w;
//logic [10:0] addr_r=address_r;
always_ff @(posedge clk50) begin
	if(wren) begin
		memory_cell[address_w] <= data_input;
//		addr_w <= addr_w+1'd1;
//		if(addr_w==11'd2047)
//			addr_w<=11'd0;
	end 
	
end

always_ff @(posedge audio_clk) begin
	if(ren) begin
		data_output <= memory_cell[address_r];
//		addr_r <= addr_r + 1'd1;
//		if(addr_r==11'd2047)
//			addr_r<=11'd0;
	end
	
end
	
endmodule
