module RAM_Controller(
	input clk50,audio_clk,
	input logic [15:0] data_in,
	output logic [15:0] data
);

RAM audio_ram  (
	.clk50(clk50),
	.audio_clk(audio_clk),
	.address_w(address_w),
	.address_r(adddress_r),
	.wren(wren),
	.ren(ren),
	.data_input(data_in),
	 .data_output(data)
);

logic [8:0] address_r, adddress_w;
logic wren;
logic ren;

adddress_w = 9'd0;
adddress_r = 9'd0;


always_ff @(posedge clk50) begin
	adddress_w <= adddress_w +9'd1;
	wren <= 1'd1;	
	if(adddress_w==9'd511)
		adddress_w <= 9'd0;
end


always_ff @(posedge audio_clk) begin
	if(adddress_w>=256) begin
	ren = 1'd1;
	adddress_r <= adddress_r + 9'd1;
	else
		ren = 1'd0;
	if(adddress_r==9'd511)
		adddress_r <= 9'd0;
end