module RAM_Controller(
	input clk50,audio_clk,
	input logic [15:0] data_in,
	input logic sample_req_c,
	output logic [15:0] data_out,
	input [10:0] address_r,
	input ren,
	input c
);

RAM audio_ram  (
	.clk50(clk50),
	.audio_clk(audio_clk),
	.address_w(address_w[10:0]),
	.address_r(address_r[10:0]),
	.wren(wren),
	.ren(ren),
	.data_input(data_in),
	 .data_output(data_out)
);


//logic [10:0] address_r = 11'd0;
logic wren=1'd1;
//logic ren=1'd0;
//reg [7:0] indexr=7'd0;
//reg [7:0] indexw=7'd0;

logic [10:0] address_w = 11'd0;

//logic [10:0] counter1=11'd0;
//logic [10:0] counter2=11'd0;
//logic [15:0] buffer1[0:99];
//logic [15:0] buffer2[0:99];
//logic buf_cnt;

always_ff @(posedge audio_clk) begin
	

		end
		

//end

always_ff @(posedge clk50) begin


if(wren)	begin
	address_w<=address_w+11'd1;
//		if(address_w>=11'd2046) begin
//			wren<= 1'b0;
//		end
	end
	if(c)
		wren <= 1'b1;
	else wren <= 1'b0;
//	end else if (address_r>=11'd2046) begin
//		address_w<=11'd0;
//		wren <= 1'b1;
//	end
	end




endmodule