module RAM_Controller(
	input clk50,audio_clk,
	input logic [15:0] data_in,
	output logic [15:0] data
);

RAM audio_ram  (
	.clk50(clk50),
	.audio_clk(audio_clk),
	.address_w(address_w[10:0]),
	.address_r(address_r[10:0]),
	.wren(wren),
	.ren(ren),
	.data_input(data_in),
	 .data_output(data)
);


logic [11:0] address_r = 12'd0;
logic wren=1'd1;
logic ren=1'd0;

logic [11:0] address_w = 12'd0;

//logic [10:0] counter1=11'd0;
//logic [10:0] counter2=11'd0;


always_ff @(posedge clk50) begin
/*
	if(wren) begin
		counter1 <= counter1+1'd1;
		if(counter1[9:0]==10'b1111111111) begin
			ren<=1'd1;
			
		end
		if(counter1==11'b11111111111)begin
			counter1<=11'd0;
			wren<=1'b0;
		end
		
	end
	
	
		if(ren) begin
		if(counter2[9:0]==10'b1111111111) begin
		wren<=1'b1;
		address_w=11'd1024;
		end
		
	if (counter2==11'b11111111111) begin
		
		wren<=1'b1;
		address_w<=11'd0;
	end
	end
*/
/*	
	//wren <= 1'd1;	
	if(wren) begin
		address_w <= adddress_w +9'd1;
		ren<=1'd1;
	end 
	if (address_w==9'd255)begin
		
		wren<=1'd0;
		
	end 
	if (address_r==9'd255) begin
		wren<=1;
		if(address_w==9'd511) begin
			adddress_w <= 9'd0;
			if(adddress_r<9'd511)
				wren<=1'd0;
			else 
				wren<=1'd1;
		end
	end
	*/
/*	
	if(wren)
			address_w <= address_w + 12'd1;

	if(address_w[11]) begin
			wren <= 1'b0;
			
		
	//	address_w <= 12'd0;
	end
	
	if(address_r[11]) begin
			wren <=1'b1;
			address_w <= 12'd0;
			
				
	end
*/	
	/*
	if(adddress_w>=0 && adddress_w<9'd511 && adddress_r<9'd511) begin	
		ren <= 1'd0;
		wren <= 1'd1;
	end
	if(adddress_w==9'd511 && adddress_r < 9'd511) begin
		wren <=1'd0;
		ren <= 1'd1;
	end
	if(adddress_r==9'd511 && adddress_w ==9'd511) begin
		wren <= 1'd1;
		adddress_w <= 9'd0;
		ren <= 1'd0;
		adddress_r <=9'd0;
	end
	*/
	
end

always_ff @(posedge audio_clk) begin
/*
	if (ren) begin
			counter2<=counter2+1'b1;
	if (counter2==11'b11111111111) 
		counter2<=11'd0;
*/	

/*
	if(ren) 
	address_r <= address_r + 12'd1;
	if(address_w[11]) begin
		ren<=1'b1;
		address_r<=12'd0;
	end
	if(address_r[11]) begin
		ren<=1'b0;
		address_r <= 12'd0;
	end
//end
*/	
end

endmodule