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# THIS IS A WIZARD-GENERATED FILE.                           
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# Version 13.1.1 Build 166 11/26/2013 SJ Full Version
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# Copyright (C) 1991-2013 Altera Corporation
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# Clock constraints

create_clock -name "clk" -period 20.000ns [get_ports {OSC_50_B4A}]


# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks

# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty

# tsu/th constraints

# tco constraints

# tpd constraints

