module linear_transform (
    input logic clk,
    input logic reset,
    input logic on,
    input logic signed [31:0] M_1, M_2, M_3, M_4, M_5, M_6, M_7, M_8, M_9, M_10, M_11, M_12, M_13, M_14, M_15, M_16,
    input logic signed [31:0] c_1, c_2, c_3, c_4, c_5, c_6, c_7, c_8, c_9, c_10, c_11, c_12, c_13, c_14, c_15, c_16,

    output logic write,
    output logic signed [31:0] y
);

logic signed [31:0] temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8, temp9, temp10, temp11, temp12, temp13, temp14, temp15, temp16;


assign temp1 = M_1 * c_1;
assign temp2 = M_2 * c_2;
assign temp3 = M_3 * c_3;
assign temp4 = M_4 * c_4;
assign temp5 = M_5 * c_5;
assign temp6 = M_6 * c_6;
assign temp7 = M_7 * c_7;
assign temp8 = M_8 * c_8;
assign temp9 = M_9 * c_9;
assign temp10 = M_10 * c_10;
assign temp11 = M_11 * c_11;
assign temp12 = M_12 * c_12;
assign temp13 = M_13 * c_13;
assign temp14 = M_14 * c_14;
assign temp15 = M_15 * c_15;
assign temp16 = M_16 * c_16;

always @(posedge clk) begin
    if (reset) begin
        write <= 0;
        y <= 32'b 0;
    end

    else if (on) begin
            write <= 1;
            y <= temp1 + temp2 + temp3 + temp4 + temp5 + temp6 + temp7 + temp8 + temp9 + temp10 + temp11 + temp12 + temp13 + temp14 + temp15 + temp16;
    end

    else begin
        write <= 0;
        y <= 32'b 0;
    end
end



endmodule