module vector_addition (
    input logic clk,
    input logic reset,
    input logic start,
    input logic signed [31:0] c_1_1,
    input logic signed [31:0] c_1_2,
    input logic signed [31:0] c_1_3,
    input logic signed [31:0] c_1_4,
    input logic signed [31:0] c_1_5,
    input logic signed [31:0] c_1_6,
    input logic signed [31:0] c_1_7,
    input logic signed [31:0] c_1_8,
    input logic signed [31:0] c_1_9,
    input logic signed [31:0] c_1_10,
    input logic signed [31:0] c_1_11,
    input logic signed [31:0] c_1_12,
    input logic signed [31:0] c_1_13,
    input logic signed [31:0] c_1_14,
    input logic signed [31:0] c_1_15,
    input logic signed [31:0] c_1_16,

    input logic signed [31:0] c_2_1,
    input logic signed [31:0] c_2_2,
    input logic signed [31:0] c_2_3,
    input logic signed [31:0] c_2_4,
    input logic signed [31:0] c_2_5,
    input logic signed [31:0] c_2_6,
    input logic signed [31:0] c_2_7,
    input logic signed [31:0] c_2_8,
    input logic signed [31:0] c_2_9,
    input logic signed [31:0] c_2_10,
    input logic signed [31:0] c_2_11,
    input logic signed [31:0] c_2_12,
    input logic signed [31:0] c_2_13,
    input logic signed [31:0] c_2_14,
    input logic signed [31:0] c_2_15,
    input logic signed [31:0] c_2_16,
    
    output logic done,
    output logic signed [31:0] c_1,
    output logic signed [31:0] c_2,
    output logic signed [31:0] c_3,
    output logic signed [31:0] c_4,
    output logic signed [31:0] c_5,
    output logic signed [31:0] c_6,
    output logic signed [31:0] c_7,
    output logic signed [31:0] c_8,
    output logic signed [31:0] c_9,
    output logic signed [31:0] c_10,
    output logic signed [31:0] c_11,
    output logic signed [31:0] c_12,
    output logic signed [31:0] c_13,
    output logic signed [31:0] c_14,
    output logic signed [31:0] c_15,
    output logic signed [31:0] c_16);

adder adder_1 (clk, reset, start, c_1_1, c_2_1, c_1, done);
adder adder_2 (clk, reset, start, c_1_2, c_2_2, c_2, done);
adder adder_3 (clk, reset, start, c_1_3, c_2_3, c_3, done);
adder adder_4 (clk, reset, start, c_1_4, c_2_4, c_4, done);
adder adder_5 (clk, reset, start, c_1_5, c_2_5, c_5, done);
adder adder_6 (clk, reset, start, c_1_6, c_2_6, c_6, done);
adder adder_7 (clk, reset, start, c_1_7, c_2_7, c_7, done);
adder adder_8 (clk, reset, start, c_1_8, c_2_8, c_8, done);
adder adder_9 (clk, reset, start, c_1_9, c_2_9, c_9, done);
adder adder_10 (clk, reset, start, c_1_10, c_2_10, c_10, done);
adder adder_11 (clk, reset, start, c_1_11, c_2_11, c_11, done);
adder adder_12 (clk, reset, start, c_1_12, c_2_12, c_12, done);
adder adder_13 (clk, reset, start, c_1_13, c_2_13, c_13, done);
adder adder_14 (clk, reset, start, c_1_14, c_2_14, c_14, done);
adder adder_15 (clk, reset, start, c_1_15, c_2_15, c_15, done);
adder adder_16 (clk, reset, start, c_1_16, c_2_16, c_16, done);

endmodule


module adder(
    input logic clk,
    input logic reset,
    input logic on,
    input logic signed [31:0] c1,
    input logic signed [31:0] c2,

    output logic signed [31:0] c,
    output logic done
);

    always @(posedge clk) begin
        if(reset) begin
            done <= 0;
            c <= 32'b0;
        end

        else if (on) begin
            done <= 1;
            c <= c1 + c2;
        end

        else begin
            done <= 0;
            c <= 32'b0;
        end
    end

endmodule