# TCL File Generated by Component Editor 21.1
# Tue May 10 18:56:43 EDT 2022
# DO NOT MODIFY


# 
# encrypted_domain "Encrypted Domain" v1.0
#  2022.05.10.18:56:43
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module encrypted_domain
# 
set_module_property DESCRIPTION ""
set_module_property NAME encrypted_domain
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "Encrypted Domain"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
set_module_assignment embeddedsw.dts.vendor "csee4840-sonny-hu"
set_module_assignment embeddedsw.dts.name "encrypted_domain_accelerator"
set_module_assignment embeddedsw.dts.group "encrypted_domain"

# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL encrypted_domain
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file encrypted_domain.sv SYSTEM_VERILOG PATH ../encrypted_domain/encrypted_domain.sv TOP_LEVEL_FILE


# 
# parameters
# 


# 
# display items
# 


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1


# 
# connection point reset
# 
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset reset reset Input 1


# 
# connection point avalon_slave_0
# 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock
set_interface_property avalon_slave_0 associatedReset reset
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
set_interface_property avalon_slave_0 EXPORT_OF ""
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""

add_interface_port avalon_slave_0 writedata writedata Input 32
add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 chipselect chipselect Input 1
add_interface_port avalon_slave_0 address address Input 4
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0


# 
# connection point ed
# 
add_interface ed conduit end
set_interface_property ed associatedClock clock
set_interface_property ed associatedReset ""
set_interface_property ed ENABLED true
set_interface_property ed EXPORT_OF ""
set_interface_property ed PORT_NAME_MAP ""
set_interface_property ed CMSIS_SVD_VARIABLES ""
set_interface_property ed SVD_ADDRESS_GROUP ""

add_interface_port ed DATA_OUT_0 data_out_0 Output 32
add_interface_port ed DATA_OUT_1 data_out_1 Output 32
add_interface_port ed DATA_OUT_2 data_out_2 Output 32
add_interface_port ed DATA_OUT_3 data_out_3 Output 32
add_interface_port ed DATA_OUT_4 data_out_4 Output 32
add_interface_port ed DATA_OUT_5 data_out_5 Output 32
add_interface_port ed DATA_OUT_6 data_out_6 Output 32
add_interface_port ed DATA_OUT_7 data_out_7 Output 32
add_interface_port ed DATA_OUT_8 data_out_8 Output 32
add_interface_port ed DATA_OUT_9 data_out_9 Output 32
add_interface_port ed DATA_OUT_10 data_out_10 Output 32
add_interface_port ed DATA_OUT_11 data_out_11 Output 32
add_interface_port ed DATA_OUT_12 data_out_12 Output 32
add_interface_port ed DATA_OUT_13 data_out_13 Output 32
add_interface_port ed DATA_OUT_14 data_out_14 Output 32
add_interface_port ed DATA_OUT_15 data_out_15 Output 32
add_interface_port ed all_loaded all_loaded Input 1
add_interface_port ed OUTPUT_LENGTH output_length Output 5
add_interface_port ed OUTPUT_WIDTH output_width Output 5
add_interface_port ed DONE done Output 1

