module lfsr (clk, resetn, seed, lfsr_out);

    input logic clk, resetn;
    input logic [15:0] seed;
    output logic signed [15:0] lfsr_out;

	logic [15:0] lfsr_next;

        always @(posedge clk) begin
            if (resetn) begin
                lfsr_out <= seed;
            end
            else begin
                lfsr_out <= lfsr_next;
            end
        end

	assign lfsr_next = {lfsr_out[14:0], lfsr_out[15]^lfsr_out[12]^lfsr_out[5]^lfsr_out[0]};

endmodule