# ----------------------------- TESTBENCH STARTS ----------------------------- 
.PHONY: default program clean vector_addition lint

SVFILES = vector_addition.sv linear_transform.sv weighted_inner_product.sv encrypted_domain.sv

# Path to USB Blaster II firmware file in Quartus, only for openFPGALoader

BLASTER-6810 = /opt/intelFPGA_lite/21.1/quartus/linux64/blaster_6810.hex

default :
	@echo "No target given. Try:\n  make vector_addition.vcd\nmake linear_transform.vcd\n  make weighted_inner_product.vcd\n make encrypted_domain.vcd\n make lint\n  make program"

# Program the FPGA through the USB Blaster connection
# It is the second thing on the JTAG chain (the HPS block is first), hence @2

program : output_files/encrypted_domain.sof
	quartus_pgm -c 1 -m jtag -o "p;output_files/encrypted_domain.sof@2"


# Compile the project in Quartus

output_files/encrypted_domain.sof : encrypted_domain.qpf $(SVFILES)
	quartus_sh --flow compile encrypted_domain

# Create the Quartus project files from a Tcl script

encrypted_domain.qpf encrypted_domain.qsf encrypted_domain.sdc : soc_system.tcl
	quartus_sh -t soc_system.tcl


# Program the FPGA using openFPGALoader, an alternative to the
# Quartus programmer

program-open : output_files/encrypted_domain.svf
	openFPGALoader -b de1Soc \
	  --probe-firmware $(BLASTER-6810) \
	  output_files/encrypted_domain.svf

# Convert the .sof to to an .svf file for openFPGALoader

output_files/encrypted_domain.svf : output_files/encrypted_domain.sof
	quartus_cpf -c \
		--operation p --voltage 3.3 --freq 24.0MHz \
		output_files/encrypted_domain.sof output_files/encrypted_domain.svf



# Quickly check the System Verilog files for errors

lint :
	for file in $(SVFILES); do \
	verilator --lint-only -Wall $$file; done



# Run Verilator simulations

vector_addition.vcd : obj_dir/Vvector_addition
	obj_dir/Vvector_addition

linear_transform.vcd : obj_dir/Vlinear_transform
	obj_dir/Vlinear_transform

weighted_inner_product.vcd : obj_dir/Vweighted_inner_product
	obj_dir/Vweighted_inner_product

encrypted_domain.vcd : obj_dir/Vencrypted_domain
	obj_dir/Vencrypted_domain

# Create Verilator simulations

obj_dir/Vvector_addition : vector_addition.sv vector_addition.cpp
	verilator -trace -cc vector_addition.sv -exe vector_addition.cpp \
		-top-module vector_addition
	cd obj_dir && make -j -f Vvector_addition.mk

obj_dir/Vlinear_transform : linear_transform.sv linear_transform.cpp
	verilator -trace -cc linear_transform.sv -exe linear_transform.cpp \
		-top-module linear_transform
	cd obj_dir && make -j -f Vlinear_transform.mk

obj_dir/Vweighted_inner_product : weighted_inner_product.sv weighted_inner_product.cpp
	verilator -trace -cc weighted_inner_product.sv -exe weighted_inner_product.cpp \
		-top-module weighted_inner_product
	cd obj_dir && make -j -f Vweighted_inner_product.mk

obj_dir/Vencrypted_domain : encrypted_domain.sv encrypted_domain.cpp
	verilator -trace -cc encrypted_domain.sv -exe encrypted_domain.cpp \
		-top-module encrypted_domain
	cd obj_dir && make -j -f Vencrypted_domain.mk

clean_test: rm -rf obj_dir db incremental_db output_files \
	encrypted_domain.qpf encrypted_domain.qsf encrypted_domain.sdc encrypted_domain.qws c5_pin_model_dump.txt
# ------------------------------ TESTBENCH ENDS ------------------------------