# TCL File Generated by Component Editor 21.1
# Sat Mar 26 18:49:37 EDT 2022
# DO NOT MODIFY


# 
# new_component "new_component" v1.0
#  2022.03.26.18:49:37
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module new_component
# 
set_module_property DESCRIPTION ""
set_module_property NAME new_component
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME new_component
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL DE1_SoC_TV
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file DE1_SoC_TV.v VERILOG PATH DE1_SoC_TV.v TOP_LEVEL_FILE
add_fileset_file DIV.v VERILOG PATH v/DIV.v
add_fileset_file I2C_AV_Config.v VERILOG PATH v/I2C_AV_Config.v
add_fileset_file I2C_Controller.v VERILOG PATH v/I2C_Controller.v
add_fileset_file ITU_656_Decoder.v VERILOG PATH v/ITU_656_Decoder.v
add_fileset_file Line_Buffer.v VERILOG PATH v/Line_Buffer.v
add_fileset_file MAC_3.v VERILOG PATH v/MAC_3.v
add_fileset_file PLL.v VERILOG PATH v/PLL.v
add_fileset_file Reset_Delay.v VERILOG PATH v/Reset_Delay.v
add_fileset_file SEG7_LUT.v VERILOG PATH v/SEG7_LUT.v
add_fileset_file SEG7_LUT_6.v VERILOG PATH v/SEG7_LUT_6.v
add_fileset_file SEG7_LUT_8.v VERILOG PATH v/SEG7_LUT_8.v
add_fileset_file Sdram_PLL.v VERILOG PATH v/Sdram_PLL.v
add_fileset_file TD_Detect.v VERILOG PATH v/TD_Detect.v
add_fileset_file TP_RAM.v VERILOG PATH v/TP_RAM.v
add_fileset_file VGA_Ctrl.v VERILOG PATH v/VGA_Ctrl.v
add_fileset_file YCbCr2RGB.v VERILOG PATH v/YCbCr2RGB.v
add_fileset_file YUV422_to_444.v VERILOG PATH v/YUV422_to_444.v
add_fileset_file Sdram_PLL_0002.v VERILOG PATH v/Sdram_PLL/Sdram_PLL_0002.v


# 
# parameters
# 


# 
# display items
# 


# 
# connection point avalon_slave_0
# 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock ""
set_interface_property avalon_slave_0 associatedReset ""
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
set_interface_property avalon_slave_0 EXPORT_OF ""
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""

add_interface_port avalon_slave_0 ADC_CS_N export Bidir 1
add_interface_port avalon_slave_0 ADC_DIN writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 ADC_DOUT beginbursttransfer Input 1
add_interface_port avalon_slave_0 ADC_SCLK writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 AUD_ADCDAT beginbursttransfer Input 1
add_interface_port avalon_slave_0 AUD_ADCLRCK export Bidir 1
add_interface_port avalon_slave_0 AUD_BCLK export Bidir 1
add_interface_port avalon_slave_0 AUD_DACDAT writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 AUD_DACLRCK export Bidir 1
add_interface_port avalon_slave_0 AUD_XCK writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 CLOCK2_50 beginbursttransfer Input 1
add_interface_port avalon_slave_0 CLOCK3_50 beginbursttransfer Input 1
add_interface_port avalon_slave_0 CLOCK4_50 beginbursttransfer Input 1
add_interface_port avalon_slave_0 CLOCK_50 beginbursttransfer Input 1
add_interface_port avalon_slave_0 DRAM_ADDR readdata Output 13
add_interface_port avalon_slave_0 DRAM_BA readdata Output 2
add_interface_port avalon_slave_0 DRAM_CAS_N writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 DRAM_CKE writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 DRAM_CLK writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 DRAM_CS_N writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 DRAM_DQ export Bidir 16
add_interface_port avalon_slave_0 DRAM_LDQM writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 DRAM_RAS_N writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 DRAM_UDQM writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 DRAM_WE_N writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 FAN_CTRL writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 FPGA_I2C_SCLK writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 FPGA_I2C_SDAT export Bidir 1
add_interface_port avalon_slave_0 GPIO_0 export Bidir 36
add_interface_port avalon_slave_0 GPIO_1 export Bidir 36
add_interface_port avalon_slave_0 HEX0 readdata Output 7
add_interface_port avalon_slave_0 HEX1 readdata Output 7
add_interface_port avalon_slave_0 HEX2 readdata Output 7
add_interface_port avalon_slave_0 HEX3 readdata Output 7
add_interface_port avalon_slave_0 HEX4 readdata Output 7
add_interface_port avalon_slave_0 HEX5 readdata Output 7
add_interface_port avalon_slave_0 IRDA_RXD beginbursttransfer Input 1
add_interface_port avalon_slave_0 IRDA_TXD writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 KEY writebyteenable_n Input 4
add_interface_port avalon_slave_0 LEDR readdata Output 10
add_interface_port avalon_slave_0 PS2_CLK export Bidir 1
add_interface_port avalon_slave_0 PS2_CLK2 export Bidir 1
add_interface_port avalon_slave_0 PS2_DAT export Bidir 1
add_interface_port avalon_slave_0 PS2_DAT2 export Bidir 1
add_interface_port avalon_slave_0 SW writebyteenable_n Input 10
add_interface_port avalon_slave_0 TD_CLK27 beginbursttransfer Input 1
add_interface_port avalon_slave_0 TD_DATA writebyteenable_n Input 8
add_interface_port avalon_slave_0 TD_HS beginbursttransfer Input 1
add_interface_port avalon_slave_0 TD_RESET_N writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 TD_VS beginbursttransfer Input 1
add_interface_port avalon_slave_0 VGA_B readdata Output 8
add_interface_port avalon_slave_0 VGA_BLANK_N writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 VGA_CLK writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 VGA_G readdata Output 8
add_interface_port avalon_slave_0 VGA_HS writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 VGA_R readdata Output 8
add_interface_port avalon_slave_0 VGA_SYNC_N writeresponsevalid_n Output 1
add_interface_port avalon_slave_0 VGA_VS writeresponsevalid_n Output 1
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0

