# TCL File Generated by Component Editor 21.1
# Mon May 13 19:49:21 EDT 2024
# DO NOT MODIFY


# 
# bram "BRAM" v1.0
#  2024.05.13.19:49:21
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module bram
# 
set_module_property DESCRIPTION ""
set_module_property NAME bram
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME BRAM
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
set_module_assignment embeddedsw.dts.vendor "csee4840"
set_module_assignment embeddedsw.dts.name "bram"
set_module_assignment embeddedsw.dts.group "bram"

# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL twoportbram
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file bram.sv SYSTEM_VERILOG PATH bram.sv TOP_LEVEL_FILE


# 
# parameters
# 
add_parameter RAM_WIDTH INTEGER 24
set_parameter_property RAM_WIDTH DEFAULT_VALUE 24
set_parameter_property RAM_WIDTH DISPLAY_NAME RAM_WIDTH
set_parameter_property RAM_WIDTH TYPE INTEGER
set_parameter_property RAM_WIDTH UNITS None
set_parameter_property RAM_WIDTH HDL_PARAMETER true
add_parameter RAM_ADDR_BITS INTEGER 16
set_parameter_property RAM_ADDR_BITS DEFAULT_VALUE 16
set_parameter_property RAM_ADDR_BITS DISPLAY_NAME RAM_ADDR_BITS
set_parameter_property RAM_ADDR_BITS TYPE INTEGER
set_parameter_property RAM_ADDR_BITS UNITS None
set_parameter_property RAM_ADDR_BITS HDL_PARAMETER true
add_parameter RAM_WORDS STD_LOGIC_VECTOR 65535
set_parameter_property RAM_WORDS DEFAULT_VALUE 65535
set_parameter_property RAM_WORDS DISPLAY_NAME RAM_WORDS
set_parameter_property RAM_WORDS TYPE STD_LOGIC_VECTOR
set_parameter_property RAM_WORDS UNITS None
set_parameter_property RAM_WORDS ALLOWED_RANGES 0:262143
set_parameter_property RAM_WORDS HDL_PARAMETER true


# 
# display items
# 


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1


# 
# connection point bram
# 
add_interface bram conduit end
set_interface_property bram associatedClock clock
set_interface_property bram associatedReset ""
set_interface_property bram ENABLED true
set_interface_property bram EXPORT_OF ""
set_interface_property bram PORT_NAME_MAP ""
set_interface_property bram CMSIS_SVD_VARIABLES ""
set_interface_property bram SVD_ADDRESS_GROUP ""

add_interface_port bram ra read_address Input "((RAM_ADDR_BITS-1)) - (0) + 1"
add_interface_port bram wa write_address Input "((RAM_ADDR_BITS-1)) - (0) + 1"
add_interface_port bram write write_enable Input 1
add_interface_port bram data_in data_in Input "((RAM_WIDTH-1)) - (0) + 1"
add_interface_port bram data_out data_out Output "((RAM_WIDTH-1)) - (0) + 1"

