# TCL File Generated by Component Editor 21.1
# Mon May 13 18:24:02 EDT 2024
# DO NOT MODIFY


# 
# filter "filter" v1.0
#  2024.05.13.18:24:02
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module filter
# 
set_module_property DESCRIPTION ""
set_module_property NAME filter
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME filter
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
set_module_assignment embeddedsw.dts.vendor "csee4840"
set_module_assignment embeddedsw.dts.name "filter"
set_module_assignment embeddedsw.dts.group "filter"

# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL filter
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file filter.sv SYSTEM_VERILOG PATH filter.sv TOP_LEVEL_FILE


# 
# parameters
# 
add_parameter word_width INTEGER 16
set_parameter_property word_width DEFAULT_VALUE 16
set_parameter_property word_width DISPLAY_NAME word_width
set_parameter_property word_width TYPE INTEGER
set_parameter_property word_width UNITS None
set_parameter_property word_width ALLOWED_RANGES -2147483648:2147483647
set_parameter_property word_width HDL_PARAMETER true
add_parameter order INTEGER 17
set_parameter_property order DEFAULT_VALUE 17
set_parameter_property order DISPLAY_NAME order
set_parameter_property order TYPE INTEGER
set_parameter_property order UNITS None
set_parameter_property order ALLOWED_RANGES -2147483648:2147483647
set_parameter_property order HDL_PARAMETER true


# 
# display items
# 


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1


# 
# connection point reset
# 
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset reset reset Input 1


# 
# connection point filter_signal_out
# 
add_interface filter_signal_out conduit end
set_interface_property filter_signal_out associatedClock clock
set_interface_property filter_signal_out associatedReset reset
set_interface_property filter_signal_out ENABLED true
set_interface_property filter_signal_out EXPORT_OF ""
set_interface_property filter_signal_out PORT_NAME_MAP ""
set_interface_property filter_signal_out CMSIS_SVD_VARIABLES ""
set_interface_property filter_signal_out SVD_ADDRESS_GROUP ""

add_interface_port filter_signal_out filtered_signal filtered_signal Output 32


# 
# connection point filter_input
# 
add_interface filter_input conduit end
set_interface_property filter_input associatedClock clock
set_interface_property filter_input associatedReset reset
set_interface_property filter_input ENABLED true
set_interface_property filter_input EXPORT_OF ""
set_interface_property filter_input PORT_NAME_MAP ""
set_interface_property filter_input CMSIS_SVD_VARIABLES ""
set_interface_property filter_input SVD_ADDRESS_GROUP ""

add_interface_port filter_input input_signal raw_data Input 16

