.PHONY: clean lint

SVFILES = arb_avalon_interface.sv bettor_arb.sv calc_manager.sv twoport_memory.sv calc_odds.sv iterator.sv

# Run Verilator simulations
# NOTE: need to copy .sv files from hardware directory into simulation directory

arb_avalon_interface : obj_dir/Varb_avalon_interface
	obj_dir/Varb_avalon_interface
	gtkwave --save=arb_avalon_interface.gtkw arb_avalon_interface.vcd &

bettor_arb: obj_dir/Vbettor_arb
	obj_dir/Vbettor_arb

calc_manager : obj_dir/Vcalc_manager
	obj_dir/Vcalc_manager
	gtkwave --save=calc_manager.gtkw calc_manager.vcd &

iterator : obj_dir/Viterator
	obj_dir/Viterator
	gtkwave --save=iterator.gtkw iterator.vcd &

write_manager : obj_dir/Vwrite_manager
	obj_dir/Vwrite_manager
	gtkwave --save=write_manager.gtkw write_manager.vcd &

twoport_memory : obj_dir/Vtwoport_memory
	obj_dir/Vtwoport_memory
	gtkwave --save=twoport_memory.gtkw twoport_memory.vcd &

calc_odds : obj_dir/Vcalc_odds
	obj_dir/Vcalc_odds

# Create Verilator simulations

obj_dir/Varb_avalon_interface : arb_avalon_interface.cpp $(SVFILES)
	verilator -trace -Wall -cc $(SVFILES) \
		-exe arb_avalon_interface.cpp \
		-top-module arb_avalon_interface
	make -C obj_dir -j -f Varb_avalon_interface.mk

obj_dir/Vbettor_arb : bettor_arb.sv bettor_arb.cpp calc_manager.sv twoport_memory.sv calc_odds.sv iterator.sv
	verilator -trace -Wall -cc bettor_arb.sv calc_manager.sv twoport_memory.sv calc_odds.sv iterator.sv \
		-exe bettor_arb.cpp \
		-top-module bettor_arb
	make -C obj_dir -j -f Vbettor_arb.mk

obj_dir/Vcalc_manager : calc_manager.sv calc_manager.cpp twoport_memory.sv calc_odds.sv iterator.sv
	verilator -trace -Wall -cc calc_manager.sv twoport_memory.sv calc_odds.sv iterator.sv \
		-exe calc_manager.cpp -top-module calc_manager
	make -C obj_dir -j -f Vcalc_manager.mk

obj_dir/Viterator : iterator.sv iterator.cpp
	verilator -trace -Wall -cc iterator.sv \
		-exe iterator.cpp \
		-top-module iterator
	make -C obj_dir -j -f Viterator.mk

obj_dir/Vwrite_manager : write_manager.sv write_manager.cpp
	verilator -trace -Wall -cc write_manager.sv \
		-exe write_manager.cpp \
		-top-module write_manager
	make -C obj_dir -j -f Vwrite_manager.mk

obj_dir/Vtwoport_memory : twoport_memory.sv twoport_memory.cpp
	verilator -trace -Wall -cc twoport_memory.sv \
		-exe twoport_memory.cpp \
		-top-module twoport_memory
	make -C obj_dir -j -f Vtwoport_memory.mk

obj_dir/Vcalc_odds : calc_odds.sv calc_odds.cpp
	verilator -Wall -cc calc_odds.sv -exe calc_odds.cpp \
		-top-module calc_odds
	make -C obj_dir -j -f Vcalc_odds.mk

# Quickly check the System Verilog files for errors

lint :
	for file in $(SVFILES); do \
	verilator --lint-only -Wall $$file; done

clean :
	rm -rf obj_dir output_files *.vcd
