# TCL File Generated by Component Editor 21.1
# Thu May 15 17:08:30 EDT 2025
# DO NOT MODIFY


# 
# my_pll "my_pll" v1.0
#  2025.05.15.17:08:30
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module my_pll
# 
set_module_property DESCRIPTION ""
set_module_property NAME my_pll
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME my_pll
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL pll_0002
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file pll_0002.v VERILOG PATH pll/pll_0002.v TOP_LEVEL_FILE


# 
# parameters
# 


# 
# display items
# 


# 
# connection point outclk0
# 
add_interface outclk0 clock start
set_interface_property outclk0 associatedDirectClock ""
set_interface_property outclk0 clockRate 0
set_interface_property outclk0 clockRateKnown false
set_interface_property outclk0 ENABLED true
set_interface_property outclk0 EXPORT_OF ""
set_interface_property outclk0 PORT_NAME_MAP ""
set_interface_property outclk0 CMSIS_SVD_VARIABLES ""
set_interface_property outclk0 SVD_ADDRESS_GROUP ""

add_interface_port outclk0 outclk_0 clk Output 1


# 
# connection point refclk
# 
add_interface refclk clock end
set_interface_property refclk clockRate 0
set_interface_property refclk ENABLED true
set_interface_property refclk EXPORT_OF ""
set_interface_property refclk PORT_NAME_MAP ""
set_interface_property refclk CMSIS_SVD_VARIABLES ""
set_interface_property refclk SVD_ADDRESS_GROUP ""

add_interface_port refclk refclk clk Input 1


# 
# connection point reset
# 
add_interface reset reset end
set_interface_property reset associatedClock refclk
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset rst reset Input 1


# 
# connection point locked
# 
add_interface locked conduit end
set_interface_property locked associatedClock refclk
set_interface_property locked associatedReset ""
set_interface_property locked ENABLED true
set_interface_property locked EXPORT_OF ""
set_interface_property locked PORT_NAME_MAP ""
set_interface_property locked CMSIS_SVD_VARIABLES ""
set_interface_property locked SVD_ADDRESS_GROUP ""

add_interface_port locked locked locked Output 1

