# system info my_fft on 2025.05.15.01:30:03
system_info:
name,value
DEVICE,5CEBA2F17A7
DEVICE_FAMILY,Cyclone V
GENERATION_ID,1747287000
#
#
# Files generated for my_fft on 2025.05.15.01:30:03
files:
filepath,kind,attributes,module,is_top
simulation/my_fft.v,VERILOG,,my_fft,true
simulation/submodules/my_fft_fft_ii_0_opt_twr3.hex,HEX,,my_fft_fft_ii_0,false
simulation/submodules/my_fft_fft_ii_0_opt_twi4.hex,HEX,,my_fft_fft_ii_0,false
simulation/submodules/my_fft_fft_ii_0_opt_twi1.hex,HEX,,my_fft_fft_ii_0,false
simulation/submodules/my_fft_fft_ii_0_opt_twr4.hex,HEX,,my_fft_fft_ii_0,false
simulation/submodules/my_fft_fft_ii_0_opt_twi5.hex,HEX,,my_fft_fft_ii_0,false
simulation/submodules/my_fft_fft_ii_0_opt_twr1.hex,HEX,,my_fft_fft_ii_0,false
simulation/submodules/my_fft_fft_ii_0_opt_twr5.hex,HEX,,my_fft_fft_ii_0,false
simulation/submodules/my_fft_fft_ii_0_opt_twi2.hex,HEX,,my_fft_fft_ii_0,false
simulation/submodules/my_fft_fft_ii_0_opt_twr2.hex,HEX,,my_fft_fft_ii_0,false
simulation/submodules/my_fft_fft_ii_0_opt_twi3.hex,HEX,,my_fft_fft_ii_0,false
simulation/submodules/auk_dspip_text_pkg.vhd,VHDL,,my_fft_fft_ii_0,false
simulation/submodules/auk_dspip_math_pkg.vhd,VHDL,,my_fft_fft_ii_0,false
simulation/submodules/auk_dspip_lib_pkg.vhd,VHDL,,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_avalon_streaming_block_sink.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_avalon_streaming_block_sink.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_avalon_streaming_block_sink.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_avalon_streaming_block_sink.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_avalon_streaming_block_source.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_avalon_streaming_block_source.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_avalon_streaming_block_source.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_avalon_streaming_block_source.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/auk_dspip_roundsat.vhd,VHDL,,my_fft_fft_ii_0,false
simulation/submodules/mentor/apn_fft_mult_can.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/apn_fft_mult_can.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/apn_fft_mult_can.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/apn_fft_mult_can.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/apn_fft_mult_cpx_1825.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/apn_fft_mult_cpx_1825.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/apn_fft_mult_cpx_1825.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/apn_fft_mult_cpx_1825.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/apn_fft_mult_cpx.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/apn_fft_mult_cpx.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/apn_fft_mult_cpx.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/apn_fft_mult_cpx.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/auk_dspip_r22sdf_top.ocp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/mentor/hyper_opt_OFF_pkg.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/hyper_opt_OFF_pkg.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/hyper_opt_OFF_pkg.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/hyper_opt_OFF_pkg.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/altera_fft_dual_port_ram.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/altera_fft_dual_port_ram.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/altera_fft_dual_port_ram.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/altera_fft_dual_port_ram.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/altera_fft_dual_port_rom.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/altera_fft_dual_port_rom.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/altera_fft_dual_port_rom.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/altera_fft_dual_port_rom.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/altera_fft_mult_add.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/altera_fft_mult_add.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/altera_fft_mult_add.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/altera_fft_mult_add.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/altera_fft_single_port_rom.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/altera_fft_single_port_rom.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/altera_fft_single_port_rom.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/altera_fft_single_port_rom.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_fft_pkg.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_fft_pkg.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_fft_pkg.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_fft_pkg.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/hyper_pipeline_interface.v,VERILOG_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/hyper_pipeline_interface.v,VERILOG_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/hyper_pipeline_interface.v,VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/hyper_pipeline_interface.v,VERILOG_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/counter_module.sv,SYSTEM_VERILOG_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/counter_module.sv,SYSTEM_VERILOG_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/counter_module.sv,SYSTEM_VERILOG_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/counter_module.sv,SYSTEM_VERILOG_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_lib_pkg.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_lib_pkg.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_lib_pkg.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_lib_pkg.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_bit_reverse_reverse_carry_adder.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_bit_reverse_reverse_carry_adder.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_bit_reverse_reverse_carry_adder.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_bit_reverse_reverse_carry_adder.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_bit_reverse_addr_control.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_bit_reverse_addr_control.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_bit_reverse_addr_control.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_bit_reverse_addr_control.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_bit_reverse_core.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_bit_reverse_core.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_bit_reverse_core.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_bit_reverse_core.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_adder_fp.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_adder_fp.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_adder_fp.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_adder_fp.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_addsub.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_addsub.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_addsub.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_addsub.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_bf_control.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_bf_control.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_bf_control.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_bf_control.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_bfi.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_bfi.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_bfi.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_bfi.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_bfii.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_bfii.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_bfii.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_bfii.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_cma.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_cma.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_cma.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_cma.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_cma_adder_fp.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_cma_adder_fp.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_cma_adder_fp.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_cma_adder_fp.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_cma_bfi_fp.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_cma_bfi_fp.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_cma_bfi_fp.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_cma_bfi_fp.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_cma_fp.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_cma_fp.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_cma_fp.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_cma_fp.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_core.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_core.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_core.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_core.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_counter.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_counter.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_counter.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_counter.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_delay.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_delay.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_delay.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_delay.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_enable_control.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_enable_control.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_enable_control.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_enable_control.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_stage.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_stage.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_stage.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_stage.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_stg_out_pipe.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_stg_out_pipe.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_stg_out_pipe.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_stg_out_pipe.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_stg_pipe.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_stg_pipe.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_stg_pipe.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_stg_pipe.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_top.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_top.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_top.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_top.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/mentor/auk_dspip_r22sdf_twrom.vhd,VHDL_ENCRYPT,MENTOR_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/aldec/auk_dspip_r22sdf_twrom.vhd,VHDL_ENCRYPT,ALDEC_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/synopsys/auk_dspip_r22sdf_twrom.vhd,VHDL_ENCRYPT,SYNOPSYS_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/cadence/auk_dspip_r22sdf_twrom.vhd,VHDL_ENCRYPT,CADENCE_SPECIFIC,my_fft_fft_ii_0,false
simulation/submodules/my_fft_fft_ii_0.sv,SYSTEM_VERILOG,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/How_To_Build.txt,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/SVSfftmodel.mexglx,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/SVSfftmodel.mexw32,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/expression.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/expression.h,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/fft.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/fft.h,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/fpCompiler.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/fpCompiler.h,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/model_c_wrapper.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/util.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/mr42/util.h,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/old_arch/Sfftmodel.c,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/old_arch/Sfftmodel.mexa64,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/old_arch/Sfftmodel.mexglx,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/old_arch/Sfftmodel.mexw32,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/old_arch/imag_input.txt,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/old_arch/model.c,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/old_arch/model_c_wrapper.c,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/old_arch/real_input.txt,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/old_arch/run_c_wrapper.sh,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/old_arch/run_model_c.sh,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/old_arch/tbcmex.m,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/SVSfftmodel.mexa64,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/SVSfftmodel.mexglx,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/SVSfftmodel.mexw32,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/blksize_report.txt,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/create_static_library.sh,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/expected_imag_out.txt,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/expected_real_out.txt,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/expression.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/expression.h,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/fft.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/fft.h,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/fft_model.m,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/fft_tb.m,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/fpCompiler.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/fpCompiler.h,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/how_to_compile.txt,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/imag_input.txt,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/main.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/model.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/model_c_wrapper.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/readme.txt,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/real_input.txt,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/sink.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/sink.h,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/source.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/source.h,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/system.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/system.h,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/util.cpp,OTHER,,my_fft_fft_ii_0,false
simulation/submodules/c_model/r22sdf/util.h,OTHER,,my_fft_fft_ii_0,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
my_fft.fft_ii_0,my_fft_fft_ii_0
