# TCL File Generated by Component Editor 21.1
# Thu May 15 06:07:21 EDT 2025
# DO NOT MODIFY


# 
# mic "mic" v1.0
#  2025.05.15.06:07:21
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module mic
# 
set_module_property DESCRIPTION ""
set_module_property NAME mic
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME mic
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL mic
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file mic.sv SYSTEM_VERILOG PATH modules/mic.sv TOP_LEVEL_FILE


# 
# parameters
# 


# 
# display items
# 


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock SCK clk Input 1


# 
# connection point reset
# 
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset reset reset Input 1


# 
# connection point i2s
# 
add_interface i2s conduit end
set_interface_property i2s associatedClock clock
set_interface_property i2s associatedReset reset
set_interface_property i2s ENABLED true
set_interface_property i2s EXPORT_OF ""
set_interface_property i2s PORT_NAME_MAP ""
set_interface_property i2s CMSIS_SVD_VARIABLES ""
set_interface_property i2s SVD_ADDRESS_GROUP ""

add_interface_port i2s i2s_sd1 sd Input 1
add_interface_port i2s i2s_ws ws Output 1
add_interface_port i2s i2s_btn_record key Input 1
add_interface_port i2s i2s_hex hex Output 7
add_interface_port i2s sck_new sck_new Output 1


# 
# connection point avalon_streaming_source
# 
add_interface avalon_streaming_source avalon_streaming start
set_interface_property avalon_streaming_source associatedClock clock
set_interface_property avalon_streaming_source associatedReset reset
set_interface_property avalon_streaming_source dataBitsPerSymbol 16
set_interface_property avalon_streaming_source errorDescriptor ""
set_interface_property avalon_streaming_source firstSymbolInHighOrderBits true
set_interface_property avalon_streaming_source maxChannel 0
set_interface_property avalon_streaming_source readyLatency 0
set_interface_property avalon_streaming_source ENABLED true
set_interface_property avalon_streaming_source EXPORT_OF ""
set_interface_property avalon_streaming_source PORT_NAME_MAP ""
set_interface_property avalon_streaming_source CMSIS_SVD_VARIABLES ""
set_interface_property avalon_streaming_source SVD_ADDRESS_GROUP ""

add_interface_port avalon_streaming_source sample_data data Output 16
add_interface_port avalon_streaming_source sample_valid valid Output 1
add_interface_port avalon_streaming_source out_startofpacket startofpacket Output 1
add_interface_port avalon_streaming_source out_endofpacket endofpacket Output 1

