# TCL File Generated by Component Editor 21.1
# Thu May 15 06:09:27 EDT 2025
# DO NOT MODIFY


# 
# driver "driver" v1.0
#  2025.05.15.06:09:27
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module driver
# 
set_module_property DESCRIPTION ""
set_module_property NAME driver
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME driver
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL driver_interface
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file driver_interface.sv SYSTEM_VERILOG PATH modules/driver_interface.sv TOP_LEVEL_FILE


# 
# parameters
# 
add_parameter DATA_SIZE STRING 28
set_parameter_property DATA_SIZE DEFAULT_VALUE 28
set_parameter_property DATA_SIZE DISPLAY_NAME DATA_SIZE
set_parameter_property DATA_SIZE TYPE STRING
set_parameter_property DATA_SIZE UNITS None
set_parameter_property DATA_SIZE HDL_PARAMETER true


# 
# module assignments
# 
set_module_assignment embeddedsw.dts.group driver
set_module_assignment embeddedsw.dts.name driver
set_module_assignment embeddedsw.dts.vendor csee4840


# 
# display items
# 


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1


# 
# connection point reset
# 
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset reset reset Input 1


# 
# connection point avalon_slave_0
# 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock
set_interface_property avalon_slave_0 associatedReset reset
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
set_interface_property avalon_slave_0 EXPORT_OF ""
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""

add_interface_port avalon_slave_0 chipselect chipselect Input 1
add_interface_port avalon_slave_0 address address Input 1
add_interface_port avalon_slave_0 read read Input 1
add_interface_port avalon_slave_0 read_data readdata Output 32
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0


# 
# connection point fft_to_driver_interface
# 
add_interface fft_to_driver_interface conduit end
set_interface_property fft_to_driver_interface associatedClock clock
set_interface_property fft_to_driver_interface associatedReset reset
set_interface_property fft_to_driver_interface ENABLED true
set_interface_property fft_to_driver_interface EXPORT_OF ""
set_interface_property fft_to_driver_interface PORT_NAME_MAP ""
set_interface_property fft_to_driver_interface CMSIS_SVD_VARIABLES ""
set_interface_property fft_to_driver_interface SVD_ADDRESS_GROUP ""

add_interface_port fft_to_driver_interface source_ready source_ready Output 1
add_interface_port fft_to_driver_interface source_valid source_valid Input 1
add_interface_port fft_to_driver_interface source_data source_real Input "((DATA_SIZE-1)) - (0) + 1"

