<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2025.05.15.17:14:22"
 outputDirectory="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Cyclone V"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="5CSEMA5F31C6"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="6"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <interface name="clk" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="rst" kind="reset" start="0">
   <property name="associatedClock" value="clk" />
   <property name="synchronousEdges" value="DEASSERT" />
   <port name="reset_n" direction="input" role="reset_n" width="1" />
  </interface>
  <interface name="sink" kind="conduit" start="0">
   <property name="associatedClock" value="clk" />
   <property name="associatedReset" value="rst" />
   <port name="sink_valid" direction="input" role="sink_valid" width="1" />
   <port name="sink_ready" direction="output" role="sink_ready" width="1" />
   <port name="sink_error" direction="input" role="sink_error" width="2" />
   <port name="sink_sop" direction="input" role="sink_sop" width="1" />
   <port name="sink_eop" direction="input" role="sink_eop" width="1" />
   <port name="sink_real" direction="input" role="sink_real" width="16" />
   <port name="sink_imag" direction="input" role="sink_imag" width="16" />
   <port name="fftpts_in" direction="input" role="fftpts_in" width="12" />
   <port name="inverse" direction="input" role="inverse" width="1" />
  </interface>
  <interface name="source" kind="conduit" start="0">
   <property name="associatedClock" value="clk" />
   <property name="associatedReset" value="rst" />
   <port name="source_valid" direction="output" role="source_valid" width="1" />
   <port name="source_ready" direction="input" role="source_ready" width="1" />
   <port name="source_error" direction="output" role="source_error" width="2" />
   <port name="source_sop" direction="output" role="source_sop" width="1" />
   <port name="source_eop" direction="output" role="source_eop" width="1" />
   <port name="source_real" direction="output" role="source_real" width="28" />
   <port name="source_imag" direction="output" role="source_imag" width="28" />
   <port name="fftpts_out" direction="output" role="fftpts_out" width="12" />
  </interface>
 </perimeter>
 <entity
   path=""
   parameterizationKey="my_fft:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=5CSEMA5F31C6,AUTO_DEVICE_FAMILY=Cyclone V,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1747343662,AUTO_UNIQUE_ID=(altera_fft_ii:21.1:CALC_LATENCY=2048,THROUGHPUT_LATENCY=4096,data_flow=Variable Streaming,data_rep=Fixed Point,design_env=NATIVE,direction=Bi-directional,dsp_resource_opt=false,engine_arch=Quad Output,hard_fp=false,hyper_opt=false,in_order=Natural,in_width=16,in_width_derived=16,length=2048,num_engines=1,num_engines_derived=1,out_order=Natural,out_width=28,out_width_derived=28,selected_device_family=Cyclone V,twid_width=16,twid_width_derived=16)"
   instancePathKey="my_fft"
   kind="my_fft"
   version="1.0"
   name="my_fft">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_GENERATION_ID" value="1747343662" />
  <parameter name="AUTO_DEVICE" value="5CSEMA5F31C6" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
  <generatedFiles>
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/my_fft.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twr3.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twi4.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twi1.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twr4.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twi5.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twr1.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twr5.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twi2.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twr2.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twi3.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_text_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_math_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_lib_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_avalon_streaming_block_sink.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_avalon_streaming_block_source.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_roundsat.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/apn_fft_mult_can.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/apn_fft_mult_cpx_1825.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/apn_fft_mult_cpx.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_top.ocp"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/hyper_opt_OFF_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/altera_fft_dual_port_ram.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/altera_fft_dual_port_rom.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/altera_fft_mult_add.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/altera_fft_single_port_rom.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_fft_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/hyper_pipeline_interface.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/counter_module.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_lib_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_bit_reverse_reverse_carry_adder.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_bit_reverse_addr_control.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_bit_reverse_core.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_adder_fp.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_addsub.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_bf_control.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_bfi.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_bfii.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_cma.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_cma_adder_fp.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_cma_bfi_fp.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_cma_fp.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_core.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_counter.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_delay.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_enable_control.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_stage.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_stg_out_pipe.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_stg_pipe.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_top.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_twrom.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft.qsys" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/dsp/altera_fft_ii/altera_fft_ii_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/dsp/altera_fft_ii/fft_helper.jar" />
  </childSourceFiles>
  <messages>
   <message level="Debug" culprit="my_fft">queue size: 0 starting:my_fft "my_fft"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="my_fft"><![CDATA["<b>my_fft</b>" reuses <b>altera_fft_ii</b> "<b>submodules/my_fft_fft_ii_0</b>"]]></message>
   <message level="Debug" culprit="my_fft">queue size: 0 starting:altera_fft_ii "submodules/my_fft_fft_ii_0"</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twr3.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twi4.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twi1.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twr4.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twi5.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twr1.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twr5.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twi2.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twr2.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twi3.hex</message>
   <message level="Info" culprit="fft_ii_0"><![CDATA["<b>my_fft</b>" instantiated <b>altera_fft_ii</b> "<b>fft_ii_0</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_fft_ii:21.1:CALC_LATENCY=2048,THROUGHPUT_LATENCY=4096,data_flow=Variable Streaming,data_rep=Fixed Point,design_env=NATIVE,direction=Bi-directional,dsp_resource_opt=false,engine_arch=Quad Output,hard_fp=false,hyper_opt=false,in_order=Natural,in_width=16,in_width_derived=16,length=2048,num_engines=1,num_engines_derived=1,out_order=Natural,out_width=28,out_width_derived=28,selected_device_family=Cyclone V,twid_width=16,twid_width_derived=16"
   instancePathKey="my_fft:.:fft_ii_0"
   kind="altera_fft_ii"
   version="21.1"
   name="my_fft_fft_ii_0">
  <parameter name="THROUGHPUT_LATENCY" value="4096" />
  <parameter name="in_width_derived" value="16" />
  <parameter name="in_order" value="Natural" />
  <parameter name="hyper_opt" value="false" />
  <parameter name="num_engines_derived" value="1" />
  <parameter name="twid_width_derived" value="16" />
  <parameter name="length" value="2048" />
  <parameter name="out_order" value="Natural" />
  <parameter name="selected_device_family" value="Cyclone V" />
  <parameter name="dsp_resource_opt" value="false" />
  <parameter name="CALC_LATENCY" value="2048" />
  <parameter name="design_env" value="NATIVE" />
  <parameter name="data_rep" value="Fixed Point" />
  <parameter name="in_width" value="16" />
  <parameter name="engine_arch" value="Quad Output" />
  <parameter name="data_flow" value="Variable Streaming" />
  <parameter name="out_width" value="28" />
  <parameter name="num_engines" value="1" />
  <parameter name="out_width_derived" value="28" />
  <parameter name="hard_fp" value="false" />
  <parameter name="twid_width" value="16" />
  <parameter name="direction" value="Bi-directional" />
  <generatedFiles>
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twr3.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twi4.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twi1.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twr4.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twi5.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twr1.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twr5.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twi2.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twr2.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0_opt_twi3.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_text_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_math_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_lib_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_avalon_streaming_block_sink.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_avalon_streaming_block_source.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_roundsat.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/apn_fft_mult_can.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/apn_fft_mult_cpx_1825.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/apn_fft_mult_cpx.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_top.ocp"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/hyper_opt_OFF_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/altera_fft_dual_port_ram.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/altera_fft_dual_port_rom.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/altera_fft_mult_add.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/altera_fft_single_port_rom.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_fft_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/hyper_pipeline_interface.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/counter_module.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_lib_pkg.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_bit_reverse_reverse_carry_adder.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_bit_reverse_addr_control.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_bit_reverse_core.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_adder_fp.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_addsub.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_bf_control.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_bfi.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_bfii.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_cma.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_cma_adder_fp.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_cma_bfi_fp.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_cma_fp.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_core.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_counter.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_delay.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_enable_control.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_stage.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_stg_out_pipe.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_stg_pipe.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_top.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/auk_dspip_r22sdf_twrom.vhd"
       type="VHDL"
       attributes="" />
   <file
       path="/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis/submodules/my_fft_fft_ii_0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/dsp/altera_fft_ii/altera_fft_ii_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/dsp/altera_fft_ii/fft_helper.jar" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="my_fft" as="fft_ii_0" />
  <messages>
   <message level="Debug" culprit="my_fft">queue size: 0 starting:altera_fft_ii "submodules/my_fft_fft_ii_0"</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twr3.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twi4.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twi1.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twr4.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twi5.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twr1.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twr5.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twi2.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twr2.hex</message>
   <message level="Info" culprit="fft_ii_0">--- add file: my_fft_fft_ii_0_opt_twi3.hex</message>
   <message level="Info" culprit="fft_ii_0"><![CDATA["<b>my_fft</b>" instantiated <b>altera_fft_ii</b> "<b>fft_ii_0</b>"]]></message>
  </messages>
 </entity>
</deploy>
