Info: Starting: Create simulation model
Info: qsys-generate /homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/simulation --family="Cyclone V" --part=5CEBA2F17A7
Progress: Loading hardware/my_fft.qsys
Progress: Reading input file
Progress: Adding fft_ii_0 [altera_fft_ii 21.1]
Progress: Parameterizing module fft_ii_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: my_fft.fft_ii_0: Radix-2 digit reverse implied
Info: my_fft: Generating my_fft "my_fft" for SIM_VERILOG
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr3.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi4.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi1.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr4.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi5.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr1.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr5.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi2.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr2.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi3.hex
Info: fft_ii_0: "my_fft" instantiated altera_fft_ii "fft_ii_0"
Info: my_fft: Done "my_fft" with 2 modules, 210 files
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --spd=/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/my_fft.spd --output-directory=/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/simulation/ --use-relative-paths=true
Info: Doing: ip-make-simscript --spd=/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/my_fft.spd --output-directory=/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/simulation/ --use-relative-paths=true
Info: Generating the following file(s) for MODELSIM simulator in /homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/simulation/ directory:
Info: 	mentor/msim_setup.tcl
Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
Info: Generating the following file(s) for VCSMX simulator in /homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/simulation/ directory:
Info: 	synopsys/vcsmx/synopsys_sim.setup
Info: 	synopsys/vcsmx/vcsmx_setup.sh
Info: Generating the following file(s) for NCSIM simulator in /homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/simulation/ directory:
Info: 	cadence/cds.lib
Info: 	cadence/hdl.var
Info: 	cadence/ncsim_setup.sh
Info: 	1 .cds.lib files in cadence/cds_libs/ directory
Info: Generating the following file(s) for RIVIERA simulator in /homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/simulation/ directory:
Info: 	aldec/rivierapro_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/simulation/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft.qsys --block-symbol-file --output-directory=/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft --family="Cyclone V" --part=5CEBA2F17A7
Progress: Loading hardware/my_fft.qsys
Progress: Reading input file
Progress: Adding fft_ii_0 [altera_fft_ii 21.1]
Progress: Parameterizing module fft_ii_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: my_fft.fft_ii_0: Radix-2 digit reverse implied
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft.qsys --synthesis=VERILOG --output-directory=/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis --family="Cyclone V" --part=5CEBA2F17A7
Progress: Loading hardware/my_fft.qsys
Progress: Reading input file
Progress: Adding fft_ii_0 [altera_fft_ii 21.1]
Progress: Parameterizing module fft_ii_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: my_fft.fft_ii_0: Radix-2 digit reverse implied
Info: my_fft: Generating my_fft "my_fft" for QUARTUS_SYNTH
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr3.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi4.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi1.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr4.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi5.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr1.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr5.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi2.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr2.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi3.hex
Info: fft_ii_0: "my_fft" instantiated altera_fft_ii "fft_ii_0"
Info: my_fft: Done "my_fft" with 2 modules, 52 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
