Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft.qsys --block-symbol-file --output-directory=/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft --family="Cyclone V" --part=5CSEMA5F31C6
Progress: Loading hardware/my_fft.qsys
Progress: Reading input file
Progress: Adding fft_ii_0 [altera_fft_ii 21.1]
Progress: Parameterizing module fft_ii_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: my_fft.fft_ii_0: Radix-2 digit reverse implied
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft.qsys --synthesis=VERILOG --output-directory=/homes/user/stud/fall24/jm5912/ee4840-spring-2025/final_project/hardware/my_fft/synthesis --family="Cyclone V" --part=5CSEMA5F31C6
Progress: Loading hardware/my_fft.qsys
Progress: Reading input file
Progress: Adding fft_ii_0 [altera_fft_ii 21.1]
Progress: Parameterizing module fft_ii_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: my_fft.fft_ii_0: Radix-2 digit reverse implied
Info: my_fft: Generating my_fft "my_fft" for QUARTUS_SYNTH
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr3.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi4.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi1.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr4.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi5.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr1.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr5.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi2.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twr2.hex
Info: fft_ii_0: --- add file: my_fft_fft_ii_0_opt_twi3.hex
Info: fft_ii_0: "my_fft" instantiated altera_fft_ii "fft_ii_0"
Info: my_fft: Done "my_fft" with 2 modules, 52 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
