Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system.qsys --block-symbol-file --output-directory=/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system --family="Cyclone V" --part=5CSEMA5F31C6
Progress: Loading test_final_4840/soc_system.qsys
Progress: Reading input file
Progress: Adding RAM [altera_avalon_onchip_memory2 21.1]
Progress: Parameterizing module RAM
Progress: Adding admm_solver_0 [admm_solver 1.0]
Progress: Parameterizing module admm_solver_0
Progress: Adding clk_0 [clock_source 21.1]
Progress: Parameterizing module clk_0
Progress: Adding hps_0 [altera_hps 21.1]
Progress: Parameterizing module hps_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: soc_system.hps_0: HPS Main PLL counter settings: n = 0  m = 73
Info: soc_system.hps_0: HPS peripherial PLL counter settings: n = 0  m = 39
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system.qsys --synthesis=VERILOG --output-directory=/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis --family="Cyclone V" --part=5CSEMA5F31C6
Progress: Loading test_final_4840/soc_system.qsys
Progress: Reading input file
Progress: Adding RAM [altera_avalon_onchip_memory2 21.1]
Progress: Parameterizing module RAM
Progress: Adding admm_solver_0 [admm_solver 1.0]
Progress: Parameterizing module admm_solver_0
Progress: Adding clk_0 [clock_source 21.1]
Progress: Parameterizing module clk_0
Progress: Adding hps_0 [altera_hps 21.1]
Progress: Parameterizing module hps_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: soc_system.hps_0: HPS Main PLL counter settings: n = 0  m = 73
Info: soc_system.hps_0: HPS peripherial PLL counter settings: n = 0  m = 39
Info: soc_system: Generating soc_system "soc_system" for QUARTUS_SYNTH
Info: RAM: Starting RTL generation for module 'soc_system_RAM'
Info: RAM:   Generation command is [exec /tools/intel/intelFPGA/21.1/quartus/linux64/perl/bin/perl -I /tools/intel/intelFPGA/21.1/quartus/linux64/perl/lib -I /tools/intel/intelFPGA/21.1/quartus/sopc_builder/bin/europa -I /tools/intel/intelFPGA/21.1/quartus/sopc_builder/bin -I /tools/intel/intelFPGA/21.1/quartus/../ip/altera/sopc_builder_ip/common -I /tools/intel/intelFPGA/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /tools/intel/intelFPGA/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=soc_system_RAM --dir=/tmp/alt0222_6716290417732710698.dir/0293_RAM_gen/ --quartus_dir=/tools/intel/intelFPGA/21.1/quartus --verilog --config=/tmp/alt0222_6716290417732710698.dir/0293_RAM_gen//soc_system_RAM_component_configuration.pl  --do_build_sim=0  ]
Info: RAM: Done RTL generation for module 'soc_system_RAM'
Info: RAM: "soc_system" instantiated altera_avalon_onchip_memory2 "RAM"
Info: admm_solver_0: "soc_system" instantiated admm_solver "admm_solver_0"
Info: hps_0: "Running  for module: hps_0"
Info: hps_0: HPS Main PLL counter settings: n = 0  m = 73
Info: hps_0: HPS peripherial PLL counter settings: n = 0  m = 39
Info: hps_0: "soc_system" instantiated altera_hps "hps_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: rst_controller: "soc_system" instantiated altera_reset_controller "rst_controller"
Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces"
Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io"
Info: admm_solver_0_avalon_slave_0_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "admm_solver_0_avalon_slave_0_translator"
Info: hps_0_h2f_lw_axi_master_agent: "mm_interconnect_0" instantiated altera_merlin_axi_master_ni "hps_0_h2f_lw_axi_master_agent"
Info: admm_solver_0_avalon_slave_0_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "admm_solver_0_avalon_slave_0_agent"
Info: admm_solver_0_avalon_slave_0_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "admm_solver_0_avalon_slave_0_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: router_003: "mm_interconnect_0" instantiated altera_merlin_router "router_003"
Info: hps_0_h2f_lw_axi_master_wr_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "hps_0_h2f_lw_axi_master_wr_limiter"
Info: Reusing file /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v
Info: admm_solver_0_avalon_slave_0_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "admm_solver_0_avalon_slave_0_burst_adapter"
Info: Reusing file /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv
Info: RAM_s1_rsp_width_adapter: "mm_interconnect_0" instantiated altera_merlin_width_adapter "RAM_s1_rsp_width_adapter"
Info: Reusing file /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: avalon_st_adapter_001: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter_001"
Info: border: "hps_io" instantiated altera_interface_generator "border"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: error_adapter_0: "avalon_st_adapter_001" instantiated error_adapter "error_adapter_0"
Info: soc_system: Done "soc_system" with 27 modules, 91 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
