Analysis & Synthesis report for soc_system
Wed May 14 22:33:16 2025
Quartus Prime Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis IP Cores Summary
  6. Analysis & Synthesis Messages
  7. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2021  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.



+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                              ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Failed - Wed May 14 22:33:16 2025           ;
; Quartus Prime Version       ; 21.1.0 Build 842 10/21/2021 SJ Lite Edition ;
; Revision Name               ; soc_system                                  ;
; Top-level Entity Name       ; soc_system_top                              ;
; Family                      ; Cyclone V                                   ;
; Logic utilization (in ALMs) ; N/A until Partition Merge                   ;
; Total registers             ; N/A until Partition Merge                   ;
; Total pins                  ; N/A until Partition Merge                   ;
; Total virtual pins          ; N/A until Partition Merge                   ;
; Total block memory bits     ; N/A until Partition Merge                   ;
; Total PLLs                  ; N/A until Partition Merge                   ;
; Total DLLs                  ; N/A until Partition Merge                   ;
+-----------------------------+---------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                             ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                          ; Setting            ; Default Value      ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
; Top-level entity name                                                           ; soc_system_top     ; soc_system         ;
; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
; Maximum processors allowed for parallel compilation                             ; 4                  ;                    ;
; Use smart compilation                                                           ; Off                ; Off                ;
; Enable parallel Assembler and Timing Analyzer during compilation                ; On                 ; On                 ;
; Enable compact report table                                                     ; Off                ; Off                ;
; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
; Preserve fewer node names                                                       ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                                   ; Enable             ; Enable             ;
; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                        ; Auto               ; Auto               ;
; Safe State Machine                                                              ; Off                ; Off                ;
; Extract Verilog State Machines                                                  ; On                 ; On                 ;
; Extract VHDL State Machines                                                     ; On                 ; On                 ;
; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
; Parallel Synthesis                                                              ; On                 ; On                 ;
; DSP Block Balancing                                                             ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                              ; On                 ; On                 ;
; Power-Up Don't Care                                                             ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
; Remove Duplicate Registers                                                      ; On                 ; On                 ;
; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
; Optimization Technique                                                          ; Balanced           ; Balanced           ;
; Carry Chain Length                                                              ; 70                 ; 70                 ;
; Auto Carry Chains                                                               ; On                 ; On                 ;
; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
; Auto ROM Replacement                                                            ; On                 ; On                 ;
; Auto RAM Replacement                                                            ; On                 ; On                 ;
; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
; Strict RAM Replacement                                                          ; Off                ; Off                ;
; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                           ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
; Report Parameter Settings                                                       ; On                 ; On                 ;
; Report Source Assignments                                                       ; On                 ; On                 ;
; Report Connectivity Checks                                                      ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
; Power Optimization During Synthesis                                             ; Normal compilation ; Normal compilation ;
; HDL message level                                                               ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                            ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
; Block Design Naming                                                             ; Auto               ; Auto               ;
; SDC constraint protection                                                       ; Off                ; Off                ;
; Synthesis Effort                                                                ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
+---------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 20          ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                    ;
+--------+--------------+---------+--------------+--------------+----------------------------------------+-----------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                        ; IP Include File ;
+--------+--------------+---------+--------------+--------------+----------------------------------------+-----------------+
; N/A    ; Qsys         ; 21.1    ; N/A          ; N/A          ; |soc_system_top|soc_system:soc_system0 ; soc_system.qsys ;
+--------+--------------+---------+--------------+--------------+----------------------------------------+-----------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
    Info: Copyright (C) 2021  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and any partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details, at
    Info: https://fpgasoftware.intel.com/eula.
    Info: Processing started: Wed May 14 22:32:58 2025
Info: Command: quartus_map soc_system
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (12021): Found 1 design units, including 1 entities, in source file soc_system_top.sv
    Info (12023): Found entity 1: soc_system_top File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system_top.sv Line: 33
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/soc_system.v
    Info (12023): Found entity 1: soc_system File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/soc_system.v Line: 6
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_reset_controller.v
    Info (12023): Found entity 1: altera_reset_controller File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_reset_controller.v Line: 42
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_reset_synchronizer.v
    Info (12023): Found entity 1: altera_reset_synchronizer File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_reset_synchronizer.v Line: 24
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v
    Info (12023): Found entity 1: soc_system_mm_interconnect_0 File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_avalon_st_adapter_001 File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv Line: 66
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_avalon_st_adapter File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0 File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv Line: 66
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_width_adapter.sv
    Info (12023): Found entity 1: altera_merlin_width_adapter File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_width_adapter.sv Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_address_alignment.sv
    Info (12023): Found entity 1: altera_merlin_address_alignment File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv Line: 26
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv
    Info (12023): Found entity 1: altera_merlin_burst_uncompressor File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv Line: 40
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_rsp_mux File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv Line: 51
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/altera_merlin_arbitrator.sv
    Info (12023): Found entity 1: altera_merlin_arbitrator File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 103
    Info (12023): Found entity 2: altera_merlin_arb_adder File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Line: 228
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_rsp_demux File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_cmd_mux File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv Line: 51
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_cmd_demux File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv Line: 43
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv
    Info (12023): Found entity 1: altera_merlin_burst_adapter File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv
    Info (12023): Found entity 1: altera_merlin_burst_adapter_uncompressed_only File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv Line: 39
Info (12021): Found 5 design units, including 5 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv
    Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 40
    Info (12023): Found entity 2: altera_merlin_burst_adapter_adder File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 55
    Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 77
    Info (12023): Found entity 4: altera_merlin_burst_adapter_min File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 98
    Info (12023): Found entity 5: altera_merlin_burst_adapter_13_1 File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 264
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv
    Info (12023): Found entity 1: altera_merlin_burst_adapter_new File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_incr_burst_converter.sv
    Info (12023): Found entity 1: altera_incr_burst_converter File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_incr_burst_converter.sv Line: 28
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_wrap_burst_converter.sv
    Info (12023): Found entity 1: altera_wrap_burst_converter File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_wrap_burst_converter.sv Line: 27
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_default_burst_converter.sv
    Info (12023): Found entity 1: altera_default_burst_converter File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_default_burst_converter.sv Line: 30
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv
    Info (12023): Found entity 1: altera_avalon_st_pipeline_stage File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v
    Info (12023): Found entity 1: altera_avalon_st_pipeline_base File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv
    Info (12023): Found entity 1: altera_merlin_traffic_limiter File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv Line: 49
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv
    Info (12023): Found entity 1: altera_merlin_reorder_memory File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 28
    Info (12023): Found entity 2: memory_pointer_controller File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv Line: 185
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_sc_fifo.v
    Info (12023): Found entity 1: altera_avalon_sc_fifo File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v Line: 21
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_router_003_default_decode File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_0_router_003 File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_router_002_default_decode File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_0_router_002 File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv Line: 84
Info (12021): Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv
    Info (12023): Found entity 1: soc_system_mm_interconnect_0_router_default_decode File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv Line: 45
    Info (12023): Found entity 2: soc_system_mm_interconnect_0_router File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv Line: 84
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_slave_agent.sv
    Info (12023): Found entity 1: altera_merlin_slave_agent File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_slave_agent.sv Line: 34
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv
    Info (12023): Found entity 1: altera_merlin_axi_master_ni File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv Line: 27
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_slave_translator.sv
    Info (12023): Found entity 1: altera_merlin_slave_translator File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_slave_translator.sv Line: 35
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0.v
    Info (12023): Found entity 1: soc_system_hps_0 File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v
    Info (12023): Found entity 1: soc_system_hps_0_hps_io File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram.v
    Info (12023): Found entity 1: hps_sdram File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram.v Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv
    Info (12023): Found entity 1: altera_mem_if_dll_cyclonev File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv
    Info (12023): Found entity 1: altera_mem_if_oct_cyclonev File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv
    Info (12023): Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 18
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v
    Info (12023): Found entity 1: altera_mem_if_hhp_qseq_synth_top File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v Line: 15
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv
    Info (12023): Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Line: 19
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v
    Info (12023): Found entity 1: hps_sdram_p0_altdqdqs File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0.sv
    Info (12023): Found entity 1: hps_sdram_p0 File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.sv Line: 18
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v
    Info (12023): Found entity 1: hps_sdram_p0_iss_probe File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv
    Info (12023): Found entity 1: hps_sdram_p0_phy_csr File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv Line: 31
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v
    Info (12023): Found entity 1: hps_sdram_p0_reset_sync File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_reset.v
    Info (12023): Found entity 1: hps_sdram_p0_reset File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset.v Line: 18
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v
    Info (12023): Found entity 1: hps_sdram_p0_generic_ddio File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v
    Info (12023): Found entity 1: hps_sdram_p0_acv_hard_io_pads File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v
    Info (12023): Found entity 1: hps_sdram_p0_acv_ldc File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v
    Info (12023): Found entity 1: hps_sdram_p0_acv_hard_memphy File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v Line: 21
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v
    Info (12023): Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 17
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v
    Info (12023): Found entity 1: hps_sdram_p0_clock_pair_generator File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Line: 29
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_pll.sv
    Info (12023): Found entity 1: hps_sdram_pll File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_pll.sv Line: 25
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv
    Info (12023): Found entity 1: soc_system_hps_0_hps_io_border File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv Line: 14
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv
    Info (12023): Found entity 1: soc_system_hps_0_fpga_interfaces File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv Line: 14
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/admm_solver.sv
    Info (12023): Found entity 1: admm_solver File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/dual_update.sv
    Info (12023): Found entity 1: dual_update File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv Line: 4
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/primal_update.sv
    Info (12023): Found entity 1: primal_update File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/primal_update.sv Line: 4
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/residual_calculator.sv
    Info (12023): Found entity 1: residual_calculator File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/residual_calculator.sv Line: 4
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/slack_update.sv
    Info (12023): Found entity 1: slack_update File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/slack_update.sv Line: 4
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/memory_interface.sv
    Info (12023): Found entity 1: memory_interface File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/memory_interface.sv Line: 2
Info (12021): Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_RAM.v
    Info (12023): Found entity 1: soc_system_RAM File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_RAM.v Line: 21
Info (12127): Elaborating entity "soc_system_top" for the top level hierarchy
Info (12128): Elaborating entity "soc_system" for hierarchy "soc_system:soc_system0" File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system_top.sv Line: 270
Error (10203): Verilog HDL Declaration error at admm_solver.sv(158): vector has more than 2**20 bits File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 158
Error (12152): Can't elaborate user hierarchy "soc_system:soc_system0" File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system_top.sv Line: 270
Info (144001): Generated suppressed messages file /homes/user/stud/spring25/rjh2173/test_final_4840/output_files/soc_system.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
    Error: Peak virtual memory: 709 megabytes
    Error: Processing ended: Wed May 14 22:36:39 2025
    Error: Elapsed time: 00:03:41
    Error: Total CPU time (on all processors): 00:03:52


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /homes/user/stud/spring25/rjh2173/test_final_4840/output_files/soc_system.map.smsg.


