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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map soc_system " "Command: quartus_map soc_system" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276378915 ""}
{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1747276382831 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system_top.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system_top.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_top " "Found entity 1: soc_system_top" {  } { { "soc_system_top.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system_top.sv" 33 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276394852 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276394852 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/soc_system.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/soc_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system " "Found entity 1: soc_system" {  } { { "soc_system/synthesis/soc_system.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/soc_system.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276394874 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276394874 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" {  } { { "soc_system/synthesis/submodules/altera_reset_controller.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_reset_controller.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276394894 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276394894 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" {  } { { "soc_system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276394923 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276394923 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0 " "Found entity 1: soc_system_mm_interconnect_0" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276394948 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276394948 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0_avalon_st_adapter_001 " "Found entity 1: soc_system_mm_interconnect_0_avalon_st_adapter_001" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276394968 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276394968 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 " "Found entity 1: soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv" 66 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276394986 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276394986 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0_avalon_st_adapter " "Found entity 1: soc_system_mm_interconnect_0_avalon_st_adapter" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395014 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395014 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0 " "Found entity 1: soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" 66 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395034 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395034 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_width_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_width_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_width_adapter " "Found entity 1: altera_merlin_width_adapter" {  } { { "soc_system/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_width_adapter.sv" 25 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395057 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395057 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" {  } { { "soc_system/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395079 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395079 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" {  } { { "soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395099 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395099 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0_rsp_mux " "Found entity 1: soc_system_mm_interconnect_0_rsp_mux" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395118 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395118 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" {  } { { "soc_system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395140 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" {  } { { "soc_system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395140 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395140 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0_rsp_demux " "Found entity 1: soc_system_mm_interconnect_0_rsp_demux" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395160 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395160 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0_cmd_mux " "Found entity 1: soc_system_mm_interconnect_0_cmd_mux" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395181 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395181 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0_cmd_demux " "Found entity 1: soc_system_mm_interconnect_0_cmd_demux" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395204 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395204 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter " "Found entity 1: altera_merlin_burst_adapter" {  } { { "soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395222 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395222 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_uncompressed_only " "Found entity 1: altera_merlin_burst_adapter_uncompressed_only" {  } { { "soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395243 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395243 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv 5 5 " "Found 5 design units, including 5 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" {  } { { "soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395267 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" {  } { { "soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 55 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395267 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" {  } { { "soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 77 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395267 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" {  } { { "soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 98 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395267 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter_13_1 " "Found entity 5: altera_merlin_burst_adapter_13_1" {  } { { "soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 264 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395267 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395267 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BYTE_TO_WORD_SHIFT byte_to_word_shift altera_merlin_burst_adapter_new.sv(139) " "Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object \"BYTE_TO_WORD_SHIFT\" differs only in case from object \"byte_to_word_shift\" in the same scope" {  } { { "soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 139 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276395305 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_new " "Found entity 1: altera_merlin_burst_adapter_new" {  } { { "soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 25 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395309 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395309 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_incr_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_incr_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_incr_burst_converter " "Found entity 1: altera_incr_burst_converter" {  } { { "soc_system/synthesis/submodules/altera_incr_burst_converter.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_incr_burst_converter.sv" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395327 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395327 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "addr_incr ADDR_INCR altera_wrap_burst_converter.sv(279) " "Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object \"addr_incr\" differs only in case from object \"ADDR_INCR\" in the same scope" {  } { { "soc_system/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_wrap_burst_converter.sv" 279 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276395343 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_wrap_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_wrap_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_wrap_burst_converter " "Found entity 1: altera_wrap_burst_converter" {  } { { "soc_system/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_wrap_burst_converter.sv" 27 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395346 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395346 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_default_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_default_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_default_burst_converter " "Found entity 1: altera_default_burst_converter" {  } { { "soc_system/synthesis/submodules/altera_default_burst_converter.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_default_burst_converter.sv" 30 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395365 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395365 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_stage " "Found entity 1: altera_avalon_st_pipeline_stage" {  } { { "soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395389 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395389 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" {  } { { "soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395426 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395426 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" {  } { { "soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395469 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395469 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv 2 2 " "Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_reorder_memory " "Found entity 1: altera_merlin_reorder_memory" {  } { { "soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395490 ""} { "Info" "ISGN_ENTITY_NAME" "2 memory_pointer_controller " "Found entity 2: memory_pointer_controller" {  } { { "soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv" 185 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395490 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395490 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" {  } { { "soc_system/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395516 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395516 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel soc_system_mm_interconnect_0_router_003.sv(48) " "Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_003.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276395541 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel soc_system_mm_interconnect_0_router_003.sv(49) " "Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_003.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276395541 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv 2 2 " "Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0_router_003_default_decode " "Found entity 1: soc_system_mm_interconnect_0_router_003_default_decode" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395546 ""} { "Info" "ISGN_ENTITY_NAME" "2 soc_system_mm_interconnect_0_router_003 " "Found entity 2: soc_system_mm_interconnect_0_router_003" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395546 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395546 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel soc_system_mm_interconnect_0_router_002.sv(48) " "Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276395566 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel soc_system_mm_interconnect_0_router_002.sv(49) " "Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276395566 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0_router_002_default_decode " "Found entity 1: soc_system_mm_interconnect_0_router_002_default_decode" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395570 ""} { "Info" "ISGN_ENTITY_NAME" "2 soc_system_mm_interconnect_0_router_002 " "Found entity 2: soc_system_mm_interconnect_0_router_002" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395570 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395570 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel soc_system_mm_interconnect_0_router.sv(48) " "Verilog HDL Declaration information at soc_system_mm_interconnect_0_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276395606 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel soc_system_mm_interconnect_0_router.sv(49) " "Verilog HDL Declaration information at soc_system_mm_interconnect_0_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276395606 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_mm_interconnect_0_router_default_decode " "Found entity 1: soc_system_mm_interconnect_0_router_default_decode" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395614 ""} { "Info" "ISGN_ENTITY_NAME" "2 soc_system_mm_interconnect_0_router " "Found entity 2: soc_system_mm_interconnect_0_router" {  } { { "soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395614 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395614 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" {  } { { "soc_system/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395648 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395648 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_axi_master_ni " "Found entity 1: altera_merlin_axi_master_ni" {  } { { "soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv" 27 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395668 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395668 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" {  } { { "soc_system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395691 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395691 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_hps_0.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_hps_0 " "Found entity 1: soc_system_hps_0" {  } { { "soc_system/synthesis/submodules/soc_system_hps_0.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395714 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395714 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_hps_0_hps_io " "Found entity 1: soc_system_hps_0_hps_io" {  } { { "soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395737 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395737 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram " "Found entity 1: hps_sdram" {  } { { "soc_system/synthesis/submodules/hps_sdram.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395779 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395779 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_dll_cyclonev " "Found entity 1: altera_mem_if_dll_cyclonev" {  } { { "soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" 23 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395803 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395803 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_oct_cyclonev " "Found entity 1: altera_mem_if_oct_cyclonev" {  } { { "soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" 23 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395824 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395824 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hard_memory_controller_top_cyclonev " "Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev" {  } { { "soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395850 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395850 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hhp_qseq_synth_top " "Found entity 1: altera_mem_if_hhp_qseq_synth_top" {  } { { "soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" 15 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395873 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395873 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altdq_dqs2_acv_connect_to_hard_phy_cyclonev " "Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev" {  } { { "soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" 19 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395905 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395905 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_altdqdqs " "Found entity 1: hps_sdram_p0_altdqdqs" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395926 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395926 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0 " "Found entity 1: hps_sdram_p0" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.sv" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395955 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395955 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_iss_probe " "Found entity 1: hps_sdram_p0_iss_probe" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395976 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395976 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_phy_csr " "Found entity 1: hps_sdram_p0_phy_csr" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv" 31 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276395996 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276395996 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset_sync " "Found entity 1: hps_sdram_p0_reset_sync" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396021 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396021 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0_reset.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset " "Found entity 1: hps_sdram_p0_reset" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0_reset.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396048 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396048 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_generic_ddio " "Found entity 1: hps_sdram_p0_generic_ddio" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396096 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396096 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_io_pads " "Found entity 1: hps_sdram_p0_acv_hard_io_pads" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396132 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396132 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_ldc " "Found entity 1: hps_sdram_p0_acv_ldc" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396150 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396150 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_memphy " "Found entity 1: hps_sdram_p0_acv_hard_memphy" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396170 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396170 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_addr_cmd_pads " "Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396190 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396190 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_clock_pair_generator " "Found entity 1: hps_sdram_p0_clock_pair_generator" {  } { { "soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396256 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396256 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/hps_sdram_pll.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/hps_sdram_pll.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_pll " "Found entity 1: hps_sdram_pll" {  } { { "soc_system/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_pll.sv" 25 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396273 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396273 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_hps_0_hps_io_border " "Found entity 1: soc_system_hps_0_hps_io_border" {  } { { "soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv" 14 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396298 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396298 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_hps_0_fpga_interfaces " "Found entity 1: soc_system_hps_0_fpga_interfaces" {  } { { "soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv" 14 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396316 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396316 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "Q_rdaddress q_rdaddress admm_solver.sv(58) " "Verilog HDL Declaration information at admm_solver.sv(58): object \"Q_rdaddress\" differs only in case from object \"q_rdaddress\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 58 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "Q_wraddress q_wraddress admm_solver.sv(58) " "Verilog HDL Declaration information at admm_solver.sv(58): object \"Q_wraddress\" differs only in case from object \"q_wraddress\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 58 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "Q_data_out q_data_out admm_solver.sv(59) " "Verilog HDL Declaration information at admm_solver.sv(59): object \"Q_data_out\" differs only in case from object \"q_data_out\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 59 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "Q_data_in q_data_in admm_solver.sv(59) " "Verilog HDL Declaration information at admm_solver.sv(59): object \"Q_data_in\" differs only in case from object \"q_data_in\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 59 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "Q_wren q_wren admm_solver.sv(60) " "Verilog HDL Declaration information at admm_solver.sv(60): object \"Q_wren\" differs only in case from object \"q_wren\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 60 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "R_rdaddress r_rdaddress admm_solver.sv(62) " "Verilog HDL Declaration information at admm_solver.sv(62): object \"R_rdaddress\" differs only in case from object \"r_rdaddress\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 62 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "R_wraddress r_wraddress admm_solver.sv(62) " "Verilog HDL Declaration information at admm_solver.sv(62): object \"R_wraddress\" differs only in case from object \"r_wraddress\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 62 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "R_data_out r_data_out admm_solver.sv(63) " "Verilog HDL Declaration information at admm_solver.sv(63): object \"R_data_out\" differs only in case from object \"r_data_out\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 63 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "R_data_in r_data_in admm_solver.sv(63) " "Verilog HDL Declaration information at admm_solver.sv(63): object \"R_data_in\" differs only in case from object \"r_data_in\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 63 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "R_wren r_wren admm_solver.sv(64) " "Verilog HDL Declaration information at admm_solver.sv(64): object \"R_wren\" differs only in case from object \"r_wren\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 64 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "P_rdaddress p_rdaddress admm_solver.sv(79) " "Verilog HDL Declaration information at admm_solver.sv(79): object \"P_rdaddress\" differs only in case from object \"p_rdaddress\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 79 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "P_wraddress p_wraddress admm_solver.sv(79) " "Verilog HDL Declaration information at admm_solver.sv(79): object \"P_wraddress\" differs only in case from object \"p_wraddress\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 79 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "P_data_out p_data_out admm_solver.sv(80) " "Verilog HDL Declaration information at admm_solver.sv(80): object \"P_data_out\" differs only in case from object \"p_data_out\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 80 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "P_data_in p_data_in admm_solver.sv(80) " "Verilog HDL Declaration information at admm_solver.sv(80): object \"P_data_in\" differs only in case from object \"p_data_in\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 80 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "P_wren p_wren admm_solver.sv(81) " "Verilog HDL Declaration information at admm_solver.sv(81): object \"P_wren\" differs only in case from object \"p_wren\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 81 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "Q_ram q_ram admm_solver.sv(211) " "Verilog HDL Declaration information at admm_solver.sv(211): object \"Q_ram\" differs only in case from object \"q_ram\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 211 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "R_ram r_ram admm_solver.sv(226) " "Verilog HDL Declaration information at admm_solver.sv(226): object \"R_ram\" differs only in case from object \"r_ram\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 226 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "P_ram p_ram admm_solver.sv(286) " "Verilog HDL Declaration information at admm_solver.sv(286): object \"P_ram\" differs only in case from object \"p_ram\" in the same scope" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 286 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396331 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/admm_solver.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/admm_solver.sv" { { "Info" "ISGN_ENTITY_NAME" "1 admm_solver " "Found entity 1: admm_solver" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396334 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396334 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dual_update.sv(155) " "Verilog HDL information at dual_update.sv(155): always construct contains both blocking and non-blocking assignments" {  } { { "soc_system/synthesis/submodules/dual_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv" 155 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1747276396352 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "r_rdaddress R_rdaddress dual_update.sv(51) " "Verilog HDL Declaration information at dual_update.sv(51): object \"r_rdaddress\" differs only in case from object \"R_rdaddress\" in the same scope" {  } { { "soc_system/synthesis/submodules/dual_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv" 51 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396353 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "r_data_out R_data_out dual_update.sv(52) " "Verilog HDL Declaration information at dual_update.sv(52): object \"r_data_out\" differs only in case from object \"R_data_out\" in the same scope" {  } { { "soc_system/synthesis/submodules/dual_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv" 52 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396353 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "q_rdaddress Q_rdaddress dual_update.sv(58) " "Verilog HDL Declaration information at dual_update.sv(58): object \"q_rdaddress\" differs only in case from object \"Q_rdaddress\" in the same scope" {  } { { "soc_system/synthesis/submodules/dual_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv" 58 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396353 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "q_data_out Q_data_out dual_update.sv(59) " "Verilog HDL Declaration information at dual_update.sv(59): object \"q_data_out\" differs only in case from object \"Q_data_out\" in the same scope" {  } { { "soc_system/synthesis/submodules/dual_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv" 59 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396353 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "p_rdaddress P_rdaddress dual_update.sv(65) " "Verilog HDL Declaration information at dual_update.sv(65): object \"p_rdaddress\" differs only in case from object \"P_rdaddress\" in the same scope" {  } { { "soc_system/synthesis/submodules/dual_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv" 65 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396353 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "p_data_out P_data_out dual_update.sv(66) " "Verilog HDL Declaration information at dual_update.sv(66): object \"p_data_out\" differs only in case from object \"P_data_out\" in the same scope" {  } { { "soc_system/synthesis/submodules/dual_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv" 66 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396353 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "temp_r temp_R dual_update.sv(123) " "Verilog HDL Declaration information at dual_update.sv(123): object \"temp_r\" differs only in case from object \"temp_R\" in the same scope" {  } { { "soc_system/synthesis/submodules/dual_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv" 123 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396353 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "temp_q temp_Q dual_update.sv(124) " "Verilog HDL Declaration information at dual_update.sv(124): object \"temp_q\" differs only in case from object \"temp_Q\" in the same scope" {  } { { "soc_system/synthesis/submodules/dual_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv" 124 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396353 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "temp_p temp_P dual_update.sv(125) " "Verilog HDL Declaration information at dual_update.sv(125): object \"temp_p\" differs only in case from object \"temp_P\" in the same scope" {  } { { "soc_system/synthesis/submodules/dual_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv" 125 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1747276396353 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/dual_update.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/dual_update.sv" { { "Info" "ISGN_ENTITY_NAME" "1 dual_update " "Found entity 1: dual_update" {  } { { "soc_system/synthesis/submodules/dual_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396357 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396357 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/primal_update.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/primal_update.sv" { { "Info" "ISGN_ENTITY_NAME" "1 primal_update " "Found entity 1: primal_update" {  } { { "soc_system/synthesis/submodules/primal_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/primal_update.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396400 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396400 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "residual_calculator.sv(66) " "Verilog HDL information at residual_calculator.sv(66): always construct contains both blocking and non-blocking assignments" {  } { { "soc_system/synthesis/submodules/residual_calculator.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/residual_calculator.sv" 66 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1747276396424 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/residual_calculator.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/residual_calculator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 residual_calculator " "Found entity 1: residual_calculator" {  } { { "soc_system/synthesis/submodules/residual_calculator.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/residual_calculator.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396429 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396429 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "slack_update.sv(65) " "Verilog HDL information at slack_update.sv(65): always construct contains both blocking and non-blocking assignments" {  } { { "soc_system/synthesis/submodules/slack_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/slack_update.sv" 65 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1747276396458 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/slack_update.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/slack_update.sv" { { "Info" "ISGN_ENTITY_NAME" "1 slack_update " "Found entity 1: slack_update" {  } { { "soc_system/synthesis/submodules/slack_update.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/slack_update.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396461 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396461 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/memory_interface.sv 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/memory_interface.sv" { { "Info" "ISGN_ENTITY_NAME" "1 memory_interface " "Found entity 1: memory_interface" {  } { { "soc_system/synthesis/submodules/memory_interface.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/memory_interface.sv" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396479 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396479 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "soc_system/synthesis/submodules/soc_system_RAM.v 1 1 " "Found 1 design units, including 1 entities, in source file soc_system/synthesis/submodules/soc_system_RAM.v" { { "Info" "ISGN_ENTITY_NAME" "1 soc_system_RAM " "Found entity 1: soc_system_RAM" {  } { { "soc_system/synthesis/submodules/soc_system_RAM.v" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_RAM.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1747276396502 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396502 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for \"pll_dr_clk\"" {  } { { "soc_system/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "Analysis & Synthesis" 0 -1 1747276396503 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "soc_system_top " "Elaborating entity \"soc_system_top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1747276396814 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "soc_system soc_system:soc_system0 " "Elaborating entity \"soc_system\" for hierarchy \"soc_system:soc_system0\"" {  } { { "soc_system_top.sv" "soc_system0" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system_top.sv" 270 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747276396844 ""}
{ "Error" "EVRFX_VERI_BIG_VEC_ERROR" "20 admm_solver.sv(158) " "Verilog HDL Declaration error at admm_solver.sv(158): vector has more than 2**20 bits" {  } { { "soc_system/synthesis/submodules/admm_solver.sv" "" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv" 158 0 0 } }  } 0 10203 "Verilog HDL Declaration error at %2!s!: vector has more than 2**%1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1747276396846 ""}
{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "soc_system:soc_system0 " "Can't elaborate user hierarchy \"soc_system:soc_system0\"" {  } { { "soc_system_top.sv" "soc_system0" { Text "/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system_top.sv" 270 0 0 } }  } 0 12152 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1747276396897 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/homes/user/stud/spring25/rjh2173/test_final_4840/output_files/soc_system.map.smsg " "Generated suppressed messages file /homes/user/stud/spring25/rjh2173/test_final_4840/output_files/soc_system.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276396986 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "709 " "Peak virtual memory: 709 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1747276599875 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed May 14 22:36:39 2025 " "Processing ended: Wed May 14 22:36:39 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1747276599875 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:03:41 " "Elapsed time: 00:03:41" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1747276599875 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:03:52 " "Total CPU time (on all processors): 00:03:52" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1747276599875 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1747276599875 ""}
