Info (10281): Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object "BYTE_TO_WORD_SHIFT" differs only in case from object "byte_to_word_shift" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv Line: 139
Info (10281): Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object "addr_incr" differs only in case from object "ADDR_INCR" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_wrap_burst_converter.sv Line: 279
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_003.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv Line: 48
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_003.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv Line: 49
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv Line: 48
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv Line: 49
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv Line: 48
Info (10281): Verilog HDL Declaration information at soc_system_mm_interconnect_0_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv Line: 49
Info (10281): Verilog HDL Declaration information at admm_solver.sv(58): object "Q_rdaddress" differs only in case from object "q_rdaddress" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 58
Info (10281): Verilog HDL Declaration information at admm_solver.sv(58): object "Q_wraddress" differs only in case from object "q_wraddress" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 58
Info (10281): Verilog HDL Declaration information at admm_solver.sv(59): object "Q_data_out" differs only in case from object "q_data_out" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 59
Info (10281): Verilog HDL Declaration information at admm_solver.sv(59): object "Q_data_in" differs only in case from object "q_data_in" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 59
Info (10281): Verilog HDL Declaration information at admm_solver.sv(60): object "Q_wren" differs only in case from object "q_wren" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 60
Info (10281): Verilog HDL Declaration information at admm_solver.sv(62): object "R_rdaddress" differs only in case from object "r_rdaddress" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 62
Info (10281): Verilog HDL Declaration information at admm_solver.sv(62): object "R_wraddress" differs only in case from object "r_wraddress" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 62
Info (10281): Verilog HDL Declaration information at admm_solver.sv(63): object "R_data_out" differs only in case from object "r_data_out" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 63
Info (10281): Verilog HDL Declaration information at admm_solver.sv(63): object "R_data_in" differs only in case from object "r_data_in" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 63
Info (10281): Verilog HDL Declaration information at admm_solver.sv(64): object "R_wren" differs only in case from object "r_wren" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 64
Info (10281): Verilog HDL Declaration information at admm_solver.sv(79): object "P_rdaddress" differs only in case from object "p_rdaddress" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 79
Info (10281): Verilog HDL Declaration information at admm_solver.sv(79): object "P_wraddress" differs only in case from object "p_wraddress" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 79
Info (10281): Verilog HDL Declaration information at admm_solver.sv(80): object "P_data_out" differs only in case from object "p_data_out" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 80
Info (10281): Verilog HDL Declaration information at admm_solver.sv(80): object "P_data_in" differs only in case from object "p_data_in" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 80
Info (10281): Verilog HDL Declaration information at admm_solver.sv(81): object "P_wren" differs only in case from object "p_wren" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 81
Info (10281): Verilog HDL Declaration information at admm_solver.sv(211): object "Q_ram" differs only in case from object "q_ram" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 211
Info (10281): Verilog HDL Declaration information at admm_solver.sv(226): object "R_ram" differs only in case from object "r_ram" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 226
Info (10281): Verilog HDL Declaration information at admm_solver.sv(286): object "P_ram" differs only in case from object "p_ram" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv Line: 286
Warning (10268): Verilog HDL information at dual_update.sv(155): always construct contains both blocking and non-blocking assignments File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv Line: 155
Info (10281): Verilog HDL Declaration information at dual_update.sv(51): object "r_rdaddress" differs only in case from object "R_rdaddress" in the same scope File: /homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv Line: 51
