# TCL File Generated by Component Editor 21.1
# Wed May 14 22:31:08 EDT 2025
# DO NOT MODIFY


# 
# admm_solver "ADMM_SOLVER" v1.0
#  2025.05.14.22:31:08
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module admm_solver
# 
set_module_property DESCRIPTION ""
set_module_property NAME admm_solver
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME ADMM_SOLVER
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
set_module_assignment embeddedsw.dts.vender "csee4840"
set_module_assignment embeddedsw.dts.name "admm_solver"
set_module_assignment embeddedsw.dts.group "admm"

# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL admm_solver
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file admm_solver.sv SYSTEM_VERILOG PATH admm_solver.sv TOP_LEVEL_FILE
add_fileset_file dual_update.sv SYSTEM_VERILOG PATH dual_update.sv
add_fileset_file primal_update.sv SYSTEM_VERILOG PATH primal_update.sv
add_fileset_file residual_calculator.sv SYSTEM_VERILOG PATH residual_calculator.sv
add_fileset_file slack_update.sv SYSTEM_VERILOG PATH slack_update.sv
add_fileset_file memory_interface.sv SYSTEM_VERILOG PATH memory_interface.sv


# 
# parameters
# 
add_parameter STATE_DIM STRING 12 ""
set_parameter_property STATE_DIM DEFAULT_VALUE 12
set_parameter_property STATE_DIM DISPLAY_NAME STATE_DIM
set_parameter_property STATE_DIM TYPE STRING
set_parameter_property STATE_DIM UNITS None
set_parameter_property STATE_DIM DESCRIPTION ""
set_parameter_property STATE_DIM HDL_PARAMETER true
add_parameter INPUT_DIM INTEGER 4 ""
set_parameter_property INPUT_DIM DEFAULT_VALUE 4
set_parameter_property INPUT_DIM DISPLAY_NAME INPUT_DIM
set_parameter_property INPUT_DIM TYPE INTEGER
set_parameter_property INPUT_DIM UNITS None
set_parameter_property INPUT_DIM ALLOWED_RANGES -2147483648:2147483647
set_parameter_property INPUT_DIM DESCRIPTION ""
set_parameter_property INPUT_DIM HDL_PARAMETER true
add_parameter HORIZON INTEGER 30
set_parameter_property HORIZON DEFAULT_VALUE 30
set_parameter_property HORIZON DISPLAY_NAME HORIZON
set_parameter_property HORIZON TYPE INTEGER
set_parameter_property HORIZON UNITS None
set_parameter_property HORIZON ALLOWED_RANGES -2147483648:2147483647
set_parameter_property HORIZON HDL_PARAMETER true
add_parameter MAX_ITER INTEGER 100 ""
set_parameter_property MAX_ITER DEFAULT_VALUE 100
set_parameter_property MAX_ITER DISPLAY_NAME MAX_ITER
set_parameter_property MAX_ITER TYPE INTEGER
set_parameter_property MAX_ITER UNITS None
set_parameter_property MAX_ITER ALLOWED_RANGES -2147483648:2147483647
set_parameter_property MAX_ITER DESCRIPTION ""
set_parameter_property MAX_ITER HDL_PARAMETER true
add_parameter EXT_DATA_WIDTH STRING 32
set_parameter_property EXT_DATA_WIDTH DEFAULT_VALUE 32
set_parameter_property EXT_DATA_WIDTH DISPLAY_NAME EXT_DATA_WIDTH
set_parameter_property EXT_DATA_WIDTH TYPE STRING
set_parameter_property EXT_DATA_WIDTH UNITS None
set_parameter_property EXT_DATA_WIDTH HDL_PARAMETER true
add_parameter DATA_WIDTH INTEGER 16 ""
set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
set_parameter_property DATA_WIDTH TYPE INTEGER
set_parameter_property DATA_WIDTH UNITS None
set_parameter_property DATA_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property DATA_WIDTH DESCRIPTION ""
set_parameter_property DATA_WIDTH HDL_PARAMETER true
add_parameter FRAC_BITS INTEGER 8
set_parameter_property FRAC_BITS DEFAULT_VALUE 8
set_parameter_property FRAC_BITS DISPLAY_NAME FRAC_BITS
set_parameter_property FRAC_BITS TYPE INTEGER
set_parameter_property FRAC_BITS UNITS None
set_parameter_property FRAC_BITS ALLOWED_RANGES -2147483648:2147483647
set_parameter_property FRAC_BITS HDL_PARAMETER true
add_parameter ADDR_WIDTH STRING 16
set_parameter_property ADDR_WIDTH DEFAULT_VALUE 16
set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH
set_parameter_property ADDR_WIDTH TYPE STRING
set_parameter_property ADDR_WIDTH UNITS None
set_parameter_property ADDR_WIDTH HDL_PARAMETER true
add_parameter MEM_ADDR_WIDTH INTEGER 9
set_parameter_property MEM_ADDR_WIDTH DEFAULT_VALUE 9
set_parameter_property MEM_ADDR_WIDTH DISPLAY_NAME MEM_ADDR_WIDTH
set_parameter_property MEM_ADDR_WIDTH TYPE INTEGER
set_parameter_property MEM_ADDR_WIDTH UNITS None
set_parameter_property MEM_ADDR_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property MEM_ADDR_WIDTH HDL_PARAMETER true


# 
# module assignments
# 
set_module_assignment embeddedsw.dts.group admm
set_module_assignment embeddedsw.dts.name admm_solver
set_module_assignment embeddedsw.dts.vender csee4840


# 
# display items
# 


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1


# 
# connection point reset
# 
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset rst reset Input 1


# 
# connection point avalon_slave_0
# 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock
set_interface_property avalon_slave_0 associatedReset reset
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
set_interface_property avalon_slave_0 EXPORT_OF ""
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""

add_interface_port avalon_slave_0 writedata writedata Input "((EXT_DATA_WIDTH-1)) - (0) + 1"
add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 addr address Input "((ADDR_WIDTH-1)) - (0) + 1"
add_interface_port avalon_slave_0 chipselect chipselect Input 1
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0


# 
# connection point admm
# 
add_interface admm conduit end
set_interface_property admm associatedClock clock
set_interface_property admm associatedReset ""
set_interface_property admm ENABLED true
set_interface_property admm EXPORT_OF ""
set_interface_property admm PORT_NAME_MAP ""
set_interface_property admm CMSIS_SVD_VARIABLES ""
set_interface_property admm SVD_ADDRESS_GROUP ""

add_interface_port admm read read Input 1
add_interface_port admm readdata readdata Output "((EXT_DATA_WIDTH-1)) - (0) + 1"

