<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2025.05.14.22:32:31"
 outputDirectory="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Cyclone V"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="5CSEMA5F31C6"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="6"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <interface name="admm" kind="conduit" start="0">
   <property name="associatedClock" value="clk" />
   <property name="associatedReset" value="" />
   <port name="admm_read" direction="input" role="read" width="1" />
   <port name="admm_readdata" direction="output" role="readdata" width="32" />
  </interface>
  <interface name="clk" kind="clock" start="0">
   <property name="clockRate" value="50000000" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="clk_clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="hps" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <port
       name="hps_hps_io_emac1_inst_TX_CLK"
       direction="output"
       role="hps_io_emac1_inst_TX_CLK"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_TXD0"
       direction="output"
       role="hps_io_emac1_inst_TXD0"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_TXD1"
       direction="output"
       role="hps_io_emac1_inst_TXD1"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_TXD2"
       direction="output"
       role="hps_io_emac1_inst_TXD2"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_TXD3"
       direction="output"
       role="hps_io_emac1_inst_TXD3"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_RXD0"
       direction="input"
       role="hps_io_emac1_inst_RXD0"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_MDIO"
       direction="bidir"
       role="hps_io_emac1_inst_MDIO"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_MDC"
       direction="output"
       role="hps_io_emac1_inst_MDC"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_RX_CTL"
       direction="input"
       role="hps_io_emac1_inst_RX_CTL"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_TX_CTL"
       direction="output"
       role="hps_io_emac1_inst_TX_CTL"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_RX_CLK"
       direction="input"
       role="hps_io_emac1_inst_RX_CLK"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_RXD1"
       direction="input"
       role="hps_io_emac1_inst_RXD1"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_RXD2"
       direction="input"
       role="hps_io_emac1_inst_RXD2"
       width="1" />
   <port
       name="hps_hps_io_emac1_inst_RXD3"
       direction="input"
       role="hps_io_emac1_inst_RXD3"
       width="1" />
   <port
       name="hps_hps_io_sdio_inst_CMD"
       direction="bidir"
       role="hps_io_sdio_inst_CMD"
       width="1" />
   <port
       name="hps_hps_io_sdio_inst_D0"
       direction="bidir"
       role="hps_io_sdio_inst_D0"
       width="1" />
   <port
       name="hps_hps_io_sdio_inst_D1"
       direction="bidir"
       role="hps_io_sdio_inst_D1"
       width="1" />
   <port
       name="hps_hps_io_sdio_inst_CLK"
       direction="output"
       role="hps_io_sdio_inst_CLK"
       width="1" />
   <port
       name="hps_hps_io_sdio_inst_D2"
       direction="bidir"
       role="hps_io_sdio_inst_D2"
       width="1" />
   <port
       name="hps_hps_io_sdio_inst_D3"
       direction="bidir"
       role="hps_io_sdio_inst_D3"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_D0"
       direction="bidir"
       role="hps_io_usb1_inst_D0"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_D1"
       direction="bidir"
       role="hps_io_usb1_inst_D1"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_D2"
       direction="bidir"
       role="hps_io_usb1_inst_D2"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_D3"
       direction="bidir"
       role="hps_io_usb1_inst_D3"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_D4"
       direction="bidir"
       role="hps_io_usb1_inst_D4"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_D5"
       direction="bidir"
       role="hps_io_usb1_inst_D5"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_D6"
       direction="bidir"
       role="hps_io_usb1_inst_D6"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_D7"
       direction="bidir"
       role="hps_io_usb1_inst_D7"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_CLK"
       direction="input"
       role="hps_io_usb1_inst_CLK"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_STP"
       direction="output"
       role="hps_io_usb1_inst_STP"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_DIR"
       direction="input"
       role="hps_io_usb1_inst_DIR"
       width="1" />
   <port
       name="hps_hps_io_usb1_inst_NXT"
       direction="input"
       role="hps_io_usb1_inst_NXT"
       width="1" />
   <port
       name="hps_hps_io_spim1_inst_CLK"
       direction="output"
       role="hps_io_spim1_inst_CLK"
       width="1" />
   <port
       name="hps_hps_io_spim1_inst_MOSI"
       direction="output"
       role="hps_io_spim1_inst_MOSI"
       width="1" />
   <port
       name="hps_hps_io_spim1_inst_MISO"
       direction="input"
       role="hps_io_spim1_inst_MISO"
       width="1" />
   <port
       name="hps_hps_io_spim1_inst_SS0"
       direction="output"
       role="hps_io_spim1_inst_SS0"
       width="1" />
   <port
       name="hps_hps_io_uart0_inst_RX"
       direction="input"
       role="hps_io_uart0_inst_RX"
       width="1" />
   <port
       name="hps_hps_io_uart0_inst_TX"
       direction="output"
       role="hps_io_uart0_inst_TX"
       width="1" />
   <port
       name="hps_hps_io_i2c0_inst_SDA"
       direction="bidir"
       role="hps_io_i2c0_inst_SDA"
       width="1" />
   <port
       name="hps_hps_io_i2c0_inst_SCL"
       direction="bidir"
       role="hps_io_i2c0_inst_SCL"
       width="1" />
   <port
       name="hps_hps_io_i2c1_inst_SDA"
       direction="bidir"
       role="hps_io_i2c1_inst_SDA"
       width="1" />
   <port
       name="hps_hps_io_i2c1_inst_SCL"
       direction="bidir"
       role="hps_io_i2c1_inst_SCL"
       width="1" />
   <port
       name="hps_hps_io_gpio_inst_GPIO09"
       direction="bidir"
       role="hps_io_gpio_inst_GPIO09"
       width="1" />
   <port
       name="hps_hps_io_gpio_inst_GPIO35"
       direction="bidir"
       role="hps_io_gpio_inst_GPIO35"
       width="1" />
   <port
       name="hps_hps_io_gpio_inst_GPIO40"
       direction="bidir"
       role="hps_io_gpio_inst_GPIO40"
       width="1" />
   <port
       name="hps_hps_io_gpio_inst_GPIO48"
       direction="bidir"
       role="hps_io_gpio_inst_GPIO48"
       width="1" />
   <port
       name="hps_hps_io_gpio_inst_GPIO53"
       direction="bidir"
       role="hps_io_gpio_inst_GPIO53"
       width="1" />
   <port
       name="hps_hps_io_gpio_inst_GPIO54"
       direction="bidir"
       role="hps_io_gpio_inst_GPIO54"
       width="1" />
   <port
       name="hps_hps_io_gpio_inst_GPIO61"
       direction="bidir"
       role="hps_io_gpio_inst_GPIO61"
       width="1" />
  </interface>
  <interface name="hps_ddr3" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <port name="hps_ddr3_mem_a" direction="output" role="mem_a" width="15" />
   <port name="hps_ddr3_mem_ba" direction="output" role="mem_ba" width="3" />
   <port name="hps_ddr3_mem_ck" direction="output" role="mem_ck" width="1" />
   <port name="hps_ddr3_mem_ck_n" direction="output" role="mem_ck_n" width="1" />
   <port name="hps_ddr3_mem_cke" direction="output" role="mem_cke" width="1" />
   <port name="hps_ddr3_mem_cs_n" direction="output" role="mem_cs_n" width="1" />
   <port
       name="hps_ddr3_mem_ras_n"
       direction="output"
       role="mem_ras_n"
       width="1" />
   <port
       name="hps_ddr3_mem_cas_n"
       direction="output"
       role="mem_cas_n"
       width="1" />
   <port name="hps_ddr3_mem_we_n" direction="output" role="mem_we_n" width="1" />
   <port
       name="hps_ddr3_mem_reset_n"
       direction="output"
       role="mem_reset_n"
       width="1" />
   <port name="hps_ddr3_mem_dq" direction="bidir" role="mem_dq" width="32" />
   <port name="hps_ddr3_mem_dqs" direction="bidir" role="mem_dqs" width="4" />
   <port
       name="hps_ddr3_mem_dqs_n"
       direction="bidir"
       role="mem_dqs_n"
       width="4" />
   <port name="hps_ddr3_mem_odt" direction="output" role="mem_odt" width="1" />
   <port name="hps_ddr3_mem_dm" direction="output" role="mem_dm" width="4" />
   <port
       name="hps_ddr3_oct_rzqin"
       direction="input"
       role="oct_rzqin"
       width="1" />
  </interface>
  <interface name="reset" kind="reset" start="0">
   <property name="associatedClock" value="" />
   <property name="synchronousEdges" value="NONE" />
   <port name="reset_reset_n" direction="input" role="reset_n" width="1" />
  </interface>
 </perimeter>
 <entity
   path=""
   parameterizationKey="soc_system:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=5CSEMA5F31C6,AUTO_DEVICE_FAMILY=Cyclone V,AUTO_DEVICE_SPEEDGRADE=6,AUTO_GENERATION_ID=1747276302,AUTO_UNIQUE_ID=(altera_avalon_onchip_memory2:21.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=soc_system_RAM,blockType=M10K,copyInitFile=false,dataWidth=16,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=M10K,derived_init_file_name=soc_system_RAM.hex,derived_is_hardcopy=false,derived_set_addr_width=12,derived_set_addr_width2=12,derived_set_data_width=16,derived_set_data_width2=16,derived_singleClockOperation=false,deviceFamily=Cyclone V,deviceFeatures=COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 1 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1,dualPort=false,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=true,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=8192,readDuringWriteMode=DONT_CARE,resetrequest_enabled=true,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true)(admm_solver:1.0:ADDR_WIDTH=16,DATA_WIDTH=16,EXT_DATA_WIDTH=32,FRAC_BITS=8,HORIZON=30,INPUT_DIM=4,MAX_ITER=100,MEM_ADDR_WIDTH=9,STATE_DIM=12)(clock_source:21.1:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_hps:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0010001110001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0010101110000,AC_ROM_MR0_DLL_RESET_MIRR=0010011101000,AC_ROM_MR0_MIRR=0010001101001,AC_ROM_MR1=0000000000110,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000110,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0001000011000,AC_ROM_MR2_MIRR=0001000011000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=1,ADDR_ORDER=0,ADDR_RATE_RATIO=2,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=30,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=1,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=1,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=8,AFI_DQ_WIDTH=64,AFI_ODT_WIDTH=1,AFI_RATE_RATIO=1,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=4,ALLOCATED_RFIFO_PORT=None,None,None,None,None,None,ALLOCATED_WFIFO_PORT=None,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=27,AVL_ADDR_WIDTH_PORT_0=1,AVL_ADDR_WIDTH_PORT_1=1,AVL_ADDR_WIDTH_PORT_2=1,AVL_ADDR_WIDTH_PORT_3=1,AVL_ADDR_WIDTH_PORT_4=1,AVL_ADDR_WIDTH_PORT_5=1,AVL_BE_WIDTH=8,AVL_DATA_WIDTH=64,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=1,AVL_DATA_WIDTH_PORT_1=1,AVL_DATA_WIDTH_PORT_2=1,AVL_DATA_WIDTH_PORT_3=1,AVL_DATA_WIDTH_PORT_4=1,AVL_DATA_WIDTH_PORT_5=1,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=8,AVL_NUM_SYMBOLS_PORT_0=1,AVL_NUM_SYMBOLS_PORT_1=1,AVL_NUM_SYMBOLS_PORT_2=1,AVL_NUM_SYMBOLS_PORT_3=1,AVL_NUM_SYMBOLS_PORT_4=1,AVL_NUM_SYMBOLS_PORT_5=1,AVL_PORT=Port 0,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BONDING_OUT_ENABLED=false,BOOTFROMFPGA_Enable=false,BSEL=1,BSEL_EN=false,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=12,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=10,CAN0_Mode=N/A,CAN0_PinMuxing=Unused,CAN1_Mode=N/A,CAN1_PinMuxing=Unused,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=32,CFG_MEM_CLK_ENTRY_CYCLES=10,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSEL=0,CSEL_EN=false,CSR_ADDR_WIDTH=10,CSR_BE_WIDTH=1,CSR_DATA_WIDTH=8,CTI_Enable=false,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=true,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=2,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=1,CV_AVL_ADDR_WIDTH_PORT_1=1,CV_AVL_ADDR_WIDTH_PORT_2=1,CV_AVL_ADDR_WIDTH_PORT_3=1,CV_AVL_ADDR_WIDTH_PORT_4=1,CV_AVL_ADDR_WIDTH_PORT_5=1,CV_AVL_DATA_WIDTH_PORT_0=1,CV_AVL_DATA_WIDTH_PORT_1=1,CV_AVL_DATA_WIDTH_PORT_2=1,CV_AVL_DATA_WIDTH_PORT_3=1,CV_AVL_DATA_WIDTH_PORT_4=1,CV_AVL_DATA_WIDTH_PORT_5=1,CV_AVL_NUM_SYMBOLS_PORT_0=1,CV_AVL_NUM_SYMBOLS_PORT_1=1,CV_AVL_NUM_SYMBOLS_PORT_2=1,CV_AVL_NUM_SYMBOLS_PORT_3=1,CV_AVL_NUM_SYMBOLS_PORT_4=1,CV_AVL_NUM_SYMBOLS_PORT_5=1,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_32_BIT,CV_ENUM_PORT1_WIDTH=PORT_32_BIT,CV_ENUM_PORT2_WIDTH=PORT_32_BIT,CV_ENUM_PORT3_WIDTH=PORT_32_BIT,CV_ENUM_PORT4_WIDTH=PORT_32_BIT,CV_ENUM_PORT5_WIDTH=PORT_32_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_1,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_1,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_1,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_1,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_1,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_1,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_1,CV_ENUM_USER_PRIORITY_1=PRIORITY_1,CV_ENUM_USER_PRIORITY_2=PRIORITY_1,CV_ENUM_USER_PRIORITY_3=PRIORITY_1,CV_ENUM_USER_PRIORITY_4=PRIORITY_1,CV_ENUM_USER_PRIORITY_5=PRIORITY_1,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,Customer_Pin_Name_DERIVED=RGMII0_TX_CLK,RGMII0_TXD0,RGMII0_TXD1,RGMII0_TXD2,RGMII0_TXD3,RGMII0_RXD0,RGMII0_MDIO,RGMII0_MDC ,RGMII0_RX_CTL,RGMII0_TX_CTL,RGMII0_RX_CLK,RGMII0_RXD1,RGMII0_RXD2,RGMII0_RXD3,NAND_ALE,NAND_CE,NAND_CLE,NAND_RE,NAND_RB,NAND_DQ0,NAND_DQ1,NAND_DQ2,NAND_DQ3,NAND_DQ4,NAND_DQ5,NAND_DQ6,NAND_DQ7,NAND_WP,NAND_WE,QSPI_IO0,QSPI_IO1,QSPI_IO2,QSPI_IO3,QSPI_SS0,QSPI_CLK,QSPI_SS1,SDMMC_CMD,SDMMC_PWREN,SDMMC_D0,SDMMC_D1,SDMMC_D4,SDMMC_D5,SDMMC_D6,SDMMC_D7,HPS_GPIO44,SDMMC_CCLK_OUT,SDMMC_D2,SDMMC_D3,TRACE_CLK,TRACE_D0,TRACE_D1,TRACE_D2,TRACE_D3,TRACE_D4,TRACE_D5,TRACE_D6,TRACE_D7,SPIM0_CLK,SPIM0_MOSI,SPIM0_MISO,SPIM0_SS0,UART0_RX,UART0_TX,I2C0_SDA,I2C0_SCL,CAN0_RX,CAN0_TX,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DB_bfm_types=,DB_iface_ports=can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}},DB_periph_ifaces=USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}},DB_port_pins=i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd},DEBUGAPB_Enable=false,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=25,DELAY_PER_DQS_EN_DCHAIN_TAP=25,DELAY_PER_OPA_TAP=312,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=Cyclone V,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=7,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DMA_Enable=No,No,No,No,No,No,No,No,DMA_PeriphId_DERIVED=0,1,2,3,4,5,6,7,DQS_DELAY_CHAIN_PHASE_SETTING=0,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=31,DQS_IN_DELAY_MAX=31,DQS_PHASE_SHIFT=0,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=true,DWIDTH_RATIO=2,EARLY_ADDR_CMD_CLK_TRANSFER=true,ED_EXPORT_SEQ_DEBUG=false,EMAC0_Mode=N/A,EMAC0_PTP=false,EMAC0_PinMuxing=Unused,EMAC1_Mode=RGMII,EMAC1_PTP=false,EMAC1_PinMuxing=HPS I/O Set 0,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=true,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=true,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=SELF_RFSH_EXIT_CYCLES_512,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_10,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_ROW_BANK_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=ENABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_0,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_10,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_15,ENUM_MEM_IF_SPEEDBIN=DDR3_1600_8_8_8,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_11,ENUM_MEM_IF_TCWL=TCWL_8,ENUM_MEM_IF_TFAW=TFAW_12,ENUM_MEM_IF_TMRD=TMRD_4,ENUM_MEM_IF_TRAS=TRAS_14,ENUM_MEM_IF_TRC=TRC_20,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_3,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_32_BIT,ENUM_PORT1_WIDTH=PORT_32_BIT,ENUM_PORT2_WIDTH=PORT_32_BIT,ENUM_PORT3_WIDTH=PORT_32_BIT,ENUM_PORT4_WIDTH=PORT_32_BIT,ENUM_PORT5_WIDTH=PORT_32_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_1,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_1,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_1,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_1,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_1,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_1,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_1,ENUM_USER_PRIORITY_1=PRIORITY_1,ENUM_USER_PRIORITY_2=PRIORITY_1,ENUM_USER_PRIORITY_3=PRIORITY_1,ENUM_USER_PRIORITY_4=PRIORITY_1,ENUM_USER_PRIORITY_5=PRIORITY_1,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=WRITE_CHIP0_ODT0_CHIP1,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,F2H_AXI_CLOCK_FREQ=50000000,F2H_SDRAM0_CLOCK_FREQ=100,F2H_SDRAM1_CLOCK_FREQ=100,F2H_SDRAM2_CLOCK_FREQ=100,F2H_SDRAM3_CLOCK_FREQ=100,F2H_SDRAM4_CLOCK_FREQ=100,F2H_SDRAM5_CLOCK_FREQ=100,F2SCLK_COLDRST_Enable=false,F2SCLK_DBGRST_Enable=false,F2SCLK_PERIPHCLK_Enable=false,F2SCLK_PERIPHCLK_FREQ=0,F2SCLK_PERIPHCLK_FREQ_MHZ=0.0,F2SCLK_SDRAMCLK_Enable=false,F2SCLK_SDRAMCLK_FREQ=0,F2SCLK_SDRAMCLK_FREQ_MHZ=0.0,F2SCLK_WARMRST_Enable=false,F2SDRAM_CMD_PORT_USED=0x0,F2SDRAM_Name_DERIVED=,F2SDRAM_RD_PORT_USED=0x0,F2SDRAM_RST_PORT_USED=0x0,F2SDRAM_Type=,F2SDRAM_WR_PORT_USED=0x0,F2SDRAM_Width=,F2SDRAM_Width_Last_Size=0,F2SINTERRUPT_Enable=false,F2S_Width=2,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK=125,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK=2.5,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK=125,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK=2.5,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT=100,GENERIC_PLL=true,GPIO_Conflict_DERIVED=,USB1.D0,USB1.D1,USB1.D2,USB1.D3,USB1.D4,USB1.D5,USB1.D6,USB1.D7,,USB1.CLK,USB1.STP,USB1.DIR,USB1.NXT,EMAC1.TX_CLK,EMAC1.TXD0,EMAC1.TXD1,EMAC1.TXD2,EMAC1.TXD3,EMAC1.RXD0,EMAC1.MDIO,EMAC1.MDC,EMAC1.RX_CTL,EMAC1.TX_CTL,EMAC1.RX_CLK,EMAC1.RXD1,EMAC1.RXD2,EMAC1.RXD3,,,,,,,,,SDIO.CMD,,SDIO.D0,SDIO.D1,,,,,,SDIO.CLK,SDIO.D2,SDIO.D3,,UART0.RX,UART0.TX,I2C1.SDA,I2C1.SCL,,,I2C0.SDA,I2C0.SCL,,,,,,,SPIM1.CLK,SPIM1.MOSI,SPIM1.MISO,SPIM1.SS0,GPIO_Enable=No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,Yes,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,GPIO_Name_DERIVED=GPIO00,GPIO01,GPIO02,GPIO03,GPIO04,GPIO05,GPIO06,GPIO07,GPIO08,GPIO09,GPIO10,GPIO11,GPIO12,GPIO13,GPIO14,GPIO15,GPIO16,GPIO17,GPIO18,GPIO19,GPIO20,GPIO21,GPIO22,GPIO23,GPIO24,GPIO25,GPIO26,GPIO27,GPIO28,GPIO29,GPIO30,GPIO31,GPIO32,GPIO33,GPIO34,GPIO35,GPIO36,GPIO37,GPIO38,GPIO39,GPIO40,GPIO41,GPIO42,GPIO43,GPIO44,GPIO45,GPIO46,GPIO47,GPIO48,GPIO49,GPIO50,GPIO51,GPIO52,GPIO53,GPIO54,GPIO55,GPIO56,GPIO57,GPIO58,GPIO59,GPIO60,GPIO61,GPIO62,GPIO63,GPIO64,GPIO65,GPIO66,GPIO_Pin_Used_DERIVED=true,GP_Enable=false,H2F_AXI_CLOCK_FREQ=50000000,H2F_CTI_CLOCK_FREQ=100,H2F_DEBUG_APB_CLOCK_FREQ=100,H2F_LW_AXI_CLOCK_FREQ=50000000,H2F_TPIU_CLOCK_IN_FREQ=100,HARD_EMIF=true,HARD_PHY=true,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HLGPI_Enable=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,I2C0_Mode=I2C,I2C0_PinMuxing=HPS I/O Set 0,I2C1_Mode=I2C,I2C1_PinMuxing=HPS I/O Set 0,I2C2_Mode=N/A,I2C2_PinMuxing=Unused,I2C3_Mode=N/A,I2C3_PinMuxing=Unused,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=2,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=2,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=2,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=3,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=3,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=3,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=104,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=4,IO_DQS_OUT_RESERVE=4,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=31,IO_OUT1_DELAY_MAX=31,IO_OUT2_DELAY_MAX=0,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,JAVA_CAN0_DATA=CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}},JAVA_CAN1_DATA=CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}},JAVA_CONFLICT_PIN=No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,JAVA_EMAC0_DATA=EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}},JAVA_EMAC1_DATA=EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}},JAVA_GUI_PIN_LIST=EMACIO0,EMACIO1,EMACIO2,EMACIO3,EMACIO4,EMACIO5,EMACIO6,EMACIO7,EMACIO8,EMACIO9,EMACIO10,EMACIO11,EMACIO12,EMACIO13,MIXED1IO0,MIXED1IO1,MIXED1IO2,MIXED1IO3,MIXED1IO4,MIXED1IO5,MIXED1IO6,MIXED1IO7,MIXED1IO8,MIXED1IO9,MIXED1IO10,MIXED1IO11,MIXED1IO12,MIXED1IO13,MIXED1IO14,MIXED1IO15,MIXED1IO16,MIXED1IO17,MIXED1IO18,MIXED1IO19,MIXED1IO20,MIXED1IO21,FLASHIO0,FLASHIO1,FLASHIO2,FLASHIO3,FLASHIO4,FLASHIO5,FLASHIO6,FLASHIO7,FLASHIO8,FLASHIO9,FLASHIO10,FLASHIO11,GENERALIO0,GENERALIO1,GENERALIO2,GENERALIO3,GENERALIO4,GENERALIO5,GENERALIO6,GENERALIO7,GENERALIO8,GENERALIO9,GENERALIO10,GENERALIO11,GENERALIO12,GENERALIO13,GENERALIO14,GENERALIO15,GENERALIO16,GENERALIO17,GENERALIO18,JAVA_I2C0_DATA=I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}},JAVA_I2C1_DATA=I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}},JAVA_I2C2_DATA=I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}},JAVA_I2C3_DATA=I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}},JAVA_NAND_DATA=NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}},JAVA_QSPI_DATA=QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}},JAVA_SDIO_DATA=SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}},JAVA_SPIM0_DATA=SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}},JAVA_SPIM1_DATA=SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}},JAVA_SPIS0_DATA=SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}},JAVA_SPIS1_DATA=SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}},JAVA_TRACE_DATA=TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}},JAVA_UART0_DATA=UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}},JAVA_UART1_DATA=UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}},JAVA_USB0_DATA=USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}},JAVA_USB1_DATA=USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}},LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOANIO_Enable=No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,LOANIO_Name_DERIVED=LOANIO00,LOANIO01,LOANIO02,LOANIO03,LOANIO04,LOANIO05,LOANIO06,LOANIO07,LOANIO08,LOANIO09,LOANIO10,LOANIO11,LOANIO12,LOANIO13,LOANIO14,LOANIO15,LOANIO16,LOANIO17,LOANIO18,LOANIO19,LOANIO20,LOANIO21,LOANIO22,LOANIO23,LOANIO24,LOANIO25,LOANIO26,LOANIO27,LOANIO28,LOANIO29,LOANIO30,LOANIO31,LOANIO32,LOANIO33,LOANIO34,LOANIO35,LOANIO36,LOANIO37,LOANIO38,LOANIO39,LOANIO40,LOANIO41,LOANIO42,LOANIO43,LOANIO44,LOANIO45,LOANIO46,LOANIO47,LOANIO48,LOANIO49,LOANIO50,LOANIO51,LOANIO52,LOANIO53,LOANIO54,LOANIO55,LOANIO56,LOANIO57,LOANIO58,LOANIO59,LOANIO60,LOANIO61,LOANIO62,LOANIO63,LOANIO64,LOANIO65,LOANIO66,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,LWH2F_Enable=true,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=5,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=400.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=2.5,MEM_CLK_PS=2500.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=450,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=15,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=4,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=4,MEM_IF_DQ_WIDTH=32,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=4,MEM_IF_ROW_ADDR_WIDTH=15,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=4,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=false,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=1,MEM_TFAW=12,MEM_TFAW_NS=30.0,MEM_TINIT_CK=200000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=14,MEM_TRAS_NS=35.0,MEM_TRC=20,MEM_TRCD=6,MEM_TRCD_NS=13.75,MEM_TREFI=3120,MEM_TREFI_US=7.8,MEM_TRFC=104,MEM_TRFC_NS=260.0,MEM_TRP=6,MEM_TRP_NS=13.75,MEM_TRRD=4,MEM_TRRD_NS=7.7,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=6,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=DDR3,MEM_T_RL=11,MEM_T_WL=8,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=8,MPU_EVENTS_Enable=false,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=7,MR0_DLL=1,MR0_PD=0,MR0_WR=2,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=3,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NAND_Mode=N/A,NAND_PinMuxing=Unused,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=16,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=CYCLONEV,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=CYCLONEV,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=true,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=211,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=2,PLL_ADDR_CMD_CLK_DIV_CACHE=2,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=400.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=400.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=2500 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=2500 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=400.0 MHz,PLL_ADDR_CMD_CLK_MULT=32,PLL_ADDR_CMD_CLK_MULT_CACHE=32,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=270.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=270.0,PLL_ADDR_CMD_CLK_PHASE_PS=1875,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=1875,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=1875,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=1875 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=1875 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=1875 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=400.0,PLL_AFI_CLK_FREQ_CACHE=400.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=2500 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=2500 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=400.0 MHz,PLL_AFI_CLK_MULT=32,PLL_AFI_CLK_MULT_CACHE=32,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=2,PLL_AFI_HALF_CLK_DIV_CACHE=2,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=400.0,PLL_AFI_HALF_CLK_FREQ_CACHE=400.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=5000 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=5000 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=400.0 MHz,PLL_AFI_HALF_CLK_MULT=32,PLL_AFI_HALF_CLK_MULT_CACHE=32,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=0 ps,PLL_AFI_PHY_CLK_DIV=1000000,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=400.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=2500 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=18000000,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=22.2222222222,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=45000 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=2,PLL_MEM_CLK_DIV_CACHE=2,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=400.0,PLL_MEM_CLK_FREQ_CACHE=400.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=2500 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=2500 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=400.0 MHz,PLL_MEM_CLK_MULT=32,PLL_MEM_CLK_MULT_CACHE=32,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=6000000,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=66.6666666667,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=15000 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=10.0,PLL_NIOS_CLK_PHASE_DEG_SIM=10.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=2,PLL_WRITE_CLK_DIV_CACHE=2,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=400.0,PLL_WRITE_CLK_FREQ_CACHE=400.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=2500 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=400.0 MHz,PLL_WRITE_CLK_MULT=32,PLL_WRITE_CLK_MULT_CACHE=32,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=1875,PLL_WRITE_CLK_PHASE_PS_CACHE=1875,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=1875,PLL_WRITE_CLK_PHASE_PS_SIM_STR=1875 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=1875 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=1875 ps,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=1,PRIORITY_PORT_1=1,PRIORITY_PORT_2=1,PRIORITY_PORT_3=1,PRIORITY_PORT_4=1,PRIORITY_PORT_5=1,QSPI_Mode=N/A,QSPI_PinMuxing=Unused,QVLD_EXTRA_FLOP_STAGES=5,QVLD_WR_ADDRESS_OFFSET=5,RATE=Full,RATE_CACHE=Full,RDBUFFER_ADDR_WIDTH=8,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=25.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=25.0 MHz,REF_CLK_NS=40.0,REF_CLK_PS=40000.0,REGISTER_C2P=false,S2FCLK_COLDRST_Enable=false,S2FCLK_PENDINGRST_Enable=false,S2FCLK_USER0CLK_Enable=false,S2FCLK_USER0CLK_FREQ=97.368421,S2FCLK_USER0CLK_FREQ_HZ=97368421,S2FCLK_USER1CLK_Enable=true,S2FCLK_USER1CLK_FREQ=100.0,S2FCLK_USER1CLK_FREQ_HZ=100000000,S2FCLK_USER2CLK=5,S2FCLK_USER2CLK_Enable=false,S2FCLK_USER2CLK_FREQ=100.0,S2FCLK_USER2CLK_FREQ_HZ=100000000,S2FINTERRUPT_CAN_Enable=false,S2FINTERRUPT_CLOCKPERIPHERAL_Enable=false,S2FINTERRUPT_CTI_Enable=false,S2FINTERRUPT_DMA_Enable=false,S2FINTERRUPT_EMAC_Enable=false,S2FINTERRUPT_FPGAMANAGER_Enable=false,S2FINTERRUPT_GPIO_Enable=false,S2FINTERRUPT_I2CEMAC_Enable=false,S2FINTERRUPT_I2CPERIPHERAL_Enable=false,S2FINTERRUPT_L4TIMER_Enable=false,S2FINTERRUPT_NAND_Enable=false,S2FINTERRUPT_OSCTIMER_Enable=false,S2FINTERRUPT_QSPI_Enable=false,S2FINTERRUPT_SDMMC_Enable=false,S2FINTERRUPT_SPIMASTER_Enable=false,S2FINTERRUPT_SPISLAVE_Enable=false,S2FINTERRUPT_UART_Enable=false,S2FINTERRUPT_USB_Enable=false,S2FINTERRUPT_WATCHDOG_Enable=false,S2F_Width=2,SCC_DATA_WIDTH=1,SDIO_Mode=4-bit Data,SDIO_PinMuxing=HPS I/O Set 0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=NIOS,SEQ_BURST_COUNT_WIDTH=2,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=7,SPIM0_Mode=N/A,SPIM0_PinMuxing=Unused,SPIM1_Mode=Single Slave Select,SPIM1_PinMuxing=HPS I/O Set 0,SPIS0_Mode=N/A,SPIS0_PinMuxing=Unused,SPIS1_Mode=N/A,SPIS1_PinMuxing=Unused,STARVE_LIMIT=10,STM_Enable=false,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=400.0,TB_MEM_IF_DQ_WIDTH=32,TB_MEM_IF_READ_DQS_WIDTH=4,TB_PLL_DLL_MASTER=true,TB_RATE=FULL,TEST_Enable=false,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.09,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.165,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.18,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.24,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.33,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TPIUFPGA_Enable=false,TPIUFPGA_alt=false,TRACE_Mode=N/A,TRACE_PinMuxing=Unused,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,UART0_Mode=No Flow Control,UART0_PinMuxing=HPS I/O Set 0,UART1_Mode=N/A,UART1_PinMuxing=Unused,USB0_Mode=N/A,USB0_PinMuxing=Unused,USB1_Mode=SDR,USB1_PinMuxing=HPS I/O Set 0,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=true,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=true,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=true,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,can0_clk_div=1,can0_clk_div_auto=4,can0_clk_hz=12500000,can0_clk_mhz=12.5,can1_clk_div=1,can1_clk_div_auto=4,can1_clk_hz=12500000,can1_clk_mhz=12.5,cfg_clk_hz=97368421,cfg_clk_mhz=97.368421,cfg_h2f_user0_clk_hz=97368421,cfg_h2f_user0_clk_mhz=97.368421,configure_advanced_parameters=false,customize_device_pll_info=false,dbctrl_stayosc1=true,dbg_at_clk_div=0,dbg_at_clk_hz=25000000,dbg_at_clk_mhz=25.0,dbg_base_clk_hz=25000000,dbg_base_clk_mhz=25.0,dbg_clk_div=1,dbg_clk_hz=12500000,dbg_clk_mhz=12.5,dbg_timer_clk_hz=25000000,dbg_timer_clk_mhz=25.0,dbg_trace_clk_div=0,dbg_trace_clk_hz=25000000,dbg_trace_clk_mhz=25.0,default_mpu_clk_hz=925000000,default_mpu_clk_mhz=925.0,desired_can0_clk_hz=100000000,desired_can0_clk_mhz=100.0,desired_can1_clk_hz=100000000,desired_can1_clk_mhz=100.0,desired_cfg_clk_hz=97368421,desired_cfg_clk_mhz=97.368421,desired_emac0_clk_hz=250000000,desired_emac0_clk_mhz=250.0,desired_emac1_clk_hz=250000000,desired_emac1_clk_mhz=250.0,desired_gpio_db_clk_hz=32000,desired_l4_mp_clk_hz=100000000,desired_l4_mp_clk_mhz=100.0,desired_l4_sp_clk_hz=100000000,desired_l4_sp_clk_mhz=100.0,desired_mpu_clk_hz=800000000,desired_mpu_clk_mhz=800.0,desired_nand_clk_hz=12500000,desired_nand_clk_mhz=12.5,desired_qspi_clk_hz=400000000,desired_qspi_clk_mhz=400.0,desired_sdmmc_clk_hz=200000000,desired_sdmmc_clk_mhz=200.0,desired_spi_m_clk_hz=200000000,desired_spi_m_clk_mhz=200.0,desired_usb_mp_clk_hz=200000000,desired_usb_mp_clk_mhz=200.0,device_name=5CSEMA5F31C6,device_pll_info_auto={320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000},device_pll_info_manual={320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000},emac0_clk_hz=1953125,emac0_clk_mhz=1.953125,emac1_clk_hz=250000000,emac1_clk_mhz=250.0,eosc1_clk_hz=25000000,eosc1_clk_mhz=25.0,eosc2_clk_hz=25000000,eosc2_clk_mhz=25.0,gpio_db_clk_div=6249,gpio_db_clk_div_auto=6249,gpio_db_clk_hz=32000,h2f_user0_clk_hz=97368421,h2f_user0_clk_mhz=97.368421,h2f_user1_clk_hz=100000000,h2f_user1_clk_mhz=100.0,hps_device_family=Cyclone V,l3_mp_clk_div=1,l3_mp_clk_hz=185000000,l3_mp_clk_mhz=185.0,l3_sp_clk_div=1,l3_sp_clk_hz=92500000,l3_sp_clk_mhz=92.5,l4_mp_clk_div=1,l4_mp_clk_div_auto=1,l4_mp_clk_hz=100000000,l4_mp_clk_mhz=100.0,l4_mp_clk_source=1,l4_sp_clk_div=1,l4_sp_clk_div_auto=1,l4_sp_clk_hz=100000000,l4_sp_clk_mhz=100.0,l4_sp_clk_source=1,main_clk_hz=370000000,main_clk_mhz=370.0,main_nand_sdmmc_clk_hz=3613281,main_nand_sdmmc_clk_mhz=3.613281,main_pll_c0_internal=1,main_pll_c0_internal_auto=1,main_pll_c1_internal=4,main_pll_c1_internal_auto=4,main_pll_c2_internal=4,main_pll_c2_internal_auto=4,main_pll_c3=3,main_pll_c3_auto=511,main_pll_c4=3,main_pll_c4_auto=511,main_pll_c5=15,main_pll_c5_auto=18,main_pll_m=63,main_pll_m_auto=73,main_pll_n=0,main_pll_n_auto=0,main_pll_vco_auto_hz=1850000000,main_pll_vco_auto_mhz=1850.0,main_pll_vco_hz=1600000000,main_pll_vco_mhz=1600.0,main_qspi_clk_hz=3613281,main_qspi_clk_mhz=3.613281,mpu_base_clk_hz=925000000,mpu_base_clk_mhz=925.0,mpu_clk_hz=925000000,mpu_clk_mhz=925.0,mpu_l2_ram_clk_hz=462500000,mpu_l2_ram_clk_mhz=462.5,mpu_periph_clk_hz=231250000,mpu_periph_clk_mhz=231.25,nand_clk_hz=50000000,nand_clk_mhz=50.0,nand_clk_source=2,nand_x_clk_hz=200000000,nand_x_clk_mhz=200.0,periph_base_clk_hz=200000000,periph_base_clk_mhz=200.0,periph_nand_sdmmc_clk_hz=200000000,periph_nand_sdmmc_clk_mhz=200.0,periph_pll_c0=3,periph_pll_c0_auto=511,periph_pll_c1=3,periph_pll_c1_auto=3,periph_pll_c2=1,periph_pll_c2_auto=511,periph_pll_c3=19,periph_pll_c3_auto=4,periph_pll_c4=4,periph_pll_c4_auto=4,periph_pll_c5=9,periph_pll_c5_auto=9,periph_pll_m=79,periph_pll_m_auto=39,periph_pll_n=1,periph_pll_n_auto=0,periph_pll_source=0,periph_pll_vco_auto_hz=1000000000,periph_pll_vco_auto_mhz=1000.0,periph_pll_vco_hz=1000000000,periph_pll_vco_mhz=1000.0,periph_qspi_clk_hz=1953125,periph_qspi_clk_mhz=1.953125,pin_muxing={USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS},pin_muxing_check=Cyclone V+5CSEMA5F31C6,qspi_clk_hz=3613281,qspi_clk_mhz=3.613281,qspi_clk_source=1,quartus_ini_hps_emif_pll=false,quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces=false,quartus_ini_hps_ip_enable_bsel_csel=false,quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface=false,quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces=false,quartus_ini_hps_ip_enable_test_interface=false,quartus_ini_hps_ip_f2sdram_bonding_out=false,quartus_ini_hps_ip_fast_f2sdram_sim_model=false,quartus_ini_hps_ip_suppress_sdram_synth=false,sdmmc_clk_hz=200000000,sdmmc_clk_mhz=200.0,sdmmc_clk_source=2,show_advanced_parameters=false,show_debug_info_as_warning_msg=false,show_warning_as_error_msg=false,spi_m_clk_div=0,spi_m_clk_div_auto=0,spi_m_clk_hz=200000000,spi_m_clk_mhz=200.0,test_iface_definition=DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output,usb_mp_clk_div=0,usb_mp_clk_div_auto=0,usb_mp_clk_hz=200000000,usb_mp_clk_mhz=200.0,use_default_mpu_clk=true(altera_interface_generator:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=,AC_ROM_MR0_DLL_RESET_MIRR=,AC_ROM_MR0_MIRR=,AC_ROM_MR1=,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=,AC_ROM_MR2_MIRR=,AC_ROM_MR3=,AC_ROM_MR3_MIRR=,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=0,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=0,AFI_BANKADDR_WIDTH=0,AFI_CLK_EN_WIDTH=0,AFI_CLK_PAIR_COUNT=0,AFI_CONTROL_WIDTH=0,AFI_CS_WIDTH=0,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=0,AFI_DQ_WIDTH=0,AFI_ODT_WIDTH=0,AFI_RATE_RATIO=0,AFI_RLAT_WIDTH=0,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=0,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=0,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=0,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=0,AVL_DATA_WIDTH=0,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=2,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=0,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=-1,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=-1,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=0,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=0,CFG_MEM_CLK_ENTRY_CYCLES=0,CFG_PDN_EXIT_CYCLES=0,CFG_PORT_WIDTH_READ_ODT_CHIP=0,CFG_PORT_WIDTH_WRITE_ODT_CHIP=0,CFG_POWER_SAVING_EXIT_CYCLES=0,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=0,CFG_STARVE_LIMIT=0,CFG_TCCD=0,CFG_TCCD_NS=2.5,CFG_TYPE=0,CFG_WRITE_ODT_CHIP=0,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=0,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=0,CTL_ECC_MULTIPLES_40_72=0,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=0,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=0,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=0,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=-1,DELAY_PER_DQS_EN_DCHAIN_TAP=-1,DELAY_PER_OPA_TAP=-1,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=false,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=-1,DQS_IN_DELAY_MAX=-1,DQS_PHASE_SHIFT=9000,DQ_DDR=0,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=true,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=true,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=0,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=-1,IO_OUT1_DELAY_MAX=-1,IO_OUT2_DELAY_MAX=-1,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=6,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=2.5,MEM_CLK_MAX_PS=2500.0,MEM_CLK_NS=0.0,MEM_CLK_PS=0.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=0,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=0,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=0,MEM_IF_ADDR_WIDTH_MIN=10,MEM_IF_BANKADDR_WIDTH=0,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=-1,MEM_IF_CK_WIDTH=0,MEM_IF_CLK_EN_WIDTH=0,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=0,MEM_IF_CONTROL_WIDTH=0,MEM_IF_CS_PER_DIMM=0,MEM_IF_CS_PER_RANK=0,MEM_IF_CS_WIDTH=0,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=0,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=0,MEM_IF_DQ_WIDTH=0,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=0,MEM_IF_ODT_WIDTH=0,MEM_IF_RD_TO_WR_TURNAROUND_OCT=0,MEM_IF_READ_DQS_WIDTH=0,MEM_IF_ROW_ADDR_WIDTH=0,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=0,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=2,MEM_TFAW=0,MEM_TFAW_NS=30.0,MEM_TINIT_CK=499,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=0,MEM_TRAS_NS=35.0,MEM_TRC=0,MEM_TRCD=0,MEM_TRCD_NS=13.75,MEM_TREFI=0,MEM_TREFI_US=7.8,MEM_TRFC=0,MEM_TRFC_NS=260.0,MEM_TRP=0,MEM_TRP_NS=13.75,MEM_TRRD=0,MEM_TRRD_NS=7.7,MEM_TRTP=0,MEM_TRTP_NS=7.5,MEM_TWR=0,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=,MEM_T_RL=0,MEM_T_WL=0,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=6,MR0_BL=2,MR0_BT=0,MR0_CAS_LATENCY=3,MR0_DLL=1,MR0_PD=0,MR0_WR=4,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=1,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=false,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=0,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=0,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=false,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=0,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=0,PLL_ADDR_CMD_CLK_DIV_CACHE=0,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=0.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=0.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=,PLL_ADDR_CMD_CLK_MULT=0,PLL_ADDR_CMD_CLK_MULT_CACHE=0,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=,PLL_AFI_CLK_DIV=0,PLL_AFI_CLK_DIV_CACHE=0,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=0.0,PLL_AFI_CLK_FREQ_CACHE=0.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=,PLL_AFI_CLK_MULT=0,PLL_AFI_CLK_MULT_CACHE=0,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=,PLL_AFI_HALF_CLK_DIV=0,PLL_AFI_HALF_CLK_DIV_CACHE=0,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=0.0,PLL_AFI_HALF_CLK_FREQ_CACHE=0.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=,PLL_AFI_HALF_CLK_MULT=0,PLL_AFI_HALF_CLK_MULT_CACHE=0,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=false,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=false,PLL_MEM_CLK_DIV=0,PLL_MEM_CLK_DIV_CACHE=0,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=0.0,PLL_MEM_CLK_FREQ_CACHE=0.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=,PLL_MEM_CLK_MULT=0,PLL_MEM_CLK_MULT_CACHE=0,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=0,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=0,PLL_WRITE_CLK_DIV_CACHE=0,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=0.0,PLL_WRITE_CLK_FREQ_CACHE=0.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=,PLL_WRITE_CLK_MULT=0,PLL_WRITE_CLK_MULT_CACHE=0,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=0.0,PLL_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_WRITE_CLK_PHASE_PS=0,PLL_WRITE_CLK_PHASE_PS_CACHE=0,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=0,PLL_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=0,RATE=Full,RATE_CACHE=Unknown,RDBUFFER_ADDR_WIDTH=6,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=false,REF_CLK_FREQ_MAX_CACHE=0.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=0.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=,REF_CLK_NS=0.0,REF_CLK_PS=0.0,REGISTER_C2P=false,SCC_DATA_WIDTH=0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=0,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=0.0,TB_MEM_IF_DQ_WIDTH=0,TB_MEM_IF_READ_DQS_WIDTH=0,TB_PLL_DLL_MASTER=true,TB_RATE=,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.05,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.01,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=-0.01,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.0,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.0,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.0,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.0,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=0,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=false,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,device=5CSEMA5F31C6,hps_parameter_map=,ignoreSimulation=false,interfaceDefinition=instances {boot_from_fpga {entity_name cyclonev_hps_interface_boot_from_fpga location HPSINTERFACEBOOTFROMFPGA_X52_Y74_N111 signal_widths {boot_from_fpga_ready 1 boot_from_fpga_on_failure 1 bsel_en 1 csel_en 1 csel 2 bsel 3} signal_terminations {boot_from_fpga_ready {0:0 0} boot_from_fpga_on_failure {0:0 0} bsel_en {0:0 0} csel_en {0:0 0} csel {1:0 1} bsel {2:0 1}} parameters {} signal_default_terminations {boot_from_fpga_ready 0 boot_from_fpga_on_failure 0 bsel_en 0 csel_en 0 csel 0 bsel 0}} tpiu {entity_name cyclonev_hps_interface_tpiu_trace location HPSINTERFACETPIUTRACE_X52_Y39_N111 signal_widths {traceclk_ctl 1} parameters {} signal_terminations {traceclk_ctl {0:0 1}} signal_default_terminations {traceclk_ctl 1}} clocks_resets {entity_name cyclonev_hps_interface_clocks_resets location HPSINTERFACECLOCKSRESETS_X52_Y78_N111 signal_widths {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 1 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 1} signal_terminations {f2h_warm_rst_req_n {0:0 1} f2h_pending_rst_ack {0:0 1} f2h_sdram_ref_clk {} f2h_dbg_rst_req_n {0:0 1} f2h_cold_rst_req_n {0:0 1} f2h_periph_ref_clk {}} parameters {} signal_default_terminations {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 0 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 0}} @orderednames {clocks_resets debug_apb tpiu boot_from_fpga} debug_apb {entity_name cyclonev_hps_interface_dbg_apb location HPSINTERFACEDBGAPB_X52_Y80_N111 signal_widths {DBG_APB_DISABLE 1 P_CLK_EN 1} signal_terminations {DBG_APB_DISABLE {0:0 0} P_CLK_EN {0:0 0}} parameters {} signal_default_terminations {DBG_APB_DISABLE 0 P_CLK_EN 0}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{create_clock -period 10.0 [get_pins -compatibility_mode *|fpga_interfaces|clocks_resets|h2f_user1_clk]}} properties {} bfm_types {} intermediate_wire_count 0 wires_to_fragments {} interfaces {@orderednames {h2f_reset h2f_user1_clock} h2f_reset {properties {associatedResetSinks none synchronousEdges none} type reset direction Output signals {@orderednames h2f_rst_n h2f_rst_n {fragments {} properties {} internal_name h2f_rst_n width 1 instance_name clocks_resets direction Output role reset_n}}} h2f_user1_clock {properties {clockRate 100000000.0 clockRateKnown true} type clock direction Output signals {@orderednames h2f_user1_clk h2f_user1_clk {fragments {} properties {} internal_name h2f_user1_clk width 1 instance_name clocks_resets direction Output role clk}}}} raw_assign_sim_style {},qipEntries=)(altera_hps_io:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=,AC_ROM_MR0_DLL_RESET_MIRR=,AC_ROM_MR0_MIRR=,AC_ROM_MR1=,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=,AC_ROM_MR2_MIRR=,AC_ROM_MR3=,AC_ROM_MR3_MIRR=,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=0,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=0,AFI_BANKADDR_WIDTH=0,AFI_CLK_EN_WIDTH=0,AFI_CLK_PAIR_COUNT=0,AFI_CONTROL_WIDTH=0,AFI_CS_WIDTH=0,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=0,AFI_DQ_WIDTH=0,AFI_ODT_WIDTH=0,AFI_RATE_RATIO=0,AFI_RLAT_WIDTH=0,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=0,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=0,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=5CSEMA5F31C6,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=0,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=0,AVL_DATA_WIDTH=0,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=2,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=0,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=-1,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=-1,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=0,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=0,CFG_MEM_CLK_ENTRY_CYCLES=0,CFG_PDN_EXIT_CYCLES=0,CFG_PORT_WIDTH_READ_ODT_CHIP=0,CFG_PORT_WIDTH_WRITE_ODT_CHIP=0,CFG_POWER_SAVING_EXIT_CYCLES=0,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=0,CFG_STARVE_LIMIT=0,CFG_TCCD=0,CFG_TCCD_NS=2.5,CFG_TYPE=0,CFG_WRITE_ODT_CHIP=0,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=0,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=0,CTL_ECC_MULTIPLES_40_72=0,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=0,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=0,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=0,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=-1,DELAY_PER_DQS_EN_DCHAIN_TAP=-1,DELAY_PER_OPA_TAP=-1,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=false,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=-1,DQS_IN_DELAY_MAX=-1,DQS_PHASE_SHIFT=9000,DQ_DDR=0,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=true,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=0,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=-1,IO_OUT1_DELAY_MAX=-1,IO_OUT2_DELAY_MAX=-1,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=6,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=2.5,MEM_CLK_MAX_PS=2500.0,MEM_CLK_NS=0.0,MEM_CLK_PS=0.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=0,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=0,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=0,MEM_IF_ADDR_WIDTH_MIN=10,MEM_IF_BANKADDR_WIDTH=0,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=-1,MEM_IF_CK_WIDTH=0,MEM_IF_CLK_EN_WIDTH=0,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=0,MEM_IF_CONTROL_WIDTH=0,MEM_IF_CS_PER_DIMM=0,MEM_IF_CS_PER_RANK=0,MEM_IF_CS_WIDTH=0,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=0,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=0,MEM_IF_DQ_WIDTH=0,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=0,MEM_IF_ODT_WIDTH=0,MEM_IF_RD_TO_WR_TURNAROUND_OCT=0,MEM_IF_READ_DQS_WIDTH=0,MEM_IF_ROW_ADDR_WIDTH=0,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=0,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=2,MEM_TFAW=0,MEM_TFAW_NS=30.0,MEM_TINIT_CK=499,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=0,MEM_TRAS_NS=35.0,MEM_TRC=0,MEM_TRCD=0,MEM_TRCD_NS=13.75,MEM_TREFI=0,MEM_TREFI_US=7.8,MEM_TRFC=0,MEM_TRFC_NS=260.0,MEM_TRP=0,MEM_TRP_NS=13.75,MEM_TRRD=0,MEM_TRRD_NS=7.7,MEM_TRTP=0,MEM_TRTP_NS=7.5,MEM_TWR=0,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=,MEM_T_RL=0,MEM_T_WL=0,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=6,MR0_BL=2,MR0_BT=0,MR0_CAS_LATENCY=3,MR0_DLL=1,MR0_PD=0,MR0_WR=4,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=1,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=false,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=0,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=0,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=false,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=0,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=0,PLL_ADDR_CMD_CLK_DIV_CACHE=0,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=0.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=0.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=,PLL_ADDR_CMD_CLK_MULT=0,PLL_ADDR_CMD_CLK_MULT_CACHE=0,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=,PLL_AFI_CLK_DIV=0,PLL_AFI_CLK_DIV_CACHE=0,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=0.0,PLL_AFI_CLK_FREQ_CACHE=0.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=,PLL_AFI_CLK_MULT=0,PLL_AFI_CLK_MULT_CACHE=0,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=,PLL_AFI_HALF_CLK_DIV=0,PLL_AFI_HALF_CLK_DIV_CACHE=0,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=0.0,PLL_AFI_HALF_CLK_FREQ_CACHE=0.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=,PLL_AFI_HALF_CLK_MULT=0,PLL_AFI_HALF_CLK_MULT_CACHE=0,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=false,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=false,PLL_MEM_CLK_DIV=0,PLL_MEM_CLK_DIV_CACHE=0,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=0.0,PLL_MEM_CLK_FREQ_CACHE=0.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=,PLL_MEM_CLK_MULT=0,PLL_MEM_CLK_MULT_CACHE=0,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=0,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=0,PLL_WRITE_CLK_DIV_CACHE=0,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=0.0,PLL_WRITE_CLK_FREQ_CACHE=0.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=,PLL_WRITE_CLK_MULT=0,PLL_WRITE_CLK_MULT_CACHE=0,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=0.0,PLL_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_WRITE_CLK_PHASE_PS=0,PLL_WRITE_CLK_PHASE_PS_CACHE=0,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=0,PLL_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=0,RATE=Full,RATE_CACHE=Unknown,RDBUFFER_ADDR_WIDTH=6,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=false,REF_CLK_FREQ_MAX_CACHE=0.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=0.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=,REF_CLK_NS=0.0,REF_CLK_PS=0.0,REGISTER_C2P=false,SCC_DATA_WIDTH=0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=0,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=0.0,TB_MEM_IF_DQ_WIDTH=0,TB_MEM_IF_READ_DQS_WIDTH=0,TB_PLL_DLL_MASTER=true,TB_RATE=,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.05,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.01,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=-0.01,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.0,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.0,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.0,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.0,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=0,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=false,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,border_description=instances {sdio_inst {entity_name cyclonev_hps_peripheral_sdmmc location HPSPERIPHERALSDMMC_X87_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} emac1_inst {entity_name cyclonev_hps_peripheral_emac location HPSPERIPHERALEMAC_X77_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c1_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y65_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} spim1_inst {entity_name cyclonev_hps_peripheral_spi_master location HPSPERIPHERALSPIMASTER_X87_Y53_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} uart0_inst {entity_name cyclonev_hps_peripheral_uart location HPSPERIPHERALUART_X87_Y45_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} @orderednames {emac1_inst sdio_inst usb1_inst spim1_inst uart0_inst i2c0_inst i2c1_inst gpio_inst hps_sdram_inst} usb1_inst {entity_name cyclonev_hps_peripheral_usb location HPSPERIPHERALUSB_X55_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} gpio_inst {entity_name cyclonev_hps_peripheral_gpio location HPSPERIPHERALGPIO_X87_Y74_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps_sdram_inst {entity_name hps_sdram location {} signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c0_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y67_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD0]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD1]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD2]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD3]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD0] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_MDIO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDIO]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDC]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CTL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CTL]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CLK] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD1] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD2] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD3] -to *} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1]} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D1]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D4] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D4]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D5] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D5]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D6] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D6]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D7] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D7]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_CLK] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_STP]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_DIR] -to *} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_NXT] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_MOSI]} {set_false_path -from [get_ports hps_io_hps_io_spim1_inst_MISO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_SS0]} {set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO09] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO09]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO35] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO35]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO40] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO40]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO48] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO48]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO53] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO53]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO54] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO54]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO61] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO61]}} properties {SUPPRESS_SDRAM_SYNTH 0 GENERATE_ISW 1} bfm_types {} intermediate_wire_count 48 wires_to_fragments {{intermediate 9} {output sdio_inst:SDMMC_DATA_OE(2:2)} {intermediate 8} {output sdio_inst:SDMMC_DATA_O(2:2)} {intermediate 7} {output sdio_inst:SDMMC_DATA_OE(1:1)} {intermediate 6} {output sdio_inst:SDMMC_DATA_O(1:1)} {intermediate 5} {output sdio_inst:SDMMC_DATA_OE(0:0)} {intermediate 4} {output sdio_inst:SDMMC_DATA_O(0:0)} {intermediate 3} {output sdio_inst:SDMMC_CMD_OE(0:0)} {intermediate 2} {output sdio_inst:SDMMC_CMD_O(0:0)} {intermediate 1} {output emac1_inst:EMAC_GMII_MDO_OE(0:0)} {intermediate 0} {output emac1_inst:EMAC_GMII_MDO_O(0:0)} {intermediate 19} {output usb1_inst:USB_ULPI_DATA_OE(3:3)} {intermediate 18} {output usb1_inst:USB_ULPI_DATA_O(3:3)} {intermediate 17} {output usb1_inst:USB_ULPI_DATA_OE(2:2)} {intermediate 16} {output usb1_inst:USB_ULPI_DATA_O(2:2)} {intermediate 47} {output gpio_inst:GPIO2_PORTA_OE(3:3)} {intermediate 15} {output usb1_inst:USB_ULPI_DATA_OE(1:1)} {intermediate 46} {output gpio_inst:GPIO2_PORTA_O(3:3)} {intermediate 14} {output usb1_inst:USB_ULPI_DATA_O(1:1)} {intermediate 45} {output gpio_inst:GPIO1_PORTA_OE(25:25)} {intermediate 13} {output usb1_inst:USB_ULPI_DATA_OE(0:0)} {intermediate 44} {output gpio_inst:GPIO1_PORTA_O(25:25)} {intermediate 12} {output usb1_inst:USB_ULPI_DATA_O(0:0)} {intermediate 43} {output gpio_inst:GPIO1_PORTA_OE(24:24)} {intermediate 11} {output sdio_inst:SDMMC_DATA_OE(3:3)} {intermediate 42} {output gpio_inst:GPIO1_PORTA_O(24:24)} {intermediate 10} {output sdio_inst:SDMMC_DATA_O(3:3)} {intermediate 41} {output gpio_inst:GPIO1_PORTA_OE(19:19)} {intermediate 40} {output gpio_inst:GPIO1_PORTA_O(19:19)} {intermediate 39} {output gpio_inst:GPIO1_PORTA_OE(11:11)} {intermediate 38} {output gpio_inst:GPIO1_PORTA_O(11:11)} {intermediate 37} {output gpio_inst:GPIO1_PORTA_OE(6:6)} {intermediate 36} {output gpio_inst:GPIO1_PORTA_O(6:6)} {intermediate 35} {output gpio_inst:GPIO0_PORTA_OE(9:9)} {intermediate 34} {output gpio_inst:GPIO0_PORTA_O(9:9)} {intermediate 33} {output i2c1_inst:I2C_CLK_OE(0:0)} {intermediate 32} {output i2c1_inst:I2C_DATA_OE(0:0)} {intermediate 31} {output i2c0_inst:I2C_CLK_OE(0:0)} {intermediate 30} {output i2c0_inst:I2C_DATA_OE(0:0)} {intermediate 29} {output spim1_inst:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 28} {output spim1_inst:SPI_MASTER_TXD(0:0)} {intermediate 27} {output usb1_inst:USB_ULPI_DATA_OE(7:7)} {intermediate 26} {output usb1_inst:USB_ULPI_DATA_O(7:7)} {intermediate 25} {output usb1_inst:USB_ULPI_DATA_OE(6:6)} {intermediate 24} {output usb1_inst:USB_ULPI_DATA_O(6:6)} {intermediate 23} {output usb1_inst:USB_ULPI_DATA_OE(5:5)} {intermediate 22} {output usb1_inst:USB_ULPI_DATA_O(5:5)} {intermediate 21} {output usb1_inst:USB_ULPI_DATA_OE(4:4)} {intermediate 20} {output usb1_inst:USB_ULPI_DATA_O(4:4)}} interfaces {@orderednames {memory hps_io} memory {properties {} type conduit direction end signals {@orderednames {mem_a mem_ba mem_ck mem_ck_n mem_cke mem_cs_n mem_ras_n mem_cas_n mem_we_n mem_reset_n mem_dq mem_dqs mem_dqs_n mem_odt mem_dm oct_rzqin} mem_a {fragments {} properties {} internal_name mem_a width 15 instance_name hps_sdram_inst direction Output role mem_a} mem_ba {fragments {} properties {} internal_name mem_ba width 3 instance_name hps_sdram_inst direction Output role mem_ba} mem_ck {fragments {} properties {} internal_name mem_ck width 1 instance_name hps_sdram_inst direction Output role mem_ck} mem_ck_n {fragments {} properties {} internal_name mem_ck_n width 1 instance_name hps_sdram_inst direction Output role mem_ck_n} mem_cke {fragments {} properties {} internal_name mem_cke width 1 instance_name hps_sdram_inst direction Output role mem_cke} mem_cs_n {fragments {} properties {} internal_name mem_cs_n width 1 instance_name hps_sdram_inst direction Output role mem_cs_n} mem_ras_n {fragments {} properties {} internal_name mem_ras_n width 1 instance_name hps_sdram_inst direction Output role mem_ras_n} mem_cas_n {fragments {} properties {} internal_name mem_cas_n width 1 instance_name hps_sdram_inst direction Output role mem_cas_n} mem_we_n {fragments {} properties {} internal_name mem_we_n width 1 instance_name hps_sdram_inst direction Output role mem_we_n} mem_reset_n {fragments {} properties {} internal_name mem_reset_n width 1 instance_name hps_sdram_inst direction Output role mem_reset_n} mem_dq {fragments {} properties {} internal_name mem_dq width 32 instance_name hps_sdram_inst direction Bidir role mem_dq} mem_dqs {fragments {} properties {} internal_name mem_dqs width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs} mem_dqs_n {fragments {} properties {} internal_name mem_dqs_n width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs_n} mem_odt {fragments {} properties {} internal_name mem_odt width 1 instance_name hps_sdram_inst direction Output role mem_odt} mem_dm {fragments {} properties {} internal_name mem_dm width 4 instance_name hps_sdram_inst direction Output role mem_dm} oct_rzqin {fragments {} properties {} internal_name oct_rzqin width 1 instance_name hps_sdram_inst direction Input role oct_rzqin}}} hps_io {properties {} type conduit direction input signals {@orderednames {hps_io_emac1_inst_TX_CLK hps_io_emac1_inst_TXD0 hps_io_emac1_inst_TXD1 hps_io_emac1_inst_TXD2 hps_io_emac1_inst_TXD3 hps_io_emac1_inst_RXD0 hps_io_emac1_inst_MDIO hps_io_emac1_inst_MDC hps_io_emac1_inst_RX_CTL hps_io_emac1_inst_TX_CTL hps_io_emac1_inst_RX_CLK hps_io_emac1_inst_RXD1 hps_io_emac1_inst_RXD2 hps_io_emac1_inst_RXD3 hps_io_sdio_inst_CMD hps_io_sdio_inst_D0 hps_io_sdio_inst_D1 hps_io_sdio_inst_CLK hps_io_sdio_inst_D2 hps_io_sdio_inst_D3 hps_io_usb1_inst_D0 hps_io_usb1_inst_D1 hps_io_usb1_inst_D2 hps_io_usb1_inst_D3 hps_io_usb1_inst_D4 hps_io_usb1_inst_D5 hps_io_usb1_inst_D6 hps_io_usb1_inst_D7 hps_io_usb1_inst_CLK hps_io_usb1_inst_STP hps_io_usb1_inst_DIR hps_io_usb1_inst_NXT hps_io_spim1_inst_CLK hps_io_spim1_inst_MOSI hps_io_spim1_inst_MISO hps_io_spim1_inst_SS0 hps_io_uart0_inst_RX hps_io_uart0_inst_TX hps_io_i2c0_inst_SDA hps_io_i2c0_inst_SCL hps_io_i2c1_inst_SDA hps_io_i2c1_inst_SCL hps_io_gpio_inst_GPIO09 hps_io_gpio_inst_GPIO35 hps_io_gpio_inst_GPIO40 hps_io_gpio_inst_GPIO48 hps_io_gpio_inst_GPIO53 hps_io_gpio_inst_GPIO54 hps_io_gpio_inst_GPIO61} hps_io_emac1_inst_TX_CLK {fragments emac1_inst:EMAC_CLK_TX(0:0) properties {} internal_name hps_io_emac1_inst_TX_CLK width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CLK} hps_io_emac1_inst_TXD0 {fragments emac1_inst:EMAC_PHY_TXD(0:0) properties {} internal_name hps_io_emac1_inst_TXD0 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD0} hps_io_emac1_inst_TXD1 {fragments emac1_inst:EMAC_PHY_TXD(1:1) properties {} internal_name hps_io_emac1_inst_TXD1 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD1} hps_io_emac1_inst_TXD2 {fragments emac1_inst:EMAC_PHY_TXD(2:2) properties {} internal_name hps_io_emac1_inst_TXD2 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD2} hps_io_emac1_inst_TXD3 {fragments emac1_inst:EMAC_PHY_TXD(3:3) properties {} internal_name hps_io_emac1_inst_TXD3 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD3} hps_io_emac1_inst_RXD0 {fragments emac1_inst:EMAC_PHY_RXD(0:0) properties {} internal_name hps_io_emac1_inst_RXD0 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD0} hps_io_emac1_inst_MDIO {fragments emac1_inst:EMAC_GMII_MDO_I(0:0) properties {} internal_name hps_io_emac1_inst_MDIO width 1 instance_name hps_io tristate_output {{intermediate 1} {intermediate 0}} direction bidir role hps_io_emac1_inst_MDIO} hps_io_emac1_inst_MDC {fragments emac1_inst:EMAC_GMII_MDC(0:0) properties {} internal_name hps_io_emac1_inst_MDC width 1 instance_name hps_io direction output role hps_io_emac1_inst_MDC} hps_io_emac1_inst_RX_CTL {fragments emac1_inst:EMAC_PHY_RXDV(0:0) properties {} internal_name hps_io_emac1_inst_RX_CTL width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CTL} hps_io_emac1_inst_TX_CTL {fragments emac1_inst:EMAC_PHY_TX_OE(0:0) properties {} internal_name hps_io_emac1_inst_TX_CTL width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CTL} hps_io_emac1_inst_RX_CLK {fragments emac1_inst:EMAC_CLK_RX(0:0) properties {} internal_name hps_io_emac1_inst_RX_CLK width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CLK} hps_io_emac1_inst_RXD1 {fragments emac1_inst:EMAC_PHY_RXD(1:1) properties {} internal_name hps_io_emac1_inst_RXD1 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD1} hps_io_emac1_inst_RXD2 {fragments emac1_inst:EMAC_PHY_RXD(2:2) properties {} internal_name hps_io_emac1_inst_RXD2 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD2} hps_io_emac1_inst_RXD3 {fragments emac1_inst:EMAC_PHY_RXD(3:3) properties {} internal_name hps_io_emac1_inst_RXD3 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD3} hps_io_sdio_inst_CMD {fragments sdio_inst:SDMMC_CMD_I(0:0) properties {} internal_name hps_io_sdio_inst_CMD width 1 instance_name hps_io tristate_output {{intermediate 3} {intermediate 2}} direction bidir role hps_io_sdio_inst_CMD} hps_io_sdio_inst_D0 {fragments sdio_inst:SDMMC_DATA_I(0:0) properties {} internal_name hps_io_sdio_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 5} {intermediate 4}} direction bidir role hps_io_sdio_inst_D0} hps_io_sdio_inst_D1 {fragments sdio_inst:SDMMC_DATA_I(1:1) properties {} internal_name hps_io_sdio_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 7} {intermediate 6}} direction bidir role hps_io_sdio_inst_D1} hps_io_sdio_inst_CLK {fragments sdio_inst:SDMMC_CCLK(0:0) properties {} internal_name hps_io_sdio_inst_CLK width 1 instance_name hps_io direction output role hps_io_sdio_inst_CLK} hps_io_sdio_inst_D2 {fragments sdio_inst:SDMMC_DATA_I(2:2) properties {} internal_name hps_io_sdio_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 9} {intermediate 8}} direction bidir role hps_io_sdio_inst_D2} hps_io_sdio_inst_D3 {fragments sdio_inst:SDMMC_DATA_I(3:3) properties {} internal_name hps_io_sdio_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 11} {intermediate 10}} direction bidir role hps_io_sdio_inst_D3} hps_io_usb1_inst_D0 {fragments usb1_inst:USB_ULPI_DATA_I(0:0) properties {} internal_name hps_io_usb1_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 13} {intermediate 12}} direction bidir role hps_io_usb1_inst_D0} hps_io_usb1_inst_D1 {fragments usb1_inst:USB_ULPI_DATA_I(1:1) properties {} internal_name hps_io_usb1_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 15} {intermediate 14}} direction bidir role hps_io_usb1_inst_D1} hps_io_usb1_inst_D2 {fragments usb1_inst:USB_ULPI_DATA_I(2:2) properties {} internal_name hps_io_usb1_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 17} {intermediate 16}} direction bidir role hps_io_usb1_inst_D2} hps_io_usb1_inst_D3 {fragments usb1_inst:USB_ULPI_DATA_I(3:3) properties {} internal_name hps_io_usb1_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 19} {intermediate 18}} direction bidir role hps_io_usb1_inst_D3} hps_io_usb1_inst_D4 {fragments usb1_inst:USB_ULPI_DATA_I(4:4) properties {} internal_name hps_io_usb1_inst_D4 width 1 instance_name hps_io tristate_output {{intermediate 21} {intermediate 20}} direction bidir role hps_io_usb1_inst_D4} hps_io_usb1_inst_D5 {fragments usb1_inst:USB_ULPI_DATA_I(5:5) properties {} internal_name hps_io_usb1_inst_D5 width 1 instance_name hps_io tristate_output {{intermediate 23} {intermediate 22}} direction bidir role hps_io_usb1_inst_D5} hps_io_usb1_inst_D6 {fragments usb1_inst:USB_ULPI_DATA_I(6:6) properties {} internal_name hps_io_usb1_inst_D6 width 1 instance_name hps_io tristate_output {{intermediate 25} {intermediate 24}} direction bidir role hps_io_usb1_inst_D6} hps_io_usb1_inst_D7 {fragments usb1_inst:USB_ULPI_DATA_I(7:7) properties {} internal_name hps_io_usb1_inst_D7 width 1 instance_name hps_io tristate_output {{intermediate 27} {intermediate 26}} direction bidir role hps_io_usb1_inst_D7} hps_io_usb1_inst_CLK {fragments usb1_inst:USB_ULPI_CLK(0:0) properties {} internal_name hps_io_usb1_inst_CLK width 1 instance_name hps_io direction input role hps_io_usb1_inst_CLK} hps_io_usb1_inst_STP {fragments usb1_inst:USB_ULPI_STP(0:0) properties {} internal_name hps_io_usb1_inst_STP width 1 instance_name hps_io direction output role hps_io_usb1_inst_STP} hps_io_usb1_inst_DIR {fragments usb1_inst:USB_ULPI_DIR(0:0) properties {} internal_name hps_io_usb1_inst_DIR width 1 instance_name hps_io direction input role hps_io_usb1_inst_DIR} hps_io_usb1_inst_NXT {fragments usb1_inst:USB_ULPI_NXT(0:0) properties {} internal_name hps_io_usb1_inst_NXT width 1 instance_name hps_io direction input role hps_io_usb1_inst_NXT} hps_io_spim1_inst_CLK {fragments spim1_inst:SPI_MASTER_SCLK(0:0) properties {} internal_name hps_io_spim1_inst_CLK width 1 instance_name hps_io direction output role hps_io_spim1_inst_CLK} hps_io_spim1_inst_MOSI {fragments {} properties {} internal_name hps_io_spim1_inst_MOSI width 1 instance_name hps_io tristate_output {{intermediate 29} {intermediate 28}} direction output role hps_io_spim1_inst_MOSI} hps_io_spim1_inst_MISO {fragments spim1_inst:SPI_MASTER_RXD(0:0) properties {} internal_name hps_io_spim1_inst_MISO width 1 instance_name hps_io direction input role hps_io_spim1_inst_MISO} hps_io_spim1_inst_SS0 {fragments spim1_inst:SPI_MASTER_SS_0_N(0:0) properties {} internal_name hps_io_spim1_inst_SS0 width 1 instance_name hps_io direction output role hps_io_spim1_inst_SS0} hps_io_uart0_inst_RX {fragments uart0_inst:UART_RXD(0:0) properties {} internal_name hps_io_uart0_inst_RX width 1 instance_name hps_io direction input role hps_io_uart0_inst_RX} hps_io_uart0_inst_TX {fragments uart0_inst:UART_TXD(0:0) properties {} internal_name hps_io_uart0_inst_TX width 1 instance_name hps_io direction output role hps_io_uart0_inst_TX} hps_io_i2c0_inst_SDA {fragments i2c0_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c0_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 30} {}} direction bidir role hps_io_i2c0_inst_SDA} hps_io_i2c0_inst_SCL {fragments i2c0_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c0_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 31} {}} direction bidir role hps_io_i2c0_inst_SCL} hps_io_i2c1_inst_SDA {fragments i2c1_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c1_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 32} {}} direction bidir role hps_io_i2c1_inst_SDA} hps_io_i2c1_inst_SCL {fragments i2c1_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c1_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 33} {}} direction bidir role hps_io_i2c1_inst_SCL} hps_io_gpio_inst_GPIO09 {fragments gpio_inst:GPIO0_PORTA_I(9:9) properties {} internal_name hps_io_gpio_inst_GPIO09 width 1 instance_name hps_io tristate_output {{intermediate 35} {intermediate 34}} direction bidir role hps_io_gpio_inst_GPIO09} hps_io_gpio_inst_GPIO35 {fragments gpio_inst:GPIO1_PORTA_I(6:6) properties {} internal_name hps_io_gpio_inst_GPIO35 width 1 instance_name hps_io tristate_output {{intermediate 37} {intermediate 36}} direction bidir role hps_io_gpio_inst_GPIO35} hps_io_gpio_inst_GPIO40 {fragments gpio_inst:GPIO1_PORTA_I(11:11) properties {} internal_name hps_io_gpio_inst_GPIO40 width 1 instance_name hps_io tristate_output {{intermediate 39} {intermediate 38}} direction bidir role hps_io_gpio_inst_GPIO40} hps_io_gpio_inst_GPIO48 {fragments gpio_inst:GPIO1_PORTA_I(19:19) properties {} internal_name hps_io_gpio_inst_GPIO48 width 1 instance_name hps_io tristate_output {{intermediate 41} {intermediate 40}} direction bidir role hps_io_gpio_inst_GPIO48} hps_io_gpio_inst_GPIO53 {fragments gpio_inst:GPIO1_PORTA_I(24:24) properties {} internal_name hps_io_gpio_inst_GPIO53 width 1 instance_name hps_io tristate_output {{intermediate 43} {intermediate 42}} direction bidir role hps_io_gpio_inst_GPIO53} hps_io_gpio_inst_GPIO54 {fragments gpio_inst:GPIO1_PORTA_I(25:25) properties {} internal_name hps_io_gpio_inst_GPIO54 width 1 instance_name hps_io tristate_output {{intermediate 45} {intermediate 44}} direction bidir role hps_io_gpio_inst_GPIO54} hps_io_gpio_inst_GPIO61 {fragments gpio_inst:GPIO2_PORTA_I(3:3) properties {} internal_name hps_io_gpio_inst_GPIO61 width 1 instance_name hps_io tristate_output {{intermediate 47} {intermediate 46}} direction bidir role hps_io_gpio_inst_GPIO61}}}} raw_assign_sim_style {},hps_parameter_map=AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 1.25 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 200000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 32 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 4 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 1000.0 MEM_TRCD 6 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA5F31C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 14 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 25.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 64 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 125 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.02 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 32 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 25.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 25000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 2500.0 periph_pll_vco_hz 1000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 30 PLL_WRITE_CLK_PHASE_PS_CACHE 1875 UART0_PinMuxing {HPS I/O Set 0} sdmmc_clk_hz 200000000 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode RGMII NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz 1600000000 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 2.5 PLL_AFI_CLK_MULT_CACHE 32 PLL_ADDR_CMD_CLK_DIV 2 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 3 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 32 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {45000 ps} PLL_AFI_CLK_DIV 2 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 13.75 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 400.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 2 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.8 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.08 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 25000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 200.0 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 180 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {25.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.03 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 6 TIMING_TIH 140 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 0 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing {HPS I/O Set 0} desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 200000000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_8 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 1875 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 200.0 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 30 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 6 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 65 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {2500 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 20 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 32 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 64 PLL_AFI_PHY_CLK_FREQ 400.0 periph_nand_sdmmc_clk_mhz 200.0 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000110 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No Yes No No No No Yes No No No No No No No Yes No No No No Yes Yes No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 4 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {400.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode I2C IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 12500000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.09 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 200000000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 35.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 2 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {2500 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED true TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode {No Flow Control} S2FCLK_USER0CLK_FREQ_HZ 97368421 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 800.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 4 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 1875 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 8 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 10 dbg_timer_clk_hz 25000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode {Single Slave Select} hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 97.368421 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM RZQ/4 AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 40000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_6 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 13.75 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 8 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.16 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 40.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 2 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 400.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_6 MR2_RTT_WR 1 MEM_TCL 11 GPIO_Pin_Used_DERIVED true JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 104 USE_2X_FF false ENUM_MEM_IF_TRC TRC_20 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 27 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 50000000 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable true desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 2 F2SDRAM_Width {} dbg_clk_hz 12500000 PLL_AFI_CLK_FREQ 400.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.18 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 400.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 66.6666666667 dbg_timer_clk_mhz 25.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {2500 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 9 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 0 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {1875 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 15 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 100.0 PLL_AFI_HALF_CLK_MULT_CACHE 32 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 32 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 400.0 AFI_WRITE_DQS_WIDTH 4 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 200.0 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 25000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.16 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 10 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 200.0 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz 1600.0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.33 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {1875 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {2500 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 15 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {1875 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0010011101000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/7 MEM_IF_DM_WIDTH 4 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.7 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 32 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 32 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 30.0 DELAY_PER_OPA_TAP 312 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing {HPS I/O Set 0} MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {2500 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 12.5 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 6000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 2 ENUM_MEM_IF_TCL TCL_11 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR JEDEC device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing {HPS I/O Set 0} CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_4 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 2 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 97.368421 MR2_CWL 3 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 211 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 39 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 12.5 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 73 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 400.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 15 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 1 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 32000 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 MR0_BT 0 PLL_CONFIG_CLK_FREQ 22.2222222222 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 1 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {400.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 32 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 25.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR RZQ/4 TIMING_TDQSCK 255 REF_CLK_FREQ_CACHE 25.0 AC_ROM_MR0_DLL_RESET 0010101110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {15000 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0010001101001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 12 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {400.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing {HPS I/O Set 0} MEM_TREFI 3120 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 32 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 25.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.09 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {2500 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 4 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 10 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_6 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 50000000 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.165 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {2500 ps} emac1_clk_mhz 250.0 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 500 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 32 TIMING_BOARD_SKEW_WITHIN_DQS 0.01 ENUM_MEM_IF_TRAS TRAS_14 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 1 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.03 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 7 H2F_LW_AXI_CLOCK_FREQ 50000000 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {400.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 2 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {1875 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 12500000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 250000000 eosc2_clk_mhz 25.0 PLL_MEM_CLK_DIV_CACHE 2 periph_base_clk_mhz 200.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_32 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 8 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.24 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing {HPS I/O Set 0} INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 400.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 25.0 desired_cfg_clk_hz 97368421 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 2 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 200000000 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 4 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {5000 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 8 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 11 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 200000000 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 6249 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0001000011000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode I2C quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 3120 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 1875 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {400.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 4 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 260.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY true ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 4 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 1 pin_muxing_check {Cyclone V+5CSEMA5F31C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 100000000 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 2 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 200000 PLL_WRITE_CLK_MULT_CACHE 32 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 400.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 4 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 50.0 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} USB1.D0 USB1.D1 USB1.D2 USB1.D3 USB1.D4 USB1.D5 USB1.D6 USB1.D7 {} USB1.CLK USB1.STP USB1.DIR USB1.NXT EMAC1.TX_CLK EMAC1.TXD0 EMAC1.TXD1 EMAC1.TXD2 EMAC1.TXD3 EMAC1.RXD0 EMAC1.MDIO EMAC1.MDC EMAC1.RX_CTL EMAC1.TX_CTL EMAC1.RX_CLK EMAC1.RXD1 EMAC1.RXD2 EMAC1.RXD3 {} {} {} {} {} {} {} {} SDIO.CMD {} SDIO.D0 SDIO.D1 {} {} {} {} {} SDIO.CLK SDIO.D2 SDIO.D3 {} UART0.RX UART0.TX I2C1.SDA I2C1.SCL {} {} I2C0.SDA I2C0.SCL {} {} {} {} {} {} SPIM1.CLK SPIM1.MOSI SPIM1.MISO SPIM1.SS0} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 8 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 400.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 8 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 32 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0001000011000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000000000110 TB_MEM_CLK_FREQ 400.0 AC_ROM_MR0 0010001110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 18000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 400.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {2500 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 12.5 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 5 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_4 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing {HPS I/O Set 0} CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 25000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {5000 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode SDR ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.4 dbg_base_clk_hz 25000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 400.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 2 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 1250.0 S2FCLK_USER1CLK_Enable true SDIO_Mode {4-bit Data} desired_qspi_clk_mhz 400.0 MEM_TRFC 104 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2(altera_interface_generator:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=,AC_ROM_MR0_DLL_RESET_MIRR=,AC_ROM_MR0_MIRR=,AC_ROM_MR1=,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=,AC_ROM_MR2_MIRR=,AC_ROM_MR3=,AC_ROM_MR3_MIRR=,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=0,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=0,AFI_BANKADDR_WIDTH=0,AFI_CLK_EN_WIDTH=0,AFI_CLK_PAIR_COUNT=0,AFI_CONTROL_WIDTH=0,AFI_CS_WIDTH=0,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=0,AFI_DQ_WIDTH=0,AFI_ODT_WIDTH=0,AFI_RATE_RATIO=0,AFI_RLAT_WIDTH=0,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=0,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=0,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=0,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=0,AVL_DATA_WIDTH=0,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=2,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=0,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=-1,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=-1,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=0,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=0,CFG_MEM_CLK_ENTRY_CYCLES=0,CFG_PDN_EXIT_CYCLES=0,CFG_PORT_WIDTH_READ_ODT_CHIP=0,CFG_PORT_WIDTH_WRITE_ODT_CHIP=0,CFG_POWER_SAVING_EXIT_CYCLES=0,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=0,CFG_STARVE_LIMIT=0,CFG_TCCD=0,CFG_TCCD_NS=2.5,CFG_TYPE=0,CFG_WRITE_ODT_CHIP=0,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=0,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=0,CTL_ECC_MULTIPLES_40_72=0,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=0,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=0,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=0,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=-1,DELAY_PER_DQS_EN_DCHAIN_TAP=-1,DELAY_PER_OPA_TAP=-1,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=false,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=-1,DQS_IN_DELAY_MAX=-1,DQS_PHASE_SHIFT=9000,DQ_DDR=0,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=true,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=0,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=-1,IO_OUT1_DELAY_MAX=-1,IO_OUT2_DELAY_MAX=-1,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=6,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=2.5,MEM_CLK_MAX_PS=2500.0,MEM_CLK_NS=0.0,MEM_CLK_PS=0.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=0,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=0,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=0,MEM_IF_ADDR_WIDTH_MIN=10,MEM_IF_BANKADDR_WIDTH=0,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=-1,MEM_IF_CK_WIDTH=0,MEM_IF_CLK_EN_WIDTH=0,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=0,MEM_IF_CONTROL_WIDTH=0,MEM_IF_CS_PER_DIMM=0,MEM_IF_CS_PER_RANK=0,MEM_IF_CS_WIDTH=0,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=0,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=0,MEM_IF_DQ_WIDTH=0,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=0,MEM_IF_ODT_WIDTH=0,MEM_IF_RD_TO_WR_TURNAROUND_OCT=0,MEM_IF_READ_DQS_WIDTH=0,MEM_IF_ROW_ADDR_WIDTH=0,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=0,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=2,MEM_TFAW=0,MEM_TFAW_NS=30.0,MEM_TINIT_CK=499,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=0,MEM_TRAS_NS=35.0,MEM_TRC=0,MEM_TRCD=0,MEM_TRCD_NS=13.75,MEM_TREFI=0,MEM_TREFI_US=7.8,MEM_TRFC=0,MEM_TRFC_NS=260.0,MEM_TRP=0,MEM_TRP_NS=13.75,MEM_TRRD=0,MEM_TRRD_NS=7.7,MEM_TRTP=0,MEM_TRTP_NS=7.5,MEM_TWR=0,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=,MEM_T_RL=0,MEM_T_WL=0,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=6,MR0_BL=2,MR0_BT=0,MR0_CAS_LATENCY=3,MR0_DLL=1,MR0_PD=0,MR0_WR=4,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=1,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=false,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=0,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=0,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=false,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=0,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=0,PLL_ADDR_CMD_CLK_DIV_CACHE=0,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=0.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=0.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=,PLL_ADDR_CMD_CLK_MULT=0,PLL_ADDR_CMD_CLK_MULT_CACHE=0,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=,PLL_AFI_CLK_DIV=0,PLL_AFI_CLK_DIV_CACHE=0,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=0.0,PLL_AFI_CLK_FREQ_CACHE=0.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=,PLL_AFI_CLK_MULT=0,PLL_AFI_CLK_MULT_CACHE=0,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=,PLL_AFI_HALF_CLK_DIV=0,PLL_AFI_HALF_CLK_DIV_CACHE=0,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=0.0,PLL_AFI_HALF_CLK_FREQ_CACHE=0.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=,PLL_AFI_HALF_CLK_MULT=0,PLL_AFI_HALF_CLK_MULT_CACHE=0,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=false,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=false,PLL_MEM_CLK_DIV=0,PLL_MEM_CLK_DIV_CACHE=0,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=0.0,PLL_MEM_CLK_FREQ_CACHE=0.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=,PLL_MEM_CLK_MULT=0,PLL_MEM_CLK_MULT_CACHE=0,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=0,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=0,PLL_WRITE_CLK_DIV_CACHE=0,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=0.0,PLL_WRITE_CLK_FREQ_CACHE=0.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=,PLL_WRITE_CLK_MULT=0,PLL_WRITE_CLK_MULT_CACHE=0,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=0.0,PLL_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_WRITE_CLK_PHASE_PS=0,PLL_WRITE_CLK_PHASE_PS_CACHE=0,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=0,PLL_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=0,RATE=Full,RATE_CACHE=Unknown,RDBUFFER_ADDR_WIDTH=6,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=false,REF_CLK_FREQ_MAX_CACHE=0.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=0.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=,REF_CLK_NS=0.0,REF_CLK_PS=0.0,REGISTER_C2P=false,SCC_DATA_WIDTH=0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=0,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=0.0,TB_MEM_IF_DQ_WIDTH=0,TB_MEM_IF_READ_DQS_WIDTH=0,TB_PLL_DLL_MASTER=true,TB_RATE=,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.05,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.01,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=-0.01,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.0,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.0,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.0,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.0,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=0,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=false,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,device=5CSEMA5F31C6,hps_parameter_map=AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 1.25 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 200000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 32 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 4 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 1000.0 MEM_TRCD 6 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA5F31C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 14 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 25.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 64 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 125 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.02 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 32 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 25.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 25000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 2500.0 periph_pll_vco_hz 1000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 30 PLL_WRITE_CLK_PHASE_PS_CACHE 1875 UART0_PinMuxing {HPS I/O Set 0} sdmmc_clk_hz 200000000 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode RGMII NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz 1600000000 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 2.5 PLL_AFI_CLK_MULT_CACHE 32 PLL_ADDR_CMD_CLK_DIV 2 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 3 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 32 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {45000 ps} PLL_AFI_CLK_DIV 2 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 13.75 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 400.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 2 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.8 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.08 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 25000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 200.0 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 180 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {25.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.03 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 6 TIMING_TIH 140 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 0 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing {HPS I/O Set 0} desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 200000000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_8 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 1875 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 200.0 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 30 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 6 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 65 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {2500 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 20 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 32 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 64 PLL_AFI_PHY_CLK_FREQ 400.0 periph_nand_sdmmc_clk_mhz 200.0 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000110 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No Yes No No No No Yes No No No No No No No Yes No No No No Yes Yes No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 4 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {400.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode I2C IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 12500000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.09 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 200000000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 35.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 2 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {2500 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED true TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode {No Flow Control} S2FCLK_USER0CLK_FREQ_HZ 97368421 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 800.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 4 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 1875 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 8 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 10 dbg_timer_clk_hz 25000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode {Single Slave Select} hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 97.368421 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM RZQ/4 AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 40000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_6 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 13.75 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 8 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.16 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 40.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 2 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 400.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_6 MR2_RTT_WR 1 MEM_TCL 11 GPIO_Pin_Used_DERIVED true JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 104 USE_2X_FF false ENUM_MEM_IF_TRC TRC_20 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 27 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 50000000 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable true desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 2 F2SDRAM_Width {} dbg_clk_hz 12500000 PLL_AFI_CLK_FREQ 400.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.18 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 400.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 66.6666666667 dbg_timer_clk_mhz 25.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {2500 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 9 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 0 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {1875 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 15 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 100.0 PLL_AFI_HALF_CLK_MULT_CACHE 32 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 32 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 400.0 AFI_WRITE_DQS_WIDTH 4 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 200.0 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 25000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.16 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 10 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 200.0 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz 1600.0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.33 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {1875 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {2500 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 15 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {1875 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0010011101000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/7 MEM_IF_DM_WIDTH 4 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.7 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 32 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 32 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 30.0 DELAY_PER_OPA_TAP 312 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing {HPS I/O Set 0} MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {2500 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 12.5 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 6000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 2 ENUM_MEM_IF_TCL TCL_11 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR JEDEC device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing {HPS I/O Set 0} CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_4 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 2 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 97.368421 MR2_CWL 3 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 211 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 39 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 12.5 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 73 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 400.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 15 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 1 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 32000 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 MR0_BT 0 PLL_CONFIG_CLK_FREQ 22.2222222222 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 1 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {400.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 32 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 25.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR RZQ/4 TIMING_TDQSCK 255 REF_CLK_FREQ_CACHE 25.0 AC_ROM_MR0_DLL_RESET 0010101110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {15000 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0010001101001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 12 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {400.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing {HPS I/O Set 0} MEM_TREFI 3120 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 32 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 25.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.09 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {2500 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 4 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 10 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_6 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 50000000 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.165 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {2500 ps} emac1_clk_mhz 250.0 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 500 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 32 TIMING_BOARD_SKEW_WITHIN_DQS 0.01 ENUM_MEM_IF_TRAS TRAS_14 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 1 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.03 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 7 H2F_LW_AXI_CLOCK_FREQ 50000000 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {400.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 2 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {1875 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 12500000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 250000000 eosc2_clk_mhz 25.0 PLL_MEM_CLK_DIV_CACHE 2 periph_base_clk_mhz 200.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_32 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 8 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.24 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing {HPS I/O Set 0} INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 400.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 25.0 desired_cfg_clk_hz 97368421 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 2 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 200000000 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 4 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {5000 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 8 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 11 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 200000000 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 6249 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0001000011000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode I2C quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 3120 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 1875 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {400.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 4 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 260.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY true ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 4 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 1 pin_muxing_check {Cyclone V+5CSEMA5F31C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 100000000 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 2 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 200000 PLL_WRITE_CLK_MULT_CACHE 32 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 400.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 4 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 50.0 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} USB1.D0 USB1.D1 USB1.D2 USB1.D3 USB1.D4 USB1.D5 USB1.D6 USB1.D7 {} USB1.CLK USB1.STP USB1.DIR USB1.NXT EMAC1.TX_CLK EMAC1.TXD0 EMAC1.TXD1 EMAC1.TXD2 EMAC1.TXD3 EMAC1.RXD0 EMAC1.MDIO EMAC1.MDC EMAC1.RX_CTL EMAC1.TX_CTL EMAC1.RX_CLK EMAC1.RXD1 EMAC1.RXD2 EMAC1.RXD3 {} {} {} {} {} {} {} {} SDIO.CMD {} SDIO.D0 SDIO.D1 {} {} {} {} {} SDIO.CLK SDIO.D2 SDIO.D3 {} UART0.RX UART0.TX I2C1.SDA I2C1.SCL {} {} I2C0.SDA I2C0.SCL {} {} {} {} {} {} SPIM1.CLK SPIM1.MOSI SPIM1.MISO SPIM1.SS0} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 8 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 400.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 8 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 32 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0001000011000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000000000110 TB_MEM_CLK_FREQ 400.0 AC_ROM_MR0 0010001110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 18000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 400.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {2500 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 12.5 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 5 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_4 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing {HPS I/O Set 0} CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 25000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {5000 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode SDR ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.4 dbg_base_clk_hz 25000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 400.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 2 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 1250.0 S2FCLK_USER1CLK_Enable true SDIO_Mode {4-bit Data} desired_qspi_clk_mhz 400.0 MEM_TRFC 104 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2,ignoreSimulation=true,interfaceDefinition=instances {sdio_inst {entity_name cyclonev_hps_peripheral_sdmmc location HPSPERIPHERALSDMMC_X87_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} emac1_inst {entity_name cyclonev_hps_peripheral_emac location HPSPERIPHERALEMAC_X77_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c1_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y65_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} spim1_inst {entity_name cyclonev_hps_peripheral_spi_master location HPSPERIPHERALSPIMASTER_X87_Y53_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} uart0_inst {entity_name cyclonev_hps_peripheral_uart location HPSPERIPHERALUART_X87_Y45_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} @orderednames {emac1_inst sdio_inst usb1_inst spim1_inst uart0_inst i2c0_inst i2c1_inst gpio_inst hps_sdram_inst} usb1_inst {entity_name cyclonev_hps_peripheral_usb location HPSPERIPHERALUSB_X55_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} gpio_inst {entity_name cyclonev_hps_peripheral_gpio location HPSPERIPHERALGPIO_X87_Y74_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps_sdram_inst {entity_name hps_sdram location {} signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c0_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y67_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD0]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD1]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD2]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD3]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD0] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_MDIO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDIO]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDC]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CTL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CTL]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CLK] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD1] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD2] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD3] -to *} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1]} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D1]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D4] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D4]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D5] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D5]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D6] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D6]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D7] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D7]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_CLK] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_STP]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_DIR] -to *} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_NXT] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_MOSI]} {set_false_path -from [get_ports hps_io_hps_io_spim1_inst_MISO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_SS0]} {set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO09] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO09]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO35] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO35]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO40] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO40]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO48] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO48]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO53] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO53]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO54] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO54]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO61] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO61]}} properties {SUPPRESS_SDRAM_SYNTH 0 GENERATE_ISW 1} bfm_types {} intermediate_wire_count 48 interfaces {@orderednames {memory hps_io} memory {properties {} type conduit direction end signals {@orderednames {mem_a mem_ba mem_ck mem_ck_n mem_cke mem_cs_n mem_ras_n mem_cas_n mem_we_n mem_reset_n mem_dq mem_dqs mem_dqs_n mem_odt mem_dm oct_rzqin} mem_a {fragments {} properties {} internal_name mem_a width 15 instance_name hps_sdram_inst direction Output role mem_a} mem_ba {fragments {} properties {} internal_name mem_ba width 3 instance_name hps_sdram_inst direction Output role mem_ba} mem_ck {fragments {} properties {} internal_name mem_ck width 1 instance_name hps_sdram_inst direction Output role mem_ck} mem_ck_n {fragments {} properties {} internal_name mem_ck_n width 1 instance_name hps_sdram_inst direction Output role mem_ck_n} mem_cke {fragments {} properties {} internal_name mem_cke width 1 instance_name hps_sdram_inst direction Output role mem_cke} mem_cs_n {fragments {} properties {} internal_name mem_cs_n width 1 instance_name hps_sdram_inst direction Output role mem_cs_n} mem_ras_n {fragments {} properties {} internal_name mem_ras_n width 1 instance_name hps_sdram_inst direction Output role mem_ras_n} mem_cas_n {fragments {} properties {} internal_name mem_cas_n width 1 instance_name hps_sdram_inst direction Output role mem_cas_n} mem_we_n {fragments {} properties {} internal_name mem_we_n width 1 instance_name hps_sdram_inst direction Output role mem_we_n} mem_reset_n {fragments {} properties {} internal_name mem_reset_n width 1 instance_name hps_sdram_inst direction Output role mem_reset_n} mem_dq {fragments {} properties {} internal_name mem_dq width 32 instance_name hps_sdram_inst direction Bidir role mem_dq} mem_dqs {fragments {} properties {} internal_name mem_dqs width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs} mem_dqs_n {fragments {} properties {} internal_name mem_dqs_n width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs_n} mem_odt {fragments {} properties {} internal_name mem_odt width 1 instance_name hps_sdram_inst direction Output role mem_odt} mem_dm {fragments {} properties {} internal_name mem_dm width 4 instance_name hps_sdram_inst direction Output role mem_dm} oct_rzqin {fragments {} properties {} internal_name oct_rzqin width 1 instance_name hps_sdram_inst direction Input role oct_rzqin}}} hps_io {properties {} type conduit direction input signals {@orderednames {hps_io_emac1_inst_TX_CLK hps_io_emac1_inst_TXD0 hps_io_emac1_inst_TXD1 hps_io_emac1_inst_TXD2 hps_io_emac1_inst_TXD3 hps_io_emac1_inst_RXD0 hps_io_emac1_inst_MDIO hps_io_emac1_inst_MDC hps_io_emac1_inst_RX_CTL hps_io_emac1_inst_TX_CTL hps_io_emac1_inst_RX_CLK hps_io_emac1_inst_RXD1 hps_io_emac1_inst_RXD2 hps_io_emac1_inst_RXD3 hps_io_sdio_inst_CMD hps_io_sdio_inst_D0 hps_io_sdio_inst_D1 hps_io_sdio_inst_CLK hps_io_sdio_inst_D2 hps_io_sdio_inst_D3 hps_io_usb1_inst_D0 hps_io_usb1_inst_D1 hps_io_usb1_inst_D2 hps_io_usb1_inst_D3 hps_io_usb1_inst_D4 hps_io_usb1_inst_D5 hps_io_usb1_inst_D6 hps_io_usb1_inst_D7 hps_io_usb1_inst_CLK hps_io_usb1_inst_STP hps_io_usb1_inst_DIR hps_io_usb1_inst_NXT hps_io_spim1_inst_CLK hps_io_spim1_inst_MOSI hps_io_spim1_inst_MISO hps_io_spim1_inst_SS0 hps_io_uart0_inst_RX hps_io_uart0_inst_TX hps_io_i2c0_inst_SDA hps_io_i2c0_inst_SCL hps_io_i2c1_inst_SDA hps_io_i2c1_inst_SCL hps_io_gpio_inst_GPIO09 hps_io_gpio_inst_GPIO35 hps_io_gpio_inst_GPIO40 hps_io_gpio_inst_GPIO48 hps_io_gpio_inst_GPIO53 hps_io_gpio_inst_GPIO54 hps_io_gpio_inst_GPIO61} hps_io_emac1_inst_TX_CLK {fragments emac1_inst:EMAC_CLK_TX(0:0) properties {} internal_name hps_io_emac1_inst_TX_CLK width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CLK} hps_io_emac1_inst_TXD0 {fragments emac1_inst:EMAC_PHY_TXD(0:0) properties {} internal_name hps_io_emac1_inst_TXD0 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD0} hps_io_emac1_inst_TXD1 {fragments emac1_inst:EMAC_PHY_TXD(1:1) properties {} internal_name hps_io_emac1_inst_TXD1 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD1} hps_io_emac1_inst_TXD2 {fragments emac1_inst:EMAC_PHY_TXD(2:2) properties {} internal_name hps_io_emac1_inst_TXD2 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD2} hps_io_emac1_inst_TXD3 {fragments emac1_inst:EMAC_PHY_TXD(3:3) properties {} internal_name hps_io_emac1_inst_TXD3 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD3} hps_io_emac1_inst_RXD0 {fragments emac1_inst:EMAC_PHY_RXD(0:0) properties {} internal_name hps_io_emac1_inst_RXD0 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD0} hps_io_emac1_inst_MDIO {fragments emac1_inst:EMAC_GMII_MDO_I(0:0) properties {} internal_name hps_io_emac1_inst_MDIO width 1 instance_name hps_io tristate_output {{intermediate 1} {intermediate 0}} direction bidir role hps_io_emac1_inst_MDIO} hps_io_emac1_inst_MDC {fragments emac1_inst:EMAC_GMII_MDC(0:0) properties {} internal_name hps_io_emac1_inst_MDC width 1 instance_name hps_io direction output role hps_io_emac1_inst_MDC} hps_io_emac1_inst_RX_CTL {fragments emac1_inst:EMAC_PHY_RXDV(0:0) properties {} internal_name hps_io_emac1_inst_RX_CTL width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CTL} hps_io_emac1_inst_TX_CTL {fragments emac1_inst:EMAC_PHY_TX_OE(0:0) properties {} internal_name hps_io_emac1_inst_TX_CTL width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CTL} hps_io_emac1_inst_RX_CLK {fragments emac1_inst:EMAC_CLK_RX(0:0) properties {} internal_name hps_io_emac1_inst_RX_CLK width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CLK} hps_io_emac1_inst_RXD1 {fragments emac1_inst:EMAC_PHY_RXD(1:1) properties {} internal_name hps_io_emac1_inst_RXD1 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD1} hps_io_emac1_inst_RXD2 {fragments emac1_inst:EMAC_PHY_RXD(2:2) properties {} internal_name hps_io_emac1_inst_RXD2 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD2} hps_io_emac1_inst_RXD3 {fragments emac1_inst:EMAC_PHY_RXD(3:3) properties {} internal_name hps_io_emac1_inst_RXD3 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD3} hps_io_sdio_inst_CMD {fragments sdio_inst:SDMMC_CMD_I(0:0) properties {} internal_name hps_io_sdio_inst_CMD width 1 instance_name hps_io tristate_output {{intermediate 3} {intermediate 2}} direction bidir role hps_io_sdio_inst_CMD} hps_io_sdio_inst_D0 {fragments sdio_inst:SDMMC_DATA_I(0:0) properties {} internal_name hps_io_sdio_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 5} {intermediate 4}} direction bidir role hps_io_sdio_inst_D0} hps_io_sdio_inst_D1 {fragments sdio_inst:SDMMC_DATA_I(1:1) properties {} internal_name hps_io_sdio_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 7} {intermediate 6}} direction bidir role hps_io_sdio_inst_D1} hps_io_sdio_inst_CLK {fragments sdio_inst:SDMMC_CCLK(0:0) properties {} internal_name hps_io_sdio_inst_CLK width 1 instance_name hps_io direction output role hps_io_sdio_inst_CLK} hps_io_sdio_inst_D2 {fragments sdio_inst:SDMMC_DATA_I(2:2) properties {} internal_name hps_io_sdio_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 9} {intermediate 8}} direction bidir role hps_io_sdio_inst_D2} hps_io_sdio_inst_D3 {fragments sdio_inst:SDMMC_DATA_I(3:3) properties {} internal_name hps_io_sdio_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 11} {intermediate 10}} direction bidir role hps_io_sdio_inst_D3} hps_io_usb1_inst_D0 {fragments usb1_inst:USB_ULPI_DATA_I(0:0) properties {} internal_name hps_io_usb1_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 13} {intermediate 12}} direction bidir role hps_io_usb1_inst_D0} hps_io_usb1_inst_D1 {fragments usb1_inst:USB_ULPI_DATA_I(1:1) properties {} internal_name hps_io_usb1_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 15} {intermediate 14}} direction bidir role hps_io_usb1_inst_D1} hps_io_usb1_inst_D2 {fragments usb1_inst:USB_ULPI_DATA_I(2:2) properties {} internal_name hps_io_usb1_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 17} {intermediate 16}} direction bidir role hps_io_usb1_inst_D2} hps_io_usb1_inst_D3 {fragments usb1_inst:USB_ULPI_DATA_I(3:3) properties {} internal_name hps_io_usb1_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 19} {intermediate 18}} direction bidir role hps_io_usb1_inst_D3} hps_io_usb1_inst_D4 {fragments usb1_inst:USB_ULPI_DATA_I(4:4) properties {} internal_name hps_io_usb1_inst_D4 width 1 instance_name hps_io tristate_output {{intermediate 21} {intermediate 20}} direction bidir role hps_io_usb1_inst_D4} hps_io_usb1_inst_D5 {fragments usb1_inst:USB_ULPI_DATA_I(5:5) properties {} internal_name hps_io_usb1_inst_D5 width 1 instance_name hps_io tristate_output {{intermediate 23} {intermediate 22}} direction bidir role hps_io_usb1_inst_D5} hps_io_usb1_inst_D6 {fragments usb1_inst:USB_ULPI_DATA_I(6:6) properties {} internal_name hps_io_usb1_inst_D6 width 1 instance_name hps_io tristate_output {{intermediate 25} {intermediate 24}} direction bidir role hps_io_usb1_inst_D6} hps_io_usb1_inst_D7 {fragments usb1_inst:USB_ULPI_DATA_I(7:7) properties {} internal_name hps_io_usb1_inst_D7 width 1 instance_name hps_io tristate_output {{intermediate 27} {intermediate 26}} direction bidir role hps_io_usb1_inst_D7} hps_io_usb1_inst_CLK {fragments usb1_inst:USB_ULPI_CLK(0:0) properties {} internal_name hps_io_usb1_inst_CLK width 1 instance_name hps_io direction input role hps_io_usb1_inst_CLK} hps_io_usb1_inst_STP {fragments usb1_inst:USB_ULPI_STP(0:0) properties {} internal_name hps_io_usb1_inst_STP width 1 instance_name hps_io direction output role hps_io_usb1_inst_STP} hps_io_usb1_inst_DIR {fragments usb1_inst:USB_ULPI_DIR(0:0) properties {} internal_name hps_io_usb1_inst_DIR width 1 instance_name hps_io direction input role hps_io_usb1_inst_DIR} hps_io_usb1_inst_NXT {fragments usb1_inst:USB_ULPI_NXT(0:0) properties {} internal_name hps_io_usb1_inst_NXT width 1 instance_name hps_io direction input role hps_io_usb1_inst_NXT} hps_io_spim1_inst_CLK {fragments spim1_inst:SPI_MASTER_SCLK(0:0) properties {} internal_name hps_io_spim1_inst_CLK width 1 instance_name hps_io direction output role hps_io_spim1_inst_CLK} hps_io_spim1_inst_MOSI {fragments {} properties {} internal_name hps_io_spim1_inst_MOSI width 1 instance_name hps_io tristate_output {{intermediate 29} {intermediate 28}} direction output role hps_io_spim1_inst_MOSI} hps_io_spim1_inst_MISO {fragments spim1_inst:SPI_MASTER_RXD(0:0) properties {} internal_name hps_io_spim1_inst_MISO width 1 instance_name hps_io direction input role hps_io_spim1_inst_MISO} hps_io_spim1_inst_SS0 {fragments spim1_inst:SPI_MASTER_SS_0_N(0:0) properties {} internal_name hps_io_spim1_inst_SS0 width 1 instance_name hps_io direction output role hps_io_spim1_inst_SS0} hps_io_uart0_inst_RX {fragments uart0_inst:UART_RXD(0:0) properties {} internal_name hps_io_uart0_inst_RX width 1 instance_name hps_io direction input role hps_io_uart0_inst_RX} hps_io_uart0_inst_TX {fragments uart0_inst:UART_TXD(0:0) properties {} internal_name hps_io_uart0_inst_TX width 1 instance_name hps_io direction output role hps_io_uart0_inst_TX} hps_io_i2c0_inst_SDA {fragments i2c0_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c0_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 30} {}} direction bidir role hps_io_i2c0_inst_SDA} hps_io_i2c0_inst_SCL {fragments i2c0_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c0_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 31} {}} direction bidir role hps_io_i2c0_inst_SCL} hps_io_i2c1_inst_SDA {fragments i2c1_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c1_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 32} {}} direction bidir role hps_io_i2c1_inst_SDA} hps_io_i2c1_inst_SCL {fragments i2c1_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c1_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 33} {}} direction bidir role hps_io_i2c1_inst_SCL} hps_io_gpio_inst_GPIO09 {fragments gpio_inst:GPIO0_PORTA_I(9:9) properties {} internal_name hps_io_gpio_inst_GPIO09 width 1 instance_name hps_io tristate_output {{intermediate 35} {intermediate 34}} direction bidir role hps_io_gpio_inst_GPIO09} hps_io_gpio_inst_GPIO35 {fragments gpio_inst:GPIO1_PORTA_I(6:6) properties {} internal_name hps_io_gpio_inst_GPIO35 width 1 instance_name hps_io tristate_output {{intermediate 37} {intermediate 36}} direction bidir role hps_io_gpio_inst_GPIO35} hps_io_gpio_inst_GPIO40 {fragments gpio_inst:GPIO1_PORTA_I(11:11) properties {} internal_name hps_io_gpio_inst_GPIO40 width 1 instance_name hps_io tristate_output {{intermediate 39} {intermediate 38}} direction bidir role hps_io_gpio_inst_GPIO40} hps_io_gpio_inst_GPIO48 {fragments gpio_inst:GPIO1_PORTA_I(19:19) properties {} internal_name hps_io_gpio_inst_GPIO48 width 1 instance_name hps_io tristate_output {{intermediate 41} {intermediate 40}} direction bidir role hps_io_gpio_inst_GPIO48} hps_io_gpio_inst_GPIO53 {fragments gpio_inst:GPIO1_PORTA_I(24:24) properties {} internal_name hps_io_gpio_inst_GPIO53 width 1 instance_name hps_io tristate_output {{intermediate 43} {intermediate 42}} direction bidir role hps_io_gpio_inst_GPIO53} hps_io_gpio_inst_GPIO54 {fragments gpio_inst:GPIO1_PORTA_I(25:25) properties {} internal_name hps_io_gpio_inst_GPIO54 width 1 instance_name hps_io tristate_output {{intermediate 45} {intermediate 44}} direction bidir role hps_io_gpio_inst_GPIO54} hps_io_gpio_inst_GPIO61 {fragments gpio_inst:GPIO2_PORTA_I(3:3) properties {} internal_name hps_io_gpio_inst_GPIO61 width 1 instance_name hps_io tristate_output {{intermediate 47} {intermediate 46}} direction bidir role hps_io_gpio_inst_GPIO61}}}} wires_to_fragments {{intermediate 9} {output sdio_inst:SDMMC_DATA_OE(2:2)} {intermediate 8} {output sdio_inst:SDMMC_DATA_O(2:2)} {intermediate 7} {output sdio_inst:SDMMC_DATA_OE(1:1)} {intermediate 6} {output sdio_inst:SDMMC_DATA_O(1:1)} {intermediate 5} {output sdio_inst:SDMMC_DATA_OE(0:0)} {intermediate 4} {output sdio_inst:SDMMC_DATA_O(0:0)} {intermediate 3} {output sdio_inst:SDMMC_CMD_OE(0:0)} {intermediate 2} {output sdio_inst:SDMMC_CMD_O(0:0)} {intermediate 1} {output emac1_inst:EMAC_GMII_MDO_OE(0:0)} {intermediate 0} {output emac1_inst:EMAC_GMII_MDO_O(0:0)} {intermediate 19} {output usb1_inst:USB_ULPI_DATA_OE(3:3)} {intermediate 18} {output usb1_inst:USB_ULPI_DATA_O(3:3)} {intermediate 17} {output usb1_inst:USB_ULPI_DATA_OE(2:2)} {intermediate 16} {output usb1_inst:USB_ULPI_DATA_O(2:2)} {intermediate 47} {output gpio_inst:GPIO2_PORTA_OE(3:3)} {intermediate 15} {output usb1_inst:USB_ULPI_DATA_OE(1:1)} {intermediate 46} {output gpio_inst:GPIO2_PORTA_O(3:3)} {intermediate 14} {output usb1_inst:USB_ULPI_DATA_O(1:1)} {intermediate 45} {output gpio_inst:GPIO1_PORTA_OE(25:25)} {intermediate 13} {output usb1_inst:USB_ULPI_DATA_OE(0:0)} {intermediate 44} {output gpio_inst:GPIO1_PORTA_O(25:25)} {intermediate 12} {output usb1_inst:USB_ULPI_DATA_O(0:0)} {intermediate 43} {output gpio_inst:GPIO1_PORTA_OE(24:24)} {intermediate 11} {output sdio_inst:SDMMC_DATA_OE(3:3)} {intermediate 42} {output gpio_inst:GPIO1_PORTA_O(24:24)} {intermediate 10} {output sdio_inst:SDMMC_DATA_O(3:3)} {intermediate 41} {output gpio_inst:GPIO1_PORTA_OE(19:19)} {intermediate 40} {output gpio_inst:GPIO1_PORTA_O(19:19)} {intermediate 39} {output gpio_inst:GPIO1_PORTA_OE(11:11)} {intermediate 38} {output gpio_inst:GPIO1_PORTA_O(11:11)} {intermediate 37} {output gpio_inst:GPIO1_PORTA_OE(6:6)} {intermediate 36} {output gpio_inst:GPIO1_PORTA_O(6:6)} {intermediate 35} {output gpio_inst:GPIO0_PORTA_OE(9:9)} {intermediate 34} {output gpio_inst:GPIO0_PORTA_O(9:9)} {intermediate 33} {output i2c1_inst:I2C_CLK_OE(0:0)} {intermediate 32} {output i2c1_inst:I2C_DATA_OE(0:0)} {intermediate 31} {output i2c0_inst:I2C_CLK_OE(0:0)} {intermediate 30} {output i2c0_inst:I2C_DATA_OE(0:0)} {intermediate 29} {output spim1_inst:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 28} {output spim1_inst:SPI_MASTER_TXD(0:0)} {intermediate 27} {output usb1_inst:USB_ULPI_DATA_OE(7:7)} {intermediate 26} {output usb1_inst:USB_ULPI_DATA_O(7:7)} {intermediate 25} {output usb1_inst:USB_ULPI_DATA_OE(6:6)} {intermediate 24} {output usb1_inst:USB_ULPI_DATA_O(6:6)} {intermediate 23} {output usb1_inst:USB_ULPI_DATA_OE(5:5)} {intermediate 22} {output usb1_inst:USB_ULPI_DATA_O(5:5)} {intermediate 21} {output usb1_inst:USB_ULPI_DATA_OE(4:4)} {intermediate 20} {output usb1_inst:USB_ULPI_DATA_O(4:4)}} raw_assign_sim_style {},qipEntries={set_instance_assignment -name hps_partition on -entity %entityName% -library %libraryName%}))(hps_clk_src:21.1:)(hps_bridge_avalon:21.1:BONDING_OUT_ENABLED=false,F2H_SDRAM0_CLOCK_FREQ=100,F2H_SDRAM1_CLOCK_FREQ=100,F2H_SDRAM2_CLOCK_FREQ=100,F2H_SDRAM3_CLOCK_FREQ=100,F2H_SDRAM4_CLOCK_FREQ=100,F2H_SDRAM5_CLOCK_FREQ=100,F2SDRAM_Type=,F2SDRAM_Width=,F2S_Width=2,LWH2F_Enable=true,S2F_Width=2,address_map=&lt;address-map&gt;&lt;slave name=&apos;axi_sdram.axi_slave0&apos; start=&apos;0x0&apos; end=&apos;0x80000000&apos; /&gt;&lt;slave name=&apos;gmac0.axi_slave0&apos; start=&apos;0xFF700000&apos; end=&apos;0xFF702000&apos; /&gt;&lt;slave name=&apos;gmac1.axi_slave0&apos; start=&apos;0xFF702000&apos; end=&apos;0xFF704000&apos; /&gt;&lt;slave name=&apos;sdmmc.axi_slave0&apos; start=&apos;0xFF704000&apos; end=&apos;0xFF705000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave0&apos; start=&apos;0xFF705000&apos; end=&apos;0xFF705100&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave0&apos; start=&apos;0xFF706000&apos; end=&apos;0xFF707000&apos; /&gt;&lt;slave name=&apos;gpio0.axi_slave0&apos; start=&apos;0xFF708000&apos; end=&apos;0xFF708100&apos; /&gt;&lt;slave name=&apos;gpio1.axi_slave0&apos; start=&apos;0xFF709000&apos; end=&apos;0xFF709100&apos; /&gt;&lt;slave name=&apos;gpio2.axi_slave0&apos; start=&apos;0xFF70A000&apos; end=&apos;0xFF70A100&apos; /&gt;&lt;slave name=&apos;l3regs.axi_slave0&apos; start=&apos;0xFF800000&apos; end=&apos;0xFF801000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave0&apos; start=&apos;0xFF900000&apos; end=&apos;0xFF910000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave1&apos; start=&apos;0xFFA00000&apos; end=&apos;0xFFA00100&apos; /&gt;&lt;slave name=&apos;usb0.axi_slave0&apos; start=&apos;0xFFB00000&apos; end=&apos;0xFFB40000&apos; /&gt;&lt;slave name=&apos;usb1.axi_slave0&apos; start=&apos;0xFFB40000&apos; end=&apos;0xFFB80000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave1&apos; start=&apos;0xFFB80000&apos; end=&apos;0xFFB90000&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave1&apos; start=&apos;0xFFB90000&apos; end=&apos;0xFFB90100&apos; /&gt;&lt;slave name=&apos;dcan0.axi_slave0&apos; start=&apos;0xFFC00000&apos; end=&apos;0xFFC01000&apos; /&gt;&lt;slave name=&apos;dcan1.axi_slave0&apos; start=&apos;0xFFC01000&apos; end=&apos;0xFFC02000&apos; /&gt;&lt;slave name=&apos;uart0.axi_slave0&apos; start=&apos;0xFFC02000&apos; end=&apos;0xFFC02100&apos; /&gt;&lt;slave name=&apos;uart1.axi_slave0&apos; start=&apos;0xFFC03000&apos; end=&apos;0xFFC03100&apos; /&gt;&lt;slave name=&apos;i2c0.axi_slave0&apos; start=&apos;0xFFC04000&apos; end=&apos;0xFFC04100&apos; /&gt;&lt;slave name=&apos;i2c1.axi_slave0&apos; start=&apos;0xFFC05000&apos; end=&apos;0xFFC05100&apos; /&gt;&lt;slave name=&apos;i2c2.axi_slave0&apos; start=&apos;0xFFC06000&apos; end=&apos;0xFFC06100&apos; /&gt;&lt;slave name=&apos;i2c3.axi_slave0&apos; start=&apos;0xFFC07000&apos; end=&apos;0xFFC07100&apos; /&gt;&lt;slave name=&apos;timer0.axi_slave0&apos; start=&apos;0xFFC08000&apos; end=&apos;0xFFC08100&apos; /&gt;&lt;slave name=&apos;timer1.axi_slave0&apos; start=&apos;0xFFC09000&apos; end=&apos;0xFFC09100&apos; /&gt;&lt;slave name=&apos;sdrctl.axi_slave0&apos; start=&apos;0xFFC25000&apos; end=&apos;0xFFC26000&apos; /&gt;&lt;slave name=&apos;timer2.axi_slave0&apos; start=&apos;0xFFD00000&apos; end=&apos;0xFFD00100&apos; /&gt;&lt;slave name=&apos;timer3.axi_slave0&apos; start=&apos;0xFFD01000&apos; end=&apos;0xFFD01100&apos; /&gt;&lt;slave name=&apos;clkmgr.axi_slave0&apos; start=&apos;0xFFD04000&apos; end=&apos;0xFFD05000&apos; /&gt;&lt;slave name=&apos;rstmgr.axi_slave0&apos; start=&apos;0xFFD05000&apos; end=&apos;0xFFD05100&apos; /&gt;&lt;slave name=&apos;sysmgr.axi_slave0&apos; start=&apos;0xFFD08000&apos; end=&apos;0xFFD08400&apos; /&gt;&lt;slave name=&apos;dma.axi_slave0&apos; start=&apos;0xFFE01000&apos; end=&apos;0xFFE02000&apos; /&gt;&lt;slave name=&apos;spim0.axi_slave0&apos; start=&apos;0xFFF00000&apos; end=&apos;0xFFF00100&apos; /&gt;&lt;slave name=&apos;spim1.axi_slave0&apos; start=&apos;0xFFF01000&apos; end=&apos;0xFFF01100&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave1&apos; start=&apos;0xFFFEC100&apos; end=&apos;0xFFFEC200&apos; /&gt;&lt;slave name=&apos;timer.axi_slave0&apos; start=&apos;0xFFFEC600&apos; end=&apos;0xFFFEC700&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave0&apos; start=&apos;0xFFFED000&apos; end=&apos;0xFFFEE000&apos; /&gt;&lt;slave name=&apos;L2.axi_slave0&apos; start=&apos;0xFFFEF000&apos; end=&apos;0xFFFF0000&apos; /&gt;&lt;slave name=&apos;axi_ocram.axi_slave0&apos; start=&apos;0xFFFF0000&apos; end=&apos;0x100000000&apos; /&gt;&lt;/address-map&gt;,quartus_ini_hps_ip_f2sdram_bonding_out=false)(hps_virt_clk:21.1:clockFrequency=25000000)(hps_virt_clk:21.1:clockFrequency=25000000)(hps_virt_clk:21.1:clockFrequency=0)(hps_virt_clk:21.1:clockFrequency=0)(arm_a9:21.1:address_map=&lt;address-map&gt;&lt;slave name=&apos;axi_sdram.axi_slave0&apos; start=&apos;0x0&apos; end=&apos;0x80000000&apos; /&gt;&lt;slave name=&apos;bridges.axi_h2f&apos; start=&apos;0xC0000000&apos; end=&apos;0xE0000000&apos; /&gt;&lt;slave name=&apos;bridges.axi_h2f_lw&apos; start=&apos;0xFF200000&apos; end=&apos;0xFF400000&apos; /&gt;&lt;slave name=&apos;gmac0.axi_slave0&apos; start=&apos;0xFF700000&apos; end=&apos;0xFF702000&apos; /&gt;&lt;slave name=&apos;gmac1.axi_slave0&apos; start=&apos;0xFF702000&apos; end=&apos;0xFF704000&apos; /&gt;&lt;slave name=&apos;sdmmc.axi_slave0&apos; start=&apos;0xFF704000&apos; end=&apos;0xFF705000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave0&apos; start=&apos;0xFF705000&apos; end=&apos;0xFF705100&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave0&apos; start=&apos;0xFF706000&apos; end=&apos;0xFF707000&apos; /&gt;&lt;slave name=&apos;gpio0.axi_slave0&apos; start=&apos;0xFF708000&apos; end=&apos;0xFF708100&apos; /&gt;&lt;slave name=&apos;gpio1.axi_slave0&apos; start=&apos;0xFF709000&apos; end=&apos;0xFF709100&apos; /&gt;&lt;slave name=&apos;gpio2.axi_slave0&apos; start=&apos;0xFF70A000&apos; end=&apos;0xFF70A100&apos; /&gt;&lt;slave name=&apos;l3regs.axi_slave0&apos; start=&apos;0xFF800000&apos; end=&apos;0xFF801000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave0&apos; start=&apos;0xFF900000&apos; end=&apos;0xFF910000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave1&apos; start=&apos;0xFFA00000&apos; end=&apos;0xFFA00100&apos; /&gt;&lt;slave name=&apos;usb0.axi_slave0&apos; start=&apos;0xFFB00000&apos; end=&apos;0xFFB40000&apos; /&gt;&lt;slave name=&apos;usb1.axi_slave0&apos; start=&apos;0xFFB40000&apos; end=&apos;0xFFB80000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave1&apos; start=&apos;0xFFB80000&apos; end=&apos;0xFFB90000&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave1&apos; start=&apos;0xFFB90000&apos; end=&apos;0xFFB90100&apos; /&gt;&lt;slave name=&apos;dcan0.axi_slave0&apos; start=&apos;0xFFC00000&apos; end=&apos;0xFFC01000&apos; /&gt;&lt;slave name=&apos;dcan1.axi_slave0&apos; start=&apos;0xFFC01000&apos; end=&apos;0xFFC02000&apos; /&gt;&lt;slave name=&apos;uart0.axi_slave0&apos; start=&apos;0xFFC02000&apos; end=&apos;0xFFC02100&apos; /&gt;&lt;slave name=&apos;uart1.axi_slave0&apos; start=&apos;0xFFC03000&apos; end=&apos;0xFFC03100&apos; /&gt;&lt;slave name=&apos;i2c0.axi_slave0&apos; start=&apos;0xFFC04000&apos; end=&apos;0xFFC04100&apos; /&gt;&lt;slave name=&apos;i2c1.axi_slave0&apos; start=&apos;0xFFC05000&apos; end=&apos;0xFFC05100&apos; /&gt;&lt;slave name=&apos;i2c2.axi_slave0&apos; start=&apos;0xFFC06000&apos; end=&apos;0xFFC06100&apos; /&gt;&lt;slave name=&apos;i2c3.axi_slave0&apos; start=&apos;0xFFC07000&apos; end=&apos;0xFFC07100&apos; /&gt;&lt;slave name=&apos;timer0.axi_slave0&apos; start=&apos;0xFFC08000&apos; end=&apos;0xFFC08100&apos; /&gt;&lt;slave name=&apos;timer1.axi_slave0&apos; start=&apos;0xFFC09000&apos; end=&apos;0xFFC09100&apos; /&gt;&lt;slave name=&apos;sdrctl.axi_slave0&apos; start=&apos;0xFFC25000&apos; end=&apos;0xFFC26000&apos; /&gt;&lt;slave name=&apos;timer2.axi_slave0&apos; start=&apos;0xFFD00000&apos; end=&apos;0xFFD00100&apos; /&gt;&lt;slave name=&apos;timer3.axi_slave0&apos; start=&apos;0xFFD01000&apos; end=&apos;0xFFD01100&apos; /&gt;&lt;slave name=&apos;wd_timer0.axi_slave0&apos; start=&apos;0xFFD02000&apos; end=&apos;0xFFD02100&apos; /&gt;&lt;slave name=&apos;wd_timer1.axi_slave0&apos; start=&apos;0xFFD03000&apos; end=&apos;0xFFD03100&apos; /&gt;&lt;slave name=&apos;clkmgr.axi_slave0&apos; start=&apos;0xFFD04000&apos; end=&apos;0xFFD05000&apos; /&gt;&lt;slave name=&apos;rstmgr.axi_slave0&apos; start=&apos;0xFFD05000&apos; end=&apos;0xFFD05100&apos; /&gt;&lt;slave name=&apos;sysmgr.axi_slave0&apos; start=&apos;0xFFD08000&apos; end=&apos;0xFFD08400&apos; /&gt;&lt;slave name=&apos;dma.axi_slave0&apos; start=&apos;0xFFE01000&apos; end=&apos;0xFFE02000&apos; /&gt;&lt;slave name=&apos;spim0.axi_slave0&apos; start=&apos;0xFFF00000&apos; end=&apos;0xFFF00100&apos; /&gt;&lt;slave name=&apos;spim1.axi_slave0&apos; start=&apos;0xFFF01000&apos; end=&apos;0xFFF01100&apos; /&gt;&lt;slave name=&apos;scu.axi_slave0&apos; start=&apos;0xFFFEC000&apos; end=&apos;0xFFFEC100&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave1&apos; start=&apos;0xFFFEC100&apos; end=&apos;0xFFFEC200&apos; /&gt;&lt;slave name=&apos;timer.axi_slave0&apos; start=&apos;0xFFFEC600&apos; end=&apos;0xFFFEC700&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave0&apos; start=&apos;0xFFFED000&apos; end=&apos;0xFFFEE000&apos; /&gt;&lt;slave name=&apos;L2.axi_slave0&apos; start=&apos;0xFFFEF000&apos; end=&apos;0xFFFF0000&apos; /&gt;&lt;slave name=&apos;axi_ocram.axi_slave0&apos; start=&apos;0xFFFF0000&apos; end=&apos;0x100000000&apos; /&gt;&lt;/address-map&gt;)(arm_a9:21.1:address_map=&lt;address-map&gt;&lt;slave name=&apos;axi_sdram.axi_slave0&apos; start=&apos;0x0&apos; end=&apos;0x80000000&apos; /&gt;&lt;slave name=&apos;bridges.axi_h2f&apos; start=&apos;0xC0000000&apos; end=&apos;0xE0000000&apos; /&gt;&lt;slave name=&apos;bridges.axi_h2f_lw&apos; start=&apos;0xFF200000&apos; end=&apos;0xFF400000&apos; /&gt;&lt;slave name=&apos;gmac0.axi_slave0&apos; start=&apos;0xFF700000&apos; end=&apos;0xFF702000&apos; /&gt;&lt;slave name=&apos;gmac1.axi_slave0&apos; start=&apos;0xFF702000&apos; end=&apos;0xFF704000&apos; /&gt;&lt;slave name=&apos;sdmmc.axi_slave0&apos; start=&apos;0xFF704000&apos; end=&apos;0xFF705000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave0&apos; start=&apos;0xFF705000&apos; end=&apos;0xFF705100&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave0&apos; start=&apos;0xFF706000&apos; end=&apos;0xFF707000&apos; /&gt;&lt;slave name=&apos;gpio0.axi_slave0&apos; start=&apos;0xFF708000&apos; end=&apos;0xFF708100&apos; /&gt;&lt;slave name=&apos;gpio1.axi_slave0&apos; start=&apos;0xFF709000&apos; end=&apos;0xFF709100&apos; /&gt;&lt;slave name=&apos;gpio2.axi_slave0&apos; start=&apos;0xFF70A000&apos; end=&apos;0xFF70A100&apos; /&gt;&lt;slave name=&apos;l3regs.axi_slave0&apos; start=&apos;0xFF800000&apos; end=&apos;0xFF801000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave0&apos; start=&apos;0xFF900000&apos; end=&apos;0xFF910000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave1&apos; start=&apos;0xFFA00000&apos; end=&apos;0xFFA00100&apos; /&gt;&lt;slave name=&apos;usb0.axi_slave0&apos; start=&apos;0xFFB00000&apos; end=&apos;0xFFB40000&apos; /&gt;&lt;slave name=&apos;usb1.axi_slave0&apos; start=&apos;0xFFB40000&apos; end=&apos;0xFFB80000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave1&apos; start=&apos;0xFFB80000&apos; end=&apos;0xFFB90000&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave1&apos; start=&apos;0xFFB90000&apos; end=&apos;0xFFB90100&apos; /&gt;&lt;slave name=&apos;dcan0.axi_slave0&apos; start=&apos;0xFFC00000&apos; end=&apos;0xFFC01000&apos; /&gt;&lt;slave name=&apos;dcan1.axi_slave0&apos; start=&apos;0xFFC01000&apos; end=&apos;0xFFC02000&apos; /&gt;&lt;slave name=&apos;uart0.axi_slave0&apos; start=&apos;0xFFC02000&apos; end=&apos;0xFFC02100&apos; /&gt;&lt;slave name=&apos;uart1.axi_slave0&apos; start=&apos;0xFFC03000&apos; end=&apos;0xFFC03100&apos; /&gt;&lt;slave name=&apos;i2c0.axi_slave0&apos; start=&apos;0xFFC04000&apos; end=&apos;0xFFC04100&apos; /&gt;&lt;slave name=&apos;i2c1.axi_slave0&apos; start=&apos;0xFFC05000&apos; end=&apos;0xFFC05100&apos; /&gt;&lt;slave name=&apos;i2c2.axi_slave0&apos; start=&apos;0xFFC06000&apos; end=&apos;0xFFC06100&apos; /&gt;&lt;slave name=&apos;i2c3.axi_slave0&apos; start=&apos;0xFFC07000&apos; end=&apos;0xFFC07100&apos; /&gt;&lt;slave name=&apos;timer0.axi_slave0&apos; start=&apos;0xFFC08000&apos; end=&apos;0xFFC08100&apos; /&gt;&lt;slave name=&apos;timer1.axi_slave0&apos; start=&apos;0xFFC09000&apos; end=&apos;0xFFC09100&apos; /&gt;&lt;slave name=&apos;sdrctl.axi_slave0&apos; start=&apos;0xFFC25000&apos; end=&apos;0xFFC26000&apos; /&gt;&lt;slave name=&apos;timer2.axi_slave0&apos; start=&apos;0xFFD00000&apos; end=&apos;0xFFD00100&apos; /&gt;&lt;slave name=&apos;timer3.axi_slave0&apos; start=&apos;0xFFD01000&apos; end=&apos;0xFFD01100&apos; /&gt;&lt;slave name=&apos;wd_timer0.axi_slave0&apos; start=&apos;0xFFD02000&apos; end=&apos;0xFFD02100&apos; /&gt;&lt;slave name=&apos;wd_timer1.axi_slave0&apos; start=&apos;0xFFD03000&apos; end=&apos;0xFFD03100&apos; /&gt;&lt;slave name=&apos;clkmgr.axi_slave0&apos; start=&apos;0xFFD04000&apos; end=&apos;0xFFD05000&apos; /&gt;&lt;slave name=&apos;rstmgr.axi_slave0&apos; start=&apos;0xFFD05000&apos; end=&apos;0xFFD05100&apos; /&gt;&lt;slave name=&apos;sysmgr.axi_slave0&apos; start=&apos;0xFFD08000&apos; end=&apos;0xFFD08400&apos; /&gt;&lt;slave name=&apos;dma.axi_slave0&apos; start=&apos;0xFFE01000&apos; end=&apos;0xFFE02000&apos; /&gt;&lt;slave name=&apos;spim0.axi_slave0&apos; start=&apos;0xFFF00000&apos; end=&apos;0xFFF00100&apos; /&gt;&lt;slave name=&apos;spim1.axi_slave0&apos; start=&apos;0xFFF01000&apos; end=&apos;0xFFF01100&apos; /&gt;&lt;slave name=&apos;scu.axi_slave0&apos; start=&apos;0xFFFEC000&apos; end=&apos;0xFFFEC100&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave1&apos; start=&apos;0xFFFEC100&apos; end=&apos;0xFFFEC200&apos; /&gt;&lt;slave name=&apos;timer.axi_slave0&apos; start=&apos;0xFFFEC600&apos; end=&apos;0xFFFEC700&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave0&apos; start=&apos;0xFFFED000&apos; end=&apos;0xFFFEE000&apos; /&gt;&lt;slave name=&apos;L2.axi_slave0&apos; start=&apos;0xFFFEF000&apos; end=&apos;0xFFFF0000&apos; /&gt;&lt;slave name=&apos;axi_ocram.axi_slave0&apos; start=&apos;0xFFFF0000&apos; end=&apos;0x100000000&apos; /&gt;&lt;/address-map&gt;)(arm_gic:21.1:AUTO_ARM_GIC_PPI_INTERRUPTS_USED=8192,AUTO_F2H_IRQ_0_IRQ_RX_OFFSET_40_INTERRUPTS_USED=0,AUTO_F2H_IRQ_32_IRQ_RX_OFFSET_72_INTERRUPTS_USED=0,AUTO_IRQ_RX_OFFSET_0_INTERRUPTS_USED=0,AUTO_IRQ_RX_OFFSET_104_INTERRUPTS_USED=2569078785,AUTO_IRQ_RX_OFFSET_136_INTERRUPTS_USED=1070366985,AUTO_IRQ_RX_OFFSET_166_INTERRUPTS_USED=639,AUTO_IRQ_RX_OFFSET_32_INTERRUPTS_USED=64)(arm_pl310_L2:21.1:)(arm_pl330_dma:21.1:)(altera_sysmgr:21.1:cpu1_start_addr=4291854532)(asimov_clkmgr:21.1:F2SCLK_PERIPHCLK_Enable=false,F2SCLK_PERIPHCLK_FREQ=0,F2SCLK_PERIPHCLK_FREQ_MHZ=0.0,F2SCLK_SDRAMCLK_Enable=false,F2SCLK_SDRAMCLK_FREQ=0,F2SCLK_SDRAMCLK_FREQ_MHZ=0.0,S2FCLK_USER0CLK_Enable=false,S2FCLK_USER0CLK_FREQ=0.0,S2FCLK_USER0CLK_FREQ_HZ=0,S2FCLK_USER1CLK_Enable=true,S2FCLK_USER1CLK_FREQ=100.0,S2FCLK_USER1CLK_FREQ_HZ=0,S2FCLK_USER2CLK=5,S2FCLK_USER2CLK_Enable=false,S2FCLK_USER2CLK_FREQ=100.0,S2FCLK_USER2CLK_FREQ_HZ=0,can0_clk_div=1,can0_clk_div_auto=0,can0_clk_hz=0,can0_clk_mhz=0.0,can1_clk_div=1,can1_clk_div_auto=0,can1_clk_hz=0,can1_clk_mhz=0.0,cfg_clk_hz=0,cfg_clk_mhz=0.0,cfg_h2f_user0_clk_hz=0,cfg_h2f_user0_clk_mhz=0.0,configure_advanced_parameters=false,customize_device_pll_info=false,dbctrl_stayosc1=true,dbg_at_clk_div=0,dbg_at_clk_hz=0,dbg_at_clk_mhz=0.0,dbg_base_clk_hz=0,dbg_base_clk_mhz=0.0,dbg_clk_div=1,dbg_clk_hz=0,dbg_clk_mhz=0.0,dbg_timer_clk_hz=0,dbg_timer_clk_mhz=0.0,dbg_trace_clk_div=0,dbg_trace_clk_hz=0,dbg_trace_clk_mhz=0.0,default_mpu_clk_hz=0,default_mpu_clk_mhz=0.0,desired_can0_clk_hz=0,desired_can0_clk_mhz=100.0,desired_can1_clk_hz=0,desired_can1_clk_mhz=100.0,desired_cfg_clk_hz=0,desired_cfg_clk_mhz=97.368421,desired_emac0_clk_hz=0,desired_emac0_clk_mhz=250.0,desired_emac1_clk_hz=0,desired_emac1_clk_mhz=250.0,desired_gpio_db_clk_hz=32000,desired_l4_mp_clk_hz=0,desired_l4_mp_clk_mhz=100.0,desired_l4_sp_clk_hz=0,desired_l4_sp_clk_mhz=100.0,desired_mpu_clk_hz=0,desired_mpu_clk_mhz=800.0,desired_nand_clk_hz=0,desired_nand_clk_mhz=12.5,desired_qspi_clk_hz=0,desired_qspi_clk_mhz=400.0,desired_sdmmc_clk_hz=0,desired_sdmmc_clk_mhz=200.0,desired_spi_m_clk_hz=0,desired_spi_m_clk_mhz=200.0,desired_usb_mp_clk_hz=0,desired_usb_mp_clk_mhz=200.0,device_pll_info_auto=,device_pll_info_manual={320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000},emac0_clk_hz=0,emac0_clk_mhz=0.0,emac1_clk_hz=0,emac1_clk_mhz=0.0,eosc1_clk_hz=0,eosc1_clk_mhz=25.0,eosc2_clk_hz=0,eosc2_clk_mhz=25.0,gpio_db_clk_div=6249,gpio_db_clk_div_auto=1,gpio_db_clk_hz=0,h2f_user0_clk_hz=0,h2f_user0_clk_mhz=0.0,h2f_user1_clk_hz=0,h2f_user1_clk_mhz=0.0,l3_mp_clk_div=1,l3_mp_clk_hz=0,l3_mp_clk_mhz=0.0,l3_sp_clk_div=1,l3_sp_clk_hz=0,l3_sp_clk_mhz=0.0,l4_mp_clk_div=1,l4_mp_clk_div_auto=0,l4_mp_clk_hz=0,l4_mp_clk_mhz=0.0,l4_mp_clk_source=1,l4_sp_clk_div=1,l4_sp_clk_div_auto=0,l4_sp_clk_hz=0,l4_sp_clk_mhz=0.0,l4_sp_clk_source=1,main_clk_hz=0,main_clk_mhz=0.0,main_nand_sdmmc_clk_hz=0,main_nand_sdmmc_clk_mhz=0.0,main_pll_c0_internal=0,main_pll_c0_internal_auto=0,main_pll_c1_internal=0,main_pll_c1_internal_auto=0,main_pll_c2_internal=0,main_pll_c2_internal_auto=0,main_pll_c3=3,main_pll_c3_auto=0,main_pll_c4=3,main_pll_c4_auto=0,main_pll_c5=15,main_pll_c5_auto=0,main_pll_m=63,main_pll_m_auto=0,main_pll_n=0,main_pll_n_auto=0,main_pll_vco_auto_hz=0,main_pll_vco_auto_mhz=0.0,main_pll_vco_hz=0,main_pll_vco_mhz=0.0,main_qspi_clk_hz=0,main_qspi_clk_mhz=0.0,mpu_base_clk_hz=0,mpu_base_clk_mhz=0.0,mpu_clk_hz=0,mpu_clk_mhz=0.0,mpu_l2_ram_clk_hz=0,mpu_l2_ram_clk_mhz=0.0,mpu_periph_clk_hz=0,mpu_periph_clk_mhz=0.0,nand_clk_hz=0,nand_clk_mhz=0.0,nand_clk_source=2,nand_x_clk_hz=0,nand_x_clk_mhz=0.0,periph_base_clk_hz=0,periph_base_clk_mhz=0.0,periph_nand_sdmmc_clk_hz=0,periph_nand_sdmmc_clk_mhz=0.0,periph_pll_c0=3,periph_pll_c0_auto=0,periph_pll_c1=3,periph_pll_c1_auto=0,periph_pll_c2=1,periph_pll_c2_auto=0,periph_pll_c3=19,periph_pll_c3_auto=0,periph_pll_c4=4,periph_pll_c4_auto=0,periph_pll_c5=9,periph_pll_c5_auto=0,periph_pll_m=79,periph_pll_m_auto=0,periph_pll_n=1,periph_pll_n_auto=0,periph_pll_source=0,periph_pll_vco_auto_hz=0,periph_pll_vco_auto_mhz=0.0,periph_pll_vco_hz=0,periph_pll_vco_mhz=0.0,periph_qspi_clk_hz=0,periph_qspi_clk_mhz=0.0,qspi_clk_hz=0,qspi_clk_mhz=0.0,qspi_clk_source=1,sdmmc_clk_hz=0,sdmmc_clk_mhz=0.0,sdmmc_clk_source=2,show_advanced_parameters=false,show_debug_info_as_warning_msg=false,show_warning_as_error_msg=false,spi_m_clk_div=0,spi_m_clk_div_auto=0,spi_m_clk_hz=0,spi_m_clk_mhz=0.0,usb_mp_clk_div=0,usb_mp_clk_div_auto=0,usb_mp_clk_hz=0,usb_mp_clk_mhz=0.0,use_default_mpu_clk=true)(altera_rstmgr:21.1:offset=16)(altera_fpgamgr:21.1:compatible=altr,fpga-mgr altr,socfpga-fpga-mgr)(snps_uart:21.1:clk_freq_mhz=100.0,swEnabled=true)(snps_uart:21.1:clk_freq_mhz=100.0,swEnabled=false)(dw_apb_timer_sp:21.1:)(dw_apb_timer_sp:21.1:)(dw_apb_timer_osc:21.1:)(dw_apb_timer_osc:21.1:)(dw_wd_timer:21.1:)(dw_wd_timer:21.1:)(dw_gpio:21.1:embeddedsw.dts.instance.GPIO_PORTA_INTR=1,embeddedsw.dts.instance.GPIO_PWIDTH_A=29,embeddedsw.dts.instance.GPIO_PWIDTH_B=0,embeddedsw.dts.instance.GPIO_PWIDTH_C=0,embeddedsw.dts.instance.GPIO_PWIDTH_D=0)(dw_gpio:21.1:embeddedsw.dts.instance.GPIO_PORTA_INTR=1,embeddedsw.dts.instance.GPIO_PWIDTH_A=29,embeddedsw.dts.instance.GPIO_PWIDTH_B=0,embeddedsw.dts.instance.GPIO_PWIDTH_C=0,embeddedsw.dts.instance.GPIO_PWIDTH_D=0)(dw_gpio:21.1:embeddedsw.dts.instance.GPIO_PORTA_INTR=1,embeddedsw.dts.instance.GPIO_PWIDTH_A=27,embeddedsw.dts.instance.GPIO_PWIDTH_B=0,embeddedsw.dts.instance.GPIO_PWIDTH_C=0,embeddedsw.dts.instance.GPIO_PWIDTH_D=0)(designware_i2c:21.1:swEnabled=true)(designware_i2c:21.1:swEnabled=true)(designware_i2c:21.1:swEnabled=false)(designware_i2c:21.1:swEnabled=false)(denali_nand:21.1:swEnabled=false)(spi:21.1:swEnabled=false)(spi:21.1:swEnabled=true)(cadence_qspi:21.1:swEnabled=false)(sdmmc:21.1:swEnabled=true)(usb:21.1:swEnabled=false)(usb:21.1:swEnabled=true)(stmmac:21.1:compatible=altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac,rx_fifo_depth=4096,swEnabled=false,tx_fifo_depth=4096)(stmmac:21.1:compatible=altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac,rx_fifo_depth=4096,swEnabled=true,tx_fifo_depth=4096)(bosch_dcan:21.1:swEnabled=false)(bosch_dcan:21.1:swEnabled=false)(altera_l3regs:21.1:)(altera_sdrctl:21.1:)(axi_ocram:21.1:)(axi_sdram:21.1:)(arm_internal_timer:21.1:)(scu:21.1:)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xc0000000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xc0000000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff200000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff200000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(reset:21.1:)(clock:21.1:)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffed000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffed000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec100,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec100,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffef000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffef000,defaultConnection=false)(interrupt:21.1:irqNumber=6)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffe01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffe01000,defaultConnection=false)(interrupt:21.1:irqNumber=0)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd08000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd08000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd04000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd04000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd05000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd05000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff706000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff706000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb90000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb90000,defaultConnection=false)(interrupt:21.1:irqNumber=9)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc02000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc02000,defaultConnection=false)(interrupt:21.1:irqNumber=26)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc03000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc03000,defaultConnection=false)(interrupt:21.1:irqNumber=27)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc08000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc08000,defaultConnection=false)(interrupt:21.1:irqNumber=1)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc09000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc09000,defaultConnection=false)(interrupt:21.1:irqNumber=2)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd00000,defaultConnection=false)(interrupt:21.1:irqNumber=3)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd01000,defaultConnection=false)(interrupt:21.1:irqNumber=4)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd02000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd02000,defaultConnection=false)(interrupt:21.1:irqNumber=5)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd03000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd03000,defaultConnection=false)(interrupt:21.1:irqNumber=6)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff708000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff708000,defaultConnection=false)(interrupt:21.1:irqNumber=28)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff709000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff709000,defaultConnection=false)(interrupt:21.1:irqNumber=29)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff70a000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff70a000,defaultConnection=false)(interrupt:21.1:irqNumber=0)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc04000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc04000,defaultConnection=false)(interrupt:21.1:irqNumber=22)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc05000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc05000,defaultConnection=false)(interrupt:21.1:irqNumber=23)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc06000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc06000,defaultConnection=false)(interrupt:21.1:irqNumber=24)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc07000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc07000,defaultConnection=false)(interrupt:21.1:irqNumber=25)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff900000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff900000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb80000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb80000,defaultConnection=false)(interrupt:21.1:irqNumber=8)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff00000,defaultConnection=false)(interrupt:21.1:irqNumber=18)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff01000,defaultConnection=false)(interrupt:21.1:irqNumber=19)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff705000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff705000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffa00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffa00000,defaultConnection=false)(interrupt:21.1:irqNumber=15)(reset:21.1:)(clock:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff704000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff704000,defaultConnection=false)(interrupt:21.1:irqNumber=3)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb00000,defaultConnection=false)(interrupt:21.1:irqNumber=21)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb40000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb40000,defaultConnection=false)(interrupt:21.1:irqNumber=24)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff700000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff700000,defaultConnection=false)(interrupt:21.1:irqNumber=11)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff702000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff702000,defaultConnection=false)(interrupt:21.1:irqNumber=16)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc00000,defaultConnection=false)(interrupt:21.1:irqNumber=27)(interrupt:21.1:irqNumber=28)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc01000,defaultConnection=false)(interrupt:21.1:irqNumber=31)(interrupt:21.1:irqNumber=0)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff800000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff800000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc25000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc25000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffff0000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffff0000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec600,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec600,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec000,defaultConnection=false)(interrupt:21.1:irqNumber=13)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffed000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec100,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffef000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffe01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd08000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd04000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd05000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff706000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb90000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc02000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc03000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc08000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc09000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff708000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff709000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff70a000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc04000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc05000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc06000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc07000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff900000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb80000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff705000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffa00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff704000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb40000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff700000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff702000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffff0000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec600,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff800000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc25000,defaultConnection=false))(avalon:21.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0x00040000,defaultConnection=false)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(reset:21.1:)(reset:21.1:)"
   instancePathKey="soc_system"
   kind="soc_system"
   version="1.0"
   name="soc_system">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_GENERATION_ID" value="1747276302" />
  <parameter name="AUTO_DEVICE" value="5CSEMA5F31C6" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/soc_system.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_RAM.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_RAM.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv"
       type="SYSTEM_VERILOG"
       attributes="TOP_LEVEL_FILE" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/primal_update.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/residual_calculator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/slack_update.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/memory_interface.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0.v"
       type="VERILOG" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sdc"
       type="SDC"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v"
       type="VERILOG" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_inst_ROM.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_AC_ROM.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sdram_io.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/alt_types.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/system.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/tclrpt.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/tclrpt.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_defines.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/emif.pre.xml"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_parameters.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_pin_map.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_report_timing_core.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_report_timing.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_timing.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.sdc"
       type="SDC"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.ppf"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_pll.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sdc"
       type="SDC"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps.pre.xml"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v"
       type="VERILOG" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_slave_translator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_slave_agent.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_incr_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_wrap_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_default_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_width_adapter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v"
       type="VERILOG" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v"
       type="VERILOG" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_reset_controller.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_reset_synchronizer.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_reset_controller.sdc"
       type="SDC"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system.qsys" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/admm_solver_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_hps/altera_hps_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_interface_generator/altera_interface_generator_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_hps_io/altera_hps_io_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_interface_generator/altera_interface_generator_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_axi_master_ni/altera_merlin_axi_master_ni_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
  </childSourceFiles>
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 0 starting:soc_system "soc_system"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>4</b> modules, <b>9</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>4</b> modules, <b>7</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug" culprit="merlin_translator_transform"><![CDATA[After transform: <b>6</b> modules, <b>13</b> connections]]></message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces admm_solver_0_avalon_slave_0_translator.avalon_anti_slave_0 and admm_solver_0.avalon_slave_0</message>
   <message level="Debug">Transform merlin_domain_transform not run on matched interfaces RAM_s1_translator.avalon_anti_slave_0 and RAM.s1</message>
   <message level="Debug" culprit="merlin_domain_transform"><![CDATA[After transform: <b>14</b> modules, <b>52</b> connections]]></message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug" culprit="merlin_router_transform"><![CDATA[After transform: <b>18</b> modules, <b>64</b> connections]]></message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug" culprit="merlin_traffic_limiter_transform"><![CDATA[After transform: <b>20</b> modules, <b>72</b> connections]]></message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug" culprit="merlin_burst_transform"><![CDATA[After transform: <b>22</b> modules, <b>78</b> connections]]></message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug" culprit="merlin_network_to_switch_transform"><![CDATA[After transform: <b>29</b> modules, <b>94</b> connections]]></message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug" culprit="merlin_width_transform"><![CDATA[After transform: <b>31</b> modules, <b>100</b> connections]]></message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug" culprit="limiter_update_transform"><![CDATA[After transform: <b>31</b> modules, <b>102</b> connections]]></message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug" culprit="merlin_clock_and_reset_bridge_transform"><![CDATA[After transform: <b>34</b> modules, <b>134</b> connections]]></message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>5</b> modules, <b>13</b> connections]]></message>
   <message level="Debug" culprit="merlin_mm_transform"><![CDATA[After transform: <b>5</b> modules, <b>13</b> connections]]></message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug" culprit="reset_adaptation_transform"><![CDATA[After transform: <b>8</b> modules, <b>20</b> connections]]></message>
   <message level="Debug" culprit="soc_system"><![CDATA["<b>soc_system</b>" reuses <b>altera_avalon_onchip_memory2</b> "<b>submodules/soc_system_RAM</b>"]]></message>
   <message level="Debug" culprit="soc_system"><![CDATA["<b>soc_system</b>" reuses <b>admm_solver</b> "<b>submodules/admm_solver</b>"]]></message>
   <message level="Debug" culprit="soc_system"><![CDATA["<b>soc_system</b>" reuses <b>altera_hps</b> "<b>submodules/soc_system_hps_0</b>"]]></message>
   <message level="Debug" culprit="soc_system"><![CDATA["<b>soc_system</b>" reuses <b>altera_mm_interconnect</b> "<b>submodules/soc_system_mm_interconnect_0</b>"]]></message>
   <message level="Debug" culprit="soc_system"><![CDATA["<b>soc_system</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
   <message level="Debug" culprit="soc_system"><![CDATA["<b>soc_system</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 5 starting:altera_avalon_onchip_memory2 "submodules/soc_system_RAM"</message>
   <message level="Info" culprit="RAM">Starting RTL generation for module 'soc_system_RAM'</message>
   <message level="Info" culprit="RAM">  Generation command is [exec /tools/intel/intelFPGA/21.1/quartus/linux64/perl/bin/perl -I /tools/intel/intelFPGA/21.1/quartus/linux64/perl/lib -I /tools/intel/intelFPGA/21.1/quartus/sopc_builder/bin/europa -I /tools/intel/intelFPGA/21.1/quartus/sopc_builder/bin -I /tools/intel/intelFPGA/21.1/quartus/../ip/altera/sopc_builder_ip/common -I /tools/intel/intelFPGA/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /tools/intel/intelFPGA/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=soc_system_RAM --dir=/tmp/alt0223_6310717709875561394.dir/0010_RAM_gen/ --quartus_dir=/tools/intel/intelFPGA/21.1/quartus --verilog --config=/tmp/alt0223_6310717709875561394.dir/0010_RAM_gen//soc_system_RAM_component_configuration.pl  --do_build_sim=0  ]</message>
   <message level="Info" culprit="RAM">Done RTL generation for module 'soc_system_RAM'</message>
   <message level="Info" culprit="RAM"><![CDATA["<b>soc_system</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>RAM</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 4 starting:admm_solver "submodules/admm_solver"</message>
   <message level="Info" culprit="admm_solver_0"><![CDATA["<b>soc_system</b>" instantiated <b>admm_solver</b> "<b>admm_solver_0</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 3 starting:altera_hps "submodules/soc_system_hps_0"</message>
   <message level="Info" culprit="hps_0">"Running  for module: hps_0"</message>
   <message level="Info" culprit="hps_0">HPS Main PLL counter settings: n = 0  m = 73</message>
   <message level="Info" culprit="hps_0">HPS peripherial PLL counter settings: n = 0  m = 39</message>
   <message level="Debug" culprit="hps_0.fpga_interfaces">Timing: ELA:1/0.008s</message>
   <message level="Debug" culprit="hps_0.hps_io.border">Timing: ELA:1/0.004s</message>
   <message level="Debug" culprit="hps_0.hps_io">Timing: COM:2/0.023s/0.024s</message>
   <message level="Debug" culprit="hps_0">Timing: COM:1/1.640s STR:1/1.464s</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>2</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="hps_0"><![CDATA["<b>hps_0</b>" reuses <b>altera_interface_generator</b> "<b>submodules/soc_system_hps_0_fpga_interfaces</b>"]]></message>
   <message level="Debug" culprit="hps_0"><![CDATA["<b>hps_0</b>" reuses <b>altera_hps_io</b> "<b>submodules/soc_system_hps_0_hps_io</b>"]]></message>
   <message level="Info" culprit="hps_0"><![CDATA["<b>soc_system</b>" instantiated <b>altera_hps</b> "<b>hps_0</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 30 starting:altera_interface_generator "submodules/soc_system_hps_0_fpga_interfaces"</message>
   <message level="Info" culprit="fpga_interfaces"><![CDATA["<b>hps_0</b>" instantiated <b>altera_interface_generator</b> "<b>fpga_interfaces</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 29 starting:altera_hps_io "submodules/soc_system_hps_0_hps_io"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="hps_io"><![CDATA["<b>hps_io</b>" reuses <b>altera_interface_generator</b> "<b>submodules/soc_system_hps_0_hps_io_border</b>"]]></message>
   <message level="Info" culprit="hps_io"><![CDATA["<b>hps_0</b>" instantiated <b>altera_hps_io</b> "<b>hps_io</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 2 starting:altera_interface_generator "submodules/soc_system_hps_0_hps_io_border"</message>
   <message level="Info" culprit="border"><![CDATA["<b>hps_io</b>" instantiated <b>altera_interface_generator</b> "<b>border</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 4 starting:altera_mm_interconnect "submodules/soc_system_mm_interconnect_0"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>30</b> modules, <b>96</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>30</b> modules, <b>96</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>30</b> modules, <b>96</b> connections]]></message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
   <message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.000s</message>
   <message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
   <message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.006s</message>
   <message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.034s/0.048s</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Info" culprit="avalon_st_adapter_001">Inserting error_adapter: error_adapter_0</message>
   <message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.000s</message>
   <message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
   <message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.006s</message>
   <message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.018s/0.029s</message>
   <message
       level="Debug"
       culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>32</b> modules, <b>102</b> connections]]></message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_axi_master_ni</b> "<b>submodules/altera_merlin_axi_master_ni</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/soc_system_mm_interconnect_0_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/soc_system_mm_interconnect_0_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/soc_system_mm_interconnect_0_router_002</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/soc_system_mm_interconnect_0_router_003</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_cmd_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_cmd_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_rsp_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_rsp_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_rsp_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_rsp_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/soc_system_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001</b>"]]></message>
   <message level="Info" culprit="mm_interconnect_0"><![CDATA["<b>soc_system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 29 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>admm_solver_0_avalon_slave_0_translator</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 27 starting:altera_merlin_axi_master_ni "submodules/altera_merlin_axi_master_ni"</message>
   <message level="Info" culprit="hps_0_h2f_lw_axi_master_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_axi_master_ni</b> "<b>hps_0_h2f_lw_axi_master_agent</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 26 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>admm_solver_0_avalon_slave_0_agent</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 25 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>admm_solver_0_avalon_slave_0_agent_rsp_fifo</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 20 starting:altera_merlin_router "submodules/soc_system_mm_interconnect_0_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 18 starting:altera_merlin_router "submodules/soc_system_mm_interconnect_0_router_002"</message>
   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 17 starting:altera_merlin_router "submodules/soc_system_mm_interconnect_0_router_003"</message>
   <message level="Info" culprit="router_003"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_003</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 16 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"</message>
   <message level="Info" culprit="hps_0_h2f_lw_axi_master_wr_limiter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>hps_0_h2f_lw_axi_master_wr_limiter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
   <message level="Debug" culprit="soc_system">queue size: 14 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_burst_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>admm_solver_0_avalon_slave_0_burst_adapter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
   <message level="Debug" culprit="soc_system">queue size: 12 starting:altera_merlin_demultiplexer "submodules/soc_system_mm_interconnect_0_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 10 starting:altera_merlin_multiplexer "submodules/soc_system_mm_interconnect_0_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 8 starting:altera_merlin_demultiplexer "submodules/soc_system_mm_interconnect_0_rsp_demux"</message>
   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 6 starting:altera_merlin_multiplexer "submodules/soc_system_mm_interconnect_0_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="soc_system">queue size: 4 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
   <message level="Info" culprit="RAM_s1_rsp_width_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>RAM_s1_rsp_width_adapter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
   <message level="Debug" culprit="soc_system">queue size: 2 starting:altera_avalon_st_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0</b>"]]></message>
   <message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 1 starting:error_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0"</message>
   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 2 starting:altera_avalon_st_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="avalon_st_adapter_001"><![CDATA["<b>avalon_st_adapter_001</b>" reuses <b>error_adapter</b> "<b>submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0</b>"]]></message>
   <message level="Info" culprit="avalon_st_adapter_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_001</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 0 starting:error_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0"</message>
   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_001</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 32 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
   <message level="Info" culprit="rst_controller"><![CDATA["<b>soc_system</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_avalon_onchip_memory2:21.1:allowInSystemMemoryContentEditor=false,autoInitializationFileName=soc_system_RAM,blockType=M10K,copyInitFile=false,dataWidth=16,dataWidth2=32,derived_enableDiffWidth=false,derived_gui_ram_block_type=M10K,derived_init_file_name=soc_system_RAM.hex,derived_is_hardcopy=false,derived_set_addr_width=12,derived_set_addr_width2=12,derived_set_data_width=16,derived_set_data_width2=16,derived_singleClockOperation=false,deviceFamily=Cyclone V,deviceFeatures=COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 1 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1,dualPort=false,ecc_enabled=false,enPRInitMode=false,enableDiffWidth=false,initMemContent=true,initializationFileName=onchip_mem.hex,instanceID=NONE,memorySize=8192,readDuringWriteMode=DONT_CARE,resetrequest_enabled=true,simAllowMRAMContentsFile=false,simMemInitOnlyFilename=0,singleClockOperation=false,slave1Latency=1,slave2Latency=1,useNonDefaultInitFile=false,useShallowMemBlocks=false,writable=true"
   instancePathKey="soc_system:.:RAM"
   kind="altera_avalon_onchip_memory2"
   version="21.1"
   name="soc_system_RAM">
  <parameter name="derived_singleClockOperation" value="false" />
  <parameter name="derived_is_hardcopy" value="false" />
  <parameter
     name="deviceFeatures"
     value="COMPILER_SUPPORT 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 ANY_QFP 0 ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 HARDCOPY 0 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_18_BIT_MULTS 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IFP_USE_LEGACY_IO_CHECKER 1 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_BARE_DIE 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_SMI_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M144K_MEMORY 0 M10K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_MIGRATABLE 0 NOT_LISTED 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_POF 0 NO_PIN_OUT 0 NO_RPE_SUPPORT 0 NO_TDC_SUPPORT 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_CRC 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QMAP_IN_DEVELOPMENT 0 QFIT_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_OCT_AUTO_CALIBRATION 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1" />
  <parameter name="autoInitializationFileName" value="soc_system_RAM" />
  <parameter name="derived_gui_ram_block_type" value="M10K" />
  <parameter name="enPRInitMode" value="false" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="writable" value="true" />
  <parameter name="dualPort" value="false" />
  <parameter name="derived_set_addr_width2" value="12" />
  <parameter name="dataWidth" value="16" />
  <parameter name="allowInSystemMemoryContentEditor" value="false" />
  <parameter name="derived_set_addr_width" value="12" />
  <parameter name="derived_init_file_name" value="soc_system_RAM.hex" />
  <parameter name="initializationFileName" value="onchip_mem.hex" />
  <parameter name="singleClockOperation" value="false" />
  <parameter name="derived_set_data_width2" value="16" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="blockType" value="M10K" />
  <parameter name="derived_enableDiffWidth" value="false" />
  <parameter name="useNonDefaultInitFile" value="false" />
  <parameter name="resetrequest_enabled" value="true" />
  <parameter name="simMemInitOnlyFilename" value="0" />
  <parameter name="copyInitFile" value="false" />
  <parameter name="deviceFamily" value="Cyclone V" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="ecc_enabled" value="false" />
  <parameter name="derived_set_data_width" value="16" />
  <parameter name="instanceID" value="NONE" />
  <parameter name="memorySize" value="8192" />
  <parameter name="dataWidth2" value="32" />
  <parameter name="enableDiffWidth" value="false" />
  <parameter name="initMemContent" value="true" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="slave2Latency" value="1" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_RAM.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_RAM.v"
       type="VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="soc_system" as="RAM" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 5 starting:altera_avalon_onchip_memory2 "submodules/soc_system_RAM"</message>
   <message level="Info" culprit="RAM">Starting RTL generation for module 'soc_system_RAM'</message>
   <message level="Info" culprit="RAM">  Generation command is [exec /tools/intel/intelFPGA/21.1/quartus/linux64/perl/bin/perl -I /tools/intel/intelFPGA/21.1/quartus/linux64/perl/lib -I /tools/intel/intelFPGA/21.1/quartus/sopc_builder/bin/europa -I /tools/intel/intelFPGA/21.1/quartus/sopc_builder/bin -I /tools/intel/intelFPGA/21.1/quartus/../ip/altera/sopc_builder_ip/common -I /tools/intel/intelFPGA/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /tools/intel/intelFPGA/21.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=soc_system_RAM --dir=/tmp/alt0223_6310717709875561394.dir/0010_RAM_gen/ --quartus_dir=/tools/intel/intelFPGA/21.1/quartus --verilog --config=/tmp/alt0223_6310717709875561394.dir/0010_RAM_gen//soc_system_RAM_component_configuration.pl  --do_build_sim=0  ]</message>
   <message level="Info" culprit="RAM">Done RTL generation for module 'soc_system_RAM'</message>
   <message level="Info" culprit="RAM"><![CDATA["<b>soc_system</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>RAM</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="admm_solver:1.0:ADDR_WIDTH=16,DATA_WIDTH=16,EXT_DATA_WIDTH=32,FRAC_BITS=8,HORIZON=30,INPUT_DIM=4,MAX_ITER=100,MEM_ADDR_WIDTH=9,STATE_DIM=12"
   instancePathKey="soc_system:.:admm_solver_0"
   kind="admm_solver"
   version="1.0"
   name="admm_solver">
  <parameter name="ADDR_WIDTH" value="16" />
  <parameter name="EXT_DATA_WIDTH" value="32" />
  <parameter name="DATA_WIDTH" value="16" />
  <parameter name="MAX_ITER" value="100" />
  <parameter name="INPUT_DIM" value="4" />
  <parameter name="MEM_ADDR_WIDTH" value="9" />
  <parameter name="STATE_DIM" value="12" />
  <parameter name="FRAC_BITS" value="8" />
  <parameter name="HORIZON" value="30" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/admm_solver.sv"
       type="SYSTEM_VERILOG"
       attributes="TOP_LEVEL_FILE" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/dual_update.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/primal_update.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/residual_calculator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/slack_update.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/memory_interface.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/admm_solver_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="soc_system" as="admm_solver_0" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 4 starting:admm_solver "submodules/admm_solver"</message>
   <message level="Info" culprit="admm_solver_0"><![CDATA["<b>soc_system</b>" instantiated <b>admm_solver</b> "<b>admm_solver_0</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_hps:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=0010001110001,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=0010101110000,AC_ROM_MR0_DLL_RESET_MIRR=0010011101000,AC_ROM_MR0_MIRR=0010001101001,AC_ROM_MR1=0000000000110,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=0000000000110,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=0001000011000,AC_ROM_MR2_MIRR=0001000011000,AC_ROM_MR3=0000000000000,AC_ROM_MR3_MIRR=0000000000000,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=1,ADDR_ORDER=0,ADDR_RATE_RATIO=2,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=30,AFI_BANKADDR_WIDTH=6,AFI_CLK_EN_WIDTH=1,AFI_CLK_PAIR_COUNT=1,AFI_CONTROL_WIDTH=2,AFI_CS_WIDTH=1,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=8,AFI_DQ_WIDTH=64,AFI_ODT_WIDTH=1,AFI_RATE_RATIO=1,AFI_RLAT_WIDTH=6,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=6,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=4,ALLOCATED_RFIFO_PORT=None,None,None,None,None,None,ALLOCATED_WFIFO_PORT=None,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=27,AVL_ADDR_WIDTH_PORT_0=1,AVL_ADDR_WIDTH_PORT_1=1,AVL_ADDR_WIDTH_PORT_2=1,AVL_ADDR_WIDTH_PORT_3=1,AVL_ADDR_WIDTH_PORT_4=1,AVL_ADDR_WIDTH_PORT_5=1,AVL_BE_WIDTH=8,AVL_DATA_WIDTH=64,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=1,AVL_DATA_WIDTH_PORT_1=1,AVL_DATA_WIDTH_PORT_2=1,AVL_DATA_WIDTH_PORT_3=1,AVL_DATA_WIDTH_PORT_4=1,AVL_DATA_WIDTH_PORT_5=1,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=8,AVL_NUM_SYMBOLS_PORT_0=1,AVL_NUM_SYMBOLS_PORT_1=1,AVL_NUM_SYMBOLS_PORT_2=1,AVL_NUM_SYMBOLS_PORT_3=1,AVL_NUM_SYMBOLS_PORT_4=1,AVL_NUM_SYMBOLS_PORT_5=1,AVL_PORT=Port 0,AVL_SIZE_WIDTH=3,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BONDING_OUT_ENABLED=false,BOOTFROMFPGA_Enable=false,BSEL=1,BSEL_EN=false,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=12,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=10,CAN0_Mode=N/A,CAN0_PinMuxing=Unused,CAN1_Mode=N/A,CAN1_PinMuxing=Unused,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=8,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=32,CFG_MEM_CLK_ENTRY_CYCLES=10,CFG_PDN_EXIT_CYCLES=10,CFG_PORT_WIDTH_READ_ODT_CHIP=1,CFG_PORT_WIDTH_WRITE_ODT_CHIP=1,CFG_POWER_SAVING_EXIT_CYCLES=5,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=512,CFG_STARVE_LIMIT=10,CFG_TCCD=1,CFG_TCCD_NS=2.5,CFG_TYPE=2,CFG_WRITE_ODT_CHIP=1,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSEL=0,CSEL_EN=false,CSR_ADDR_WIDTH=10,CSR_BE_WIDTH=1,CSR_DATA_WIDTH=8,CTI_Enable=false,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=1,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=1,CTL_ECC_MULTIPLES_40_72=1,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=true,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=1,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=2,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=1,CV_AVL_ADDR_WIDTH_PORT_1=1,CV_AVL_ADDR_WIDTH_PORT_2=1,CV_AVL_ADDR_WIDTH_PORT_3=1,CV_AVL_ADDR_WIDTH_PORT_4=1,CV_AVL_ADDR_WIDTH_PORT_5=1,CV_AVL_DATA_WIDTH_PORT_0=1,CV_AVL_DATA_WIDTH_PORT_1=1,CV_AVL_DATA_WIDTH_PORT_2=1,CV_AVL_DATA_WIDTH_PORT_3=1,CV_AVL_DATA_WIDTH_PORT_4=1,CV_AVL_DATA_WIDTH_PORT_5=1,CV_AVL_NUM_SYMBOLS_PORT_0=1,CV_AVL_NUM_SYMBOLS_PORT_1=1,CV_AVL_NUM_SYMBOLS_PORT_2=1,CV_AVL_NUM_SYMBOLS_PORT_3=1,CV_AVL_NUM_SYMBOLS_PORT_4=1,CV_AVL_NUM_SYMBOLS_PORT_5=1,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_32_BIT,CV_ENUM_PORT1_WIDTH=PORT_32_BIT,CV_ENUM_PORT2_WIDTH=PORT_32_BIT,CV_ENUM_PORT3_WIDTH=PORT_32_BIT,CV_ENUM_PORT4_WIDTH=PORT_32_BIT,CV_ENUM_PORT5_WIDTH=PORT_32_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_1,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_1,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_1,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_1,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_1,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_1,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_1,CV_ENUM_USER_PRIORITY_1=PRIORITY_1,CV_ENUM_USER_PRIORITY_2=PRIORITY_1,CV_ENUM_USER_PRIORITY_3=PRIORITY_1,CV_ENUM_USER_PRIORITY_4=PRIORITY_1,CV_ENUM_USER_PRIORITY_5=PRIORITY_1,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,Customer_Pin_Name_DERIVED=RGMII0_TX_CLK,RGMII0_TXD0,RGMII0_TXD1,RGMII0_TXD2,RGMII0_TXD3,RGMII0_RXD0,RGMII0_MDIO,RGMII0_MDC ,RGMII0_RX_CTL,RGMII0_TX_CTL,RGMII0_RX_CLK,RGMII0_RXD1,RGMII0_RXD2,RGMII0_RXD3,NAND_ALE,NAND_CE,NAND_CLE,NAND_RE,NAND_RB,NAND_DQ0,NAND_DQ1,NAND_DQ2,NAND_DQ3,NAND_DQ4,NAND_DQ5,NAND_DQ6,NAND_DQ7,NAND_WP,NAND_WE,QSPI_IO0,QSPI_IO1,QSPI_IO2,QSPI_IO3,QSPI_SS0,QSPI_CLK,QSPI_SS1,SDMMC_CMD,SDMMC_PWREN,SDMMC_D0,SDMMC_D1,SDMMC_D4,SDMMC_D5,SDMMC_D6,SDMMC_D7,HPS_GPIO44,SDMMC_CCLK_OUT,SDMMC_D2,SDMMC_D3,TRACE_CLK,TRACE_D0,TRACE_D1,TRACE_D2,TRACE_D3,TRACE_D4,TRACE_D5,TRACE_D6,TRACE_D7,SPIM0_CLK,SPIM0_MOSI,SPIM0_MISO,SPIM0_SS0,UART0_RX,UART0_TX,I2C0_SDA,I2C0_SCL,CAN0_RX,CAN0_TX,DATA_RATE_RATIO=2,DAT_DATA_WIDTH=32,DB_bfm_types=,DB_iface_ports=can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}},DB_periph_ifaces=USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}},DB_port_pins=i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd},DEBUGAPB_Enable=false,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=25,DELAY_PER_DQS_EN_DCHAIN_TAP=25,DELAY_PER_OPA_TAP=312,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=Cyclone V,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=7,DLL_MASTER=true,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DMA_Enable=No,No,No,No,No,No,No,No,DMA_PeriphId_DERIVED=0,1,2,3,4,5,6,7,DQS_DELAY_CHAIN_PHASE_SETTING=0,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=31,DQS_IN_DELAY_MAX=31,DQS_PHASE_SHIFT=0,DQ_DDR=1,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=true,DWIDTH_RATIO=2,EARLY_ADDR_CMD_CLK_TRANSFER=true,ED_EXPORT_SEQ_DEBUG=false,EMAC0_Mode=N/A,EMAC0_PTP=false,EMAC0_PinMuxing=Unused,EMAC1_Mode=RGMII,EMAC1_PTP=false,EMAC1_PinMuxing=HPS I/O Set 0,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=true,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=true,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=SELF_RFSH_EXIT_CYCLES_512,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_10,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_ROW_BANK_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=ENABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_0,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_10,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_15,ENUM_MEM_IF_SPEEDBIN=DDR3_1600_8_8_8,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_11,ENUM_MEM_IF_TCWL=TCWL_8,ENUM_MEM_IF_TFAW=TFAW_12,ENUM_MEM_IF_TMRD=TMRD_4,ENUM_MEM_IF_TRAS=TRAS_14,ENUM_MEM_IF_TRC=TRC_20,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_3,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_32_BIT,ENUM_PORT1_WIDTH=PORT_32_BIT,ENUM_PORT2_WIDTH=PORT_32_BIT,ENUM_PORT3_WIDTH=PORT_32_BIT,ENUM_PORT4_WIDTH=PORT_32_BIT,ENUM_PORT5_WIDTH=PORT_32_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_1,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_1,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_1,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_1,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_1,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_1,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_1,ENUM_USER_PRIORITY_1=PRIORITY_1,ENUM_USER_PRIORITY_2=PRIORITY_1,ENUM_USER_PRIORITY_3=PRIORITY_1,ENUM_USER_PRIORITY_4=PRIORITY_1,ENUM_USER_PRIORITY_5=PRIORITY_1,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=WRITE_CHIP0_ODT0_CHIP1,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,F2H_AXI_CLOCK_FREQ=50000000,F2H_SDRAM0_CLOCK_FREQ=100,F2H_SDRAM1_CLOCK_FREQ=100,F2H_SDRAM2_CLOCK_FREQ=100,F2H_SDRAM3_CLOCK_FREQ=100,F2H_SDRAM4_CLOCK_FREQ=100,F2H_SDRAM5_CLOCK_FREQ=100,F2SCLK_COLDRST_Enable=false,F2SCLK_DBGRST_Enable=false,F2SCLK_PERIPHCLK_Enable=false,F2SCLK_PERIPHCLK_FREQ=0,F2SCLK_PERIPHCLK_FREQ_MHZ=0.0,F2SCLK_SDRAMCLK_Enable=false,F2SCLK_SDRAMCLK_FREQ=0,F2SCLK_SDRAMCLK_FREQ_MHZ=0.0,F2SCLK_WARMRST_Enable=false,F2SDRAM_CMD_PORT_USED=0x0,F2SDRAM_Name_DERIVED=,F2SDRAM_RD_PORT_USED=0x0,F2SDRAM_RST_PORT_USED=0x0,F2SDRAM_Type=,F2SDRAM_WR_PORT_USED=0x0,F2SDRAM_Width=,F2SDRAM_Width_Last_Size=0,F2SINTERRUPT_Enable=false,F2S_Width=2,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN=100,FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK=125,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK=2.5,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK=125,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK=2.5,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT=100,FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT=100,GENERIC_PLL=true,GPIO_Conflict_DERIVED=,USB1.D0,USB1.D1,USB1.D2,USB1.D3,USB1.D4,USB1.D5,USB1.D6,USB1.D7,,USB1.CLK,USB1.STP,USB1.DIR,USB1.NXT,EMAC1.TX_CLK,EMAC1.TXD0,EMAC1.TXD1,EMAC1.TXD2,EMAC1.TXD3,EMAC1.RXD0,EMAC1.MDIO,EMAC1.MDC,EMAC1.RX_CTL,EMAC1.TX_CTL,EMAC1.RX_CLK,EMAC1.RXD1,EMAC1.RXD2,EMAC1.RXD3,,,,,,,,,SDIO.CMD,,SDIO.D0,SDIO.D1,,,,,,SDIO.CLK,SDIO.D2,SDIO.D3,,UART0.RX,UART0.TX,I2C1.SDA,I2C1.SCL,,,I2C0.SDA,I2C0.SCL,,,,,,,SPIM1.CLK,SPIM1.MOSI,SPIM1.MISO,SPIM1.SS0,GPIO_Enable=No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,Yes,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,GPIO_Name_DERIVED=GPIO00,GPIO01,GPIO02,GPIO03,GPIO04,GPIO05,GPIO06,GPIO07,GPIO08,GPIO09,GPIO10,GPIO11,GPIO12,GPIO13,GPIO14,GPIO15,GPIO16,GPIO17,GPIO18,GPIO19,GPIO20,GPIO21,GPIO22,GPIO23,GPIO24,GPIO25,GPIO26,GPIO27,GPIO28,GPIO29,GPIO30,GPIO31,GPIO32,GPIO33,GPIO34,GPIO35,GPIO36,GPIO37,GPIO38,GPIO39,GPIO40,GPIO41,GPIO42,GPIO43,GPIO44,GPIO45,GPIO46,GPIO47,GPIO48,GPIO49,GPIO50,GPIO51,GPIO52,GPIO53,GPIO54,GPIO55,GPIO56,GPIO57,GPIO58,GPIO59,GPIO60,GPIO61,GPIO62,GPIO63,GPIO64,GPIO65,GPIO66,GPIO_Pin_Used_DERIVED=true,GP_Enable=false,H2F_AXI_CLOCK_FREQ=50000000,H2F_CTI_CLOCK_FREQ=100,H2F_DEBUG_APB_CLOCK_FREQ=100,H2F_LW_AXI_CLOCK_FREQ=50000000,H2F_TPIU_CLOCK_IN_FREQ=100,HARD_EMIF=true,HARD_PHY=true,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HLGPI_Enable=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,I2C0_Mode=I2C,I2C0_PinMuxing=HPS I/O Set 0,I2C1_Mode=I2C,I2C1_PinMuxing=HPS I/O Set 0,I2C2_Mode=N/A,I2C2_PinMuxing=Unused,I2C3_Mode=N/A,I2C3_PinMuxing=Unused,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=2,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=2,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=2,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=3,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=3,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=3,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=104,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=7,IO_DQS_IN_RESERVE=4,IO_DQS_OUT_RESERVE=4,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=31,IO_OUT1_DELAY_MAX=31,IO_OUT2_DELAY_MAX=0,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=SSTL-15,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,JAVA_CAN0_DATA=CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}},JAVA_CAN1_DATA=CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}},JAVA_CONFLICT_PIN=No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,JAVA_EMAC0_DATA=EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}},JAVA_EMAC1_DATA=EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}},JAVA_GUI_PIN_LIST=EMACIO0,EMACIO1,EMACIO2,EMACIO3,EMACIO4,EMACIO5,EMACIO6,EMACIO7,EMACIO8,EMACIO9,EMACIO10,EMACIO11,EMACIO12,EMACIO13,MIXED1IO0,MIXED1IO1,MIXED1IO2,MIXED1IO3,MIXED1IO4,MIXED1IO5,MIXED1IO6,MIXED1IO7,MIXED1IO8,MIXED1IO9,MIXED1IO10,MIXED1IO11,MIXED1IO12,MIXED1IO13,MIXED1IO14,MIXED1IO15,MIXED1IO16,MIXED1IO17,MIXED1IO18,MIXED1IO19,MIXED1IO20,MIXED1IO21,FLASHIO0,FLASHIO1,FLASHIO2,FLASHIO3,FLASHIO4,FLASHIO5,FLASHIO6,FLASHIO7,FLASHIO8,FLASHIO9,FLASHIO10,FLASHIO11,GENERALIO0,GENERALIO1,GENERALIO2,GENERALIO3,GENERALIO4,GENERALIO5,GENERALIO6,GENERALIO7,GENERALIO8,GENERALIO9,GENERALIO10,GENERALIO11,GENERALIO12,GENERALIO13,GENERALIO14,GENERALIO15,GENERALIO16,GENERALIO17,GENERALIO18,JAVA_I2C0_DATA=I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}},JAVA_I2C1_DATA=I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}},JAVA_I2C2_DATA=I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}},JAVA_I2C3_DATA=I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}},JAVA_NAND_DATA=NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}},JAVA_QSPI_DATA=QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}},JAVA_SDIO_DATA=SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}},JAVA_SPIM0_DATA=SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}},JAVA_SPIM1_DATA=SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}},JAVA_SPIS0_DATA=SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}},JAVA_SPIS1_DATA=SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}},JAVA_TRACE_DATA=TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}},JAVA_UART0_DATA=UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}},JAVA_UART1_DATA=UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}},JAVA_USB0_DATA=USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}},JAVA_USB1_DATA=USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}},LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOANIO_Enable=No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,LOANIO_Name_DERIVED=LOANIO00,LOANIO01,LOANIO02,LOANIO03,LOANIO04,LOANIO05,LOANIO06,LOANIO07,LOANIO08,LOANIO09,LOANIO10,LOANIO11,LOANIO12,LOANIO13,LOANIO14,LOANIO15,LOANIO16,LOANIO17,LOANIO18,LOANIO19,LOANIO20,LOANIO21,LOANIO22,LOANIO23,LOANIO24,LOANIO25,LOANIO26,LOANIO27,LOANIO28,LOANIO29,LOANIO30,LOANIO31,LOANIO32,LOANIO33,LOANIO34,LOANIO35,LOANIO36,LOANIO37,LOANIO38,LOANIO39,LOANIO40,LOANIO41,LOANIO42,LOANIO43,LOANIO44,LOANIO45,LOANIO46,LOANIO47,LOANIO48,LOANIO49,LOANIO50,LOANIO51,LOANIO52,LOANIO53,LOANIO54,LOANIO55,LOANIO56,LOANIO57,LOANIO58,LOANIO59,LOANIO60,LOANIO61,LOANIO62,LOANIO63,LOANIO64,LOANIO65,LOANIO66,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,LWH2F_Enable=true,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=5,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=400.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=1.25,MEM_CLK_MAX_PS=1250.0,MEM_CLK_NS=2.5,MEM_CLK_PS=2500.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=100000,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=450,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=15,MEM_IF_ADDR_WIDTH_MIN=13,MEM_IF_BANKADDR_WIDTH=3,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=1,MEM_IF_CK_WIDTH=1,MEM_IF_CLK_EN_WIDTH=1,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=10,MEM_IF_CONTROL_WIDTH=1,MEM_IF_CS_PER_DIMM=1,MEM_IF_CS_PER_RANK=1,MEM_IF_CS_WIDTH=1,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=4,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=4,MEM_IF_DQ_WIDTH=32,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=1,MEM_IF_ODT_WIDTH=1,MEM_IF_RD_TO_WR_TURNAROUND_OCT=2,MEM_IF_READ_DQS_WIDTH=4,MEM_IF_ROW_ADDR_WIDTH=15,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=4,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=false,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=1,MEM_TFAW=12,MEM_TFAW_NS=30.0,MEM_TINIT_CK=200000,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=14,MEM_TRAS_NS=35.0,MEM_TRC=20,MEM_TRCD=6,MEM_TRCD_NS=13.75,MEM_TREFI=3120,MEM_TREFI_US=7.8,MEM_TRFC=104,MEM_TRFC_NS=260.0,MEM_TRP=6,MEM_TRP_NS=13.75,MEM_TRRD=4,MEM_TRRD_NS=7.7,MEM_TRTP=3,MEM_TRTP_NS=7.5,MEM_TWR=6,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=DDR3,MEM_T_RL=11,MEM_T_WL=8,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=8,MPU_EVENTS_Enable=false,MR0_BL=1,MR0_BT=0,MR0_CAS_LATENCY=7,MR0_DLL=1,MR0_PD=0,MR0_WR=2,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=3,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NAND_Mode=N/A,NAND_PinMuxing=Unused,NEGATIVE_WRITE_CK_PHASE=true,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=../,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=1,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=1,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=16,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=CYCLONEV,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=CYCLONEV,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=true,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=true,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=211,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=2,PLL_ADDR_CMD_CLK_DIV_CACHE=2,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=400.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=400.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=2500 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=2500 ps,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=400.0 MHz,PLL_ADDR_CMD_CLK_MULT=32,PLL_ADDR_CMD_CLK_MULT_CACHE=32,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=270.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=270.0,PLL_ADDR_CMD_CLK_PHASE_PS=1875,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=1875,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=1875,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=1875 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=1875 ps,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=1875 ps,PLL_AFI_CLK_DIV=2,PLL_AFI_CLK_DIV_CACHE=2,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=400.0,PLL_AFI_CLK_FREQ_CACHE=400.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=2500 ps,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=2500 ps,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=400.0 MHz,PLL_AFI_CLK_MULT=32,PLL_AFI_CLK_MULT_CACHE=32,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=0 ps,PLL_AFI_HALF_CLK_DIV=2,PLL_AFI_HALF_CLK_DIV_CACHE=2,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=400.0,PLL_AFI_HALF_CLK_FREQ_CACHE=400.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=5000 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=5000 ps,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=400.0 MHz,PLL_AFI_HALF_CLK_MULT=32,PLL_AFI_HALF_CLK_MULT_CACHE=32,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=0 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=0 ps,PLL_AFI_PHY_CLK_DIV=1000000,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=400.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=2500 ps,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=0 ps,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=true,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=18000000,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=22.2222222222,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=45000 ps,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=0 ps,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=0 ps,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=true,PLL_MEM_CLK_DIV=2,PLL_MEM_CLK_DIV_CACHE=2,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=400.0,PLL_MEM_CLK_FREQ_CACHE=400.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=2500 ps,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=2500 ps,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=400.0 MHz,PLL_MEM_CLK_MULT=32,PLL_MEM_CLK_MULT_CACHE=32,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=0 ps,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=0 ps,PLL_NIOS_CLK_DIV=6000000,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=66.6666666667,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=15000 ps,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=10.0,PLL_NIOS_CLK_PHASE_DEG_SIM=10.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=0 ps,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=4,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=2,PLL_WRITE_CLK_DIV_CACHE=2,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=400.0,PLL_WRITE_CLK_FREQ_CACHE=400.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=2500 ps,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=2500 ps,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=400.0 MHz,PLL_WRITE_CLK_MULT=32,PLL_WRITE_CLK_MULT_CACHE=32,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=270.0,PLL_WRITE_CLK_PHASE_DEG_SIM=270.0,PLL_WRITE_CLK_PHASE_PS=1875,PLL_WRITE_CLK_PHASE_PS_CACHE=1875,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=1875,PLL_WRITE_CLK_PHASE_PS_SIM_STR=1875 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=1875 ps,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=1875 ps,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=1,PRIORITY_PORT_1=1,PRIORITY_PORT_2=1,PRIORITY_PORT_3=1,PRIORITY_PORT_4=1,PRIORITY_PORT_5=1,QSPI_Mode=N/A,QSPI_PinMuxing=Unused,QVLD_EXTRA_FLOP_STAGES=5,QVLD_WR_ADDRESS_OFFSET=5,RATE=Full,RATE_CACHE=Full,RDBUFFER_ADDR_WIDTH=8,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=25.0,REF_CLK_FREQ_CACHE_VALID=true,REF_CLK_FREQ_MAX_CACHE=500.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=10.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=25.0 MHz,REF_CLK_NS=40.0,REF_CLK_PS=40000.0,REGISTER_C2P=false,S2FCLK_COLDRST_Enable=false,S2FCLK_PENDINGRST_Enable=false,S2FCLK_USER0CLK_Enable=false,S2FCLK_USER0CLK_FREQ=97.368421,S2FCLK_USER0CLK_FREQ_HZ=97368421,S2FCLK_USER1CLK_Enable=true,S2FCLK_USER1CLK_FREQ=100.0,S2FCLK_USER1CLK_FREQ_HZ=100000000,S2FCLK_USER2CLK=5,S2FCLK_USER2CLK_Enable=false,S2FCLK_USER2CLK_FREQ=100.0,S2FCLK_USER2CLK_FREQ_HZ=100000000,S2FINTERRUPT_CAN_Enable=false,S2FINTERRUPT_CLOCKPERIPHERAL_Enable=false,S2FINTERRUPT_CTI_Enable=false,S2FINTERRUPT_DMA_Enable=false,S2FINTERRUPT_EMAC_Enable=false,S2FINTERRUPT_FPGAMANAGER_Enable=false,S2FINTERRUPT_GPIO_Enable=false,S2FINTERRUPT_I2CEMAC_Enable=false,S2FINTERRUPT_I2CPERIPHERAL_Enable=false,S2FINTERRUPT_L4TIMER_Enable=false,S2FINTERRUPT_NAND_Enable=false,S2FINTERRUPT_OSCTIMER_Enable=false,S2FINTERRUPT_QSPI_Enable=false,S2FINTERRUPT_SDMMC_Enable=false,S2FINTERRUPT_SPIMASTER_Enable=false,S2FINTERRUPT_SPISLAVE_Enable=false,S2FINTERRUPT_UART_Enable=false,S2FINTERRUPT_USB_Enable=false,S2FINTERRUPT_WATCHDOG_Enable=false,S2F_Width=2,SCC_DATA_WIDTH=1,SDIO_Mode=4-bit Data,SDIO_PinMuxing=HPS I/O Set 0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=NIOS,SEQ_BURST_COUNT_WIDTH=2,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=7,SPIM0_Mode=N/A,SPIM0_PinMuxing=Unused,SPIM1_Mode=Single Slave Select,SPIM1_PinMuxing=HPS I/O Set 0,SPIS0_Mode=N/A,SPIS0_PinMuxing=Unused,SPIS1_Mode=N/A,SPIS1_PinMuxing=Unused,STARVE_LIMIT=10,STM_Enable=false,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=400.0,TB_MEM_IF_DQ_WIDTH=32,TB_MEM_IF_READ_DQS_WIDTH=4,TB_PLL_DLL_MASTER=true,TB_RATE=FULL,TEST_Enable=false,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=0.09,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.165,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.18,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.24,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.33,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TPIUFPGA_Enable=false,TPIUFPGA_alt=false,TRACE_Mode=N/A,TRACE_PinMuxing=Unused,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,UART0_Mode=No Flow Control,UART0_PinMuxing=HPS I/O Set 0,UART1_Mode=N/A,UART1_PinMuxing=Unused,USB0_Mode=N/A,USB0_PinMuxing=Unused,USB1_Mode=SDR,USB1_PinMuxing=HPS I/O Set 0,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=true,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=true,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=2,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=true,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,can0_clk_div=1,can0_clk_div_auto=4,can0_clk_hz=12500000,can0_clk_mhz=12.5,can1_clk_div=1,can1_clk_div_auto=4,can1_clk_hz=12500000,can1_clk_mhz=12.5,cfg_clk_hz=97368421,cfg_clk_mhz=97.368421,cfg_h2f_user0_clk_hz=97368421,cfg_h2f_user0_clk_mhz=97.368421,configure_advanced_parameters=false,customize_device_pll_info=false,dbctrl_stayosc1=true,dbg_at_clk_div=0,dbg_at_clk_hz=25000000,dbg_at_clk_mhz=25.0,dbg_base_clk_hz=25000000,dbg_base_clk_mhz=25.0,dbg_clk_div=1,dbg_clk_hz=12500000,dbg_clk_mhz=12.5,dbg_timer_clk_hz=25000000,dbg_timer_clk_mhz=25.0,dbg_trace_clk_div=0,dbg_trace_clk_hz=25000000,dbg_trace_clk_mhz=25.0,default_mpu_clk_hz=925000000,default_mpu_clk_mhz=925.0,desired_can0_clk_hz=100000000,desired_can0_clk_mhz=100.0,desired_can1_clk_hz=100000000,desired_can1_clk_mhz=100.0,desired_cfg_clk_hz=97368421,desired_cfg_clk_mhz=97.368421,desired_emac0_clk_hz=250000000,desired_emac0_clk_mhz=250.0,desired_emac1_clk_hz=250000000,desired_emac1_clk_mhz=250.0,desired_gpio_db_clk_hz=32000,desired_l4_mp_clk_hz=100000000,desired_l4_mp_clk_mhz=100.0,desired_l4_sp_clk_hz=100000000,desired_l4_sp_clk_mhz=100.0,desired_mpu_clk_hz=800000000,desired_mpu_clk_mhz=800.0,desired_nand_clk_hz=12500000,desired_nand_clk_mhz=12.5,desired_qspi_clk_hz=400000000,desired_qspi_clk_mhz=400.0,desired_sdmmc_clk_hz=200000000,desired_sdmmc_clk_mhz=200.0,desired_spi_m_clk_hz=200000000,desired_spi_m_clk_mhz=200.0,desired_usb_mp_clk_hz=200000000,desired_usb_mp_clk_mhz=200.0,device_name=5CSEMA5F31C6,device_pll_info_auto={320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000},device_pll_info_manual={320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000},emac0_clk_hz=1953125,emac0_clk_mhz=1.953125,emac1_clk_hz=250000000,emac1_clk_mhz=250.0,eosc1_clk_hz=25000000,eosc1_clk_mhz=25.0,eosc2_clk_hz=25000000,eosc2_clk_mhz=25.0,gpio_db_clk_div=6249,gpio_db_clk_div_auto=6249,gpio_db_clk_hz=32000,h2f_user0_clk_hz=97368421,h2f_user0_clk_mhz=97.368421,h2f_user1_clk_hz=100000000,h2f_user1_clk_mhz=100.0,hps_device_family=Cyclone V,l3_mp_clk_div=1,l3_mp_clk_hz=185000000,l3_mp_clk_mhz=185.0,l3_sp_clk_div=1,l3_sp_clk_hz=92500000,l3_sp_clk_mhz=92.5,l4_mp_clk_div=1,l4_mp_clk_div_auto=1,l4_mp_clk_hz=100000000,l4_mp_clk_mhz=100.0,l4_mp_clk_source=1,l4_sp_clk_div=1,l4_sp_clk_div_auto=1,l4_sp_clk_hz=100000000,l4_sp_clk_mhz=100.0,l4_sp_clk_source=1,main_clk_hz=370000000,main_clk_mhz=370.0,main_nand_sdmmc_clk_hz=3613281,main_nand_sdmmc_clk_mhz=3.613281,main_pll_c0_internal=1,main_pll_c0_internal_auto=1,main_pll_c1_internal=4,main_pll_c1_internal_auto=4,main_pll_c2_internal=4,main_pll_c2_internal_auto=4,main_pll_c3=3,main_pll_c3_auto=511,main_pll_c4=3,main_pll_c4_auto=511,main_pll_c5=15,main_pll_c5_auto=18,main_pll_m=63,main_pll_m_auto=73,main_pll_n=0,main_pll_n_auto=0,main_pll_vco_auto_hz=1850000000,main_pll_vco_auto_mhz=1850.0,main_pll_vco_hz=1600000000,main_pll_vco_mhz=1600.0,main_qspi_clk_hz=3613281,main_qspi_clk_mhz=3.613281,mpu_base_clk_hz=925000000,mpu_base_clk_mhz=925.0,mpu_clk_hz=925000000,mpu_clk_mhz=925.0,mpu_l2_ram_clk_hz=462500000,mpu_l2_ram_clk_mhz=462.5,mpu_periph_clk_hz=231250000,mpu_periph_clk_mhz=231.25,nand_clk_hz=50000000,nand_clk_mhz=50.0,nand_clk_source=2,nand_x_clk_hz=200000000,nand_x_clk_mhz=200.0,periph_base_clk_hz=200000000,periph_base_clk_mhz=200.0,periph_nand_sdmmc_clk_hz=200000000,periph_nand_sdmmc_clk_mhz=200.0,periph_pll_c0=3,periph_pll_c0_auto=511,periph_pll_c1=3,periph_pll_c1_auto=3,periph_pll_c2=1,periph_pll_c2_auto=511,periph_pll_c3=19,periph_pll_c3_auto=4,periph_pll_c4=4,periph_pll_c4_auto=4,periph_pll_c5=9,periph_pll_c5_auto=9,periph_pll_m=79,periph_pll_m_auto=39,periph_pll_n=1,periph_pll_n_auto=0,periph_pll_source=0,periph_pll_vco_auto_hz=1000000000,periph_pll_vco_auto_mhz=1000.0,periph_pll_vco_hz=1000000000,periph_pll_vco_mhz=1000.0,periph_qspi_clk_hz=1953125,periph_qspi_clk_mhz=1.953125,pin_muxing={USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS},pin_muxing_check=Cyclone V+5CSEMA5F31C6,qspi_clk_hz=3613281,qspi_clk_mhz=3.613281,qspi_clk_source=1,quartus_ini_hps_emif_pll=false,quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces=false,quartus_ini_hps_ip_enable_bsel_csel=false,quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface=false,quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces=false,quartus_ini_hps_ip_enable_test_interface=false,quartus_ini_hps_ip_f2sdram_bonding_out=false,quartus_ini_hps_ip_fast_f2sdram_sim_model=false,quartus_ini_hps_ip_suppress_sdram_synth=false,sdmmc_clk_hz=200000000,sdmmc_clk_mhz=200.0,sdmmc_clk_source=2,show_advanced_parameters=false,show_debug_info_as_warning_msg=false,show_warning_as_error_msg=false,spi_m_clk_div=0,spi_m_clk_div_auto=0,spi_m_clk_hz=200000000,spi_m_clk_mhz=200.0,test_iface_definition=DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output,usb_mp_clk_div=0,usb_mp_clk_div_auto=0,usb_mp_clk_hz=200000000,usb_mp_clk_mhz=200.0,use_default_mpu_clk=true(altera_interface_generator:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=,AC_ROM_MR0_DLL_RESET_MIRR=,AC_ROM_MR0_MIRR=,AC_ROM_MR1=,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=,AC_ROM_MR2_MIRR=,AC_ROM_MR3=,AC_ROM_MR3_MIRR=,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=0,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=0,AFI_BANKADDR_WIDTH=0,AFI_CLK_EN_WIDTH=0,AFI_CLK_PAIR_COUNT=0,AFI_CONTROL_WIDTH=0,AFI_CS_WIDTH=0,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=0,AFI_DQ_WIDTH=0,AFI_ODT_WIDTH=0,AFI_RATE_RATIO=0,AFI_RLAT_WIDTH=0,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=0,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=0,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=0,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=0,AVL_DATA_WIDTH=0,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=2,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=0,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=-1,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=-1,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=0,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=0,CFG_MEM_CLK_ENTRY_CYCLES=0,CFG_PDN_EXIT_CYCLES=0,CFG_PORT_WIDTH_READ_ODT_CHIP=0,CFG_PORT_WIDTH_WRITE_ODT_CHIP=0,CFG_POWER_SAVING_EXIT_CYCLES=0,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=0,CFG_STARVE_LIMIT=0,CFG_TCCD=0,CFG_TCCD_NS=2.5,CFG_TYPE=0,CFG_WRITE_ODT_CHIP=0,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=0,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=0,CTL_ECC_MULTIPLES_40_72=0,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=0,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=0,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=0,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=-1,DELAY_PER_DQS_EN_DCHAIN_TAP=-1,DELAY_PER_OPA_TAP=-1,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=false,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=-1,DQS_IN_DELAY_MAX=-1,DQS_PHASE_SHIFT=9000,DQ_DDR=0,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=true,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=true,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=0,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=-1,IO_OUT1_DELAY_MAX=-1,IO_OUT2_DELAY_MAX=-1,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=6,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=2.5,MEM_CLK_MAX_PS=2500.0,MEM_CLK_NS=0.0,MEM_CLK_PS=0.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=0,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=0,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=0,MEM_IF_ADDR_WIDTH_MIN=10,MEM_IF_BANKADDR_WIDTH=0,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=-1,MEM_IF_CK_WIDTH=0,MEM_IF_CLK_EN_WIDTH=0,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=0,MEM_IF_CONTROL_WIDTH=0,MEM_IF_CS_PER_DIMM=0,MEM_IF_CS_PER_RANK=0,MEM_IF_CS_WIDTH=0,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=0,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=0,MEM_IF_DQ_WIDTH=0,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=0,MEM_IF_ODT_WIDTH=0,MEM_IF_RD_TO_WR_TURNAROUND_OCT=0,MEM_IF_READ_DQS_WIDTH=0,MEM_IF_ROW_ADDR_WIDTH=0,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=0,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=2,MEM_TFAW=0,MEM_TFAW_NS=30.0,MEM_TINIT_CK=499,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=0,MEM_TRAS_NS=35.0,MEM_TRC=0,MEM_TRCD=0,MEM_TRCD_NS=13.75,MEM_TREFI=0,MEM_TREFI_US=7.8,MEM_TRFC=0,MEM_TRFC_NS=260.0,MEM_TRP=0,MEM_TRP_NS=13.75,MEM_TRRD=0,MEM_TRRD_NS=7.7,MEM_TRTP=0,MEM_TRTP_NS=7.5,MEM_TWR=0,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=,MEM_T_RL=0,MEM_T_WL=0,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=6,MR0_BL=2,MR0_BT=0,MR0_CAS_LATENCY=3,MR0_DLL=1,MR0_PD=0,MR0_WR=4,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=1,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=false,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=0,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=0,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=false,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=0,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=0,PLL_ADDR_CMD_CLK_DIV_CACHE=0,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=0.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=0.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=,PLL_ADDR_CMD_CLK_MULT=0,PLL_ADDR_CMD_CLK_MULT_CACHE=0,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=,PLL_AFI_CLK_DIV=0,PLL_AFI_CLK_DIV_CACHE=0,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=0.0,PLL_AFI_CLK_FREQ_CACHE=0.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=,PLL_AFI_CLK_MULT=0,PLL_AFI_CLK_MULT_CACHE=0,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=,PLL_AFI_HALF_CLK_DIV=0,PLL_AFI_HALF_CLK_DIV_CACHE=0,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=0.0,PLL_AFI_HALF_CLK_FREQ_CACHE=0.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=,PLL_AFI_HALF_CLK_MULT=0,PLL_AFI_HALF_CLK_MULT_CACHE=0,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=false,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=false,PLL_MEM_CLK_DIV=0,PLL_MEM_CLK_DIV_CACHE=0,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=0.0,PLL_MEM_CLK_FREQ_CACHE=0.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=,PLL_MEM_CLK_MULT=0,PLL_MEM_CLK_MULT_CACHE=0,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=0,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=0,PLL_WRITE_CLK_DIV_CACHE=0,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=0.0,PLL_WRITE_CLK_FREQ_CACHE=0.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=,PLL_WRITE_CLK_MULT=0,PLL_WRITE_CLK_MULT_CACHE=0,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=0.0,PLL_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_WRITE_CLK_PHASE_PS=0,PLL_WRITE_CLK_PHASE_PS_CACHE=0,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=0,PLL_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=0,RATE=Full,RATE_CACHE=Unknown,RDBUFFER_ADDR_WIDTH=6,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=false,REF_CLK_FREQ_MAX_CACHE=0.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=0.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=,REF_CLK_NS=0.0,REF_CLK_PS=0.0,REGISTER_C2P=false,SCC_DATA_WIDTH=0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=0,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=0.0,TB_MEM_IF_DQ_WIDTH=0,TB_MEM_IF_READ_DQS_WIDTH=0,TB_PLL_DLL_MASTER=true,TB_RATE=,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.05,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.01,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=-0.01,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.0,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.0,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.0,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.0,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=0,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=false,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,device=5CSEMA5F31C6,hps_parameter_map=,ignoreSimulation=false,interfaceDefinition=instances {boot_from_fpga {entity_name cyclonev_hps_interface_boot_from_fpga location HPSINTERFACEBOOTFROMFPGA_X52_Y74_N111 signal_widths {boot_from_fpga_ready 1 boot_from_fpga_on_failure 1 bsel_en 1 csel_en 1 csel 2 bsel 3} signal_terminations {boot_from_fpga_ready {0:0 0} boot_from_fpga_on_failure {0:0 0} bsel_en {0:0 0} csel_en {0:0 0} csel {1:0 1} bsel {2:0 1}} parameters {} signal_default_terminations {boot_from_fpga_ready 0 boot_from_fpga_on_failure 0 bsel_en 0 csel_en 0 csel 0 bsel 0}} tpiu {entity_name cyclonev_hps_interface_tpiu_trace location HPSINTERFACETPIUTRACE_X52_Y39_N111 signal_widths {traceclk_ctl 1} parameters {} signal_terminations {traceclk_ctl {0:0 1}} signal_default_terminations {traceclk_ctl 1}} clocks_resets {entity_name cyclonev_hps_interface_clocks_resets location HPSINTERFACECLOCKSRESETS_X52_Y78_N111 signal_widths {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 1 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 1} signal_terminations {f2h_warm_rst_req_n {0:0 1} f2h_pending_rst_ack {0:0 1} f2h_sdram_ref_clk {} f2h_dbg_rst_req_n {0:0 1} f2h_cold_rst_req_n {0:0 1} f2h_periph_ref_clk {}} parameters {} signal_default_terminations {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 0 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 0}} @orderednames {clocks_resets debug_apb tpiu boot_from_fpga} debug_apb {entity_name cyclonev_hps_interface_dbg_apb location HPSINTERFACEDBGAPB_X52_Y80_N111 signal_widths {DBG_APB_DISABLE 1 P_CLK_EN 1} signal_terminations {DBG_APB_DISABLE {0:0 0} P_CLK_EN {0:0 0}} parameters {} signal_default_terminations {DBG_APB_DISABLE 0 P_CLK_EN 0}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{create_clock -period 10.0 [get_pins -compatibility_mode *|fpga_interfaces|clocks_resets|h2f_user1_clk]}} properties {} bfm_types {} intermediate_wire_count 0 wires_to_fragments {} interfaces {@orderednames {h2f_reset h2f_user1_clock} h2f_reset {properties {associatedResetSinks none synchronousEdges none} type reset direction Output signals {@orderednames h2f_rst_n h2f_rst_n {fragments {} properties {} internal_name h2f_rst_n width 1 instance_name clocks_resets direction Output role reset_n}}} h2f_user1_clock {properties {clockRate 100000000.0 clockRateKnown true} type clock direction Output signals {@orderednames h2f_user1_clk h2f_user1_clk {fragments {} properties {} internal_name h2f_user1_clk width 1 instance_name clocks_resets direction Output role clk}}}} raw_assign_sim_style {},qipEntries=)(altera_hps_io:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=,AC_ROM_MR0_DLL_RESET_MIRR=,AC_ROM_MR0_MIRR=,AC_ROM_MR1=,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=,AC_ROM_MR2_MIRR=,AC_ROM_MR3=,AC_ROM_MR3_MIRR=,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=0,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=0,AFI_BANKADDR_WIDTH=0,AFI_CLK_EN_WIDTH=0,AFI_CLK_PAIR_COUNT=0,AFI_CONTROL_WIDTH=0,AFI_CS_WIDTH=0,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=0,AFI_DQ_WIDTH=0,AFI_ODT_WIDTH=0,AFI_RATE_RATIO=0,AFI_RLAT_WIDTH=0,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=0,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=0,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=5CSEMA5F31C6,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=0,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=0,AVL_DATA_WIDTH=0,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=2,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=0,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=-1,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=-1,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=0,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=0,CFG_MEM_CLK_ENTRY_CYCLES=0,CFG_PDN_EXIT_CYCLES=0,CFG_PORT_WIDTH_READ_ODT_CHIP=0,CFG_PORT_WIDTH_WRITE_ODT_CHIP=0,CFG_POWER_SAVING_EXIT_CYCLES=0,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=0,CFG_STARVE_LIMIT=0,CFG_TCCD=0,CFG_TCCD_NS=2.5,CFG_TYPE=0,CFG_WRITE_ODT_CHIP=0,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=0,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=0,CTL_ECC_MULTIPLES_40_72=0,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=0,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=0,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=0,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=-1,DELAY_PER_DQS_EN_DCHAIN_TAP=-1,DELAY_PER_OPA_TAP=-1,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=false,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=-1,DQS_IN_DELAY_MAX=-1,DQS_PHASE_SHIFT=9000,DQ_DDR=0,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=true,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=0,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=-1,IO_OUT1_DELAY_MAX=-1,IO_OUT2_DELAY_MAX=-1,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=6,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=2.5,MEM_CLK_MAX_PS=2500.0,MEM_CLK_NS=0.0,MEM_CLK_PS=0.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=0,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=0,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=0,MEM_IF_ADDR_WIDTH_MIN=10,MEM_IF_BANKADDR_WIDTH=0,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=-1,MEM_IF_CK_WIDTH=0,MEM_IF_CLK_EN_WIDTH=0,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=0,MEM_IF_CONTROL_WIDTH=0,MEM_IF_CS_PER_DIMM=0,MEM_IF_CS_PER_RANK=0,MEM_IF_CS_WIDTH=0,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=0,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=0,MEM_IF_DQ_WIDTH=0,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=0,MEM_IF_ODT_WIDTH=0,MEM_IF_RD_TO_WR_TURNAROUND_OCT=0,MEM_IF_READ_DQS_WIDTH=0,MEM_IF_ROW_ADDR_WIDTH=0,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=0,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=2,MEM_TFAW=0,MEM_TFAW_NS=30.0,MEM_TINIT_CK=499,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=0,MEM_TRAS_NS=35.0,MEM_TRC=0,MEM_TRCD=0,MEM_TRCD_NS=13.75,MEM_TREFI=0,MEM_TREFI_US=7.8,MEM_TRFC=0,MEM_TRFC_NS=260.0,MEM_TRP=0,MEM_TRP_NS=13.75,MEM_TRRD=0,MEM_TRRD_NS=7.7,MEM_TRTP=0,MEM_TRTP_NS=7.5,MEM_TWR=0,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=,MEM_T_RL=0,MEM_T_WL=0,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=6,MR0_BL=2,MR0_BT=0,MR0_CAS_LATENCY=3,MR0_DLL=1,MR0_PD=0,MR0_WR=4,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=1,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=false,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=0,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=0,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=false,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=0,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=0,PLL_ADDR_CMD_CLK_DIV_CACHE=0,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=0.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=0.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=,PLL_ADDR_CMD_CLK_MULT=0,PLL_ADDR_CMD_CLK_MULT_CACHE=0,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=,PLL_AFI_CLK_DIV=0,PLL_AFI_CLK_DIV_CACHE=0,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=0.0,PLL_AFI_CLK_FREQ_CACHE=0.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=,PLL_AFI_CLK_MULT=0,PLL_AFI_CLK_MULT_CACHE=0,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=,PLL_AFI_HALF_CLK_DIV=0,PLL_AFI_HALF_CLK_DIV_CACHE=0,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=0.0,PLL_AFI_HALF_CLK_FREQ_CACHE=0.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=,PLL_AFI_HALF_CLK_MULT=0,PLL_AFI_HALF_CLK_MULT_CACHE=0,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=false,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=false,PLL_MEM_CLK_DIV=0,PLL_MEM_CLK_DIV_CACHE=0,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=0.0,PLL_MEM_CLK_FREQ_CACHE=0.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=,PLL_MEM_CLK_MULT=0,PLL_MEM_CLK_MULT_CACHE=0,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=0,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=0,PLL_WRITE_CLK_DIV_CACHE=0,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=0.0,PLL_WRITE_CLK_FREQ_CACHE=0.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=,PLL_WRITE_CLK_MULT=0,PLL_WRITE_CLK_MULT_CACHE=0,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=0.0,PLL_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_WRITE_CLK_PHASE_PS=0,PLL_WRITE_CLK_PHASE_PS_CACHE=0,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=0,PLL_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=0,RATE=Full,RATE_CACHE=Unknown,RDBUFFER_ADDR_WIDTH=6,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=false,REF_CLK_FREQ_MAX_CACHE=0.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=0.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=,REF_CLK_NS=0.0,REF_CLK_PS=0.0,REGISTER_C2P=false,SCC_DATA_WIDTH=0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=0,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=0.0,TB_MEM_IF_DQ_WIDTH=0,TB_MEM_IF_READ_DQS_WIDTH=0,TB_PLL_DLL_MASTER=true,TB_RATE=,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.05,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.01,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=-0.01,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.0,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.0,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.0,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.0,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=0,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=false,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,border_description=instances {sdio_inst {entity_name cyclonev_hps_peripheral_sdmmc location HPSPERIPHERALSDMMC_X87_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} emac1_inst {entity_name cyclonev_hps_peripheral_emac location HPSPERIPHERALEMAC_X77_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c1_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y65_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} spim1_inst {entity_name cyclonev_hps_peripheral_spi_master location HPSPERIPHERALSPIMASTER_X87_Y53_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} uart0_inst {entity_name cyclonev_hps_peripheral_uart location HPSPERIPHERALUART_X87_Y45_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} @orderednames {emac1_inst sdio_inst usb1_inst spim1_inst uart0_inst i2c0_inst i2c1_inst gpio_inst hps_sdram_inst} usb1_inst {entity_name cyclonev_hps_peripheral_usb location HPSPERIPHERALUSB_X55_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} gpio_inst {entity_name cyclonev_hps_peripheral_gpio location HPSPERIPHERALGPIO_X87_Y74_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps_sdram_inst {entity_name hps_sdram location {} signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c0_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y67_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD0]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD1]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD2]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD3]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD0] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_MDIO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDIO]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDC]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CTL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CTL]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CLK] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD1] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD2] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD3] -to *} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1]} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D1]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D4] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D4]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D5] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D5]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D6] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D6]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D7] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D7]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_CLK] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_STP]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_DIR] -to *} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_NXT] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_MOSI]} {set_false_path -from [get_ports hps_io_hps_io_spim1_inst_MISO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_SS0]} {set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO09] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO09]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO35] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO35]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO40] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO40]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO48] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO48]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO53] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO53]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO54] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO54]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO61] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO61]}} properties {SUPPRESS_SDRAM_SYNTH 0 GENERATE_ISW 1} bfm_types {} intermediate_wire_count 48 wires_to_fragments {{intermediate 9} {output sdio_inst:SDMMC_DATA_OE(2:2)} {intermediate 8} {output sdio_inst:SDMMC_DATA_O(2:2)} {intermediate 7} {output sdio_inst:SDMMC_DATA_OE(1:1)} {intermediate 6} {output sdio_inst:SDMMC_DATA_O(1:1)} {intermediate 5} {output sdio_inst:SDMMC_DATA_OE(0:0)} {intermediate 4} {output sdio_inst:SDMMC_DATA_O(0:0)} {intermediate 3} {output sdio_inst:SDMMC_CMD_OE(0:0)} {intermediate 2} {output sdio_inst:SDMMC_CMD_O(0:0)} {intermediate 1} {output emac1_inst:EMAC_GMII_MDO_OE(0:0)} {intermediate 0} {output emac1_inst:EMAC_GMII_MDO_O(0:0)} {intermediate 19} {output usb1_inst:USB_ULPI_DATA_OE(3:3)} {intermediate 18} {output usb1_inst:USB_ULPI_DATA_O(3:3)} {intermediate 17} {output usb1_inst:USB_ULPI_DATA_OE(2:2)} {intermediate 16} {output usb1_inst:USB_ULPI_DATA_O(2:2)} {intermediate 47} {output gpio_inst:GPIO2_PORTA_OE(3:3)} {intermediate 15} {output usb1_inst:USB_ULPI_DATA_OE(1:1)} {intermediate 46} {output gpio_inst:GPIO2_PORTA_O(3:3)} {intermediate 14} {output usb1_inst:USB_ULPI_DATA_O(1:1)} {intermediate 45} {output gpio_inst:GPIO1_PORTA_OE(25:25)} {intermediate 13} {output usb1_inst:USB_ULPI_DATA_OE(0:0)} {intermediate 44} {output gpio_inst:GPIO1_PORTA_O(25:25)} {intermediate 12} {output usb1_inst:USB_ULPI_DATA_O(0:0)} {intermediate 43} {output gpio_inst:GPIO1_PORTA_OE(24:24)} {intermediate 11} {output sdio_inst:SDMMC_DATA_OE(3:3)} {intermediate 42} {output gpio_inst:GPIO1_PORTA_O(24:24)} {intermediate 10} {output sdio_inst:SDMMC_DATA_O(3:3)} {intermediate 41} {output gpio_inst:GPIO1_PORTA_OE(19:19)} {intermediate 40} {output gpio_inst:GPIO1_PORTA_O(19:19)} {intermediate 39} {output gpio_inst:GPIO1_PORTA_OE(11:11)} {intermediate 38} {output gpio_inst:GPIO1_PORTA_O(11:11)} {intermediate 37} {output gpio_inst:GPIO1_PORTA_OE(6:6)} {intermediate 36} {output gpio_inst:GPIO1_PORTA_O(6:6)} {intermediate 35} {output gpio_inst:GPIO0_PORTA_OE(9:9)} {intermediate 34} {output gpio_inst:GPIO0_PORTA_O(9:9)} {intermediate 33} {output i2c1_inst:I2C_CLK_OE(0:0)} {intermediate 32} {output i2c1_inst:I2C_DATA_OE(0:0)} {intermediate 31} {output i2c0_inst:I2C_CLK_OE(0:0)} {intermediate 30} {output i2c0_inst:I2C_DATA_OE(0:0)} {intermediate 29} {output spim1_inst:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 28} {output spim1_inst:SPI_MASTER_TXD(0:0)} {intermediate 27} {output usb1_inst:USB_ULPI_DATA_OE(7:7)} {intermediate 26} {output usb1_inst:USB_ULPI_DATA_O(7:7)} {intermediate 25} {output usb1_inst:USB_ULPI_DATA_OE(6:6)} {intermediate 24} {output usb1_inst:USB_ULPI_DATA_O(6:6)} {intermediate 23} {output usb1_inst:USB_ULPI_DATA_OE(5:5)} {intermediate 22} {output usb1_inst:USB_ULPI_DATA_O(5:5)} {intermediate 21} {output usb1_inst:USB_ULPI_DATA_OE(4:4)} {intermediate 20} {output usb1_inst:USB_ULPI_DATA_O(4:4)}} interfaces {@orderednames {memory hps_io} memory {properties {} type conduit direction end signals {@orderednames {mem_a mem_ba mem_ck mem_ck_n mem_cke mem_cs_n mem_ras_n mem_cas_n mem_we_n mem_reset_n mem_dq mem_dqs mem_dqs_n mem_odt mem_dm oct_rzqin} mem_a {fragments {} properties {} internal_name mem_a width 15 instance_name hps_sdram_inst direction Output role mem_a} mem_ba {fragments {} properties {} internal_name mem_ba width 3 instance_name hps_sdram_inst direction Output role mem_ba} mem_ck {fragments {} properties {} internal_name mem_ck width 1 instance_name hps_sdram_inst direction Output role mem_ck} mem_ck_n {fragments {} properties {} internal_name mem_ck_n width 1 instance_name hps_sdram_inst direction Output role mem_ck_n} mem_cke {fragments {} properties {} internal_name mem_cke width 1 instance_name hps_sdram_inst direction Output role mem_cke} mem_cs_n {fragments {} properties {} internal_name mem_cs_n width 1 instance_name hps_sdram_inst direction Output role mem_cs_n} mem_ras_n {fragments {} properties {} internal_name mem_ras_n width 1 instance_name hps_sdram_inst direction Output role mem_ras_n} mem_cas_n {fragments {} properties {} internal_name mem_cas_n width 1 instance_name hps_sdram_inst direction Output role mem_cas_n} mem_we_n {fragments {} properties {} internal_name mem_we_n width 1 instance_name hps_sdram_inst direction Output role mem_we_n} mem_reset_n {fragments {} properties {} internal_name mem_reset_n width 1 instance_name hps_sdram_inst direction Output role mem_reset_n} mem_dq {fragments {} properties {} internal_name mem_dq width 32 instance_name hps_sdram_inst direction Bidir role mem_dq} mem_dqs {fragments {} properties {} internal_name mem_dqs width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs} mem_dqs_n {fragments {} properties {} internal_name mem_dqs_n width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs_n} mem_odt {fragments {} properties {} internal_name mem_odt width 1 instance_name hps_sdram_inst direction Output role mem_odt} mem_dm {fragments {} properties {} internal_name mem_dm width 4 instance_name hps_sdram_inst direction Output role mem_dm} oct_rzqin {fragments {} properties {} internal_name oct_rzqin width 1 instance_name hps_sdram_inst direction Input role oct_rzqin}}} hps_io {properties {} type conduit direction input signals {@orderednames {hps_io_emac1_inst_TX_CLK hps_io_emac1_inst_TXD0 hps_io_emac1_inst_TXD1 hps_io_emac1_inst_TXD2 hps_io_emac1_inst_TXD3 hps_io_emac1_inst_RXD0 hps_io_emac1_inst_MDIO hps_io_emac1_inst_MDC hps_io_emac1_inst_RX_CTL hps_io_emac1_inst_TX_CTL hps_io_emac1_inst_RX_CLK hps_io_emac1_inst_RXD1 hps_io_emac1_inst_RXD2 hps_io_emac1_inst_RXD3 hps_io_sdio_inst_CMD hps_io_sdio_inst_D0 hps_io_sdio_inst_D1 hps_io_sdio_inst_CLK hps_io_sdio_inst_D2 hps_io_sdio_inst_D3 hps_io_usb1_inst_D0 hps_io_usb1_inst_D1 hps_io_usb1_inst_D2 hps_io_usb1_inst_D3 hps_io_usb1_inst_D4 hps_io_usb1_inst_D5 hps_io_usb1_inst_D6 hps_io_usb1_inst_D7 hps_io_usb1_inst_CLK hps_io_usb1_inst_STP hps_io_usb1_inst_DIR hps_io_usb1_inst_NXT hps_io_spim1_inst_CLK hps_io_spim1_inst_MOSI hps_io_spim1_inst_MISO hps_io_spim1_inst_SS0 hps_io_uart0_inst_RX hps_io_uart0_inst_TX hps_io_i2c0_inst_SDA hps_io_i2c0_inst_SCL hps_io_i2c1_inst_SDA hps_io_i2c1_inst_SCL hps_io_gpio_inst_GPIO09 hps_io_gpio_inst_GPIO35 hps_io_gpio_inst_GPIO40 hps_io_gpio_inst_GPIO48 hps_io_gpio_inst_GPIO53 hps_io_gpio_inst_GPIO54 hps_io_gpio_inst_GPIO61} hps_io_emac1_inst_TX_CLK {fragments emac1_inst:EMAC_CLK_TX(0:0) properties {} internal_name hps_io_emac1_inst_TX_CLK width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CLK} hps_io_emac1_inst_TXD0 {fragments emac1_inst:EMAC_PHY_TXD(0:0) properties {} internal_name hps_io_emac1_inst_TXD0 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD0} hps_io_emac1_inst_TXD1 {fragments emac1_inst:EMAC_PHY_TXD(1:1) properties {} internal_name hps_io_emac1_inst_TXD1 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD1} hps_io_emac1_inst_TXD2 {fragments emac1_inst:EMAC_PHY_TXD(2:2) properties {} internal_name hps_io_emac1_inst_TXD2 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD2} hps_io_emac1_inst_TXD3 {fragments emac1_inst:EMAC_PHY_TXD(3:3) properties {} internal_name hps_io_emac1_inst_TXD3 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD3} hps_io_emac1_inst_RXD0 {fragments emac1_inst:EMAC_PHY_RXD(0:0) properties {} internal_name hps_io_emac1_inst_RXD0 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD0} hps_io_emac1_inst_MDIO {fragments emac1_inst:EMAC_GMII_MDO_I(0:0) properties {} internal_name hps_io_emac1_inst_MDIO width 1 instance_name hps_io tristate_output {{intermediate 1} {intermediate 0}} direction bidir role hps_io_emac1_inst_MDIO} hps_io_emac1_inst_MDC {fragments emac1_inst:EMAC_GMII_MDC(0:0) properties {} internal_name hps_io_emac1_inst_MDC width 1 instance_name hps_io direction output role hps_io_emac1_inst_MDC} hps_io_emac1_inst_RX_CTL {fragments emac1_inst:EMAC_PHY_RXDV(0:0) properties {} internal_name hps_io_emac1_inst_RX_CTL width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CTL} hps_io_emac1_inst_TX_CTL {fragments emac1_inst:EMAC_PHY_TX_OE(0:0) properties {} internal_name hps_io_emac1_inst_TX_CTL width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CTL} hps_io_emac1_inst_RX_CLK {fragments emac1_inst:EMAC_CLK_RX(0:0) properties {} internal_name hps_io_emac1_inst_RX_CLK width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CLK} hps_io_emac1_inst_RXD1 {fragments emac1_inst:EMAC_PHY_RXD(1:1) properties {} internal_name hps_io_emac1_inst_RXD1 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD1} hps_io_emac1_inst_RXD2 {fragments emac1_inst:EMAC_PHY_RXD(2:2) properties {} internal_name hps_io_emac1_inst_RXD2 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD2} hps_io_emac1_inst_RXD3 {fragments emac1_inst:EMAC_PHY_RXD(3:3) properties {} internal_name hps_io_emac1_inst_RXD3 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD3} hps_io_sdio_inst_CMD {fragments sdio_inst:SDMMC_CMD_I(0:0) properties {} internal_name hps_io_sdio_inst_CMD width 1 instance_name hps_io tristate_output {{intermediate 3} {intermediate 2}} direction bidir role hps_io_sdio_inst_CMD} hps_io_sdio_inst_D0 {fragments sdio_inst:SDMMC_DATA_I(0:0) properties {} internal_name hps_io_sdio_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 5} {intermediate 4}} direction bidir role hps_io_sdio_inst_D0} hps_io_sdio_inst_D1 {fragments sdio_inst:SDMMC_DATA_I(1:1) properties {} internal_name hps_io_sdio_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 7} {intermediate 6}} direction bidir role hps_io_sdio_inst_D1} hps_io_sdio_inst_CLK {fragments sdio_inst:SDMMC_CCLK(0:0) properties {} internal_name hps_io_sdio_inst_CLK width 1 instance_name hps_io direction output role hps_io_sdio_inst_CLK} hps_io_sdio_inst_D2 {fragments sdio_inst:SDMMC_DATA_I(2:2) properties {} internal_name hps_io_sdio_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 9} {intermediate 8}} direction bidir role hps_io_sdio_inst_D2} hps_io_sdio_inst_D3 {fragments sdio_inst:SDMMC_DATA_I(3:3) properties {} internal_name hps_io_sdio_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 11} {intermediate 10}} direction bidir role hps_io_sdio_inst_D3} hps_io_usb1_inst_D0 {fragments usb1_inst:USB_ULPI_DATA_I(0:0) properties {} internal_name hps_io_usb1_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 13} {intermediate 12}} direction bidir role hps_io_usb1_inst_D0} hps_io_usb1_inst_D1 {fragments usb1_inst:USB_ULPI_DATA_I(1:1) properties {} internal_name hps_io_usb1_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 15} {intermediate 14}} direction bidir role hps_io_usb1_inst_D1} hps_io_usb1_inst_D2 {fragments usb1_inst:USB_ULPI_DATA_I(2:2) properties {} internal_name hps_io_usb1_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 17} {intermediate 16}} direction bidir role hps_io_usb1_inst_D2} hps_io_usb1_inst_D3 {fragments usb1_inst:USB_ULPI_DATA_I(3:3) properties {} internal_name hps_io_usb1_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 19} {intermediate 18}} direction bidir role hps_io_usb1_inst_D3} hps_io_usb1_inst_D4 {fragments usb1_inst:USB_ULPI_DATA_I(4:4) properties {} internal_name hps_io_usb1_inst_D4 width 1 instance_name hps_io tristate_output {{intermediate 21} {intermediate 20}} direction bidir role hps_io_usb1_inst_D4} hps_io_usb1_inst_D5 {fragments usb1_inst:USB_ULPI_DATA_I(5:5) properties {} internal_name hps_io_usb1_inst_D5 width 1 instance_name hps_io tristate_output {{intermediate 23} {intermediate 22}} direction bidir role hps_io_usb1_inst_D5} hps_io_usb1_inst_D6 {fragments usb1_inst:USB_ULPI_DATA_I(6:6) properties {} internal_name hps_io_usb1_inst_D6 width 1 instance_name hps_io tristate_output {{intermediate 25} {intermediate 24}} direction bidir role hps_io_usb1_inst_D6} hps_io_usb1_inst_D7 {fragments usb1_inst:USB_ULPI_DATA_I(7:7) properties {} internal_name hps_io_usb1_inst_D7 width 1 instance_name hps_io tristate_output {{intermediate 27} {intermediate 26}} direction bidir role hps_io_usb1_inst_D7} hps_io_usb1_inst_CLK {fragments usb1_inst:USB_ULPI_CLK(0:0) properties {} internal_name hps_io_usb1_inst_CLK width 1 instance_name hps_io direction input role hps_io_usb1_inst_CLK} hps_io_usb1_inst_STP {fragments usb1_inst:USB_ULPI_STP(0:0) properties {} internal_name hps_io_usb1_inst_STP width 1 instance_name hps_io direction output role hps_io_usb1_inst_STP} hps_io_usb1_inst_DIR {fragments usb1_inst:USB_ULPI_DIR(0:0) properties {} internal_name hps_io_usb1_inst_DIR width 1 instance_name hps_io direction input role hps_io_usb1_inst_DIR} hps_io_usb1_inst_NXT {fragments usb1_inst:USB_ULPI_NXT(0:0) properties {} internal_name hps_io_usb1_inst_NXT width 1 instance_name hps_io direction input role hps_io_usb1_inst_NXT} hps_io_spim1_inst_CLK {fragments spim1_inst:SPI_MASTER_SCLK(0:0) properties {} internal_name hps_io_spim1_inst_CLK width 1 instance_name hps_io direction output role hps_io_spim1_inst_CLK} hps_io_spim1_inst_MOSI {fragments {} properties {} internal_name hps_io_spim1_inst_MOSI width 1 instance_name hps_io tristate_output {{intermediate 29} {intermediate 28}} direction output role hps_io_spim1_inst_MOSI} hps_io_spim1_inst_MISO {fragments spim1_inst:SPI_MASTER_RXD(0:0) properties {} internal_name hps_io_spim1_inst_MISO width 1 instance_name hps_io direction input role hps_io_spim1_inst_MISO} hps_io_spim1_inst_SS0 {fragments spim1_inst:SPI_MASTER_SS_0_N(0:0) properties {} internal_name hps_io_spim1_inst_SS0 width 1 instance_name hps_io direction output role hps_io_spim1_inst_SS0} hps_io_uart0_inst_RX {fragments uart0_inst:UART_RXD(0:0) properties {} internal_name hps_io_uart0_inst_RX width 1 instance_name hps_io direction input role hps_io_uart0_inst_RX} hps_io_uart0_inst_TX {fragments uart0_inst:UART_TXD(0:0) properties {} internal_name hps_io_uart0_inst_TX width 1 instance_name hps_io direction output role hps_io_uart0_inst_TX} hps_io_i2c0_inst_SDA {fragments i2c0_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c0_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 30} {}} direction bidir role hps_io_i2c0_inst_SDA} hps_io_i2c0_inst_SCL {fragments i2c0_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c0_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 31} {}} direction bidir role hps_io_i2c0_inst_SCL} hps_io_i2c1_inst_SDA {fragments i2c1_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c1_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 32} {}} direction bidir role hps_io_i2c1_inst_SDA} hps_io_i2c1_inst_SCL {fragments i2c1_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c1_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 33} {}} direction bidir role hps_io_i2c1_inst_SCL} hps_io_gpio_inst_GPIO09 {fragments gpio_inst:GPIO0_PORTA_I(9:9) properties {} internal_name hps_io_gpio_inst_GPIO09 width 1 instance_name hps_io tristate_output {{intermediate 35} {intermediate 34}} direction bidir role hps_io_gpio_inst_GPIO09} hps_io_gpio_inst_GPIO35 {fragments gpio_inst:GPIO1_PORTA_I(6:6) properties {} internal_name hps_io_gpio_inst_GPIO35 width 1 instance_name hps_io tristate_output {{intermediate 37} {intermediate 36}} direction bidir role hps_io_gpio_inst_GPIO35} hps_io_gpio_inst_GPIO40 {fragments gpio_inst:GPIO1_PORTA_I(11:11) properties {} internal_name hps_io_gpio_inst_GPIO40 width 1 instance_name hps_io tristate_output {{intermediate 39} {intermediate 38}} direction bidir role hps_io_gpio_inst_GPIO40} hps_io_gpio_inst_GPIO48 {fragments gpio_inst:GPIO1_PORTA_I(19:19) properties {} internal_name hps_io_gpio_inst_GPIO48 width 1 instance_name hps_io tristate_output {{intermediate 41} {intermediate 40}} direction bidir role hps_io_gpio_inst_GPIO48} hps_io_gpio_inst_GPIO53 {fragments gpio_inst:GPIO1_PORTA_I(24:24) properties {} internal_name hps_io_gpio_inst_GPIO53 width 1 instance_name hps_io tristate_output {{intermediate 43} {intermediate 42}} direction bidir role hps_io_gpio_inst_GPIO53} hps_io_gpio_inst_GPIO54 {fragments gpio_inst:GPIO1_PORTA_I(25:25) properties {} internal_name hps_io_gpio_inst_GPIO54 width 1 instance_name hps_io tristate_output {{intermediate 45} {intermediate 44}} direction bidir role hps_io_gpio_inst_GPIO54} hps_io_gpio_inst_GPIO61 {fragments gpio_inst:GPIO2_PORTA_I(3:3) properties {} internal_name hps_io_gpio_inst_GPIO61 width 1 instance_name hps_io tristate_output {{intermediate 47} {intermediate 46}} direction bidir role hps_io_gpio_inst_GPIO61}}}} raw_assign_sim_style {},hps_parameter_map=AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 1.25 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 200000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 32 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 4 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 1000.0 MEM_TRCD 6 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA5F31C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 14 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 25.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 64 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 125 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.02 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 32 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 25.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 25000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 2500.0 periph_pll_vco_hz 1000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 30 PLL_WRITE_CLK_PHASE_PS_CACHE 1875 UART0_PinMuxing {HPS I/O Set 0} sdmmc_clk_hz 200000000 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode RGMII NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz 1600000000 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 2.5 PLL_AFI_CLK_MULT_CACHE 32 PLL_ADDR_CMD_CLK_DIV 2 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 3 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 32 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {45000 ps} PLL_AFI_CLK_DIV 2 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 13.75 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 400.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 2 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.8 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.08 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 25000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 200.0 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 180 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {25.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.03 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 6 TIMING_TIH 140 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 0 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing {HPS I/O Set 0} desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 200000000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_8 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 1875 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 200.0 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 30 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 6 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 65 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {2500 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 20 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 32 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 64 PLL_AFI_PHY_CLK_FREQ 400.0 periph_nand_sdmmc_clk_mhz 200.0 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000110 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No Yes No No No No Yes No No No No No No No Yes No No No No Yes Yes No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 4 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {400.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode I2C IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 12500000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.09 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 200000000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 35.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 2 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {2500 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED true TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode {No Flow Control} S2FCLK_USER0CLK_FREQ_HZ 97368421 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 800.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 4 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 1875 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 8 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 10 dbg_timer_clk_hz 25000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode {Single Slave Select} hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 97.368421 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM RZQ/4 AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 40000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_6 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 13.75 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 8 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.16 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 40.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 2 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 400.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_6 MR2_RTT_WR 1 MEM_TCL 11 GPIO_Pin_Used_DERIVED true JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 104 USE_2X_FF false ENUM_MEM_IF_TRC TRC_20 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 27 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 50000000 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable true desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 2 F2SDRAM_Width {} dbg_clk_hz 12500000 PLL_AFI_CLK_FREQ 400.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.18 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 400.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 66.6666666667 dbg_timer_clk_mhz 25.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {2500 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 9 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 0 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {1875 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 15 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 100.0 PLL_AFI_HALF_CLK_MULT_CACHE 32 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 32 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 400.0 AFI_WRITE_DQS_WIDTH 4 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 200.0 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 25000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.16 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 10 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 200.0 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz 1600.0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.33 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {1875 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {2500 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 15 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {1875 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0010011101000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/7 MEM_IF_DM_WIDTH 4 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.7 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 32 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 32 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 30.0 DELAY_PER_OPA_TAP 312 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing {HPS I/O Set 0} MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {2500 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 12.5 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 6000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 2 ENUM_MEM_IF_TCL TCL_11 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR JEDEC device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing {HPS I/O Set 0} CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_4 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 2 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 97.368421 MR2_CWL 3 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 211 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 39 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 12.5 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 73 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 400.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 15 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 1 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 32000 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 MR0_BT 0 PLL_CONFIG_CLK_FREQ 22.2222222222 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 1 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {400.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 32 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 25.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR RZQ/4 TIMING_TDQSCK 255 REF_CLK_FREQ_CACHE 25.0 AC_ROM_MR0_DLL_RESET 0010101110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {15000 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0010001101001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 12 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {400.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing {HPS I/O Set 0} MEM_TREFI 3120 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 32 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 25.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.09 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {2500 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 4 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 10 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_6 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 50000000 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.165 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {2500 ps} emac1_clk_mhz 250.0 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 500 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 32 TIMING_BOARD_SKEW_WITHIN_DQS 0.01 ENUM_MEM_IF_TRAS TRAS_14 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 1 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.03 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 7 H2F_LW_AXI_CLOCK_FREQ 50000000 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {400.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 2 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {1875 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 12500000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 250000000 eosc2_clk_mhz 25.0 PLL_MEM_CLK_DIV_CACHE 2 periph_base_clk_mhz 200.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_32 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 8 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.24 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing {HPS I/O Set 0} INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 400.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 25.0 desired_cfg_clk_hz 97368421 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 2 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 200000000 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 4 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {5000 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 8 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 11 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 200000000 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 6249 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0001000011000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode I2C quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 3120 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 1875 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {400.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 4 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 260.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY true ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 4 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 1 pin_muxing_check {Cyclone V+5CSEMA5F31C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 100000000 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 2 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 200000 PLL_WRITE_CLK_MULT_CACHE 32 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 400.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 4 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 50.0 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} USB1.D0 USB1.D1 USB1.D2 USB1.D3 USB1.D4 USB1.D5 USB1.D6 USB1.D7 {} USB1.CLK USB1.STP USB1.DIR USB1.NXT EMAC1.TX_CLK EMAC1.TXD0 EMAC1.TXD1 EMAC1.TXD2 EMAC1.TXD3 EMAC1.RXD0 EMAC1.MDIO EMAC1.MDC EMAC1.RX_CTL EMAC1.TX_CTL EMAC1.RX_CLK EMAC1.RXD1 EMAC1.RXD2 EMAC1.RXD3 {} {} {} {} {} {} {} {} SDIO.CMD {} SDIO.D0 SDIO.D1 {} {} {} {} {} SDIO.CLK SDIO.D2 SDIO.D3 {} UART0.RX UART0.TX I2C1.SDA I2C1.SCL {} {} I2C0.SDA I2C0.SCL {} {} {} {} {} {} SPIM1.CLK SPIM1.MOSI SPIM1.MISO SPIM1.SS0} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 8 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 400.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 8 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 32 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0001000011000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000000000110 TB_MEM_CLK_FREQ 400.0 AC_ROM_MR0 0010001110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 18000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 400.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {2500 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 12.5 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 5 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_4 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing {HPS I/O Set 0} CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 25000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {5000 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode SDR ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.4 dbg_base_clk_hz 25000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 400.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 2 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 1250.0 S2FCLK_USER1CLK_Enable true SDIO_Mode {4-bit Data} desired_qspi_clk_mhz 400.0 MEM_TRFC 104 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2(altera_interface_generator:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=,AC_ROM_MR0_DLL_RESET_MIRR=,AC_ROM_MR0_MIRR=,AC_ROM_MR1=,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=,AC_ROM_MR2_MIRR=,AC_ROM_MR3=,AC_ROM_MR3_MIRR=,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=0,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=0,AFI_BANKADDR_WIDTH=0,AFI_CLK_EN_WIDTH=0,AFI_CLK_PAIR_COUNT=0,AFI_CONTROL_WIDTH=0,AFI_CS_WIDTH=0,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=0,AFI_DQ_WIDTH=0,AFI_ODT_WIDTH=0,AFI_RATE_RATIO=0,AFI_RLAT_WIDTH=0,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=0,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=0,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=0,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=0,AVL_DATA_WIDTH=0,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=2,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=0,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=-1,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=-1,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=0,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=0,CFG_MEM_CLK_ENTRY_CYCLES=0,CFG_PDN_EXIT_CYCLES=0,CFG_PORT_WIDTH_READ_ODT_CHIP=0,CFG_PORT_WIDTH_WRITE_ODT_CHIP=0,CFG_POWER_SAVING_EXIT_CYCLES=0,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=0,CFG_STARVE_LIMIT=0,CFG_TCCD=0,CFG_TCCD_NS=2.5,CFG_TYPE=0,CFG_WRITE_ODT_CHIP=0,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=0,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=0,CTL_ECC_MULTIPLES_40_72=0,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=0,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=0,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=0,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=-1,DELAY_PER_DQS_EN_DCHAIN_TAP=-1,DELAY_PER_OPA_TAP=-1,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=false,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=-1,DQS_IN_DELAY_MAX=-1,DQS_PHASE_SHIFT=9000,DQ_DDR=0,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=true,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=0,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=-1,IO_OUT1_DELAY_MAX=-1,IO_OUT2_DELAY_MAX=-1,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=6,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=2.5,MEM_CLK_MAX_PS=2500.0,MEM_CLK_NS=0.0,MEM_CLK_PS=0.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=0,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=0,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=0,MEM_IF_ADDR_WIDTH_MIN=10,MEM_IF_BANKADDR_WIDTH=0,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=-1,MEM_IF_CK_WIDTH=0,MEM_IF_CLK_EN_WIDTH=0,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=0,MEM_IF_CONTROL_WIDTH=0,MEM_IF_CS_PER_DIMM=0,MEM_IF_CS_PER_RANK=0,MEM_IF_CS_WIDTH=0,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=0,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=0,MEM_IF_DQ_WIDTH=0,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=0,MEM_IF_ODT_WIDTH=0,MEM_IF_RD_TO_WR_TURNAROUND_OCT=0,MEM_IF_READ_DQS_WIDTH=0,MEM_IF_ROW_ADDR_WIDTH=0,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=0,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=2,MEM_TFAW=0,MEM_TFAW_NS=30.0,MEM_TINIT_CK=499,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=0,MEM_TRAS_NS=35.0,MEM_TRC=0,MEM_TRCD=0,MEM_TRCD_NS=13.75,MEM_TREFI=0,MEM_TREFI_US=7.8,MEM_TRFC=0,MEM_TRFC_NS=260.0,MEM_TRP=0,MEM_TRP_NS=13.75,MEM_TRRD=0,MEM_TRRD_NS=7.7,MEM_TRTP=0,MEM_TRTP_NS=7.5,MEM_TWR=0,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=,MEM_T_RL=0,MEM_T_WL=0,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=6,MR0_BL=2,MR0_BT=0,MR0_CAS_LATENCY=3,MR0_DLL=1,MR0_PD=0,MR0_WR=4,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=1,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=false,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=0,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=0,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=false,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=0,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=0,PLL_ADDR_CMD_CLK_DIV_CACHE=0,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=0.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=0.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=,PLL_ADDR_CMD_CLK_MULT=0,PLL_ADDR_CMD_CLK_MULT_CACHE=0,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=,PLL_AFI_CLK_DIV=0,PLL_AFI_CLK_DIV_CACHE=0,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=0.0,PLL_AFI_CLK_FREQ_CACHE=0.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=,PLL_AFI_CLK_MULT=0,PLL_AFI_CLK_MULT_CACHE=0,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=,PLL_AFI_HALF_CLK_DIV=0,PLL_AFI_HALF_CLK_DIV_CACHE=0,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=0.0,PLL_AFI_HALF_CLK_FREQ_CACHE=0.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=,PLL_AFI_HALF_CLK_MULT=0,PLL_AFI_HALF_CLK_MULT_CACHE=0,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=false,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=false,PLL_MEM_CLK_DIV=0,PLL_MEM_CLK_DIV_CACHE=0,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=0.0,PLL_MEM_CLK_FREQ_CACHE=0.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=,PLL_MEM_CLK_MULT=0,PLL_MEM_CLK_MULT_CACHE=0,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=0,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=0,PLL_WRITE_CLK_DIV_CACHE=0,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=0.0,PLL_WRITE_CLK_FREQ_CACHE=0.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=,PLL_WRITE_CLK_MULT=0,PLL_WRITE_CLK_MULT_CACHE=0,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=0.0,PLL_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_WRITE_CLK_PHASE_PS=0,PLL_WRITE_CLK_PHASE_PS_CACHE=0,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=0,PLL_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=0,RATE=Full,RATE_CACHE=Unknown,RDBUFFER_ADDR_WIDTH=6,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=false,REF_CLK_FREQ_MAX_CACHE=0.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=0.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=,REF_CLK_NS=0.0,REF_CLK_PS=0.0,REGISTER_C2P=false,SCC_DATA_WIDTH=0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=0,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=0.0,TB_MEM_IF_DQ_WIDTH=0,TB_MEM_IF_READ_DQS_WIDTH=0,TB_PLL_DLL_MASTER=true,TB_RATE=,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.05,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.01,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=-0.01,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.0,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.0,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.0,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.0,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=0,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=false,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,device=5CSEMA5F31C6,hps_parameter_map=AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 1.25 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 200000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 32 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 4 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 1000.0 MEM_TRCD 6 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA5F31C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 14 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 25.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 64 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 125 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.02 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 32 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 25.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 25000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 2500.0 periph_pll_vco_hz 1000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 30 PLL_WRITE_CLK_PHASE_PS_CACHE 1875 UART0_PinMuxing {HPS I/O Set 0} sdmmc_clk_hz 200000000 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode RGMII NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz 1600000000 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 2.5 PLL_AFI_CLK_MULT_CACHE 32 PLL_ADDR_CMD_CLK_DIV 2 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 3 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 32 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {45000 ps} PLL_AFI_CLK_DIV 2 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 13.75 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 400.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 2 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.8 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.08 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 25000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 200.0 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 180 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {25.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.03 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 6 TIMING_TIH 140 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 0 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing {HPS I/O Set 0} desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 200000000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_8 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 1875 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 200.0 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 30 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 6 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 65 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {2500 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 20 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 32 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 64 PLL_AFI_PHY_CLK_FREQ 400.0 periph_nand_sdmmc_clk_mhz 200.0 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000110 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No Yes No No No No Yes No No No No No No No Yes No No No No Yes Yes No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 4 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {400.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode I2C IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 12500000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.09 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 200000000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 35.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 2 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {2500 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED true TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode {No Flow Control} S2FCLK_USER0CLK_FREQ_HZ 97368421 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 800.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 4 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 1875 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 8 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 10 dbg_timer_clk_hz 25000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode {Single Slave Select} hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 97.368421 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM RZQ/4 AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 40000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_6 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 13.75 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 8 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.16 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 40.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 2 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 400.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_6 MR2_RTT_WR 1 MEM_TCL 11 GPIO_Pin_Used_DERIVED true JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 104 USE_2X_FF false ENUM_MEM_IF_TRC TRC_20 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 27 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 50000000 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable true desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 2 F2SDRAM_Width {} dbg_clk_hz 12500000 PLL_AFI_CLK_FREQ 400.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.18 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 400.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 66.6666666667 dbg_timer_clk_mhz 25.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {2500 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 9 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 0 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {1875 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 15 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 100.0 PLL_AFI_HALF_CLK_MULT_CACHE 32 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 32 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 400.0 AFI_WRITE_DQS_WIDTH 4 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 200.0 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 25000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.16 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 10 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 200.0 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz 1600.0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.33 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {1875 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {2500 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 15 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {1875 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0010011101000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/7 MEM_IF_DM_WIDTH 4 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.7 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 32 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 32 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 30.0 DELAY_PER_OPA_TAP 312 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing {HPS I/O Set 0} MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {2500 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 12.5 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 6000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 2 ENUM_MEM_IF_TCL TCL_11 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR JEDEC device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing {HPS I/O Set 0} CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_4 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 2 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 97.368421 MR2_CWL 3 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 211 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 39 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 12.5 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 73 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 400.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 15 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 1 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 32000 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 MR0_BT 0 PLL_CONFIG_CLK_FREQ 22.2222222222 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 1 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {400.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 32 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 25.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR RZQ/4 TIMING_TDQSCK 255 REF_CLK_FREQ_CACHE 25.0 AC_ROM_MR0_DLL_RESET 0010101110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {15000 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0010001101001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 12 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {400.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing {HPS I/O Set 0} MEM_TREFI 3120 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 32 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 25.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.09 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {2500 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 4 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 10 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_6 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 50000000 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.165 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {2500 ps} emac1_clk_mhz 250.0 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 500 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 32 TIMING_BOARD_SKEW_WITHIN_DQS 0.01 ENUM_MEM_IF_TRAS TRAS_14 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 1 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.03 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 7 H2F_LW_AXI_CLOCK_FREQ 50000000 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {400.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 2 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {1875 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 12500000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 250000000 eosc2_clk_mhz 25.0 PLL_MEM_CLK_DIV_CACHE 2 periph_base_clk_mhz 200.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_32 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 8 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.24 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing {HPS I/O Set 0} INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 400.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 25.0 desired_cfg_clk_hz 97368421 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 2 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 200000000 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 4 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {5000 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 8 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 11 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 200000000 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 6249 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0001000011000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode I2C quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 3120 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 1875 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {400.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 4 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 260.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY true ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 4 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 1 pin_muxing_check {Cyclone V+5CSEMA5F31C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 100000000 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 2 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 200000 PLL_WRITE_CLK_MULT_CACHE 32 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 400.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 4 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 50.0 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} USB1.D0 USB1.D1 USB1.D2 USB1.D3 USB1.D4 USB1.D5 USB1.D6 USB1.D7 {} USB1.CLK USB1.STP USB1.DIR USB1.NXT EMAC1.TX_CLK EMAC1.TXD0 EMAC1.TXD1 EMAC1.TXD2 EMAC1.TXD3 EMAC1.RXD0 EMAC1.MDIO EMAC1.MDC EMAC1.RX_CTL EMAC1.TX_CTL EMAC1.RX_CLK EMAC1.RXD1 EMAC1.RXD2 EMAC1.RXD3 {} {} {} {} {} {} {} {} SDIO.CMD {} SDIO.D0 SDIO.D1 {} {} {} {} {} SDIO.CLK SDIO.D2 SDIO.D3 {} UART0.RX UART0.TX I2C1.SDA I2C1.SCL {} {} I2C0.SDA I2C0.SCL {} {} {} {} {} {} SPIM1.CLK SPIM1.MOSI SPIM1.MISO SPIM1.SS0} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 8 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 400.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 8 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 32 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0001000011000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000000000110 TB_MEM_CLK_FREQ 400.0 AC_ROM_MR0 0010001110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 18000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 400.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {2500 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 12.5 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 5 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_4 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing {HPS I/O Set 0} CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 25000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {5000 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode SDR ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.4 dbg_base_clk_hz 25000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 400.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 2 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 1250.0 S2FCLK_USER1CLK_Enable true SDIO_Mode {4-bit Data} desired_qspi_clk_mhz 400.0 MEM_TRFC 104 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2,ignoreSimulation=true,interfaceDefinition=instances {sdio_inst {entity_name cyclonev_hps_peripheral_sdmmc location HPSPERIPHERALSDMMC_X87_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} emac1_inst {entity_name cyclonev_hps_peripheral_emac location HPSPERIPHERALEMAC_X77_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c1_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y65_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} spim1_inst {entity_name cyclonev_hps_peripheral_spi_master location HPSPERIPHERALSPIMASTER_X87_Y53_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} uart0_inst {entity_name cyclonev_hps_peripheral_uart location HPSPERIPHERALUART_X87_Y45_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} @orderednames {emac1_inst sdio_inst usb1_inst spim1_inst uart0_inst i2c0_inst i2c1_inst gpio_inst hps_sdram_inst} usb1_inst {entity_name cyclonev_hps_peripheral_usb location HPSPERIPHERALUSB_X55_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} gpio_inst {entity_name cyclonev_hps_peripheral_gpio location HPSPERIPHERALGPIO_X87_Y74_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps_sdram_inst {entity_name hps_sdram location {} signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c0_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y67_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD0]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD1]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD2]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD3]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD0] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_MDIO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDIO]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDC]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CTL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CTL]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CLK] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD1] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD2] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD3] -to *} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1]} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D1]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D4] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D4]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D5] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D5]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D6] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D6]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D7] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D7]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_CLK] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_STP]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_DIR] -to *} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_NXT] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_MOSI]} {set_false_path -from [get_ports hps_io_hps_io_spim1_inst_MISO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_SS0]} {set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO09] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO09]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO35] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO35]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO40] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO40]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO48] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO48]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO53] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO53]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO54] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO54]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO61] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO61]}} properties {SUPPRESS_SDRAM_SYNTH 0 GENERATE_ISW 1} bfm_types {} intermediate_wire_count 48 interfaces {@orderednames {memory hps_io} memory {properties {} type conduit direction end signals {@orderednames {mem_a mem_ba mem_ck mem_ck_n mem_cke mem_cs_n mem_ras_n mem_cas_n mem_we_n mem_reset_n mem_dq mem_dqs mem_dqs_n mem_odt mem_dm oct_rzqin} mem_a {fragments {} properties {} internal_name mem_a width 15 instance_name hps_sdram_inst direction Output role mem_a} mem_ba {fragments {} properties {} internal_name mem_ba width 3 instance_name hps_sdram_inst direction Output role mem_ba} mem_ck {fragments {} properties {} internal_name mem_ck width 1 instance_name hps_sdram_inst direction Output role mem_ck} mem_ck_n {fragments {} properties {} internal_name mem_ck_n width 1 instance_name hps_sdram_inst direction Output role mem_ck_n} mem_cke {fragments {} properties {} internal_name mem_cke width 1 instance_name hps_sdram_inst direction Output role mem_cke} mem_cs_n {fragments {} properties {} internal_name mem_cs_n width 1 instance_name hps_sdram_inst direction Output role mem_cs_n} mem_ras_n {fragments {} properties {} internal_name mem_ras_n width 1 instance_name hps_sdram_inst direction Output role mem_ras_n} mem_cas_n {fragments {} properties {} internal_name mem_cas_n width 1 instance_name hps_sdram_inst direction Output role mem_cas_n} mem_we_n {fragments {} properties {} internal_name mem_we_n width 1 instance_name hps_sdram_inst direction Output role mem_we_n} mem_reset_n {fragments {} properties {} internal_name mem_reset_n width 1 instance_name hps_sdram_inst direction Output role mem_reset_n} mem_dq {fragments {} properties {} internal_name mem_dq width 32 instance_name hps_sdram_inst direction Bidir role mem_dq} mem_dqs {fragments {} properties {} internal_name mem_dqs width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs} mem_dqs_n {fragments {} properties {} internal_name mem_dqs_n width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs_n} mem_odt {fragments {} properties {} internal_name mem_odt width 1 instance_name hps_sdram_inst direction Output role mem_odt} mem_dm {fragments {} properties {} internal_name mem_dm width 4 instance_name hps_sdram_inst direction Output role mem_dm} oct_rzqin {fragments {} properties {} internal_name oct_rzqin width 1 instance_name hps_sdram_inst direction Input role oct_rzqin}}} hps_io {properties {} type conduit direction input signals {@orderednames {hps_io_emac1_inst_TX_CLK hps_io_emac1_inst_TXD0 hps_io_emac1_inst_TXD1 hps_io_emac1_inst_TXD2 hps_io_emac1_inst_TXD3 hps_io_emac1_inst_RXD0 hps_io_emac1_inst_MDIO hps_io_emac1_inst_MDC hps_io_emac1_inst_RX_CTL hps_io_emac1_inst_TX_CTL hps_io_emac1_inst_RX_CLK hps_io_emac1_inst_RXD1 hps_io_emac1_inst_RXD2 hps_io_emac1_inst_RXD3 hps_io_sdio_inst_CMD hps_io_sdio_inst_D0 hps_io_sdio_inst_D1 hps_io_sdio_inst_CLK hps_io_sdio_inst_D2 hps_io_sdio_inst_D3 hps_io_usb1_inst_D0 hps_io_usb1_inst_D1 hps_io_usb1_inst_D2 hps_io_usb1_inst_D3 hps_io_usb1_inst_D4 hps_io_usb1_inst_D5 hps_io_usb1_inst_D6 hps_io_usb1_inst_D7 hps_io_usb1_inst_CLK hps_io_usb1_inst_STP hps_io_usb1_inst_DIR hps_io_usb1_inst_NXT hps_io_spim1_inst_CLK hps_io_spim1_inst_MOSI hps_io_spim1_inst_MISO hps_io_spim1_inst_SS0 hps_io_uart0_inst_RX hps_io_uart0_inst_TX hps_io_i2c0_inst_SDA hps_io_i2c0_inst_SCL hps_io_i2c1_inst_SDA hps_io_i2c1_inst_SCL hps_io_gpio_inst_GPIO09 hps_io_gpio_inst_GPIO35 hps_io_gpio_inst_GPIO40 hps_io_gpio_inst_GPIO48 hps_io_gpio_inst_GPIO53 hps_io_gpio_inst_GPIO54 hps_io_gpio_inst_GPIO61} hps_io_emac1_inst_TX_CLK {fragments emac1_inst:EMAC_CLK_TX(0:0) properties {} internal_name hps_io_emac1_inst_TX_CLK width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CLK} hps_io_emac1_inst_TXD0 {fragments emac1_inst:EMAC_PHY_TXD(0:0) properties {} internal_name hps_io_emac1_inst_TXD0 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD0} hps_io_emac1_inst_TXD1 {fragments emac1_inst:EMAC_PHY_TXD(1:1) properties {} internal_name hps_io_emac1_inst_TXD1 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD1} hps_io_emac1_inst_TXD2 {fragments emac1_inst:EMAC_PHY_TXD(2:2) properties {} internal_name hps_io_emac1_inst_TXD2 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD2} hps_io_emac1_inst_TXD3 {fragments emac1_inst:EMAC_PHY_TXD(3:3) properties {} internal_name hps_io_emac1_inst_TXD3 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD3} hps_io_emac1_inst_RXD0 {fragments emac1_inst:EMAC_PHY_RXD(0:0) properties {} internal_name hps_io_emac1_inst_RXD0 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD0} hps_io_emac1_inst_MDIO {fragments emac1_inst:EMAC_GMII_MDO_I(0:0) properties {} internal_name hps_io_emac1_inst_MDIO width 1 instance_name hps_io tristate_output {{intermediate 1} {intermediate 0}} direction bidir role hps_io_emac1_inst_MDIO} hps_io_emac1_inst_MDC {fragments emac1_inst:EMAC_GMII_MDC(0:0) properties {} internal_name hps_io_emac1_inst_MDC width 1 instance_name hps_io direction output role hps_io_emac1_inst_MDC} hps_io_emac1_inst_RX_CTL {fragments emac1_inst:EMAC_PHY_RXDV(0:0) properties {} internal_name hps_io_emac1_inst_RX_CTL width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CTL} hps_io_emac1_inst_TX_CTL {fragments emac1_inst:EMAC_PHY_TX_OE(0:0) properties {} internal_name hps_io_emac1_inst_TX_CTL width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CTL} hps_io_emac1_inst_RX_CLK {fragments emac1_inst:EMAC_CLK_RX(0:0) properties {} internal_name hps_io_emac1_inst_RX_CLK width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CLK} hps_io_emac1_inst_RXD1 {fragments emac1_inst:EMAC_PHY_RXD(1:1) properties {} internal_name hps_io_emac1_inst_RXD1 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD1} hps_io_emac1_inst_RXD2 {fragments emac1_inst:EMAC_PHY_RXD(2:2) properties {} internal_name hps_io_emac1_inst_RXD2 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD2} hps_io_emac1_inst_RXD3 {fragments emac1_inst:EMAC_PHY_RXD(3:3) properties {} internal_name hps_io_emac1_inst_RXD3 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD3} hps_io_sdio_inst_CMD {fragments sdio_inst:SDMMC_CMD_I(0:0) properties {} internal_name hps_io_sdio_inst_CMD width 1 instance_name hps_io tristate_output {{intermediate 3} {intermediate 2}} direction bidir role hps_io_sdio_inst_CMD} hps_io_sdio_inst_D0 {fragments sdio_inst:SDMMC_DATA_I(0:0) properties {} internal_name hps_io_sdio_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 5} {intermediate 4}} direction bidir role hps_io_sdio_inst_D0} hps_io_sdio_inst_D1 {fragments sdio_inst:SDMMC_DATA_I(1:1) properties {} internal_name hps_io_sdio_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 7} {intermediate 6}} direction bidir role hps_io_sdio_inst_D1} hps_io_sdio_inst_CLK {fragments sdio_inst:SDMMC_CCLK(0:0) properties {} internal_name hps_io_sdio_inst_CLK width 1 instance_name hps_io direction output role hps_io_sdio_inst_CLK} hps_io_sdio_inst_D2 {fragments sdio_inst:SDMMC_DATA_I(2:2) properties {} internal_name hps_io_sdio_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 9} {intermediate 8}} direction bidir role hps_io_sdio_inst_D2} hps_io_sdio_inst_D3 {fragments sdio_inst:SDMMC_DATA_I(3:3) properties {} internal_name hps_io_sdio_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 11} {intermediate 10}} direction bidir role hps_io_sdio_inst_D3} hps_io_usb1_inst_D0 {fragments usb1_inst:USB_ULPI_DATA_I(0:0) properties {} internal_name hps_io_usb1_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 13} {intermediate 12}} direction bidir role hps_io_usb1_inst_D0} hps_io_usb1_inst_D1 {fragments usb1_inst:USB_ULPI_DATA_I(1:1) properties {} internal_name hps_io_usb1_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 15} {intermediate 14}} direction bidir role hps_io_usb1_inst_D1} hps_io_usb1_inst_D2 {fragments usb1_inst:USB_ULPI_DATA_I(2:2) properties {} internal_name hps_io_usb1_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 17} {intermediate 16}} direction bidir role hps_io_usb1_inst_D2} hps_io_usb1_inst_D3 {fragments usb1_inst:USB_ULPI_DATA_I(3:3) properties {} internal_name hps_io_usb1_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 19} {intermediate 18}} direction bidir role hps_io_usb1_inst_D3} hps_io_usb1_inst_D4 {fragments usb1_inst:USB_ULPI_DATA_I(4:4) properties {} internal_name hps_io_usb1_inst_D4 width 1 instance_name hps_io tristate_output {{intermediate 21} {intermediate 20}} direction bidir role hps_io_usb1_inst_D4} hps_io_usb1_inst_D5 {fragments usb1_inst:USB_ULPI_DATA_I(5:5) properties {} internal_name hps_io_usb1_inst_D5 width 1 instance_name hps_io tristate_output {{intermediate 23} {intermediate 22}} direction bidir role hps_io_usb1_inst_D5} hps_io_usb1_inst_D6 {fragments usb1_inst:USB_ULPI_DATA_I(6:6) properties {} internal_name hps_io_usb1_inst_D6 width 1 instance_name hps_io tristate_output {{intermediate 25} {intermediate 24}} direction bidir role hps_io_usb1_inst_D6} hps_io_usb1_inst_D7 {fragments usb1_inst:USB_ULPI_DATA_I(7:7) properties {} internal_name hps_io_usb1_inst_D7 width 1 instance_name hps_io tristate_output {{intermediate 27} {intermediate 26}} direction bidir role hps_io_usb1_inst_D7} hps_io_usb1_inst_CLK {fragments usb1_inst:USB_ULPI_CLK(0:0) properties {} internal_name hps_io_usb1_inst_CLK width 1 instance_name hps_io direction input role hps_io_usb1_inst_CLK} hps_io_usb1_inst_STP {fragments usb1_inst:USB_ULPI_STP(0:0) properties {} internal_name hps_io_usb1_inst_STP width 1 instance_name hps_io direction output role hps_io_usb1_inst_STP} hps_io_usb1_inst_DIR {fragments usb1_inst:USB_ULPI_DIR(0:0) properties {} internal_name hps_io_usb1_inst_DIR width 1 instance_name hps_io direction input role hps_io_usb1_inst_DIR} hps_io_usb1_inst_NXT {fragments usb1_inst:USB_ULPI_NXT(0:0) properties {} internal_name hps_io_usb1_inst_NXT width 1 instance_name hps_io direction input role hps_io_usb1_inst_NXT} hps_io_spim1_inst_CLK {fragments spim1_inst:SPI_MASTER_SCLK(0:0) properties {} internal_name hps_io_spim1_inst_CLK width 1 instance_name hps_io direction output role hps_io_spim1_inst_CLK} hps_io_spim1_inst_MOSI {fragments {} properties {} internal_name hps_io_spim1_inst_MOSI width 1 instance_name hps_io tristate_output {{intermediate 29} {intermediate 28}} direction output role hps_io_spim1_inst_MOSI} hps_io_spim1_inst_MISO {fragments spim1_inst:SPI_MASTER_RXD(0:0) properties {} internal_name hps_io_spim1_inst_MISO width 1 instance_name hps_io direction input role hps_io_spim1_inst_MISO} hps_io_spim1_inst_SS0 {fragments spim1_inst:SPI_MASTER_SS_0_N(0:0) properties {} internal_name hps_io_spim1_inst_SS0 width 1 instance_name hps_io direction output role hps_io_spim1_inst_SS0} hps_io_uart0_inst_RX {fragments uart0_inst:UART_RXD(0:0) properties {} internal_name hps_io_uart0_inst_RX width 1 instance_name hps_io direction input role hps_io_uart0_inst_RX} hps_io_uart0_inst_TX {fragments uart0_inst:UART_TXD(0:0) properties {} internal_name hps_io_uart0_inst_TX width 1 instance_name hps_io direction output role hps_io_uart0_inst_TX} hps_io_i2c0_inst_SDA {fragments i2c0_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c0_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 30} {}} direction bidir role hps_io_i2c0_inst_SDA} hps_io_i2c0_inst_SCL {fragments i2c0_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c0_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 31} {}} direction bidir role hps_io_i2c0_inst_SCL} hps_io_i2c1_inst_SDA {fragments i2c1_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c1_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 32} {}} direction bidir role hps_io_i2c1_inst_SDA} hps_io_i2c1_inst_SCL {fragments i2c1_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c1_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 33} {}} direction bidir role hps_io_i2c1_inst_SCL} hps_io_gpio_inst_GPIO09 {fragments gpio_inst:GPIO0_PORTA_I(9:9) properties {} internal_name hps_io_gpio_inst_GPIO09 width 1 instance_name hps_io tristate_output {{intermediate 35} {intermediate 34}} direction bidir role hps_io_gpio_inst_GPIO09} hps_io_gpio_inst_GPIO35 {fragments gpio_inst:GPIO1_PORTA_I(6:6) properties {} internal_name hps_io_gpio_inst_GPIO35 width 1 instance_name hps_io tristate_output {{intermediate 37} {intermediate 36}} direction bidir role hps_io_gpio_inst_GPIO35} hps_io_gpio_inst_GPIO40 {fragments gpio_inst:GPIO1_PORTA_I(11:11) properties {} internal_name hps_io_gpio_inst_GPIO40 width 1 instance_name hps_io tristate_output {{intermediate 39} {intermediate 38}} direction bidir role hps_io_gpio_inst_GPIO40} hps_io_gpio_inst_GPIO48 {fragments gpio_inst:GPIO1_PORTA_I(19:19) properties {} internal_name hps_io_gpio_inst_GPIO48 width 1 instance_name hps_io tristate_output {{intermediate 41} {intermediate 40}} direction bidir role hps_io_gpio_inst_GPIO48} hps_io_gpio_inst_GPIO53 {fragments gpio_inst:GPIO1_PORTA_I(24:24) properties {} internal_name hps_io_gpio_inst_GPIO53 width 1 instance_name hps_io tristate_output {{intermediate 43} {intermediate 42}} direction bidir role hps_io_gpio_inst_GPIO53} hps_io_gpio_inst_GPIO54 {fragments gpio_inst:GPIO1_PORTA_I(25:25) properties {} internal_name hps_io_gpio_inst_GPIO54 width 1 instance_name hps_io tristate_output {{intermediate 45} {intermediate 44}} direction bidir role hps_io_gpio_inst_GPIO54} hps_io_gpio_inst_GPIO61 {fragments gpio_inst:GPIO2_PORTA_I(3:3) properties {} internal_name hps_io_gpio_inst_GPIO61 width 1 instance_name hps_io tristate_output {{intermediate 47} {intermediate 46}} direction bidir role hps_io_gpio_inst_GPIO61}}}} wires_to_fragments {{intermediate 9} {output sdio_inst:SDMMC_DATA_OE(2:2)} {intermediate 8} {output sdio_inst:SDMMC_DATA_O(2:2)} {intermediate 7} {output sdio_inst:SDMMC_DATA_OE(1:1)} {intermediate 6} {output sdio_inst:SDMMC_DATA_O(1:1)} {intermediate 5} {output sdio_inst:SDMMC_DATA_OE(0:0)} {intermediate 4} {output sdio_inst:SDMMC_DATA_O(0:0)} {intermediate 3} {output sdio_inst:SDMMC_CMD_OE(0:0)} {intermediate 2} {output sdio_inst:SDMMC_CMD_O(0:0)} {intermediate 1} {output emac1_inst:EMAC_GMII_MDO_OE(0:0)} {intermediate 0} {output emac1_inst:EMAC_GMII_MDO_O(0:0)} {intermediate 19} {output usb1_inst:USB_ULPI_DATA_OE(3:3)} {intermediate 18} {output usb1_inst:USB_ULPI_DATA_O(3:3)} {intermediate 17} {output usb1_inst:USB_ULPI_DATA_OE(2:2)} {intermediate 16} {output usb1_inst:USB_ULPI_DATA_O(2:2)} {intermediate 47} {output gpio_inst:GPIO2_PORTA_OE(3:3)} {intermediate 15} {output usb1_inst:USB_ULPI_DATA_OE(1:1)} {intermediate 46} {output gpio_inst:GPIO2_PORTA_O(3:3)} {intermediate 14} {output usb1_inst:USB_ULPI_DATA_O(1:1)} {intermediate 45} {output gpio_inst:GPIO1_PORTA_OE(25:25)} {intermediate 13} {output usb1_inst:USB_ULPI_DATA_OE(0:0)} {intermediate 44} {output gpio_inst:GPIO1_PORTA_O(25:25)} {intermediate 12} {output usb1_inst:USB_ULPI_DATA_O(0:0)} {intermediate 43} {output gpio_inst:GPIO1_PORTA_OE(24:24)} {intermediate 11} {output sdio_inst:SDMMC_DATA_OE(3:3)} {intermediate 42} {output gpio_inst:GPIO1_PORTA_O(24:24)} {intermediate 10} {output sdio_inst:SDMMC_DATA_O(3:3)} {intermediate 41} {output gpio_inst:GPIO1_PORTA_OE(19:19)} {intermediate 40} {output gpio_inst:GPIO1_PORTA_O(19:19)} {intermediate 39} {output gpio_inst:GPIO1_PORTA_OE(11:11)} {intermediate 38} {output gpio_inst:GPIO1_PORTA_O(11:11)} {intermediate 37} {output gpio_inst:GPIO1_PORTA_OE(6:6)} {intermediate 36} {output gpio_inst:GPIO1_PORTA_O(6:6)} {intermediate 35} {output gpio_inst:GPIO0_PORTA_OE(9:9)} {intermediate 34} {output gpio_inst:GPIO0_PORTA_O(9:9)} {intermediate 33} {output i2c1_inst:I2C_CLK_OE(0:0)} {intermediate 32} {output i2c1_inst:I2C_DATA_OE(0:0)} {intermediate 31} {output i2c0_inst:I2C_CLK_OE(0:0)} {intermediate 30} {output i2c0_inst:I2C_DATA_OE(0:0)} {intermediate 29} {output spim1_inst:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 28} {output spim1_inst:SPI_MASTER_TXD(0:0)} {intermediate 27} {output usb1_inst:USB_ULPI_DATA_OE(7:7)} {intermediate 26} {output usb1_inst:USB_ULPI_DATA_O(7:7)} {intermediate 25} {output usb1_inst:USB_ULPI_DATA_OE(6:6)} {intermediate 24} {output usb1_inst:USB_ULPI_DATA_O(6:6)} {intermediate 23} {output usb1_inst:USB_ULPI_DATA_OE(5:5)} {intermediate 22} {output usb1_inst:USB_ULPI_DATA_O(5:5)} {intermediate 21} {output usb1_inst:USB_ULPI_DATA_OE(4:4)} {intermediate 20} {output usb1_inst:USB_ULPI_DATA_O(4:4)}} raw_assign_sim_style {},qipEntries={set_instance_assignment -name hps_partition on -entity %entityName% -library %libraryName%}))(hps_clk_src:21.1:)(hps_bridge_avalon:21.1:BONDING_OUT_ENABLED=false,F2H_SDRAM0_CLOCK_FREQ=100,F2H_SDRAM1_CLOCK_FREQ=100,F2H_SDRAM2_CLOCK_FREQ=100,F2H_SDRAM3_CLOCK_FREQ=100,F2H_SDRAM4_CLOCK_FREQ=100,F2H_SDRAM5_CLOCK_FREQ=100,F2SDRAM_Type=,F2SDRAM_Width=,F2S_Width=2,LWH2F_Enable=true,S2F_Width=2,address_map=&lt;address-map&gt;&lt;slave name=&apos;axi_sdram.axi_slave0&apos; start=&apos;0x0&apos; end=&apos;0x80000000&apos; /&gt;&lt;slave name=&apos;gmac0.axi_slave0&apos; start=&apos;0xFF700000&apos; end=&apos;0xFF702000&apos; /&gt;&lt;slave name=&apos;gmac1.axi_slave0&apos; start=&apos;0xFF702000&apos; end=&apos;0xFF704000&apos; /&gt;&lt;slave name=&apos;sdmmc.axi_slave0&apos; start=&apos;0xFF704000&apos; end=&apos;0xFF705000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave0&apos; start=&apos;0xFF705000&apos; end=&apos;0xFF705100&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave0&apos; start=&apos;0xFF706000&apos; end=&apos;0xFF707000&apos; /&gt;&lt;slave name=&apos;gpio0.axi_slave0&apos; start=&apos;0xFF708000&apos; end=&apos;0xFF708100&apos; /&gt;&lt;slave name=&apos;gpio1.axi_slave0&apos; start=&apos;0xFF709000&apos; end=&apos;0xFF709100&apos; /&gt;&lt;slave name=&apos;gpio2.axi_slave0&apos; start=&apos;0xFF70A000&apos; end=&apos;0xFF70A100&apos; /&gt;&lt;slave name=&apos;l3regs.axi_slave0&apos; start=&apos;0xFF800000&apos; end=&apos;0xFF801000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave0&apos; start=&apos;0xFF900000&apos; end=&apos;0xFF910000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave1&apos; start=&apos;0xFFA00000&apos; end=&apos;0xFFA00100&apos; /&gt;&lt;slave name=&apos;usb0.axi_slave0&apos; start=&apos;0xFFB00000&apos; end=&apos;0xFFB40000&apos; /&gt;&lt;slave name=&apos;usb1.axi_slave0&apos; start=&apos;0xFFB40000&apos; end=&apos;0xFFB80000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave1&apos; start=&apos;0xFFB80000&apos; end=&apos;0xFFB90000&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave1&apos; start=&apos;0xFFB90000&apos; end=&apos;0xFFB90100&apos; /&gt;&lt;slave name=&apos;dcan0.axi_slave0&apos; start=&apos;0xFFC00000&apos; end=&apos;0xFFC01000&apos; /&gt;&lt;slave name=&apos;dcan1.axi_slave0&apos; start=&apos;0xFFC01000&apos; end=&apos;0xFFC02000&apos; /&gt;&lt;slave name=&apos;uart0.axi_slave0&apos; start=&apos;0xFFC02000&apos; end=&apos;0xFFC02100&apos; /&gt;&lt;slave name=&apos;uart1.axi_slave0&apos; start=&apos;0xFFC03000&apos; end=&apos;0xFFC03100&apos; /&gt;&lt;slave name=&apos;i2c0.axi_slave0&apos; start=&apos;0xFFC04000&apos; end=&apos;0xFFC04100&apos; /&gt;&lt;slave name=&apos;i2c1.axi_slave0&apos; start=&apos;0xFFC05000&apos; end=&apos;0xFFC05100&apos; /&gt;&lt;slave name=&apos;i2c2.axi_slave0&apos; start=&apos;0xFFC06000&apos; end=&apos;0xFFC06100&apos; /&gt;&lt;slave name=&apos;i2c3.axi_slave0&apos; start=&apos;0xFFC07000&apos; end=&apos;0xFFC07100&apos; /&gt;&lt;slave name=&apos;timer0.axi_slave0&apos; start=&apos;0xFFC08000&apos; end=&apos;0xFFC08100&apos; /&gt;&lt;slave name=&apos;timer1.axi_slave0&apos; start=&apos;0xFFC09000&apos; end=&apos;0xFFC09100&apos; /&gt;&lt;slave name=&apos;sdrctl.axi_slave0&apos; start=&apos;0xFFC25000&apos; end=&apos;0xFFC26000&apos; /&gt;&lt;slave name=&apos;timer2.axi_slave0&apos; start=&apos;0xFFD00000&apos; end=&apos;0xFFD00100&apos; /&gt;&lt;slave name=&apos;timer3.axi_slave0&apos; start=&apos;0xFFD01000&apos; end=&apos;0xFFD01100&apos; /&gt;&lt;slave name=&apos;clkmgr.axi_slave0&apos; start=&apos;0xFFD04000&apos; end=&apos;0xFFD05000&apos; /&gt;&lt;slave name=&apos;rstmgr.axi_slave0&apos; start=&apos;0xFFD05000&apos; end=&apos;0xFFD05100&apos; /&gt;&lt;slave name=&apos;sysmgr.axi_slave0&apos; start=&apos;0xFFD08000&apos; end=&apos;0xFFD08400&apos; /&gt;&lt;slave name=&apos;dma.axi_slave0&apos; start=&apos;0xFFE01000&apos; end=&apos;0xFFE02000&apos; /&gt;&lt;slave name=&apos;spim0.axi_slave0&apos; start=&apos;0xFFF00000&apos; end=&apos;0xFFF00100&apos; /&gt;&lt;slave name=&apos;spim1.axi_slave0&apos; start=&apos;0xFFF01000&apos; end=&apos;0xFFF01100&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave1&apos; start=&apos;0xFFFEC100&apos; end=&apos;0xFFFEC200&apos; /&gt;&lt;slave name=&apos;timer.axi_slave0&apos; start=&apos;0xFFFEC600&apos; end=&apos;0xFFFEC700&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave0&apos; start=&apos;0xFFFED000&apos; end=&apos;0xFFFEE000&apos; /&gt;&lt;slave name=&apos;L2.axi_slave0&apos; start=&apos;0xFFFEF000&apos; end=&apos;0xFFFF0000&apos; /&gt;&lt;slave name=&apos;axi_ocram.axi_slave0&apos; start=&apos;0xFFFF0000&apos; end=&apos;0x100000000&apos; /&gt;&lt;/address-map&gt;,quartus_ini_hps_ip_f2sdram_bonding_out=false)(hps_virt_clk:21.1:clockFrequency=25000000)(hps_virt_clk:21.1:clockFrequency=25000000)(hps_virt_clk:21.1:clockFrequency=0)(hps_virt_clk:21.1:clockFrequency=0)(arm_a9:21.1:address_map=&lt;address-map&gt;&lt;slave name=&apos;axi_sdram.axi_slave0&apos; start=&apos;0x0&apos; end=&apos;0x80000000&apos; /&gt;&lt;slave name=&apos;bridges.axi_h2f&apos; start=&apos;0xC0000000&apos; end=&apos;0xE0000000&apos; /&gt;&lt;slave name=&apos;bridges.axi_h2f_lw&apos; start=&apos;0xFF200000&apos; end=&apos;0xFF400000&apos; /&gt;&lt;slave name=&apos;gmac0.axi_slave0&apos; start=&apos;0xFF700000&apos; end=&apos;0xFF702000&apos; /&gt;&lt;slave name=&apos;gmac1.axi_slave0&apos; start=&apos;0xFF702000&apos; end=&apos;0xFF704000&apos; /&gt;&lt;slave name=&apos;sdmmc.axi_slave0&apos; start=&apos;0xFF704000&apos; end=&apos;0xFF705000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave0&apos; start=&apos;0xFF705000&apos; end=&apos;0xFF705100&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave0&apos; start=&apos;0xFF706000&apos; end=&apos;0xFF707000&apos; /&gt;&lt;slave name=&apos;gpio0.axi_slave0&apos; start=&apos;0xFF708000&apos; end=&apos;0xFF708100&apos; /&gt;&lt;slave name=&apos;gpio1.axi_slave0&apos; start=&apos;0xFF709000&apos; end=&apos;0xFF709100&apos; /&gt;&lt;slave name=&apos;gpio2.axi_slave0&apos; start=&apos;0xFF70A000&apos; end=&apos;0xFF70A100&apos; /&gt;&lt;slave name=&apos;l3regs.axi_slave0&apos; start=&apos;0xFF800000&apos; end=&apos;0xFF801000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave0&apos; start=&apos;0xFF900000&apos; end=&apos;0xFF910000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave1&apos; start=&apos;0xFFA00000&apos; end=&apos;0xFFA00100&apos; /&gt;&lt;slave name=&apos;usb0.axi_slave0&apos; start=&apos;0xFFB00000&apos; end=&apos;0xFFB40000&apos; /&gt;&lt;slave name=&apos;usb1.axi_slave0&apos; start=&apos;0xFFB40000&apos; end=&apos;0xFFB80000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave1&apos; start=&apos;0xFFB80000&apos; end=&apos;0xFFB90000&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave1&apos; start=&apos;0xFFB90000&apos; end=&apos;0xFFB90100&apos; /&gt;&lt;slave name=&apos;dcan0.axi_slave0&apos; start=&apos;0xFFC00000&apos; end=&apos;0xFFC01000&apos; /&gt;&lt;slave name=&apos;dcan1.axi_slave0&apos; start=&apos;0xFFC01000&apos; end=&apos;0xFFC02000&apos; /&gt;&lt;slave name=&apos;uart0.axi_slave0&apos; start=&apos;0xFFC02000&apos; end=&apos;0xFFC02100&apos; /&gt;&lt;slave name=&apos;uart1.axi_slave0&apos; start=&apos;0xFFC03000&apos; end=&apos;0xFFC03100&apos; /&gt;&lt;slave name=&apos;i2c0.axi_slave0&apos; start=&apos;0xFFC04000&apos; end=&apos;0xFFC04100&apos; /&gt;&lt;slave name=&apos;i2c1.axi_slave0&apos; start=&apos;0xFFC05000&apos; end=&apos;0xFFC05100&apos; /&gt;&lt;slave name=&apos;i2c2.axi_slave0&apos; start=&apos;0xFFC06000&apos; end=&apos;0xFFC06100&apos; /&gt;&lt;slave name=&apos;i2c3.axi_slave0&apos; start=&apos;0xFFC07000&apos; end=&apos;0xFFC07100&apos; /&gt;&lt;slave name=&apos;timer0.axi_slave0&apos; start=&apos;0xFFC08000&apos; end=&apos;0xFFC08100&apos; /&gt;&lt;slave name=&apos;timer1.axi_slave0&apos; start=&apos;0xFFC09000&apos; end=&apos;0xFFC09100&apos; /&gt;&lt;slave name=&apos;sdrctl.axi_slave0&apos; start=&apos;0xFFC25000&apos; end=&apos;0xFFC26000&apos; /&gt;&lt;slave name=&apos;timer2.axi_slave0&apos; start=&apos;0xFFD00000&apos; end=&apos;0xFFD00100&apos; /&gt;&lt;slave name=&apos;timer3.axi_slave0&apos; start=&apos;0xFFD01000&apos; end=&apos;0xFFD01100&apos; /&gt;&lt;slave name=&apos;wd_timer0.axi_slave0&apos; start=&apos;0xFFD02000&apos; end=&apos;0xFFD02100&apos; /&gt;&lt;slave name=&apos;wd_timer1.axi_slave0&apos; start=&apos;0xFFD03000&apos; end=&apos;0xFFD03100&apos; /&gt;&lt;slave name=&apos;clkmgr.axi_slave0&apos; start=&apos;0xFFD04000&apos; end=&apos;0xFFD05000&apos; /&gt;&lt;slave name=&apos;rstmgr.axi_slave0&apos; start=&apos;0xFFD05000&apos; end=&apos;0xFFD05100&apos; /&gt;&lt;slave name=&apos;sysmgr.axi_slave0&apos; start=&apos;0xFFD08000&apos; end=&apos;0xFFD08400&apos; /&gt;&lt;slave name=&apos;dma.axi_slave0&apos; start=&apos;0xFFE01000&apos; end=&apos;0xFFE02000&apos; /&gt;&lt;slave name=&apos;spim0.axi_slave0&apos; start=&apos;0xFFF00000&apos; end=&apos;0xFFF00100&apos; /&gt;&lt;slave name=&apos;spim1.axi_slave0&apos; start=&apos;0xFFF01000&apos; end=&apos;0xFFF01100&apos; /&gt;&lt;slave name=&apos;scu.axi_slave0&apos; start=&apos;0xFFFEC000&apos; end=&apos;0xFFFEC100&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave1&apos; start=&apos;0xFFFEC100&apos; end=&apos;0xFFFEC200&apos; /&gt;&lt;slave name=&apos;timer.axi_slave0&apos; start=&apos;0xFFFEC600&apos; end=&apos;0xFFFEC700&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave0&apos; start=&apos;0xFFFED000&apos; end=&apos;0xFFFEE000&apos; /&gt;&lt;slave name=&apos;L2.axi_slave0&apos; start=&apos;0xFFFEF000&apos; end=&apos;0xFFFF0000&apos; /&gt;&lt;slave name=&apos;axi_ocram.axi_slave0&apos; start=&apos;0xFFFF0000&apos; end=&apos;0x100000000&apos; /&gt;&lt;/address-map&gt;)(arm_a9:21.1:address_map=&lt;address-map&gt;&lt;slave name=&apos;axi_sdram.axi_slave0&apos; start=&apos;0x0&apos; end=&apos;0x80000000&apos; /&gt;&lt;slave name=&apos;bridges.axi_h2f&apos; start=&apos;0xC0000000&apos; end=&apos;0xE0000000&apos; /&gt;&lt;slave name=&apos;bridges.axi_h2f_lw&apos; start=&apos;0xFF200000&apos; end=&apos;0xFF400000&apos; /&gt;&lt;slave name=&apos;gmac0.axi_slave0&apos; start=&apos;0xFF700000&apos; end=&apos;0xFF702000&apos; /&gt;&lt;slave name=&apos;gmac1.axi_slave0&apos; start=&apos;0xFF702000&apos; end=&apos;0xFF704000&apos; /&gt;&lt;slave name=&apos;sdmmc.axi_slave0&apos; start=&apos;0xFF704000&apos; end=&apos;0xFF705000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave0&apos; start=&apos;0xFF705000&apos; end=&apos;0xFF705100&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave0&apos; start=&apos;0xFF706000&apos; end=&apos;0xFF707000&apos; /&gt;&lt;slave name=&apos;gpio0.axi_slave0&apos; start=&apos;0xFF708000&apos; end=&apos;0xFF708100&apos; /&gt;&lt;slave name=&apos;gpio1.axi_slave0&apos; start=&apos;0xFF709000&apos; end=&apos;0xFF709100&apos; /&gt;&lt;slave name=&apos;gpio2.axi_slave0&apos; start=&apos;0xFF70A000&apos; end=&apos;0xFF70A100&apos; /&gt;&lt;slave name=&apos;l3regs.axi_slave0&apos; start=&apos;0xFF800000&apos; end=&apos;0xFF801000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave0&apos; start=&apos;0xFF900000&apos; end=&apos;0xFF910000&apos; /&gt;&lt;slave name=&apos;qspi.axi_slave1&apos; start=&apos;0xFFA00000&apos; end=&apos;0xFFA00100&apos; /&gt;&lt;slave name=&apos;usb0.axi_slave0&apos; start=&apos;0xFFB00000&apos; end=&apos;0xFFB40000&apos; /&gt;&lt;slave name=&apos;usb1.axi_slave0&apos; start=&apos;0xFFB40000&apos; end=&apos;0xFFB80000&apos; /&gt;&lt;slave name=&apos;nand0.axi_slave1&apos; start=&apos;0xFFB80000&apos; end=&apos;0xFFB90000&apos; /&gt;&lt;slave name=&apos;fpgamgr.axi_slave1&apos; start=&apos;0xFFB90000&apos; end=&apos;0xFFB90100&apos; /&gt;&lt;slave name=&apos;dcan0.axi_slave0&apos; start=&apos;0xFFC00000&apos; end=&apos;0xFFC01000&apos; /&gt;&lt;slave name=&apos;dcan1.axi_slave0&apos; start=&apos;0xFFC01000&apos; end=&apos;0xFFC02000&apos; /&gt;&lt;slave name=&apos;uart0.axi_slave0&apos; start=&apos;0xFFC02000&apos; end=&apos;0xFFC02100&apos; /&gt;&lt;slave name=&apos;uart1.axi_slave0&apos; start=&apos;0xFFC03000&apos; end=&apos;0xFFC03100&apos; /&gt;&lt;slave name=&apos;i2c0.axi_slave0&apos; start=&apos;0xFFC04000&apos; end=&apos;0xFFC04100&apos; /&gt;&lt;slave name=&apos;i2c1.axi_slave0&apos; start=&apos;0xFFC05000&apos; end=&apos;0xFFC05100&apos; /&gt;&lt;slave name=&apos;i2c2.axi_slave0&apos; start=&apos;0xFFC06000&apos; end=&apos;0xFFC06100&apos; /&gt;&lt;slave name=&apos;i2c3.axi_slave0&apos; start=&apos;0xFFC07000&apos; end=&apos;0xFFC07100&apos; /&gt;&lt;slave name=&apos;timer0.axi_slave0&apos; start=&apos;0xFFC08000&apos; end=&apos;0xFFC08100&apos; /&gt;&lt;slave name=&apos;timer1.axi_slave0&apos; start=&apos;0xFFC09000&apos; end=&apos;0xFFC09100&apos; /&gt;&lt;slave name=&apos;sdrctl.axi_slave0&apos; start=&apos;0xFFC25000&apos; end=&apos;0xFFC26000&apos; /&gt;&lt;slave name=&apos;timer2.axi_slave0&apos; start=&apos;0xFFD00000&apos; end=&apos;0xFFD00100&apos; /&gt;&lt;slave name=&apos;timer3.axi_slave0&apos; start=&apos;0xFFD01000&apos; end=&apos;0xFFD01100&apos; /&gt;&lt;slave name=&apos;wd_timer0.axi_slave0&apos; start=&apos;0xFFD02000&apos; end=&apos;0xFFD02100&apos; /&gt;&lt;slave name=&apos;wd_timer1.axi_slave0&apos; start=&apos;0xFFD03000&apos; end=&apos;0xFFD03100&apos; /&gt;&lt;slave name=&apos;clkmgr.axi_slave0&apos; start=&apos;0xFFD04000&apos; end=&apos;0xFFD05000&apos; /&gt;&lt;slave name=&apos;rstmgr.axi_slave0&apos; start=&apos;0xFFD05000&apos; end=&apos;0xFFD05100&apos; /&gt;&lt;slave name=&apos;sysmgr.axi_slave0&apos; start=&apos;0xFFD08000&apos; end=&apos;0xFFD08400&apos; /&gt;&lt;slave name=&apos;dma.axi_slave0&apos; start=&apos;0xFFE01000&apos; end=&apos;0xFFE02000&apos; /&gt;&lt;slave name=&apos;spim0.axi_slave0&apos; start=&apos;0xFFF00000&apos; end=&apos;0xFFF00100&apos; /&gt;&lt;slave name=&apos;spim1.axi_slave0&apos; start=&apos;0xFFF01000&apos; end=&apos;0xFFF01100&apos; /&gt;&lt;slave name=&apos;scu.axi_slave0&apos; start=&apos;0xFFFEC000&apos; end=&apos;0xFFFEC100&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave1&apos; start=&apos;0xFFFEC100&apos; end=&apos;0xFFFEC200&apos; /&gt;&lt;slave name=&apos;timer.axi_slave0&apos; start=&apos;0xFFFEC600&apos; end=&apos;0xFFFEC700&apos; /&gt;&lt;slave name=&apos;arm_gic_0.axi_slave0&apos; start=&apos;0xFFFED000&apos; end=&apos;0xFFFEE000&apos; /&gt;&lt;slave name=&apos;L2.axi_slave0&apos; start=&apos;0xFFFEF000&apos; end=&apos;0xFFFF0000&apos; /&gt;&lt;slave name=&apos;axi_ocram.axi_slave0&apos; start=&apos;0xFFFF0000&apos; end=&apos;0x100000000&apos; /&gt;&lt;/address-map&gt;)(arm_gic:21.1:AUTO_ARM_GIC_PPI_INTERRUPTS_USED=8192,AUTO_F2H_IRQ_0_IRQ_RX_OFFSET_40_INTERRUPTS_USED=0,AUTO_F2H_IRQ_32_IRQ_RX_OFFSET_72_INTERRUPTS_USED=0,AUTO_IRQ_RX_OFFSET_0_INTERRUPTS_USED=0,AUTO_IRQ_RX_OFFSET_104_INTERRUPTS_USED=2569078785,AUTO_IRQ_RX_OFFSET_136_INTERRUPTS_USED=1070366985,AUTO_IRQ_RX_OFFSET_166_INTERRUPTS_USED=639,AUTO_IRQ_RX_OFFSET_32_INTERRUPTS_USED=64)(arm_pl310_L2:21.1:)(arm_pl330_dma:21.1:)(altera_sysmgr:21.1:cpu1_start_addr=4291854532)(asimov_clkmgr:21.1:F2SCLK_PERIPHCLK_Enable=false,F2SCLK_PERIPHCLK_FREQ=0,F2SCLK_PERIPHCLK_FREQ_MHZ=0.0,F2SCLK_SDRAMCLK_Enable=false,F2SCLK_SDRAMCLK_FREQ=0,F2SCLK_SDRAMCLK_FREQ_MHZ=0.0,S2FCLK_USER0CLK_Enable=false,S2FCLK_USER0CLK_FREQ=0.0,S2FCLK_USER0CLK_FREQ_HZ=0,S2FCLK_USER1CLK_Enable=true,S2FCLK_USER1CLK_FREQ=100.0,S2FCLK_USER1CLK_FREQ_HZ=0,S2FCLK_USER2CLK=5,S2FCLK_USER2CLK_Enable=false,S2FCLK_USER2CLK_FREQ=100.0,S2FCLK_USER2CLK_FREQ_HZ=0,can0_clk_div=1,can0_clk_div_auto=0,can0_clk_hz=0,can0_clk_mhz=0.0,can1_clk_div=1,can1_clk_div_auto=0,can1_clk_hz=0,can1_clk_mhz=0.0,cfg_clk_hz=0,cfg_clk_mhz=0.0,cfg_h2f_user0_clk_hz=0,cfg_h2f_user0_clk_mhz=0.0,configure_advanced_parameters=false,customize_device_pll_info=false,dbctrl_stayosc1=true,dbg_at_clk_div=0,dbg_at_clk_hz=0,dbg_at_clk_mhz=0.0,dbg_base_clk_hz=0,dbg_base_clk_mhz=0.0,dbg_clk_div=1,dbg_clk_hz=0,dbg_clk_mhz=0.0,dbg_timer_clk_hz=0,dbg_timer_clk_mhz=0.0,dbg_trace_clk_div=0,dbg_trace_clk_hz=0,dbg_trace_clk_mhz=0.0,default_mpu_clk_hz=0,default_mpu_clk_mhz=0.0,desired_can0_clk_hz=0,desired_can0_clk_mhz=100.0,desired_can1_clk_hz=0,desired_can1_clk_mhz=100.0,desired_cfg_clk_hz=0,desired_cfg_clk_mhz=97.368421,desired_emac0_clk_hz=0,desired_emac0_clk_mhz=250.0,desired_emac1_clk_hz=0,desired_emac1_clk_mhz=250.0,desired_gpio_db_clk_hz=32000,desired_l4_mp_clk_hz=0,desired_l4_mp_clk_mhz=100.0,desired_l4_sp_clk_hz=0,desired_l4_sp_clk_mhz=100.0,desired_mpu_clk_hz=0,desired_mpu_clk_mhz=800.0,desired_nand_clk_hz=0,desired_nand_clk_mhz=12.5,desired_qspi_clk_hz=0,desired_qspi_clk_mhz=400.0,desired_sdmmc_clk_hz=0,desired_sdmmc_clk_mhz=200.0,desired_spi_m_clk_hz=0,desired_spi_m_clk_mhz=200.0,desired_usb_mp_clk_hz=0,desired_usb_mp_clk_mhz=200.0,device_pll_info_auto=,device_pll_info_manual={320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000},emac0_clk_hz=0,emac0_clk_mhz=0.0,emac1_clk_hz=0,emac1_clk_mhz=0.0,eosc1_clk_hz=0,eosc1_clk_mhz=25.0,eosc2_clk_hz=0,eosc2_clk_mhz=25.0,gpio_db_clk_div=6249,gpio_db_clk_div_auto=1,gpio_db_clk_hz=0,h2f_user0_clk_hz=0,h2f_user0_clk_mhz=0.0,h2f_user1_clk_hz=0,h2f_user1_clk_mhz=0.0,l3_mp_clk_div=1,l3_mp_clk_hz=0,l3_mp_clk_mhz=0.0,l3_sp_clk_div=1,l3_sp_clk_hz=0,l3_sp_clk_mhz=0.0,l4_mp_clk_div=1,l4_mp_clk_div_auto=0,l4_mp_clk_hz=0,l4_mp_clk_mhz=0.0,l4_mp_clk_source=1,l4_sp_clk_div=1,l4_sp_clk_div_auto=0,l4_sp_clk_hz=0,l4_sp_clk_mhz=0.0,l4_sp_clk_source=1,main_clk_hz=0,main_clk_mhz=0.0,main_nand_sdmmc_clk_hz=0,main_nand_sdmmc_clk_mhz=0.0,main_pll_c0_internal=0,main_pll_c0_internal_auto=0,main_pll_c1_internal=0,main_pll_c1_internal_auto=0,main_pll_c2_internal=0,main_pll_c2_internal_auto=0,main_pll_c3=3,main_pll_c3_auto=0,main_pll_c4=3,main_pll_c4_auto=0,main_pll_c5=15,main_pll_c5_auto=0,main_pll_m=63,main_pll_m_auto=0,main_pll_n=0,main_pll_n_auto=0,main_pll_vco_auto_hz=0,main_pll_vco_auto_mhz=0.0,main_pll_vco_hz=0,main_pll_vco_mhz=0.0,main_qspi_clk_hz=0,main_qspi_clk_mhz=0.0,mpu_base_clk_hz=0,mpu_base_clk_mhz=0.0,mpu_clk_hz=0,mpu_clk_mhz=0.0,mpu_l2_ram_clk_hz=0,mpu_l2_ram_clk_mhz=0.0,mpu_periph_clk_hz=0,mpu_periph_clk_mhz=0.0,nand_clk_hz=0,nand_clk_mhz=0.0,nand_clk_source=2,nand_x_clk_hz=0,nand_x_clk_mhz=0.0,periph_base_clk_hz=0,periph_base_clk_mhz=0.0,periph_nand_sdmmc_clk_hz=0,periph_nand_sdmmc_clk_mhz=0.0,periph_pll_c0=3,periph_pll_c0_auto=0,periph_pll_c1=3,periph_pll_c1_auto=0,periph_pll_c2=1,periph_pll_c2_auto=0,periph_pll_c3=19,periph_pll_c3_auto=0,periph_pll_c4=4,periph_pll_c4_auto=0,periph_pll_c5=9,periph_pll_c5_auto=0,periph_pll_m=79,periph_pll_m_auto=0,periph_pll_n=1,periph_pll_n_auto=0,periph_pll_source=0,periph_pll_vco_auto_hz=0,periph_pll_vco_auto_mhz=0.0,periph_pll_vco_hz=0,periph_pll_vco_mhz=0.0,periph_qspi_clk_hz=0,periph_qspi_clk_mhz=0.0,qspi_clk_hz=0,qspi_clk_mhz=0.0,qspi_clk_source=1,sdmmc_clk_hz=0,sdmmc_clk_mhz=0.0,sdmmc_clk_source=2,show_advanced_parameters=false,show_debug_info_as_warning_msg=false,show_warning_as_error_msg=false,spi_m_clk_div=0,spi_m_clk_div_auto=0,spi_m_clk_hz=0,spi_m_clk_mhz=0.0,usb_mp_clk_div=0,usb_mp_clk_div_auto=0,usb_mp_clk_hz=0,usb_mp_clk_mhz=0.0,use_default_mpu_clk=true)(altera_rstmgr:21.1:offset=16)(altera_fpgamgr:21.1:compatible=altr,fpga-mgr altr,socfpga-fpga-mgr)(snps_uart:21.1:clk_freq_mhz=100.0,swEnabled=true)(snps_uart:21.1:clk_freq_mhz=100.0,swEnabled=false)(dw_apb_timer_sp:21.1:)(dw_apb_timer_sp:21.1:)(dw_apb_timer_osc:21.1:)(dw_apb_timer_osc:21.1:)(dw_wd_timer:21.1:)(dw_wd_timer:21.1:)(dw_gpio:21.1:embeddedsw.dts.instance.GPIO_PORTA_INTR=1,embeddedsw.dts.instance.GPIO_PWIDTH_A=29,embeddedsw.dts.instance.GPIO_PWIDTH_B=0,embeddedsw.dts.instance.GPIO_PWIDTH_C=0,embeddedsw.dts.instance.GPIO_PWIDTH_D=0)(dw_gpio:21.1:embeddedsw.dts.instance.GPIO_PORTA_INTR=1,embeddedsw.dts.instance.GPIO_PWIDTH_A=29,embeddedsw.dts.instance.GPIO_PWIDTH_B=0,embeddedsw.dts.instance.GPIO_PWIDTH_C=0,embeddedsw.dts.instance.GPIO_PWIDTH_D=0)(dw_gpio:21.1:embeddedsw.dts.instance.GPIO_PORTA_INTR=1,embeddedsw.dts.instance.GPIO_PWIDTH_A=27,embeddedsw.dts.instance.GPIO_PWIDTH_B=0,embeddedsw.dts.instance.GPIO_PWIDTH_C=0,embeddedsw.dts.instance.GPIO_PWIDTH_D=0)(designware_i2c:21.1:swEnabled=true)(designware_i2c:21.1:swEnabled=true)(designware_i2c:21.1:swEnabled=false)(designware_i2c:21.1:swEnabled=false)(denali_nand:21.1:swEnabled=false)(spi:21.1:swEnabled=false)(spi:21.1:swEnabled=true)(cadence_qspi:21.1:swEnabled=false)(sdmmc:21.1:swEnabled=true)(usb:21.1:swEnabled=false)(usb:21.1:swEnabled=true)(stmmac:21.1:compatible=altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac,rx_fifo_depth=4096,swEnabled=false,tx_fifo_depth=4096)(stmmac:21.1:compatible=altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac,rx_fifo_depth=4096,swEnabled=true,tx_fifo_depth=4096)(bosch_dcan:21.1:swEnabled=false)(bosch_dcan:21.1:swEnabled=false)(altera_l3regs:21.1:)(altera_sdrctl:21.1:)(axi_ocram:21.1:)(axi_sdram:21.1:)(arm_internal_timer:21.1:)(scu:21.1:)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xc0000000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xc0000000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff200000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff200000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(reset:21.1:)(clock:21.1:)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffed000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffed000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec100,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec100,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffef000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffef000,defaultConnection=false)(interrupt:21.1:irqNumber=6)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffe01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffe01000,defaultConnection=false)(interrupt:21.1:irqNumber=0)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd08000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd08000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd04000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd04000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd05000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd05000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff706000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff706000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb90000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb90000,defaultConnection=false)(interrupt:21.1:irqNumber=9)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc02000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc02000,defaultConnection=false)(interrupt:21.1:irqNumber=26)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc03000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc03000,defaultConnection=false)(interrupt:21.1:irqNumber=27)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc08000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc08000,defaultConnection=false)(interrupt:21.1:irqNumber=1)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc09000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc09000,defaultConnection=false)(interrupt:21.1:irqNumber=2)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd00000,defaultConnection=false)(interrupt:21.1:irqNumber=3)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd01000,defaultConnection=false)(interrupt:21.1:irqNumber=4)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd02000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd02000,defaultConnection=false)(interrupt:21.1:irqNumber=5)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd03000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd03000,defaultConnection=false)(interrupt:21.1:irqNumber=6)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff708000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff708000,defaultConnection=false)(interrupt:21.1:irqNumber=28)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff709000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff709000,defaultConnection=false)(interrupt:21.1:irqNumber=29)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff70a000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff70a000,defaultConnection=false)(interrupt:21.1:irqNumber=0)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc04000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc04000,defaultConnection=false)(interrupt:21.1:irqNumber=22)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc05000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc05000,defaultConnection=false)(interrupt:21.1:irqNumber=23)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc06000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc06000,defaultConnection=false)(interrupt:21.1:irqNumber=24)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc07000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc07000,defaultConnection=false)(interrupt:21.1:irqNumber=25)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff900000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff900000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb80000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb80000,defaultConnection=false)(interrupt:21.1:irqNumber=8)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff00000,defaultConnection=false)(interrupt:21.1:irqNumber=18)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff01000,defaultConnection=false)(interrupt:21.1:irqNumber=19)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff705000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff705000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffa00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffa00000,defaultConnection=false)(interrupt:21.1:irqNumber=15)(reset:21.1:)(clock:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff704000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff704000,defaultConnection=false)(interrupt:21.1:irqNumber=3)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb00000,defaultConnection=false)(interrupt:21.1:irqNumber=21)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb40000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb40000,defaultConnection=false)(interrupt:21.1:irqNumber=24)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff700000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff700000,defaultConnection=false)(interrupt:21.1:irqNumber=11)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff702000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff702000,defaultConnection=false)(interrupt:21.1:irqNumber=16)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc00000,defaultConnection=false)(interrupt:21.1:irqNumber=27)(interrupt:21.1:irqNumber=28)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc01000,defaultConnection=false)(interrupt:21.1:irqNumber=31)(interrupt:21.1:irqNumber=0)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff800000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff800000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc25000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc25000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffff0000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffff0000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec600,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec600,defaultConnection=false)(reset:21.1:)(clock:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec000,defaultConnection=false)(interrupt:21.1:irqNumber=13)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffed000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec100,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffef000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffe01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd08000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd04000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd05000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff706000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb90000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc02000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc03000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc08000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc09000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffd01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff708000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff709000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff70a000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc04000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc05000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc06000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc07000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff900000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb80000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfff01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff705000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffa00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff704000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffb40000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff700000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff702000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffff0000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xfffec600,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc00000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc01000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xff800000,defaultConnection=false)(avalon:21.1:arbitrationPriority=1,baseAddress=0xffc25000,defaultConnection=false)"
   instancePathKey="soc_system:.:hps_0"
   kind="altera_hps"
   version="21.1"
   name="soc_system_hps_0">
  <parameter name="VECT_ATTR_COUNTER_ZERO_MATCH" value="0" />
  <parameter name="LRDIMM_INT" value="0" />
  <parameter name="MEM_IF_ADDR_WIDTH_MIN" value="13" />
  <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
  <parameter name="MEM_LEVELING" value="false" />
  <parameter name="CV_ENUM_PRIORITY_1_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_1_2" value="WEIGHT_0" />
  <parameter name="ENUM_ATTR_COUNTER_ZERO_RESET" value="DISABLED" />
  <parameter name="CV_ENUM_PRIORITY_1_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_1_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_1_3" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR" value="2" />
  <parameter name="CV_ENUM_PRIORITY_1_5" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT" value="0" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="100" />
  <parameter
     name="DB_port_pins"
     value="i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}" />
  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
  <parameter name="INTG_MEM_IF_TRFC" value="104" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
  <parameter name="AFI_DQ_WIDTH" value="64" />
  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
  <parameter name="CALIB_LFIFO_OFFSET" value="12" />
  <parameter
     name="JAVA_I2C0_DATA"
     value="I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}" />
  <parameter name="S2FINTERRUPT_SPISLAVE_Enable" value="false" />
  <parameter name="UART1_Mode" value="N/A" />
  <parameter name="ENUM_CPORT2_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="ALLOCATED_WFIFO_PORT" value="None,None,None,None,None,None" />
  <parameter name="MEM_TRAS_NS" value="35.0" />
  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
  <parameter name="IO_DQ_OUT_RESERVE" value="0" />
  <parameter name="IO_DM_OUT_RESERVE" value="0" />
  <parameter name="ENABLE_BONDING" value="false" />
  <parameter name="I2C0_Mode" value="I2C" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
  <parameter name="dbctrl_stayosc1" value="true" />
  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="270.0" />
  <parameter name="sdmmc_clk_mhz" value="200.0" />
  <parameter name="CV_ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="AVL_DATA_WIDTH" value="64" />
  <parameter name="PLL_AFI_CLK_MULT_CACHE" value="32" />
  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
  <parameter name="MR1_RDQS" value="0" />
  <parameter name="ENUM_MEM_IF_ROWADDR_WIDTH" value="ADDR_WIDTH_15" />
  <parameter name="USB0_PinMuxing" value="Unused" />
  <parameter name="MEM_VENDOR" value="JEDEC" />
  <parameter name="CV_PORT_1_CONNECT_TO_AV_PORT" value="1" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
  <parameter name="pin_muxing_check" value="Cyclone V+5CSEMA5F31C6" />
  <parameter name="CV_ENUM_CPORT1_TYPE" value="DISABLE" />
  <parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
  <parameter name="USE_MEM_CLK_FREQ" value="false" />
  <parameter name="CV_MSB_WFIFO_PORT_5" value="5" />
  <parameter name="CFG_READ_ODT_CHIP" value="0" />
  <parameter name="CV_MSB_WFIFO_PORT_4" value="5" />
  <parameter name="CV_MSB_WFIFO_PORT_3" value="5" />
  <parameter name="IO_DQS_EN_PHASE_MAX" value="7" />
  <parameter name="ENUM_MEM_IF_COLADDR_WIDTH" value="ADDR_WIDTH_10" />
  <parameter name="SPIS1_PinMuxing" value="Unused" />
  <parameter name="main_pll_c3" value="3" />
  <parameter name="main_pll_c5" value="15" />
  <parameter name="main_pll_c4" value="3" />
  <parameter name="ENUM_PRIORITY_6_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_6_5" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_6_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_6_3" value="WEIGHT_0" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_PRIORITY_6_0" value="WEIGHT_0" />
  <parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
  <parameter name="ENUM_PRIORITY_6_1" value="WEIGHT_0" />
  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
  <parameter name="BSEL" value="1" />
  <parameter name="CV_MSB_WFIFO_PORT_2" value="5" />
  <parameter name="CV_MSB_WFIFO_PORT_1" value="5" />
  <parameter name="F2SINTERRUPT_Enable" value="false" />
  <parameter name="SPIM0_PinMuxing" value="Unused" />
  <parameter name="ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_MSB_WFIFO_PORT_0" value="5" />
  <parameter name="TG_TEMP_PORT_5" value="0" />
  <parameter name="S2FINTERRUPT_SPIMASTER_Enable" value="false" />
  <parameter name="TG_TEMP_PORT_3" value="0" />
  <parameter name="TG_TEMP_PORT_4" value="0" />
  <parameter name="TG_TEMP_PORT_1" value="0" />
  <parameter name="TG_TEMP_PORT_2" value="0" />
  <parameter name="TG_TEMP_PORT_0" value="0" />
  <parameter name="desired_emac1_clk_mhz" value="250.0" />
  <parameter name="CFG_ENABLE_NO_DM" value="0" />
  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
  <parameter name="F2SCLK_PERIPHCLK_FREQ" value="0" />
  <parameter name="INTG_MEM_CLK_ENTRY_CYCLES" value="10" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
  <parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="ENUM_MEM_IF_TCWL" value="TCWL_8" />
  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
  <parameter name="DEVICE_FAMILY_PARAM" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID" value="0" />
  <parameter name="l3_sp_clk_mhz" value="92.5" />
  <parameter name="PLL_DR_CLK_DIV" value="0" />
  <parameter name="periph_pll_c3_auto" value="4" />
  <parameter name="DELAY_PER_DCHAIN_TAP" value="25" />
  <parameter name="CSR_ADDR_WIDTH" value="10" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="mpu_l2_ram_clk_mhz" value="462.5" />
  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID" value="0" />
  <parameter name="RDIMM_INT" value="0" />
  <parameter name="ENUM_MASK_DBE_INTR" value="DISABLED" />
  <parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
  <parameter name="AC_ROM_MR0_MIRR" value="0010001101001" />
  <parameter name="MEM_TWTR" value="4" />
  <parameter name="CV_ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="F2SDRAM_WR_PORT_USED" value="0x0" />
  <parameter name="WEIGHT_PORT_2" value="0" />
  <parameter name="WEIGHT_PORT_1" value="0" />
  <parameter name="WEIGHT_PORT_0" value="0" />
  <parameter name="NAND_Mode" value="N/A" />
  <parameter name="WEIGHT_PORT_5" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="0 ps" />
  <parameter name="WEIGHT_PORT_4" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
  <parameter name="WEIGHT_PORT_3" value="0" />
  <parameter name="ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_2" value="DISABLED" />
  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
  <parameter name="CV_ENUM_ENABLE_BONDING_3" value="DISABLED" />
  <parameter name="MEM_TRFC_NS" value="260.0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_4" value="DISABLED" />
  <parameter name="CV_ENUM_ENABLE_BONDING_5" value="DISABLED" />
  <parameter name="PLL_MASTER" value="true" />
  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_0" value="DISABLED" />
  <parameter name="CV_ENUM_ENABLE_BONDING_1" value="DISABLED" />
  <parameter name="periph_qspi_clk_hz" value="1953125" />
  <parameter name="nand_x_clk_mhz" value="200.0" />
  <parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="emac0_clk_mhz" value="1.953125" />
  <parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="4" />
  <parameter name="MEM_IF_DM_WIDTH" value="4" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
  <parameter name="PHY_CLKBUF" value="false" />
  <parameter name="MAX_PENDING_WR_CMD" value="16" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_ATTR_COUNTER_ONE_RESET" value="DISABLED" />
  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
  <parameter name="MEM_IF_CHIP_BITS" value="1" />
  <parameter name="ENUM_MEM_IF_CS_PER_RANK" value="MEM_IF_CS_PER_RANK_1" />
  <parameter name="MEM_IF_CK_WIDTH" value="1" />
  <parameter
     name="JAVA_NAND_DATA"
     value="NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="32" />
  <parameter name="ENUM_LOCAL_IF_CS_WIDTH" value="ADDR_WIDTH_0" />
  <parameter name="TIMING_TDQSCK" value="255" />
  <parameter name="CTL_USR_REFRESH_EN" value="false" />
  <parameter
     name="JAVA_USB0_DATA"
     value="USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}" />
  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
  <parameter name="default_mpu_clk_hz" value="925000000" />
  <parameter name="STM_Enable" value="false" />
  <parameter name="l3_sp_clk_div" value="1" />
  <parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
  <parameter name="ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="AV_PORT_0_CONNECT_TO_CV_PORT" value="0" />
  <parameter name="PLL_MEM_CLK_DIV_CACHE" value="2" />
  <parameter name="ENUM_CTL_ECC_RMW_ENABLED" value="CTL_ECC_RMW_DISABLED" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="2" />
  <parameter name="IO_DQS_IN_RESERVE" value="4" />
  <parameter name="periph_pll_c1_auto" value="3" />
  <parameter
     name="LOANIO_Enable"
     value="No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No" />
  <parameter name="AVL_NUM_SYMBOLS" value="8" />
  <parameter name="FIX_READ_LATENCY" value="8" />
  <parameter name="CTL_OUTPUT_REGD" value="false" />
  <parameter name="CV_PORT_0_CONNECT_TO_AV_PORT" value="0" />
  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
  <parameter name="SPIM1_PinMuxing" value="HPS I/O Set 0" />
  <parameter
     name="JAVA_TRACE_DATA"
     value="TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH" value="0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="USB0_Mode" value="N/A" />
  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="MEM_INIT_FILE" value="" />
  <parameter
     name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
     value="false" />
  <parameter name="l4_mp_clk_div_auto" value="1" />
  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
  <parameter name="l3_mp_clk_hz" value="185000000" />
  <parameter name="ALLOCATED_RFIFO_PORT" value="None,None,None,None,None,None" />
  <parameter name="MEM_CK_WIDTH" value="1" />
  <parameter name="MEM_ATCL" value="Disabled" />
  <parameter name="TEST_Enable" value="false" />
  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
  <parameter name="MEM_TDQSCK" value="1" />
  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
  <parameter name="S2FINTERRUPT_OSCTIMER_Enable" value="false" />
  <parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
  <parameter name="dbg_clk_div" value="1" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="5000 ps" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="2500 ps" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD" value="0" />
  <parameter name="MEM_WTCL" value="8" />
  <parameter name="CV_ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_MEM_CLK_MULT" value="32" />
  <parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="l4_mp_clk_div" value="1" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP" value="2" />
  <parameter name="CV_ENUM_CPORT3_TYPE" value="DISABLE" />
  <parameter name="PLL_WRITE_CLK_DIV" value="2" />
  <parameter name="main_clk_mhz" value="370.0" />
  <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
  <parameter name="CV_ENUM_PORT5_WIDTH" value="PORT_32_BIT" />
  <parameter
     name="JAVA_SDIO_DATA"
     value="SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}" />
  <parameter name="MEM_DRV_STR" value="RZQ/7" />
  <parameter name="MEM_TREFI" value="3120" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="NUM_SUBGROUP_PER_READ_DQS" value="1" />
  <parameter name="MEM_TRP_NS" value="13.75" />
  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="1875 ps" />
  <parameter name="PLL_WRITE_CLK_FREQ" value="400.0" />
  <parameter name="l3_sp_clk_hz" value="92500000" />
  <parameter
     name="JAVA_EMAC1_DATA"
     value="EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}" />
  <parameter name="ENUM_MMR_CFG_MEM_BL" value="MP_BL_8" />
  <parameter name="PLL_DR_CLK_FREQ_STR" value="" />
  <parameter name="MEM_IF_CS_WIDTH" value="1" />
  <parameter name="CV_ENUM_WR_PORT_INFO_1" value="USE_NO" />
  <parameter name="STARVE_LIMIT" value="10" />
  <parameter name="CV_ENUM_WR_PORT_INFO_2" value="USE_NO" />
  <parameter name="desired_nand_clk_hz" value="12500000" />
  <parameter name="spi_m_clk_div_auto" value="0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_3" value="USE_NO" />
  <parameter name="l4_sp_clk_mhz" value="100.0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_4" value="USE_NO" />
  <parameter name="CV_ENUM_WR_PORT_INFO_0" value="USE_NO" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK" value="100" />
  <parameter name="AV_PORT_2_CONNECT_TO_CV_PORT" value="2" />
  <parameter name="CV_ENUM_WR_PORT_INFO_5" value="USE_NO" />
  <parameter name="main_clk_hz" value="370000000" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.09" />
  <parameter name="REGISTER_C2P" value="false" />
  <parameter name="MEM_IF_ROW_ADDR_WIDTH" value="15" />
  <parameter name="DQS_EN_DELAY_MAX" value="31" />
  <parameter name="ENUM_CPORT1_TYPE" value="DISABLE" />
  <parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
  <parameter name="SPIM1_Mode" value="Single Slave Select" />
  <parameter name="configure_advanced_parameters" value="false" />
  <parameter name="desired_nand_clk_mhz" value="12.5" />
  <parameter name="main_pll_c4_auto" value="511" />
  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
  <parameter name="eosc2_clk_hz" value="25000000" />
  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
  <parameter name="PLL_NIOS_CLK_DIV" value="6000000" />
  <parameter name="MR0_DLL" value="1" />
  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_5" value="1" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="2500 ps" />
  <parameter name="MR2_ASR" value="0" />
  <parameter name="main_pll_vco_auto_mhz" value="1850.0" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_3" value="1" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_4" value="1" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_1" value="1" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_2" value="1" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_0" value="1" />
  <parameter name="dbg_base_clk_hz" value="25000000" />
  <parameter name="HPS_PROTOCOL" value="DDR3" />
  <parameter name="MEM_IF_LRDIMM_RM" value="0" />
  <parameter name="desired_cfg_clk_mhz" value="97.368421" />
  <parameter name="ENUM_PRIORITY_1_5" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_1" value="WEIGHT_0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="2500 ps" />
  <parameter name="ENUM_PRIORITY_1_2" value="WEIGHT_0" />
  <parameter name="gpio_db_clk_div" value="6249" />
  <parameter name="ENUM_PRIORITY_1_0" value="WEIGHT_0" />
  <parameter name="DUPLICATE_AC" value="false" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_5" value="1" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_1" value="1" />
  <parameter name="DUAL_WRITE_CLOCK" value="false" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_2" value="1" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_3" value="1" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_4" value="1" />
  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_0" value="1" />
  <parameter name="CV_PORT_2_CONNECT_TO_AV_PORT" value="2" />
  <parameter name="AUTO_PD_CYCLES" value="0" />
  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
  <parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
  <parameter name="periph_pll_vco_auto_hz" value="1000000000" />
  <parameter name="CTL_TBP_NUM" value="4" />
  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
  <parameter
     name="DB_iface_ports"
     value="can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}" />
  <parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
  <parameter name="quartus_ini_hps_ip_fast_f2sdram_sim_model" value="false" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CFG_ECC_DECODER_REG" value="0" />
  <parameter name="S2FINTERRUPT_EMAC_Enable" value="false" />
  <parameter name="REF_CLK_FREQ_CACHE" value="25.0" />
  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="REF_CLK_FREQ_STR" value="25.0 MHz" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
  <parameter
     name="test_iface_definition"
     value="DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output" />
  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
  <parameter name="mpu_periph_clk_hz" value="231250000" />
  <parameter name="SPIS0_PinMuxing" value="Unused" />
  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="0010011101000" />
  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
  <parameter name="MEM_DLL_EN" value="true" />
  <parameter name="IS_ES_DEVICE" value="false" />
  <parameter name="PRE_V_SERIES_FAMILY" value="false" />
  <parameter name="F2SDRAM_CMD_PORT_USED" value="0x0" />
  <parameter name="HHP_HPS_SIMULATION" value="false" />
  <parameter name="dbg_at_clk_div" value="0" />
  <parameter name="CV_ENUM_PRIORITY_6_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_6_0" value="WEIGHT_0" />
  <parameter name="USB1_PinMuxing" value="HPS I/O Set 0" />
  <parameter name="S2FCLK_USER2CLK_Enable" value="false" />
  <parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
  <parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
  <parameter name="l3_mp_clk_div" value="1" />
  <parameter name="h2f_user1_clk_mhz" value="100.0" />
  <parameter name="HCX_COMPAT_MODE" value="false" />
  <parameter name="UART1_PinMuxing" value="Unused" />
  <parameter name="MEM_IF_DQSN_EN" value="true" />
  <parameter name="AC_ROM_MR0" value="0010001110001" />
  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
  <parameter
     name="pin_muxing"
     value="{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}" />
  <parameter name="periph_pll_n" value="1" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP" value="0" />
  <parameter name="MEM_TINIT_US" value="500" />
  <parameter name="periph_pll_m" value="79" />
  <parameter name="dbg_at_clk_mhz" value="25.0" />
  <parameter name="sdmmc_clk_source" value="2" />
  <parameter name="ENUM_USER_ECC_EN" value="DISABLE" />
  <parameter name="PLL_MEM_CLK_DIV" value="2" />
  <parameter name="OCT_SHARING_MODE" value="None" />
  <parameter name="AC_ROM_MR2" value="0001000011000" />
  <parameter name="periph_pll_m_auto" value="39" />
  <parameter name="AC_ROM_MR1" value="0000000000110" />
  <parameter name="AC_ROM_MR3" value="0000000000000" />
  <parameter
     name="JAVA_CONFLICT_PIN"
     value="No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No" />
  <parameter name="USE_HARD_READ_FIFO" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID" value="0" />
  <parameter name="desired_qspi_clk_hz" value="400000000" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
  <parameter name="main_pll_c2_internal" value="4" />
  <parameter name="periph_pll_c5_auto" value="9" />
  <parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
  <parameter name="CV_ENUM_PRIORITY_6_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_6_2" value="WEIGHT_0" />
  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
  <parameter name="CV_ENUM_PRIORITY_6_5" value="WEIGHT_0" />
  <parameter name="TIMING_BOARD_TIH_APPLIED" value="0.24" />
  <parameter name="CV_ENUM_PRIORITY_6_4" value="WEIGHT_0" />
  <parameter name="BOOTFROMFPGA_Enable" value="false" />
  <parameter name="S2FCLK_USER1CLK_FREQ" value="100.0" />
  <parameter name="CFG_TYPE" value="2" />
  <parameter name="ENUM_CLR_INTR" value="NO_CLR_INTR" />
  <parameter name="l4_mp_clk_mhz" value="100.0" />
  <parameter name="desired_mpu_clk_mhz" value="800.0" />
  <parameter name="F2SCLK_COLDRST_Enable" value="false" />
  <parameter name="ENUM_CPORT3_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
  <parameter name="MR3_DS" value="2" />
  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
  <parameter name="DELAY_CHAIN_LENGTH" value="8" />
  <parameter name="PLL_WRITE_CLK_DIV_CACHE" value="2" />
  <parameter name="quartus_ini_hps_ip_f2sdram_bonding_out" value="false" />
  <parameter name="desired_can0_clk_mhz" value="100.0" />
  <parameter name="ENUM_PRIORITY_5_5" value="WEIGHT_0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_PRIORITY_5_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_0" value="WEIGHT_0" />
  <parameter name="desired_emac0_clk_hz" value="250000000" />
  <parameter name="TIMING_TQHS" value="300" />
  <parameter name="usb_mp_clk_div_auto" value="0" />
  <parameter name="AV_PORT_1_CONNECT_TO_CV_PORT" value="1" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="S2FCLK_USER0CLK_FREQ_HZ" value="97368421" />
  <parameter name="cfg_h2f_user0_clk_hz" value="97368421" />
  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="2" />
  <parameter name="DEVICE_DEPTH" value="1" />
  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
  <parameter name="CV_ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="can1_clk_div_auto" value="4" />
  <parameter name="CTI_Enable" value="false" />
  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="ENUM_MASK_CORR_DROPPED_INTR" value="DISABLED" />
  <parameter name="AC_PACKAGE_DESKEW" value="false" />
  <parameter name="ENUM_ATTR_STATIC_CONFIG_VALID" value="DISABLED" />
  <parameter name="CTL_ENABLE_WDATA_PATH_LATENCY" value="false" />
  <parameter name="SEQ_BURST_COUNT_WIDTH" value="2" />
  <parameter name="CFG_BURST_LENGTH" value="8" />
  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="0 ps" />
  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="SPEED_GRADE_CACHE" value="7" />
  <parameter name="PLL_AFI_CLK_FREQ_CACHE" value="400.0" />
  <parameter name="TB_MEM_IF_DQ_WIDTH" value="32" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="1875 ps" />
  <parameter name="NEGATIVE_WRITE_CK_PHASE" value="true" />
  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
  <parameter name="CV_ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
  <parameter name="ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="MEM_ATCL_INT" value="0" />
  <parameter name="ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="400.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="TIMING_TDSS" value="0.2" />
  <parameter name="CV_ENUM_PRIORITY_2_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_0" value="WEIGHT_0" />
  <parameter name="CSR_BE_WIDTH" value="1" />
  <parameter name="CV_ENUM_PRIORITY_2_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_2" value="WEIGHT_0" />
  <parameter name="PLL_LOCATION" value="Top_Bottom" />
  <parameter name="CV_ENUM_PRIORITY_2_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_4" value="WEIGHT_0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="1875 ps" />
  <parameter name="usb_mp_clk_hz" value="200000000" />
  <parameter name="MEM_TRTP_NS" value="7.5" />
  <parameter name="F2SDRAM_Name_DERIVED" value="" />
  <parameter name="PLL_SHARING_MODE" value="None" />
  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="100" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="true" />
  <parameter name="ENUM_MEM_IF_MEMTYPE" value="DDR3_SDRAM" />
  <parameter name="TIMING_TDSH" value="0.2" />
  <parameter name="S2FINTERRUPT_CAN_Enable" value="false" />
  <parameter name="ENUM_PDN_EXIT_CYCLES" value="SLOW_EXIT" />
  <parameter name="spi_m_clk_div" value="0" />
  <parameter name="dbg_clk_mhz" value="12.5" />
  <parameter
     name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES"
     value="SELF_RFSH_EXIT_CYCLES_512" />
  <parameter
     name="LOANIO_Name_DERIVED"
     value="LOANIO00,LOANIO01,LOANIO02,LOANIO03,LOANIO04,LOANIO05,LOANIO06,LOANIO07,LOANIO08,LOANIO09,LOANIO10,LOANIO11,LOANIO12,LOANIO13,LOANIO14,LOANIO15,LOANIO16,LOANIO17,LOANIO18,LOANIO19,LOANIO20,LOANIO21,LOANIO22,LOANIO23,LOANIO24,LOANIO25,LOANIO26,LOANIO27,LOANIO28,LOANIO29,LOANIO30,LOANIO31,LOANIO32,LOANIO33,LOANIO34,LOANIO35,LOANIO36,LOANIO37,LOANIO38,LOANIO39,LOANIO40,LOANIO41,LOANIO42,LOANIO43,LOANIO44,LOANIO45,LOANIO46,LOANIO47,LOANIO48,LOANIO49,LOANIO50,LOANIO51,LOANIO52,LOANIO53,LOANIO54,LOANIO55,LOANIO56,LOANIO57,LOANIO58,LOANIO59,LOANIO60,LOANIO61,LOANIO62,LOANIO63,LOANIO64,LOANIO65,LOANIO66" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
  <parameter name="TIMING_TQSH" value="0.4" />
  <parameter name="LSB_RFIFO_PORT_0" value="5" />
  <parameter name="SPIS1_Mode" value="N/A" />
  <parameter name="AFI_CLK_PAIR_COUNT" value="1" />
  <parameter name="LSB_RFIFO_PORT_5" value="5" />
  <parameter name="LSB_RFIFO_PORT_3" value="5" />
  <parameter name="LSB_RFIFO_PORT_4" value="5" />
  <parameter name="LSB_RFIFO_PORT_1" value="5" />
  <parameter name="CV_ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
  <parameter name="LSB_RFIFO_PORT_2" value="5" />
  <parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
  <parameter name="DEBUGAPB_Enable" value="false" />
  <parameter name="DWIDTH_RATIO" value="2" />
  <parameter name="INTG_MEM_IF_TREFI" value="3120" />
  <parameter name="ENABLE_ABSTRACT_RAM" value="false" />
  <parameter name="main_pll_n" value="0" />
  <parameter name="main_pll_m" value="63" />
  <parameter name="ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
  <parameter name="ENUM_ENABLE_NO_DM" value="DISABLED" />
  <parameter name="MEM_TINIT_CK" value="200000" />
  <parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_1" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_1" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="CONTROLLER_LATENCY" value="5" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_AFI_CLK_DIV_CACHE" value="2" />
  <parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="2" />
  <parameter name="MEM_DQ_PER_DQS" value="8" />
  <parameter name="CV_ENUM_PRIORITY_0_1" value="WEIGHT_0" />
  <parameter name="ENUM_CTL_REGDIMM_ENABLED" value="REGDIMM_DISABLED" />
  <parameter name="CV_ENUM_PRIORITY_0_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_0_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_0_2" value="WEIGHT_0" />
  <parameter name="ENABLE_BURST_MERGE" value="false" />
  <parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="0" />
  <parameter name="CV_ENUM_PRIORITY_0_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_0_4" value="WEIGHT_0" />
  <parameter name="dbg_timer_clk_mhz" value="25.0" />
  <parameter name="dbg_clk_hz" value="12500000" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_1" />
  <parameter name="nand_clk_hz" value="50000000" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_1" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_1" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_1" />
  <parameter name="BONDING_OUT_ENABLED" value="false" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.08" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
  <parameter name="main_pll_c2_internal_auto" value="4" />
  <parameter name="SOPC_COMPAT_RESET" value="false" />
  <parameter name="PLL_HR_CLK_FREQ_STR" value="" />
  <parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
  <parameter name="COMMAND_PHASE_CACHE" value="0.0" />
  <parameter name="emac1_clk_mhz" value="250.0" />
  <parameter name="PLL_HR_CLK_DIV" value="0" />
  <parameter name="REF_CLK_FREQ_MIN_CACHE" value="10.0" />
  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="gpio_db_clk_hz" value="32000" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
  <parameter name="ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter
     name="JAVA_UART1_DATA"
     value="UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}" />
  <parameter name="DATA_RATE_RATIO" value="2" />
  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
  <parameter name="can1_clk_hz" value="12500000" />
  <parameter name="ENUM_ENABLE_DQS_TRACKING" value="ENABLED" />
  <parameter name="ENUM_ENABLE_BONDING_3" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_2" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_5" value="DISABLED" />
  <parameter
     name="JAVA_SPIM0_DATA"
     value="SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}" />
  <parameter name="ENUM_ENABLE_BONDING_4" value="DISABLED" />
  <parameter name="qspi_clk_mhz" value="3.613281" />
  <parameter name="CV_ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
  <parameter name="ENUM_ENABLE_BONDING_1" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_0" value="DISABLED" />
  <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
  <parameter name="RATE" value="Full" />
  <parameter name="POWER_OF_TWO_BUS" value="false" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="periph_base_clk_hz" value="200000000" />
  <parameter name="MR3_MPR_RF" value="0" />
  <parameter name="DEBUG_MODE" value="false" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="MEM_RTT_WR" value="RZQ/4" />
  <parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="1" />
  <parameter name="customize_device_pll_info" value="false" />
  <parameter name="ENUM_PRIORITY_7_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_0" value="WEIGHT_0" />
  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="125" />
  <parameter name="MEM_BURST_LENGTH" value="8" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_AFI_CLK_FREQ_STR" value="400.0 MHz" />
  <parameter name="IO_DQDQS_OUT_PHASE_MAX" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_PRIORITY_7_5" value="WEIGHT_0" />
  <parameter name="CSEL_EN" value="false" />
  <parameter name="CSEL" value="0" />
  <parameter name="MEM_INIT_EN" value="false" />
  <parameter name="TRACE_Mode" value="N/A" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CTL_REGDIMM_ENABLED" value="false" />
  <parameter name="QSPI_PinMuxing" value="Unused" />
  <parameter name="ENUM_GEN_SBE" value="GEN_SBE_DISABLED" />
  <parameter name="ENUM_THLD_JAR1_4" value="THRESHOLD_32" />
  <parameter name="MEM_RTT_NOM" value="RZQ/4" />
  <parameter name="ENUM_THLD_JAR1_5" value="THRESHOLD_32" />
  <parameter name="PLL_CONFIG_CLK_MULT" value="0" />
  <parameter name="SPIS0_Mode" value="N/A" />
  <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="desired_usb_mp_clk_mhz" value="200.0" />
  <parameter name="nand_clk_mhz" value="50.0" />
  <parameter name="MR1_DLL" value="0" />
  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
  <parameter name="ENUM_WR_PORT_INFO_0" value="USE_NO" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="ENUM_WR_PORT_INFO_5" value="USE_NO" />
  <parameter name="ENUM_WR_PORT_INFO_1" value="USE_NO" />
  <parameter name="ENUM_WR_PORT_INFO_2" value="USE_NO" />
  <parameter name="l3_mp_clk_mhz" value="185.0" />
  <parameter name="ENUM_WR_PORT_INFO_3" value="USE_NO" />
  <parameter name="VFIFO_AS_SHIFT_REG" value="true" />
  <parameter name="ENUM_WR_PORT_INFO_4" value="USE_NO" />
  <parameter name="ENUM_THLD_JAR1_0" value="THRESHOLD_32" />
  <parameter name="ENUM_THLD_JAR1_1" value="THRESHOLD_32" />
  <parameter name="ENUM_THLD_JAR1_2" value="THRESHOLD_32" />
  <parameter name="ENUM_THLD_JAR1_3" value="THRESHOLD_32" />
  <parameter name="DLL_SHARING_MODE" value="None" />
  <parameter name="ENUM_CPORT2_TYPE" value="DISABLE" />
  <parameter name="S2FINTERRUPT_UART_Enable" value="false" />
  <parameter name="desired_usb_mp_clk_hz" value="200000000" />
  <parameter name="main_pll_c1_internal_auto" value="4" />
  <parameter name="mpu_clk_hz" value="925000000" />
  <parameter name="PLL_DR_CLK_MULT" value="0" />
  <parameter name="USE_USER_RDIMM_VALUE" value="false" />
  <parameter name="MEM_FORMAT" value="DISCRETE" />
  <parameter name="I2C2_PinMuxing" value="Unused" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="AFI_WLAT_WIDTH" value="6" />
  <parameter name="BSEL_EN" value="false" />
  <parameter name="MEM_IF_WRITE_DQS_WIDTH" value="4" />
  <parameter name="RATE_CACHE" value="Full" />
  <parameter name="CTL_CS_WIDTH" value="1" />
  <parameter name="PLL_AFI_HALF_CLK_MULT" value="32" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="1875 ps" />
  <parameter name="desired_l4_mp_clk_hz" value="100000000" />
  <parameter
     name="JAVA_UART0_DATA"
     value="UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}" />
  <parameter name="F2SDRAM_Width_Last_Size" value="0" />
  <parameter name="EMAC1_Mode" value="RGMII" />
  <parameter name="ENUM_SYNC_MODE_1" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="ENUM_SYNC_MODE_0" value="ASYNCHRONOUS" />
  <parameter name="ENUM_SYNC_MODE_3" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_SYNC_MODE_2" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="ENUM_SYNC_MODE_5" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_CPORT4_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="ENUM_SYNC_MODE_4" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="MEM_CK_PHASE" value="0.0" />
  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
  <parameter name="ADDR_ORDER" value="0" />
  <parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MEM_VERBOSE" value="true" />
  <parameter name="HARD_PHY" value="true" />
  <parameter name="MR2_SRF" value="0" />
  <parameter name="ENUM_CPORT4_TYPE" value="DISABLE" />
  <parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="true" />
  <parameter
     name="JAVA_I2C3_DATA"
     value="I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}" />
  <parameter name="h2f_user0_clk_hz" value="97368421" />
  <parameter name="ENUM_MASK_SBE_INTR" value="DISABLED" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK" value="0" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
  <parameter name="TPIUFPGA_Enable" value="false" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
  <parameter name="VECT_ATTR_COUNTER_ONE_MASK" value="0" />
  <parameter name="MULTICAST_EN" value="false" />
  <parameter name="VCALIB_COUNT_WIDTH" value="2" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="AC_PARITY" value="false" />
  <parameter name="dbg_trace_clk_mhz" value="25.0" />
  <parameter name="AC_ROM_MR2_MIRR" value="0001000011000" />
  <parameter name="MR1_DQS" value="0" />
  <parameter name="MR2_SRT" value="0" />
  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="EMAC1_PTP" value="false" />
  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
  <parameter name="MR1_QOFF" value="0" />
  <parameter name="desired_l4_mp_clk_mhz" value="100.0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="CV_ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="USE_FAKE_PHY" value="false" />
  <parameter name="SEQ_MODE" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
  <parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
  <parameter name="MEM_TYPE" value="DDR3" />
  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
  <parameter
     name="JAVA_USB1_DATA"
     value="USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}" />
  <parameter name="main_qspi_clk_mhz" value="3.613281" />
  <parameter name="SDIO_Mode" value="4-bit Data" />
  <parameter name="desired_mpu_clk_hz" value="800000000" />
  <parameter name="periph_pll_vco_hz" value="1000000000" />
  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.03" />
  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="1875 ps" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="CV_ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
  <parameter name="MAX10_CFG" value="false" />
  <parameter name="DELAY_BUFFER_MODE" value="HIGH" />
  <parameter name="ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_PORT3_WIDTH" value="PORT_32_BIT" />
  <parameter name="CONTINUE_AFTER_CAL_FAIL" value="false" />
  <parameter name="S2FINTERRUPT_USB_Enable" value="false" />
  <parameter name="AFI_RRANK_WIDTH" value="0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="0 ps" />
  <parameter name="MR3_MPR" value="0" />
  <parameter
     name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
     value="false" />
  <parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
  <parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="32" />
  <parameter name="ENUM_CFG_STARVE_LIMIT" value="STARVE_LIMIT_10" />
  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.02" />
  <parameter name="MEM_IF_ODT_WIDTH" value="1" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
  <parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="TIMING_BOARD_TIS" value="0.0" />
  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
  <parameter name="ENUM_MEM_IF_TCCD" value="TCCD_4" />
  <parameter name="periph_pll_c4_auto" value="4" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="0 ps" />
  <parameter name="AVL_BE_WIDTH" value="8" />
  <parameter name="desired_l4_sp_clk_mhz" value="100.0" />
  <parameter name="TIMING_BOARD_TIH" value="0.0" />
  <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
  <parameter name="ENUM_CTL_USR_REFRESH" value="CTL_USR_REFRESH_DISABLED" />
  <parameter name="TIMING_BOARD_TDS" value="0.0" />
  <parameter name="CFG_ERRCMD_FIFO_REG" value="0" />
  <parameter name="mpu_base_clk_mhz" value="925.0" />
  <parameter name="TIMING_BOARD_TDH" value="0.0" />
  <parameter name="PACKAGE_DESKEW" value="false" />
  <parameter name="TRACKING_WATCH_TEST" value="false" />
  <parameter name="CAN1_PinMuxing" value="Unused" />
  <parameter name="AFI_DM_WIDTH" value="8" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="45000 ps" />
  <parameter name="S2FCLK_COLDRST_Enable" value="false" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
  <parameter name="BYTE_ENABLE" value="true" />
  <parameter name="main_pll_n_auto" value="0" />
  <parameter name="MEM_IF_BANKADDR_WIDTH" value="3" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="show_warning_as_error_msg" value="false" />
  <parameter name="ENUM_CAL_REQ" value="DISABLED" />
  <parameter name="ENUM_PORT0_WIDTH" value="PORT_32_BIT" />
  <parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
  <parameter name="ADDR_CMD_DDR" value="1" />
  <parameter name="GENERIC_PLL" value="true" />
  <parameter name="ENABLE_NON_DES_CAL" value="false" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="MR3_MPR_AA" value="0" />
  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="400.0" />
  <parameter name="MEM_TFAW_NS" value="30.0" />
  <parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
  <parameter name="F2S_Width" value="2" />
  <parameter name="ENUM_RD_PORT_INFO_2" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="ENUM_RD_PORT_INFO_3" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="ENUM_RD_PORT_INFO_4" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_MEM_IF_SPEEDBIN" value="DDR3_1600_8_8_8" />
  <parameter name="ENUM_RD_PORT_INFO_5" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="PLL_HR_CLK_MULT" value="0" />
  <parameter name="F2SCLK_PERIPHCLK_FREQ_MHZ" value="0.0" />
  <parameter name="CV_ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="HHP_HPS" value="true" />
  <parameter name="periph_qspi_clk_mhz" value="1.953125" />
  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" />
  <parameter name="ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
  <parameter name="AVL_SIZE_WIDTH" value="3" />
  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
  <parameter name="ENUM_RD_PORT_INFO_0" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="ENUM_RD_PORT_INFO_1" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="I2C2_Mode" value="N/A" />
  <parameter
     name="CPORT_TYPE_PORT"
     value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
  <parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="INTG_CYC_TO_RLD_JARS_5" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_4" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_3" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_2" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_1" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_0" value="1" />
  <parameter name="EMAC1_PinMuxing" value="HPS I/O Set 0" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" />
  <parameter name="CV_ENUM_PRIORITY_5_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_5_2" value="WEIGHT_0" />
  <parameter name="PLL_NIOS_CLK_FREQ" value="66.6666666667" />
  <parameter name="ENUM_PORT1_WIDTH" value="PORT_32_BIT" />
  <parameter name="CV_ENUM_PRIORITY_5_1" value="WEIGHT_0" />
  <parameter name="SPIM0_Mode" value="N/A" />
  <parameter name="AFI_ADDR_WIDTH" value="30" />
  <parameter name="TRACE_PinMuxing" value="Unused" />
  <parameter name="MEM_IF_COL_ADDR_WIDTH" value="10" />
  <parameter name="periph_nand_sdmmc_clk_hz" value="200000000" />
  <parameter name="GPIO_Pin_Used_DERIVED" value="true" />
  <parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
  <parameter name="MSB_WFIFO_PORT_0" value="5" />
  <parameter name="MSB_WFIFO_PORT_1" value="5" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="MSB_WFIFO_PORT_2" value="5" />
  <parameter name="MSB_WFIFO_PORT_3" value="5" />
  <parameter name="MEM_CLK_FREQ_CACHE" value="400.0" />
  <parameter name="MSB_WFIFO_PORT_4" value="5" />
  <parameter name="MSB_WFIFO_PORT_5" value="5" />
  <parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
  <parameter name="CFG_TCCD" value="1" />
  <parameter name="SCC_DATA_WIDTH" value="1" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="MEM_TREFI_US" value="7.8" />
  <parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
  <parameter name="ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.16" />
  <parameter name="ENUM_MEM_IF_DQS_WIDTH" value="DQS_WIDTH_4" />
  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
  <parameter name="ENUM_DFX_BYPASS_ENABLE" value="DFX_BYPASS_DISABLED" />
  <parameter name="NAND_PinMuxing" value="Unused" />
  <parameter name="MEM_TWR_NS" value="15.0" />
  <parameter name="ENUM_CTRL_WIDTH" value="DATA_WIDTH_64_BIT" />
  <parameter name="CV_ENUM_PRIORITY_5_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_5_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_5_5" value="WEIGHT_0" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK" value="100" />
  <parameter name="ENUM_PORT2_WIDTH" value="PORT_32_BIT" />
  <parameter name="TPIUFPGA_alt" value="false" />
  <parameter name="MEM_CLK_PS" value="2500.0" />
  <parameter name="IS_ES_DEVICE_CACHE" value="false" />
  <parameter name="PLL_AFI_CLK_FREQ" value="400.0" />
  <parameter name="F2SCLK_PERIPHCLK_Enable" value="false" />
  <parameter
     name="DB_periph_ifaces"
     value="USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_1" value="EMPTY" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_2" value="EMPTY" />
  <parameter name="can0_clk_div_auto" value="4" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_3" value="EMPTY" />
  <parameter name="ENUM_DELAY_BONDING" value="BONDING_LATENCY_0" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_0" value="EMPTY" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="DQS_IN_DELAY_MAX" value="31" />
  <parameter name="LSB_WFIFO_PORT_4" value="5" />
  <parameter name="LSB_WFIFO_PORT_5" value="5" />
  <parameter name="LSB_WFIFO_PORT_2" value="5" />
  <parameter name="LSB_WFIFO_PORT_3" value="5" />
  <parameter name="MR0_CAS_LATENCY" value="7" />
  <parameter name="LSB_WFIFO_PORT_0" value="5" />
  <parameter name="LSB_WFIFO_PORT_1" value="5" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.0" />
  <parameter name="CFG_PDN_EXIT_CYCLES" value="10" />
  <parameter name="MR0_WR" value="2" />
  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
  <parameter name="PLL_MEM_CLK_FREQ_STR" value="400.0 MHz" />
  <parameter name="LOCAL_ID_WIDTH" value="8" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
  <parameter name="dbg_trace_clk_div" value="0" />
  <parameter name="CAN0_Mode" value="N/A" />
  <parameter name="TIMING_TDQSS" value="0.25" />
  <parameter name="TIMING_TDQSQ" value="125" />
  <parameter name="ENUM_PRIORITY_2_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_PRIORITY_2_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_0" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_1" />
  <parameter name="ENUM_PRIORITY_2_1" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_1" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="125" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_1" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="2500 ps" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_1" />
  <parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_1" />
  <parameter name="TIMING_TDQSH" value="0.35" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_1" />
  <parameter name="USE_2X_FF" value="false" />
  <parameter name="MEM_ASR" value="Manual" />
  <parameter name="eosc1_clk_mhz" value="25.0" />
  <parameter name="ADVANCED_CK_PHASES" value="false" />
  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="true" />
  <parameter name="use_default_mpu_clk" value="true" />
  <parameter name="main_pll_vco_auto_hz" value="1850000000" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="S2FINTERRUPT_I2CPERIPHERAL_Enable" value="false" />
  <parameter name="CPORT_TYPE_PORT_3" value="0" />
  <parameter name="CPORT_TYPE_PORT_2" value="0" />
  <parameter name="CPORT_TYPE_PORT_1" value="0" />
  <parameter name="CPORT_TYPE_PORT_0" value="0" />
  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
  <parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
  <parameter name="ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="15000 ps" />
  <parameter name="S2FCLK_USER2CLK_FREQ" value="100.0" />
  <parameter name="NUM_OF_PORTS" value="1" />
  <parameter name="main_pll_c3_auto" value="511" />
  <parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="1875" />
  <parameter name="CPORT_TYPE_PORT_5" value="0" />
  <parameter name="CPORT_TYPE_PORT_4" value="0" />
  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
  <parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="0 ps" />
  <parameter name="ENUM_PORT5_WIDTH" value="PORT_32_BIT" />
  <parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
  <parameter name="ENUM_GANGED_ARF" value="DISABLED" />
  <parameter name="ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
  <parameter name="MAX_LATENCY_COUNT_WIDTH" value="5" />
  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
  <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="450" />
  <parameter name="ENUM_MEM_IF_TRRD" value="TRRD_4" />
  <parameter name="PLL_AFI_HALF_CLK_DIV" value="2" />
  <parameter name="MEM_ADD_LAT" value="0" />
  <parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
  <parameter name="ENUM_PORT4_WIDTH" value="PORT_32_BIT" />
  <parameter name="MEM_REGDIMM_ENABLED" value="false" />
  <parameter name="PLL_HR_CLK_FREQ" value="0.0" />
  <parameter name="desired_can1_clk_mhz" value="100.0" />
  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
  <parameter
     name="JAVA_EMAC0_DATA"
     value="EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}" />
  <parameter name="AP_MODE_EN" value="0" />
  <parameter name="ENUM_CPORT5_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="INTG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="VECT_ATTR_COUNTER_ZERO_MASK" value="0" />
  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="0 ps" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="INTG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="CV_ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
  <parameter name="INTG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="desired_cfg_clk_hz" value="97368421" />
  <parameter name="INTG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="DELAY_PER_OPA_TAP" value="312" />
  <parameter name="INTG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="HHP_HPS_VERIFICATION" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC" value="2" />
  <parameter name="CV_ENUM_PORT1_WIDTH" value="PORT_32_BIT" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP" value="3" />
  <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
  <parameter name="S2FCLK_USER0CLK_FREQ" value="97.368421" />
  <parameter name="periph_pll_source" value="0" />
  <parameter name="can0_clk_hz" value="12500000" />
  <parameter name="ENUM_ENABLE_INTR" value="DISABLED" />
  <parameter name="INTG_MEM_AUTO_PD_CYCLES" value="0" />
  <parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
  <parameter name="MR0_PD" value="0" />
  <parameter name="MEM_IF_CS_PER_RANK" value="1" />
  <parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="sdmmc_clk_hz" value="200000000" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="0 ps" />
  <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
  <parameter name="dbg_trace_clk_hz" value="25000000" />
  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
  <parameter name="RDIMM" value="false" />
  <parameter name="PLL_CONFIG_CLK_FREQ" value="22.2222222222" />
  <parameter name="ENABLE_USER_ECC" value="false" />
  <parameter name="PLL_PHASE_COUNTER_WIDTH" value="4" />
  <parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD" value="0" />
  <parameter name="MEM_TRC" value="20" />
  <parameter name="H2F_AXI_CLOCK_FREQ" value="50000000" />
  <parameter name="AVL_ADDR_WIDTH_PORT_2" value="1" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID" value="0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_3" value="USE_NO" />
  <parameter name="AVL_ADDR_WIDTH_PORT_1" value="1" />
  <parameter name="CV_ENUM_RD_PORT_INFO_2" value="USE_NO" />
  <parameter name="AVL_ADDR_WIDTH_PORT_0" value="1" />
  <parameter name="CV_ENUM_RD_PORT_INFO_5" value="USE_NO" />
  <parameter name="CV_ENUM_RD_PORT_INFO_4" value="USE_NO" />
  <parameter name="periph_pll_c2_auto" value="511" />
  <parameter name="AFI_CS_WIDTH" value="1" />
  <parameter name="CAN0_PinMuxing" value="Unused" />
  <parameter name="AVL_ADDR_WIDTH_PORT_5" value="1" />
  <parameter name="AVL_ADDR_WIDTH_PORT_4" value="1" />
  <parameter name="CV_ENUM_RD_PORT_INFO_1" value="USE_NO" />
  <parameter name="AVL_ADDR_WIDTH_PORT_3" value="1" />
  <parameter name="CV_ENUM_RD_PORT_INFO_0" value="USE_NO" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="PLL_NIOS_CLK_MULT" value="0" />
  <parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
  <parameter name="MEM_CLK_NS" value="2.5" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
  <parameter name="ENUM_MEM_IF_BURSTLENGTH" value="MEM_IF_BURSTLENGTH_8" />
  <parameter name="PLL_AFI_CLK_MULT" value="32" />
  <parameter name="SKIP_MEM_INIT" value="true" />
  <parameter name="MR1_TDQS" value="0" />
  <parameter name="CTL_ECC_MULTIPLES_16_24_40_72" value="1" />
  <parameter name="CV_ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="I2C0_PinMuxing" value="HPS I/O Set 0" />
  <parameter name="ENUM_MEM_IF_TRTP" value="TRTP_3" />
  <parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="270.0" />
  <parameter name="INTG_POWER_SAVING_EXIT_CYCLES" value="5" />
  <parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="25" />
  <parameter name="MEM_IF_ADDR_WIDTH" value="15" />
  <parameter name="USE_SEQUENCER_BFM" value="false" />
  <parameter name="can1_clk_div" value="1" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="2500 ps" />
  <parameter name="DB_bfm_types" value="" />
  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
  <parameter name="main_pll_c0_internal" value="1" />
  <parameter name="CV_ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="CV_ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="CV_ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="CTL_CSR_READ_ONLY" value="1" />
  <parameter name="CV_ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="CV_ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="CV_ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="READ_VALID_FIFO_SIZE" value="16" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
  <parameter
     name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
     value="100" />
  <parameter name="mpu_periph_clk_mhz" value="231.25" />
  <parameter name="DLL_MASTER" value="true" />
  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
  <parameter name="ENUM_ENABLE_BURST_INTERRUPT" value="DISABLED" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="CYCLONEV" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="desired_can1_clk_hz" value="100000000" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="2.5" />
  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="ENABLE_ISS_PROBES" value="false" />
  <parameter name="MR2_RTT_WR" value="1" />
  <parameter name="ENUM_MEM_IF_TFAW" value="TFAW_12" />
  <parameter name="TIMING_BOARD_TDS_APPLIED" value="0.18" />
  <parameter name="AFI_ODT_WIDTH" value="1" />
  <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
  <parameter name="S2FINTERRUPT_I2CEMAC_Enable" value="false" />
  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
  <parameter name="DISCRETE_FLY_BY" value="true" />
  <parameter name="QVLD_WR_ADDRESS_OFFSET" value="5" />
  <parameter name="mpu_clk_mhz" value="925.0" />
  <parameter name="dbg_at_clk_hz" value="25000000" />
  <parameter name="AVL_SYMBOL_WIDTH" value="8" />
  <parameter name="TB_PLL_DLL_MASTER" value="true" />
  <parameter name="LOCAL_CS_WIDTH" value="0" />
  <parameter name="can1_clk_mhz" value="12.5" />
  <parameter name="CTL_ECC_ENABLED" value="false" />
  <parameter name="AUTO_POWERDN_EN" value="false" />
  <parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
  <parameter name="ENABLE_ABS_RAM_INTERNAL" value="false" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_WRITE_ODT_CHIP" value="WRITE_CHIP0_ODT0_CHIP1" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
  <parameter name="MEM_TCL" value="11" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="spi_m_clk_hz" value="200000000" />
  <parameter
     name="JAVA_CAN1_DATA"
     value="CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}" />
  <parameter name="ENUM_WR_FIFO_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_WR_FIFO_IN_USE_2" value="FALSE" />
  <parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP" value="1" />
  <parameter name="ENUM_WR_FIFO_IN_USE_1" value="FALSE" />
  <parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="400.0" />
  <parameter name="ENUM_WR_FIFO_IN_USE_0" value="FALSE" />
  <parameter name="AFI_RATE_RATIO" value="1" />
  <parameter name="ENUM_THLD_JAR2_3" value="THRESHOLD_16" />
  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
  <parameter name="ENUM_THLD_JAR2_4" value="THRESHOLD_16" />
  <parameter name="ENUM_THLD_JAR2_5" value="THRESHOLD_16" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="desired_sdmmc_clk_hz" value="200000000" />
  <parameter name="F2SCLK_WARMRST_Enable" value="false" />
  <parameter name="CFG_TCCD_NS" value="2.5" />
  <parameter name="UART0_Mode" value="No Flow Control" />
  <parameter name="F2SDRAM_RD_PORT_USED" value="0x0" />
  <parameter name="ENABLE_NIOS_OCI" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
  <parameter name="CTL_CSR_ENABLED" value="false" />
  <parameter name="PHY_CSR_ENABLED" value="false" />
  <parameter name="DQ_DDR" value="1" />
  <parameter name="PLL_WRITE_CLK_PHASE_DEG" value="270.0" />
  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="0 ps" />
  <parameter
     name="JAVA_SPIS0_DATA"
     value="SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
  <parameter name="AVL_PORT" value="Port 0" />
  <parameter name="TB_RATE" value="FULL" />
  <parameter name="REF_CLK_FREQ_CACHE_VALID" value="true" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK" value="100" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MPU_EVENTS_Enable" value="false" />
  <parameter
     name="GPIO_Name_DERIVED"
     value="GPIO00,GPIO01,GPIO02,GPIO03,GPIO04,GPIO05,GPIO06,GPIO07,GPIO08,GPIO09,GPIO10,GPIO11,GPIO12,GPIO13,GPIO14,GPIO15,GPIO16,GPIO17,GPIO18,GPIO19,GPIO20,GPIO21,GPIO22,GPIO23,GPIO24,GPIO25,GPIO26,GPIO27,GPIO28,GPIO29,GPIO30,GPIO31,GPIO32,GPIO33,GPIO34,GPIO35,GPIO36,GPIO37,GPIO38,GPIO39,GPIO40,GPIO41,GPIO42,GPIO43,GPIO44,GPIO45,GPIO46,GPIO47,GPIO48,GPIO49,GPIO50,GPIO51,GPIO52,GPIO53,GPIO54,GPIO55,GPIO56,GPIO57,GPIO58,GPIO59,GPIO60,GPIO61,GPIO62,GPIO63,GPIO64,GPIO65,GPIO66" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="AC_ROM_MR0_DLL_RESET" value="0010101110000" />
  <parameter name="usb_mp_clk_div" value="0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP" value="0" />
  <parameter name="MEM_IF_CS_PER_DIMM" value="1" />
  <parameter name="eosc1_clk_hz" value="25000000" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="CYCLONEV" />
  <parameter name="CTL_ECC_CSR_ENABLED" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
  <parameter name="MEM_AUTO_PD_CYCLES" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
  <parameter name="desired_gpio_db_clk_hz" value="32000" />
  <parameter
     name="GPIO_Enable"
     value="No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,Yes,No,No,No,No,No,No,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No" />
  <parameter name="CALIB_VFIFO_OFFSET" value="10" />
  <parameter name="CTL_ECC_MULTIPLES_40_72" value="1" />
  <parameter name="MSB_RFIFO_PORT_2" value="5" />
  <parameter name="MSB_RFIFO_PORT_3" value="5" />
  <parameter name="MSB_RFIFO_PORT_4" value="5" />
  <parameter name="MSB_RFIFO_PORT_5" value="5" />
  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
  <parameter name="TIMING_BOARD_AC_SKEW" value="0.03" />
  <parameter name="MSB_RFIFO_PORT_0" value="5" />
  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="MSB_RFIFO_PORT_1" value="5" />
  <parameter name="QVLD_EXTRA_FLOP_STAGES" value="5" />
  <parameter name="cfg_clk_mhz" value="97.368421" />
  <parameter name="CAN1_Mode" value="N/A" />
  <parameter name="CTL_HRB_ENABLED" value="false" />
  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
  <parameter name="S2FCLK_USER2CLK_FREQ_HZ" value="100000000" />
  <parameter name="EXTRA_SETTINGS" value="" />
  <parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP" value="1" />
  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="true" />
  <parameter name="SEQUENCER_TYPE_CACHE" value="NIOS" />
  <parameter name="CTL_USR_REFRESH" value="0" />
  <parameter name="PLL_MEM_CLK_FREQ_CACHE" value="400.0" />
  <parameter name="qspi_clk_source" value="1" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
  <parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
  <parameter name="MR0_BT" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
  <parameter
     name="JAVA_QSPI_DATA"
     value="QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}" />
  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL" value="0" />
  <parameter name="F2H_AXI_CLOCK_FREQ" value="50000000" />
  <parameter name="MR1_AL" value="0" />
  <parameter name="DQS_PHASE_SHIFT" value="0" />
  <parameter name="MR0_BL" value="1" />
  <parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
  <parameter name="MEM_TRCD" value="6" />
  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
  <parameter name="MAX_PENDING_RD_CMD" value="32" />
  <parameter name="desired_spi_m_clk_hz" value="200000000" />
  <parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
  <parameter name="MEM_WTCL_INT" value="8" />
  <parameter name="SDIO_PinMuxing" value="HPS I/O Set 0" />
  <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
  <parameter name="main_nand_sdmmc_clk_mhz" value="3.613281" />
  <parameter name="MR1_BL" value="2" />
  <parameter name="MR1_BT" value="0" />
  <parameter name="REF_CLK_FREQ" value="25.0" />
  <parameter name="AV_PORT_5_CONNECT_TO_CV_PORT" value="5" />
  <parameter name="PINGPONGPHY_EN" value="false" />
  <parameter name="CFG_WRITE_ODT_CHIP" value="1" />
  <parameter name="F2SDRAM_Width" value="" />
  <parameter name="MR2_CWL" value="3" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV" value="2" />
  <parameter name="VECT_ATTR_COUNTER_ONE_MATCH" value="0" />
  <parameter name="QSPI_Mode" value="N/A" />
  <parameter name="CV_ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="AC_ROM_MR1_MIRR" value="0000000000110" />
  <parameter name="CFG_POWER_SAVING_EXIT_CYCLES" value="5" />
  <parameter name="MR1_DS" value="0" />
  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="ENUM_CPORT5_TYPE" value="DISABLE" />
  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
  <parameter name="main_pll_m_auto" value="73" />
  <parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD" value="0" />
  <parameter name="AFI_BANKADDR_WIDTH" value="6" />
  <parameter name="CV_ENUM_CPORT0_TYPE" value="DISABLE" />
  <parameter name="ENUM_THLD_JAR2_0" value="THRESHOLD_16" />
  <parameter name="ENUM_THLD_JAR2_1" value="THRESHOLD_16" />
  <parameter name="ENUM_THLD_JAR2_2" value="THRESHOLD_16" />
  <parameter
     name="GPIO_Conflict_DERIVED"
     value=",USB1.D0,USB1.D1,USB1.D2,USB1.D3,USB1.D4,USB1.D5,USB1.D6,USB1.D7,,USB1.CLK,USB1.STP,USB1.DIR,USB1.NXT,EMAC1.TX_CLK,EMAC1.TXD0,EMAC1.TXD1,EMAC1.TXD2,EMAC1.TXD3,EMAC1.RXD0,EMAC1.MDIO,EMAC1.MDC,EMAC1.RX_CTL,EMAC1.TX_CTL,EMAC1.RX_CLK,EMAC1.RXD1,EMAC1.RXD2,EMAC1.RXD3,,,,,,,,,SDIO.CMD,,SDIO.D0,SDIO.D1,,,,,,SDIO.CLK,SDIO.D2,SDIO.D3,,UART0.RX,UART0.TX,I2C1.SDA,I2C1.SCL,,,I2C0.SDA,I2C0.SCL,,,,,,,SPIM1.CLK,SPIM1.MOSI,SPIM1.MISO,SPIM1.SS0" />
  <parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
  <parameter name="CTL_ENABLE_BURST_TERMINATE_INT" value="false" />
  <parameter name="CTL_ENABLE_BURST_INTERRUPT_INT" value="false" />
  <parameter name="TRACKING_ERROR_TEST" value="false" />
  <parameter name="I2C1_PinMuxing" value="HPS I/O Set 0" />
  <parameter name="PLL_MEM_CLK_FREQ" value="400.0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MR1_RTT" value="1" />
  <parameter name="READ_FIFO_HALF_RATE" value="false" />
  <parameter name="emac1_clk_hz" value="250000000" />
  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
  <parameter name="CSR_DATA_WIDTH" value="8" />
  <parameter name="nand_x_clk_hz" value="200000000" />
  <parameter name="USE_MM_ADAPTOR" value="true" />
  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
  <parameter name="IO_OUT2_DELAY_MAX" value="0" />
  <parameter name="main_qspi_clk_hz" value="3613281" />
  <parameter name="PLL_MEM_CLK_MULT_CACHE" value="32" />
  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
  <parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
  <parameter name="ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter
     name="device_pll_info_auto"
     value="{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}" />
  <parameter
     name="JAVA_I2C1_DATA"
     value="I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}" />
  <parameter name="MEM_TRAS" value="14" />
  <parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_ECC_DQ_WIDTH" value="ECC_DQ_WIDTH_0" />
  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
  <parameter name="CTL_SELF_REFRESH" value="0" />
  <parameter name="ENUM_MEM_IF_TWTR" value="TWTR_4" />
  <parameter name="CALIBRATION_MODE" value="Skip" />
  <parameter name="LWH2F_Enable" value="true" />
  <parameter name="quartus_ini_hps_ip_enable_bsel_csel" value="false" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
  <parameter name="main_pll_c5_auto" value="18" />
  <parameter name="l4_mp_clk_source" value="1" />
  <parameter name="PLL_AFI_PHY_CLK_DIV" value="1000000" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="1875" />
  <parameter name="quartus_ini_hps_ip_suppress_sdram_synth" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
  <parameter name="ENUM_CFG_BURST_LENGTH" value="BL_8" />
  <parameter name="PHY_VERSION_NUMBER" value="211" />
  <parameter name="MEM_SRT" value="Normal" />
  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
  <parameter name="MEM_IF_READ_DQS_WIDTH" value="4" />
  <parameter name="PLL_WRITE_CLK_MULT_CACHE" value="32" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
  <parameter name="EXTRA_VFIFO_SHIFT" value="0" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
  <parameter
     name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
     value="false" />
  <parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
  <parameter name="UART0_PinMuxing" value="HPS I/O Set 0" />
  <parameter name="DMA_Enable" value="No,No,No,No,No,No,No,No" />
  <parameter name="mpu_l2_ram_clk_hz" value="462500000" />
  <parameter name="MR2_RLWL" value="1" />
  <parameter name="main_pll_vco_mhz" value="1600.0" />
  <parameter name="CV_ENUM_PRIORITY_4_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_2" value="WEIGHT_0" />
  <parameter name="I2C1_Mode" value="I2C" />
  <parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID" value="0" />
  <parameter name="F2SDRAM_Type" value="" />
  <parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="1" />
  <parameter name="CV_PORT_5_CONNECT_TO_AV_PORT" value="5" />
  <parameter name="eosc2_clk_mhz" value="25.0" />
  <parameter name="MEM_TMRD_CK" value="4" />
  <parameter name="CFG_INTERFACE_WIDTH" value="32" />
  <parameter name="IO_OUT1_DELAY_MAX" value="31" />
  <parameter name="desired_emac0_clk_mhz" value="250.0" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT" value="32" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="2500 ps" />
  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
  <parameter name="S2FCLK_USER2CLK" value="5" />
  <parameter name="S2FCLK_USER0CLK_Enable" value="false" />
  <parameter name="ENUM_CLOCK_OFF_2" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_1" value="DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
  <parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="ENUM_CLOCK_OFF_0" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_5" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_4" value="DISABLED" />
  <parameter name="show_advanced_parameters" value="false" />
  <parameter name="ENUM_CLOCK_OFF_3" value="DISABLED" />
  <parameter name="PHY_ONLY" value="false" />
  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="true" />
  <parameter name="TRFC" value="350" />
  <parameter name="IO_STANDARD" value="SSTL-15" />
  <parameter name="CV_ENUM_PRIORITY_4_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_4" value="WEIGHT_0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
  <parameter name="EMAC0_Mode" value="N/A" />
  <parameter name="READ_FIFO_SIZE" value="8" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
  <parameter name="CFG_MEM_CLK_ENTRY_CYCLES" value="10" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="ENUM_CFG_INTERFACE_WIDTH" value="DWIDTH_32" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
  <parameter name="CV_ENUM_CPORT4_TYPE" value="DISABLE" />
  <parameter name="CV_CPORT_TYPE_PORT_2" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_3" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_0" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_1" value="0" />
  <parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_4" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_5" value="0" />
  <parameter name="ENUM_PRIORITY_3_5" value="WEIGHT_0" />
  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="100000" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="AP_MODE" value="false" />
  <parameter name="ENUM_PRIORITY_3_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_3_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_3_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_3_2" value="WEIGHT_0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="400.0 MHz" />
  <parameter name="ENUM_PRIORITY_3_0" value="WEIGHT_0" />
  <parameter name="MEM_PD" value="DLL off" />
  <parameter name="MAX10_RTL_SEQ" value="false" />
  <parameter name="CTL_AUTOPCH_EN" value="false" />
  <parameter name="REF_CLK_FREQ_MAX_CACHE" value="500.0" />
  <parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID" value="0" />
  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
  <parameter name="MEM_DQ_WIDTH" value="32" />
  <parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
  <parameter name="F2SCLK_SDRAMCLK_Enable" value="false" />
  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
  <parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="FLY_BY" value="true" />
  <parameter name="ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="2.5" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ" value="400.0" />
  <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
  <parameter name="HARD_EMIF" value="true" />
  <parameter name="cfg_h2f_user0_clk_mhz" value="97.368421" />
  <parameter
     name="device_pll_info_manual"
     value="{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}" />
  <parameter name="MEM_CLK_MAX_NS" value="1.25" />
  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
  <parameter name="CALIB_REG_WIDTH" value="8" />
  <parameter name="CFG_CLR_INTR" value="0" />
  <parameter name="desired_sdmmc_clk_mhz" value="200.0" />
  <parameter name="ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
  <parameter name="ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="MR1_PASR" value="0" />
  <parameter name="IO_DQS_OUT_RESERVE" value="4" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
  <parameter name="desired_qspi_clk_mhz" value="400.0" />
  <parameter name="periph_pll_n_auto" value="0" />
  <parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
  <parameter name="MEM_BL" value="OTF" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="spi_m_clk_mhz" value="200.0" />
  <parameter name="ENUM_USER_PRIORITY_2" value="PRIORITY_1" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
  <parameter name="MEM_BT" value="Sequential" />
  <parameter name="ENUM_USER_PRIORITY_1" value="PRIORITY_1" />
  <parameter name="ENUM_USER_PRIORITY_4" value="PRIORITY_1" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="main_pll_c1_internal" value="4" />
  <parameter name="MEM_TRTP" value="3" />
  <parameter name="ENUM_USER_PRIORITY_3" value="PRIORITY_1" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="TREFI" value="35100" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="ENUM_USER_PRIORITY_0" value="PRIORITY_1" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="ENUM_USER_PRIORITY_5" value="PRIORITY_1" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
  <parameter name="ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
  <parameter name="main_pll_vco_hz" value="1600000000" />
  <parameter name="S2FCLK_USER1CLK_FREQ_HZ" value="100000000" />
  <parameter name="periph_pll_vco_auto_mhz" value="1000.0" />
  <parameter name="CV_ENUM_CPORT5_TYPE" value="DISABLE" />
  <parameter name="ENUM_ENABLE_BURST_TERMINATE" value="DISABLED" />
  <parameter name="desired_l4_sp_clk_hz" value="100000000" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="VECT_ATTR_DEBUG_SELECT_BYTE" value="0" />
  <parameter name="CV_PORT_4_CONNECT_TO_AV_PORT" value="4" />
  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
  <parameter name="DEVICE_WIDTH" value="1" />
  <parameter name="l4_sp_clk_div" value="1" />
  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
  <parameter name="ENUM_ENABLE_PIPELINEGLOBAL" value="DISABLED" />
  <parameter name="AFI_CONTROL_WIDTH" value="2" />
  <parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="10.0" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
  <parameter name="ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="USER_DEBUG_LEVEL" value="1" />
  <parameter name="ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="ENUM_SINGLE_READY_3" value="CONCATENATE_RDY" />
  <parameter name="ENUM_SINGLE_READY_1" value="CONCATENATE_RDY" />
  <parameter name="ENUM_SINGLE_READY_2" value="CONCATENATE_RDY" />
  <parameter name="ENUM_GEN_DBE" value="GEN_DBE_DISABLED" />
  <parameter name="ENUM_SINGLE_READY_0" value="CONCATENATE_RDY" />
  <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="50000000" />
  <parameter name="ENUM_MEM_IF_TCL" value="TCL_11" />
  <parameter name="CV_ENUM_USER_PRIORITY_5" value="PRIORITY_1" />
  <parameter name="CV_ENUM_USER_PRIORITY_4" value="PRIORITY_1" />
  <parameter name="CV_ENUM_USER_PRIORITY_3" value="PRIORITY_1" />
  <parameter name="LOW_LATENCY" value="false" />
  <parameter name="CV_ENUM_USER_PRIORITY_2" value="PRIORITY_1" />
  <parameter name="S2FCLK_USER1CLK_Enable" value="true" />
  <parameter name="CV_ENUM_USER_PRIORITY_1" value="PRIORITY_1" />
  <parameter name="CV_ENUM_USER_PRIORITY_0" value="PRIORITY_1" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="0.0" />
  <parameter name="ENUM_MEM_IF_DQ_PER_CHIP" value="MEM_IF_DQ_PER_CHIP_8" />
  <parameter name="MR1_WC" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="400.0 MHz" />
  <parameter name="ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_WRITE_CLK_FREQ_STR" value="400.0 MHz" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MR1_WL" value="0" />
  <parameter name="MR1_WR" value="1" />
  <parameter name="MEM_IF_CONTROL_WIDTH" value="1" />
  <parameter name="CFG_STARVE_LIMIT" value="10" />
  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT" value="0" />
  <parameter name="MEM_CLK_MAX_PS" value="1250.0" />
  <parameter name="MEM_IF_NUMBER_OF_RANKS" value="1" />
  <parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="2" />
  <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
  <parameter name="ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="MEM_TRRD" value="4" />
  <parameter name="ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="0 ps" />
  <parameter name="REFRESH_INTERVAL" value="15000" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH" value="0" />
  <parameter name="I2C3_Mode" value="N/A" />
  <parameter name="l4_sp_clk_div_auto" value="1" />
  <parameter name="TIMING_BOARD_TDH_APPLIED" value="0.165" />
  <parameter name="ADDR_RATE_RATIO" value="2" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
  <parameter name="CFG_SELF_RFSH_EXIT_CYCLES" value="512" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="1875 ps" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="CV_LSB_WFIFO_PORT_1" value="5" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="CV_LSB_WFIFO_PORT_0" value="5" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_0" value="1" />
  <parameter name="CV_ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="ENUM_ENABLE_BONDING_WRAPBACK" value="DISABLED" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_2" value="1" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_1" value="1" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_4" value="1" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_3" value="1" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_5" value="1" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS" value="1875" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.16" />
  <parameter name="AFI_WRANK_WIDTH" value="0" />
  <parameter name="LRDIMM" value="false" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="1875" />
  <parameter name="CFG_ADDR_ORDER" value="0" />
  <parameter name="main_pll_c0_internal_auto" value="1" />
  <parameter name="gpio_db_clk_div_auto" value="6249" />
  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
  <parameter name="CTL_ODT_ENABLED" value="true" />
  <parameter name="SEQUENCER_TYPE" value="NIOS" />
  <parameter name="MEM_IF_CLK_EN_WIDTH" value="1" />
  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="periph_base_clk_mhz" value="200.0" />
  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
  <parameter name="l4_sp_clk_hz" value="100000000" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="0 ps" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_ENABLE_ATPG" value="DISABLED" />
  <parameter name="default_mpu_clk_mhz" value="925.0" />
  <parameter name="nand_clk_source" value="2" />
  <parameter name="dbg_timer_clk_hz" value="25000000" />
  <parameter name="periph_pll_vco_mhz" value="1000.0" />
  <parameter name="EMAC0_PTP" value="false" />
  <parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
  <parameter name="CONTROLLER_TYPE" value="nextgen_v110" />
  <parameter name="dbg_base_clk_mhz" value="25.0" />
  <parameter name="l4_sp_clk_source" value="1" />
  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="COMMAND_PHASE" value="0.0" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
  <parameter name="ENUM_OUTPUT_REGD" value="DISABLED" />
  <parameter name="MR1_ODS" value="1" />
  <parameter name="MEM_TRFC" value="104" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="AV_PORT_4_CONNECT_TO_CV_PORT" value="4" />
  <parameter name="ENUM_CPORT1_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="show_debug_info_as_warning_msg" value="false" />
  <parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
  <parameter name="ENUM_CFG_TYPE" value="DDR3" />
  <parameter name="CV_ENUM_PORT3_WIDTH" value="PORT_32_BIT" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="0.09" />
  <parameter name="I2C3_PinMuxing" value="Unused" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="main_nand_sdmmc_clk_hz" value="3613281" />
  <parameter name="can0_clk_div" value="1" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="qspi_clk_hz" value="3613281" />
  <parameter name="ENUM_MEM_IF_BANKADDR_WIDTH" value="ADDR_WIDTH_3" />
  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
  <parameter name="ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_READ_ODT_CHIP" value="ODT_DISABLED" />
  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
  <parameter name="CV_ENUM_PORT4_WIDTH" value="PORT_32_BIT" />
  <parameter name="OCT_TERM_CONTROL_WIDTH" value="16" />
  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
  <parameter name="DLL_USE_DR_CLK" value="false" />
  <parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES" value="DISABLED" />
  <parameter name="ENUM_MEM_IF_TMRD" value="TMRD_4" />
  <parameter name="CV_LSB_WFIFO_PORT_3" value="5" />
  <parameter name="CV_LSB_WFIFO_PORT_2" value="5" />
  <parameter name="CV_LSB_WFIFO_PORT_5" value="5" />
  <parameter name="periph_pll_c5" value="9" />
  <parameter name="CV_LSB_WFIFO_PORT_4" value="5" />
  <parameter name="periph_pll_c3" value="19" />
  <parameter name="periph_pll_c4" value="4" />
  <parameter name="l4_mp_clk_hz" value="100000000" />
  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
  <parameter name="periph_pll_c1" value="3" />
  <parameter name="periph_pll_c2" value="1" />
  <parameter name="periph_pll_c0" value="3" />
  <parameter name="TB_MEM_CLK_FREQ" value="400.0" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="DLL_DELAY_CTRL_WIDTH" value="7" />
  <parameter name="MEM_CLK_FREQ" value="400.0" />
  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
  <parameter name="ENUM_MEM_IF_TWR" value="TWR_6" />
  <parameter name="ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
  <parameter name="REF_CLK_PS" value="40000.0" />
  <parameter name="ENUM_MEM_IF_TRAS" value="TRAS_14" />
  <parameter name="desired_can0_clk_hz" value="100000000" />
  <parameter name="ENUM_INC_SYNC" value="FIFO_SET_2" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01" />
  <parameter name="ENUM_MEM_IF_TRCD" value="TRCD_6" />
  <parameter name="MARGIN_VARIATION_TEST" value="false" />
  <parameter name="TIMING_TIS" value="180" />
  <parameter name="ENUM_PRIORITY_0_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_0_5" value="WEIGHT_0" />
  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
  <parameter name="ENUM_PRIORITY_0_2" value="WEIGHT_0" />
  <parameter name="IO_IN_DELAY_MAX" value="31" />
  <parameter name="ENUM_PRIORITY_0_3" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID" value="0" />
  <parameter name="ENUM_PRIORITY_0_0" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_0_1" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR" value="0" />
  <parameter name="FAST_SIM_CALIBRATION" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
  <parameter name="AVL_ADDR_WIDTH" value="27" />
  <parameter name="CFG_REORDER_DATA" value="true" />
  <parameter name="ENUM_ENABLE_FAST_EXIT_PPD" value="DISABLED" />
  <parameter name="ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="270.0" />
  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
  <parameter name="mpu_base_clk_hz" value="925000000" />
  <parameter name="cfg_clk_hz" value="97368421" />
  <parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="hps_device_family" value="Cyclone V" />
  <parameter
     name="JAVA_I2C2_DATA"
     value="I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}" />
  <parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
  <parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
  <parameter name="TIMING_TDQSCKDL" value="1200" />
  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
  <parameter name="USB1_Mode" value="SDR" />
  <parameter name="TIMING_TDQSCKDS" value="450" />
  <parameter name="TIMING_TDQSCKDM" value="900" />
  <parameter name="CV_ENUM_PORT2_WIDTH" value="PORT_32_BIT" />
  <parameter name="can0_clk_mhz" value="12.5" />
  <parameter name="NIOS_HEX_FILE_LOCATION" value="../" />
  <parameter name="emac0_clk_hz" value="1953125" />
  <parameter name="AVL_MAX_SIZE" value="4" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
  <parameter name="HLGPI_Enable" value="false" />
  <parameter name="h2f_user1_clk_hz" value="100000000" />
  <parameter name="PLL_WRITE_CLK_MULT" value="32" />
  <parameter name="F2SCLK_DBGRST_Enable" value="false" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
  <parameter name="CV_ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
  <parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_DEG" value="10.0" />
  <parameter name="ENUM_DISABLE_MERGING" value="MERGING_ENABLED" />
  <parameter name="CV_ENUM_PRIORITY_7_0" value="WEIGHT_0" />
  <parameter name="ENUM_CTL_ADDR_ORDER" value="CHIP_ROW_BANK_COL" />
  <parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="PLL_CONFIG_CLK_DIV" value="18000000" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
  <parameter name="ENUM_CTL_ECC_ENABLED" value="CTL_ECC_DISABLED" />
  <parameter name="USE_SHADOW_REGS" value="false" />
  <parameter name="desired_emac1_clk_hz" value="250000000" />
  <parameter name="ENUM_MEM_IF_CS_WIDTH" value="MEM_IF_CS_WIDTH_1" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="CV_ENUM_PORT0_WIDTH" value="PORT_32_BIT" />
  <parameter name="MEM_IF_DQ_WIDTH" value="32" />
  <parameter name="F2SDRAM_RST_PORT_USED" value="0x0" />
  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_1" value="1" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_0" value="1" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_3" value="1" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_2" value="1" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ" value="400.0" />
  <parameter name="AVL_DATA_WIDTH_PORT_5" value="1" />
  <parameter name="AVL_DATA_WIDTH_PORT_4" value="1" />
  <parameter name="AVL_DATA_WIDTH_PORT_3" value="1" />
  <parameter name="AVL_DATA_WIDTH_PORT_2" value="1" />
  <parameter name="AVL_DATA_WIDTH_PORT_1" value="1" />
  <parameter name="AVL_DATA_WIDTH_PORT_0" value="1" />
  <parameter name="REF_CLK_NS" value="40.0" />
  <parameter name="device_name" value="5CSEMA5F31C6" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_5" value="1" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_4" value="1" />
  <parameter name="AFI_CLK_EN_WIDTH" value="1" />
  <parameter name="TIMING_TQH" value="0.38" />
  <parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_CLK_CACHE_VALID" value="true" />
  <parameter name="ENUM_MEM_IF_DWIDTH" value="MEM_IF_DWIDTH_32" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_CPORT0_TYPE" value="DISABLE" />
  <parameter name="CV_ENUM_PRIORITY_7_2" value="WEIGHT_0" />
  <parameter name="ENUM_MEM_IF_TRP" value="TRP_6" />
  <parameter name="CV_ENUM_PRIORITY_7_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_7_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_7_3" value="WEIGHT_0" />
  <parameter
     name="JAVA_SPIM1_DATA"
     value="SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}" />
  <parameter name="CV_ENUM_PRIORITY_7_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="2500 ps" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
  <parameter name="RDBUFFER_ADDR_WIDTH" value="8" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="2500 ps" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_MEM_IF_TRC" value="TRC_20" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
  <parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
  <parameter name="DAT_DATA_WIDTH" value="32" />
  <parameter name="AC_ROM_MR1_CALIB" value="" />
  <parameter name="SPEED_GRADE" value="7" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="1875" />
  <parameter name="MEM_TRCD_NS" value="13.75" />
  <parameter
     name="JAVA_GUI_PIN_LIST"
     value="EMACIO0,EMACIO1,EMACIO2,EMACIO3,EMACIO4,EMACIO5,EMACIO6,EMACIO7,EMACIO8,EMACIO9,EMACIO10,EMACIO11,EMACIO12,EMACIO13,MIXED1IO0,MIXED1IO1,MIXED1IO2,MIXED1IO3,MIXED1IO4,MIXED1IO5,MIXED1IO6,MIXED1IO7,MIXED1IO8,MIXED1IO9,MIXED1IO10,MIXED1IO11,MIXED1IO12,MIXED1IO13,MIXED1IO14,MIXED1IO15,MIXED1IO16,MIXED1IO17,MIXED1IO18,MIXED1IO19,MIXED1IO20,MIXED1IO21,FLASHIO0,FLASHIO1,FLASHIO2,FLASHIO3,FLASHIO4,FLASHIO5,FLASHIO6,FLASHIO7,FLASHIO8,FLASHIO9,FLASHIO10,FLASHIO11,GENERALIO0,GENERALIO1,GENERALIO2,GENERALIO3,GENERALIO4,GENERALIO5,GENERALIO6,GENERALIO7,GENERALIO8,GENERALIO9,GENERALIO10,GENERALIO11,GENERALIO12,GENERALIO13,GENERALIO14,GENERALIO15,GENERALIO16,GENERALIO17,GENERALIO18" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="5000 ps" />
  <parameter name="ENUM_PRIORITY_4_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_5" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_0" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_1" value="WEIGHT_0" />
  <parameter name="USE_HPS_DQS_TRACKING" value="false" />
  <parameter name="EXPORT_CSR_PORT" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="0 ps" />
  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
  <parameter name="CV_LSB_RFIFO_PORT_5" value="5" />
  <parameter name="TIMING_TDS" value="30" />
  <parameter
     name="Customer_Pin_Name_DERIVED"
     value="RGMII0_TX_CLK,RGMII0_TXD0,RGMII0_TXD1,RGMII0_TXD2,RGMII0_TXD3,RGMII0_RXD0,RGMII0_MDIO,RGMII0_MDC ,RGMII0_RX_CTL,RGMII0_TX_CTL,RGMII0_RX_CLK,RGMII0_RXD1,RGMII0_RXD2,RGMII0_RXD3,NAND_ALE,NAND_CE,NAND_CLE,NAND_RE,NAND_RB,NAND_DQ0,NAND_DQ1,NAND_DQ2,NAND_DQ3,NAND_DQ4,NAND_DQ5,NAND_DQ6,NAND_DQ7,NAND_WP,NAND_WE,QSPI_IO0,QSPI_IO1,QSPI_IO2,QSPI_IO3,QSPI_SS0,QSPI_CLK,QSPI_SS1,SDMMC_CMD,SDMMC_PWREN,SDMMC_D0,SDMMC_D1,SDMMC_D4,SDMMC_D5,SDMMC_D6,SDMMC_D7,HPS_GPIO44,SDMMC_CCLK_OUT,SDMMC_D2,SDMMC_D3,TRACE_CLK,TRACE_D0,TRACE_D1,TRACE_D2,TRACE_D3,TRACE_D4,TRACE_D5,TRACE_D6,TRACE_D7,SPIM0_CLK,SPIM0_MOSI,SPIM0_MISO,SPIM0_SS0,UART0_RX,UART0_TX,I2C0_SDA,I2C0_SCL,CAN0_RX,CAN0_TX" />
  <parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
  <parameter name="ENUM_MEM_IF_AL" value="AL_0" />
  <parameter name="ENUM_TEST_MODE" value="NORMAL_MODE" />
  <parameter name="MEM_CS_WIDTH" value="1" />
  <parameter name="CV_LSB_RFIFO_PORT_0" value="5" />
  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
  <parameter name="ENUM_CPORT0_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="CV_LSB_RFIFO_PORT_2" value="5" />
  <parameter name="CV_LSB_RFIFO_PORT_1" value="5" />
  <parameter name="TIMING_TDH" value="65" />
  <parameter name="AV_PORT_3_CONNECT_TO_CV_PORT" value="3" />
  <parameter name="CV_LSB_RFIFO_PORT_4" value="5" />
  <parameter name="CV_LSB_RFIFO_PORT_3" value="5" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC" value="3" />
  <parameter name="CV_ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ" value="400.0" />
  <parameter name="USE_DQS_TRACKING" value="true" />
  <parameter name="MEM_LRDIMM_ENABLED" value="false" />
  <parameter name="TIMING_BOARD_TIS_APPLIED" value="0.33" />
  <parameter name="F2SCLK_SDRAMCLK_FREQ_MHZ" value="0.0" />
  <parameter name="CTL_ZQCAL_EN" value="false" />
  <parameter name="AC_ROM_MR0_CALIB" value="" />
  <parameter name="MEM_T_WL" value="8" />
  <parameter name="AFI_WRITE_DQS_WIDTH" value="4" />
  <parameter name="CV_ENUM_CPORT2_TYPE" value="DISABLE" />
  <parameter name="AFI_RLAT_WIDTH" value="6" />
  <parameter name="MEM_TRP" value="6" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR" value="0" />
  <parameter name="S2F_Width" value="2" />
  <parameter name="GP_Enable" value="false" />
  <parameter name="MEM_TRRD_NS" value="7.7" />
  <parameter name="CV_PORT_3_CONNECT_TO_AV_PORT" value="3" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter
     name="JAVA_SPIS1_DATA"
     value="SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}" />
  <parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="CV_ENUM_PRIORITY_3_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_2" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_3" value="WEIGHT_0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
  <parameter name="periph_pll_c0_auto" value="511" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="2500 ps" />
  <parameter name="h2f_user0_clk_mhz" value="97.368421" />
  <parameter name="quartus_ini_hps_emif_pll" value="false" />
  <parameter name="ENUM_RD_FIFO_IN_USE_2" value="FALSE" />
  <parameter name="PLL_DR_CLK_FREQ" value="0.0" />
  <parameter name="ENUM_RD_FIFO_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_RD_FIFO_IN_USE_0" value="FALSE" />
  <parameter name="ENUM_RD_FIFO_IN_USE_1" value="FALSE" />
  <parameter name="ENUM_REORDER_DATA" value="DATA_REORDERING" />
  <parameter name="NEXTGEN" value="true" />
  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
  <parameter name="PRIORITY_PORT_0" value="1" />
  <parameter name="MEM_T_RL" value="11" />
  <parameter name="MEM_TWR" value="6" />
  <parameter name="PRIORITY_PORT_2" value="1" />
  <parameter name="PRIORITY_PORT_1" value="1" />
  <parameter name="USE_DR_CLK" value="false" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="1875" />
  <parameter name="AC_ROM_MR3_MIRR" value="0000000000000" />
  <parameter name="ENABLE_EMIT_JTAG_MASTER" value="true" />
  <parameter name="MEM_IF_DQS_WIDTH" value="4" />
  <parameter name="TIMING_TIH" value="140" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD" value="3" />
  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
  <parameter name="USE_AXI_ADAPTOR" value="false" />
  <parameter name="PRIORITY_PORT_4" value="1" />
  <parameter name="PRIORITY_PORT_3" value="1" />
  <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
  <parameter name="PRIORITY_PORT_5" value="1" />
  <parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
  <parameter name="ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
  <parameter name="usb_mp_clk_mhz" value="200.0" />
  <parameter name="ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
  <parameter name="DMA_PeriphId_DERIVED" value="0,1,2,3,4,5,6,7" />
  <parameter name="ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
  <parameter name="CV_ENUM_PRIORITY_3_5" value="WEIGHT_0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="true" />
  <parameter name="ENUM_CPORT3_TYPE" value="DISABLE" />
  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
  <parameter name="desired_spi_m_clk_mhz" value="200.0" />
  <parameter
     name="JAVA_CAN0_DATA"
     value="CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="EMAC0_PinMuxing" value="Unused" />
  <parameter name="CV_MSB_RFIFO_PORT_1" value="5" />
  <parameter name="CV_MSB_RFIFO_PORT_0" value="5" />
  <parameter name="PLL_AFI_CLK_DIV" value="2" />
  <parameter name="periph_nand_sdmmc_clk_mhz" value="200.0" />
  <parameter name="CV_MSB_RFIFO_PORT_5" value="5" />
  <parameter name="MEM_TFAW" value="12" />
  <parameter name="CV_MSB_RFIFO_PORT_4" value="5" />
  <parameter name="CV_MSB_RFIFO_PORT_3" value="5" />
  <parameter name="CV_ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_MSB_RFIFO_PORT_2" value="5" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sdc"
       type="SDC"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v"
       type="VERILOG" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_inst_ROM.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_AC_ROM.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sdram_io.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/alt_types.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/system.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/tclrpt.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/tclrpt.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_defines.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/emif.pre.xml"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_parameters.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_pin_map.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_report_timing_core.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_report_timing.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_timing.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.sdc"
       type="SDC"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.ppf"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_pll.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sdc"
       type="SDC"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps.pre.xml"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_hps/altera_hps_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_interface_generator/altera_interface_generator_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_hps_io/altera_hps_io_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_interface_generator/altera_interface_generator_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
  </childSourceFiles>
  <instantiator instantiator="soc_system" as="hps_0" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 3 starting:altera_hps "submodules/soc_system_hps_0"</message>
   <message level="Info" culprit="hps_0">"Running  for module: hps_0"</message>
   <message level="Info" culprit="hps_0">HPS Main PLL counter settings: n = 0  m = 73</message>
   <message level="Info" culprit="hps_0">HPS peripherial PLL counter settings: n = 0  m = 39</message>
   <message level="Debug" culprit="hps_0.fpga_interfaces">Timing: ELA:1/0.008s</message>
   <message level="Debug" culprit="hps_0.hps_io.border">Timing: ELA:1/0.004s</message>
   <message level="Debug" culprit="hps_0.hps_io">Timing: COM:2/0.023s/0.024s</message>
   <message level="Debug" culprit="hps_0">Timing: COM:1/1.640s STR:1/1.464s</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>2</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="hps_0"><![CDATA["<b>hps_0</b>" reuses <b>altera_interface_generator</b> "<b>submodules/soc_system_hps_0_fpga_interfaces</b>"]]></message>
   <message level="Debug" culprit="hps_0"><![CDATA["<b>hps_0</b>" reuses <b>altera_hps_io</b> "<b>submodules/soc_system_hps_0_hps_io</b>"]]></message>
   <message level="Info" culprit="hps_0"><![CDATA["<b>soc_system</b>" instantiated <b>altera_hps</b> "<b>hps_0</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 30 starting:altera_interface_generator "submodules/soc_system_hps_0_fpga_interfaces"</message>
   <message level="Info" culprit="fpga_interfaces"><![CDATA["<b>hps_0</b>" instantiated <b>altera_interface_generator</b> "<b>fpga_interfaces</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 29 starting:altera_hps_io "submodules/soc_system_hps_0_hps_io"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="hps_io"><![CDATA["<b>hps_io</b>" reuses <b>altera_interface_generator</b> "<b>submodules/soc_system_hps_0_hps_io_border</b>"]]></message>
   <message level="Info" culprit="hps_io"><![CDATA["<b>hps_0</b>" instantiated <b>altera_hps_io</b> "<b>hps_io</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 2 starting:altera_interface_generator "submodules/soc_system_hps_0_hps_io_border"</message>
   <message level="Info" culprit="border"><![CDATA["<b>hps_io</b>" instantiated <b>altera_interface_generator</b> "<b>border</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_mm_interconnect:21.1:AUTO_DEVICE=5CSEMA5F31C6,AUTO_DEVICE_FAMILY=Cyclone V,AUTO_DEVICE_SPEEDGRADE=,COMPOSE_CONTENTS=add_instance {admm_solver_0_avalon_slave_0_translator} {altera_merlin_slave_translator};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_ADDRESS_W} {16};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_DATA_W} {32};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_DATA_W} {32};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_ADDRESS_W} {21};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_READLATENCY} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_READDATA} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_READ} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_WRITE} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_ADDRESS} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_LOCK} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {RAM_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {RAM_s1_translator} {AV_ADDRESS_W} {12};set_instance_parameter_value {RAM_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {RAM_s1_translator} {UAV_DATA_W} {16};set_instance_parameter_value {RAM_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {RAM_s1_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {RAM_s1_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {RAM_s1_translator} {UAV_ADDRESS_W} {21};set_instance_parameter_value {RAM_s1_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {RAM_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {RAM_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {RAM_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {RAM_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {RAM_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {RAM_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {RAM_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {RAM_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {RAM_s1_translator} {USE_READ} {0};set_instance_parameter_value {RAM_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {RAM_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {RAM_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {RAM_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {RAM_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {RAM_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {RAM_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {RAM_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {RAM_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {RAM_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {RAM_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {RAM_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {RAM_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {RAM_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {RAM_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {RAM_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {RAM_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {RAM_s1_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {RAM_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {RAM_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {RAM_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {RAM_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {RAM_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {RAM_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {RAM_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {RAM_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {RAM_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {RAM_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {RAM_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {hps_0_h2f_lw_axi_master_agent} {altera_merlin_axi_master_ni};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ID_WIDTH} {12};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ADDR_WIDTH} {21};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {RDATA_WIDTH} {32};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {WDATA_WIDTH} {32};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ADDR_USER_WIDTH} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {DATA_USER_WIDTH} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {USE_ADDR_USER} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {AXI_VERSION} {AXI3};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {WRITE_ISSUING_CAPABILITY} {8};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {READ_ISSUING_CAPABILITY} {8};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BEGIN_BURST} {84};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_CACHE_H} {106};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_CACHE_L} {103};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ADDR_SIDEBAND_H} {82};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ADDR_SIDEBAND_L} {82};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_PROTECTION_H} {102};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_PROTECTION_L} {100};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURST_SIZE_H} {79};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURST_SIZE_L} {77};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURST_TYPE_H} {81};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURST_TYPE_L} {80};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_RESPONSE_STATUS_L} {107};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_RESPONSE_STATUS_H} {108};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURSTWRAP_H} {76};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURSTWRAP_L} {70};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BYTE_CNT_H} {69};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BYTE_CNT_L} {63};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ADDR_H} {56};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_EXCLUSIVE} {62};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_COMPRESSED_READ} {57};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_POSTED} {58};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_READ} {60};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_SRC_ID_H} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_SRC_ID_L} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DEST_ID_H} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DEST_ID_L} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_THREAD_ID_H} {99};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_THREAD_ID_L} {88};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_QOS_L} {85};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_QOS_H} {85};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ORI_BURST_SIZE_L} {109};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ORI_BURST_SIZE_H} {111};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DATA_SIDEBAND_H} {83};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DATA_SIDEBAND_L} {83};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ST_DATA_W} {112};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ID} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;1&quot;
   name=&quot;admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000040000&quot;
   responds=&quot;0&quot;
   user_default=&quot;0&quot; /&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;RAM_s1_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000040000&quot;
   end=&quot;0x00000000000042000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {admm_solver_0_avalon_slave_0_agent} {altera_merlin_slave_agent};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_ORI_BURST_SIZE_H} {111};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_ORI_BURST_SIZE_L} {109};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_RESPONSE_STATUS_H} {108};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_RESPONSE_STATUS_L} {107};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BURST_SIZE_H} {79};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BURST_SIZE_L} {77};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BEGIN_BURST} {84};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_PROTECTION_H} {102};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_PROTECTION_L} {100};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BURSTWRAP_H} {76};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BURSTWRAP_L} {70};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BYTE_CNT_H} {69};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BYTE_CNT_L} {63};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_ADDR_H} {56};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_TRANS_COMPRESSED_READ} {57};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_TRANS_POSTED} {58};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_TRANS_READ} {60};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_DATA_H} {31};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_DATA_L} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_SRC_ID_H} {86};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_SRC_ID_L} {86};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_DEST_ID_H} {87};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_DEST_ID_L} {87};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {ST_DATA_W} {112};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {MAX_BURSTWRAP} {127};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {ID} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {ECC_ENABLE} {0};add_instance {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {BITS_PER_SYMBOL} {113};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {RAM_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {RAM_s1_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {RAM_s1_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {RAM_s1_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {RAM_s1_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {RAM_s1_agent} {PKT_BURST_SIZE_H} {61};set_instance_parameter_value {RAM_s1_agent} {PKT_BURST_SIZE_L} {59};set_instance_parameter_value {RAM_s1_agent} {PKT_TRANS_LOCK} {43};set_instance_parameter_value {RAM_s1_agent} {PKT_BEGIN_BURST} {66};set_instance_parameter_value {RAM_s1_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {RAM_s1_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {RAM_s1_agent} {PKT_BURSTWRAP_H} {58};set_instance_parameter_value {RAM_s1_agent} {PKT_BURSTWRAP_L} {52};set_instance_parameter_value {RAM_s1_agent} {PKT_BYTE_CNT_H} {51};set_instance_parameter_value {RAM_s1_agent} {PKT_BYTE_CNT_L} {45};set_instance_parameter_value {RAM_s1_agent} {PKT_ADDR_H} {38};set_instance_parameter_value {RAM_s1_agent} {PKT_ADDR_L} {18};set_instance_parameter_value {RAM_s1_agent} {PKT_TRANS_COMPRESSED_READ} {39};set_instance_parameter_value {RAM_s1_agent} {PKT_TRANS_POSTED} {40};set_instance_parameter_value {RAM_s1_agent} {PKT_TRANS_WRITE} {41};set_instance_parameter_value {RAM_s1_agent} {PKT_TRANS_READ} {42};set_instance_parameter_value {RAM_s1_agent} {PKT_DATA_H} {15};set_instance_parameter_value {RAM_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {RAM_s1_agent} {PKT_BYTEEN_H} {17};set_instance_parameter_value {RAM_s1_agent} {PKT_BYTEEN_L} {16};set_instance_parameter_value {RAM_s1_agent} {PKT_SRC_ID_H} {68};set_instance_parameter_value {RAM_s1_agent} {PKT_SRC_ID_L} {68};set_instance_parameter_value {RAM_s1_agent} {PKT_DEST_ID_H} {69};set_instance_parameter_value {RAM_s1_agent} {PKT_DEST_ID_L} {69};set_instance_parameter_value {RAM_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {RAM_s1_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {RAM_s1_agent} {ST_DATA_W} {94};set_instance_parameter_value {RAM_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {RAM_s1_agent} {AVS_BURSTCOUNT_W} {2};set_instance_parameter_value {RAM_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {RAM_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)};set_instance_parameter_value {RAM_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {RAM_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {RAM_s1_agent} {MAX_BYTE_CNT} {2};set_instance_parameter_value {RAM_s1_agent} {MAX_BURSTWRAP} {127};set_instance_parameter_value {RAM_s1_agent} {ID} {0};set_instance_parameter_value {RAM_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {RAM_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {RAM_s1_agent} {ECC_ENABLE} {0};add_instance {RAM_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {RAM_s1_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {BITS_PER_SYMBOL} {18};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {1 0 };set_instance_parameter_value {router} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {write both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 0x40000 };set_instance_parameter_value {router} {END_ADDRESS} {0x40000 0x42000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {56};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {102};set_instance_parameter_value {router} {PKT_PROTECTION_L} {100};set_instance_parameter_value {router} {PKT_DEST_ID_H} {87};set_instance_parameter_value {router} {PKT_DEST_ID_L} {87};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {router} {PKT_TRANS_READ} {60};set_instance_parameter_value {router} {ST_DATA_W} {112};set_instance_parameter_value {router} {ST_CHANNEL_W} {2};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {1};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {1 0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {write both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 0x40000 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x40000 0x42000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {56};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {102};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {100};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {87};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {87};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {60};set_instance_parameter_value {router_001} {ST_DATA_W} {112};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {1};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {write read };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {56};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {102};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {100};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {87};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {87};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {60};set_instance_parameter_value {router_002} {ST_DATA_W} {112};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {0 0 };set_instance_parameter_value {router_003} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {write read };set_instance_parameter_value {router_003} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {38};set_instance_parameter_value {router_003} {PKT_ADDR_L} {18};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {69};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {69};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {41};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {42};set_instance_parameter_value {router_003} {ST_DATA_W} {94};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_003} {DECODER_TYPE} {1};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {hps_0_h2f_lw_axi_master_wr_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_DEST_ID_H} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_DEST_ID_L} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_SRC_ID_H} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_SRC_ID_L} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_BYTE_CNT_H} {69};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_BYTE_CNT_L} {63};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_TRANS_POSTED} {58};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_THREAD_ID_H} {99};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_THREAD_ID_L} {88};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {MAX_BURST_LENGTH} {16};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {MAX_OUTSTANDING_RESPONSES} {3};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PIPELINED} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {ST_DATA_W} {112};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {ST_CHANNEL_W} {2};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {VALID_WIDTH} {2};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {REORDER} {0};add_instance {hps_0_h2f_lw_axi_master_rd_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_DEST_ID_H} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_DEST_ID_L} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_SRC_ID_H} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_SRC_ID_L} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_BYTE_CNT_H} {69};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_BYTE_CNT_L} {63};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_TRANS_POSTED} {58};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_THREAD_ID_H} {99};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_THREAD_ID_L} {88};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {MAX_BURST_LENGTH} {16};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {MAX_OUTSTANDING_RESPONSES} {3};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PIPELINED} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {ST_DATA_W} {112};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {ST_CHANNEL_W} {2};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {VALID_WIDTH} {2};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {REORDER} {0};add_instance {admm_solver_0_avalon_slave_0_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_ADDR_H} {56};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_ADDR_L} {36};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BEGIN_BURST} {84};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BYTE_CNT_H} {69};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BYTE_CNT_L} {63};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURST_SIZE_H} {79};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURST_SIZE_L} {77};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURST_TYPE_H} {81};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURST_TYPE_L} {80};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURSTWRAP_H} {76};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURSTWRAP_L} {70};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {57};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_TRANS_READ} {60};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {IN_NARROW_SIZE} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {ST_DATA_W} {112};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {OUT_BYTE_CNT_H} {65};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {OUT_BURSTWRAP_H} {76};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {BURSTWRAP_CONST_MASK} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {BURSTWRAP_CONST_VALUE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {RAM_s1_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_ADDR_H} {38};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_ADDR_L} {18};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BEGIN_BURST} {66};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BYTE_CNT_H} {51};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BYTE_CNT_L} {45};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BYTEEN_H} {17};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BYTEEN_L} {16};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURST_SIZE_H} {61};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURST_SIZE_L} {59};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURST_TYPE_H} {63};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURST_TYPE_L} {62};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURSTWRAP_H} {58};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURSTWRAP_L} {52};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {39};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_TRANS_WRITE} {41};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_TRANS_READ} {42};set_instance_parameter_value {RAM_s1_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {IN_NARROW_SIZE} {1};set_instance_parameter_value {RAM_s1_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {ST_DATA_W} {94};set_instance_parameter_value {RAM_s1_burst_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {RAM_s1_burst_adapter} {OUT_BYTE_CNT_H} {46};set_instance_parameter_value {RAM_s1_burst_adapter} {OUT_BURSTWRAP_H} {58};set_instance_parameter_value {RAM_s1_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)};set_instance_parameter_value {RAM_s1_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {RAM_s1_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {RAM_s1_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {BURSTWRAP_CONST_MASK} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {BURSTWRAP_CONST_VALUE} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {112};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {2};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {112};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {2};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {2};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {112};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {112};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {112};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {112};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {112};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {2};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {112};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {2};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {RAM_s1_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_ADDR_H} {38};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_ADDR_L} {18};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_DATA_H} {15};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BYTEEN_H} {17};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BYTEEN_L} {16};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {51};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {45};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {39};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_TRANS_WRITE} {41};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {58};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {52};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {61};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {59};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {44};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {63};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {62};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_ST_DATA_W} {94};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_ADDR_H} {56};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_ADDR_L} {36};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_DATA_H} {31};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {35};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {32};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {69};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {63};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {57};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {79};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {77};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {108};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {107};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {62};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {81};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {80};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {109};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {111};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_ST_DATA_W} {112};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {CONSTANT_BURST_SIZE} {0};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {1};add_instance {RAM_s1_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_ADDR_H} {56};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_ADDR_L} {36};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_DATA_H} {31};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BYTEEN_H} {35};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BYTEEN_L} {32};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {69};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {63};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {57};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_TRANS_WRITE} {59};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {76};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {70};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {79};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {77};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {108};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {107};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {62};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {81};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {80};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {109};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {111};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_ST_DATA_W} {112};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_ADDR_H} {38};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_ADDR_L} {18};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_DATA_H} {15};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {17};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {16};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {51};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {45};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {39};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {61};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {59};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {44};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {63};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {62};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_ST_DATA_W} {94};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {CONSTANT_BURST_SIZE} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {PACKING} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {1};add_instance {admm_solver_0_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {admm_solver_0_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {admm_solver_0_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {admm_solver_0_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {admm_solver_0_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {clk_0_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {clk_0_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {clk_0_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {admm_solver_0_avalon_slave_0_agent.m0} {admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {admm_solver_0_avalon_slave_0_agent.m0/admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {admm_solver_0_avalon_slave_0_agent.m0/admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {admm_solver_0_avalon_slave_0_agent.m0/admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {admm_solver_0_avalon_slave_0_agent.rf_source} {admm_solver_0_avalon_slave_0_agent_rsp_fifo.in} {avalon_streaming};add_connection {admm_solver_0_avalon_slave_0_agent_rsp_fifo.out} {admm_solver_0_avalon_slave_0_agent.rf_sink} {avalon_streaming};add_connection {admm_solver_0_avalon_slave_0_agent.rdata_fifo_src} {admm_solver_0_avalon_slave_0_agent_rdata_fifo.in} {avalon_streaming};add_connection {admm_solver_0_avalon_slave_0_agent_rdata_fifo.out} {admm_solver_0_avalon_slave_0_agent.rdata_fifo_sink} {avalon_streaming};add_connection {RAM_s1_agent.m0} {RAM_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {RAM_s1_agent.m0/RAM_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {RAM_s1_agent.m0/RAM_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {RAM_s1_agent.m0/RAM_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {RAM_s1_agent.rf_source} {RAM_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {RAM_s1_agent_rsp_fifo.out} {RAM_s1_agent.rf_sink} {avalon_streaming};add_connection {RAM_s1_agent.rdata_fifo_src} {RAM_s1_agent_rdata_fifo.in} {avalon_streaming};add_connection {RAM_s1_agent_rdata_fifo.out} {RAM_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {hps_0_h2f_lw_axi_master_agent.write_cp} {router.sink} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_agent.write_cp/router.sink} {qsys_mm.command};add_connection {hps_0_h2f_lw_axi_master_agent.read_cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_agent.read_cp/router_001.sink} {qsys_mm.command};add_connection {admm_solver_0_avalon_slave_0_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {admm_solver_0_avalon_slave_0_agent.rp/router_002.sink} {qsys_mm.response};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {RAM_s1_agent.rp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {RAM_s1_agent.rp/router_003.sink} {qsys_mm.response};add_connection {router.src} {hps_0_h2f_lw_axi_master_wr_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router.src/hps_0_h2f_lw_axi_master_wr_limiter.cmd_sink} {qsys_mm.command};add_connection {hps_0_h2f_lw_axi_master_wr_limiter.cmd_src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_wr_limiter.cmd_src/cmd_demux.sink} {qsys_mm.command};add_connection {rsp_mux.src} {hps_0_h2f_lw_axi_master_wr_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/hps_0_h2f_lw_axi_master_wr_limiter.rsp_sink} {qsys_mm.response};add_connection {hps_0_h2f_lw_axi_master_wr_limiter.rsp_src} {hps_0_h2f_lw_axi_master_agent.write_rp} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_wr_limiter.rsp_src/hps_0_h2f_lw_axi_master_agent.write_rp} {qsys_mm.response};add_connection {router_001.src} {hps_0_h2f_lw_axi_master_rd_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router_001.src/hps_0_h2f_lw_axi_master_rd_limiter.cmd_sink} {qsys_mm.command};add_connection {hps_0_h2f_lw_axi_master_rd_limiter.cmd_src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_rd_limiter.cmd_src/cmd_demux_001.sink} {qsys_mm.command};add_connection {rsp_mux_001.src} {hps_0_h2f_lw_axi_master_rd_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/hps_0_h2f_lw_axi_master_rd_limiter.rsp_sink} {qsys_mm.response};add_connection {hps_0_h2f_lw_axi_master_rd_limiter.rsp_src} {hps_0_h2f_lw_axi_master_agent.read_rp} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_rd_limiter.rsp_src/hps_0_h2f_lw_axi_master_agent.read_rp} {qsys_mm.response};add_connection {cmd_mux.src} {admm_solver_0_avalon_slave_0_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/admm_solver_0_avalon_slave_0_burst_adapter.sink0} {qsys_mm.command};add_connection {admm_solver_0_avalon_slave_0_burst_adapter.source0} {admm_solver_0_avalon_slave_0_agent.cp} {avalon_streaming};preview_set_connection_tag {admm_solver_0_avalon_slave_0_burst_adapter.source0/admm_solver_0_avalon_slave_0_agent.cp} {qsys_mm.command};add_connection {RAM_s1_burst_adapter.source0} {RAM_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {RAM_s1_burst_adapter.source0/RAM_s1_agent.cp} {qsys_mm.command};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {cmd_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/cmd_mux_001.sink1} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_001.src1} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src1/rsp_mux_001.sink1} {qsys_mm.response};add_connection {router_003.src} {RAM_s1_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/RAM_s1_rsp_width_adapter.sink} {qsys_mm.response};add_connection {RAM_s1_rsp_width_adapter.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {RAM_s1_rsp_width_adapter.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {cmd_mux_001.src} {RAM_s1_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/RAM_s1_cmd_width_adapter.sink} {qsys_mm.command};add_connection {RAM_s1_cmd_width_adapter.src} {RAM_s1_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {RAM_s1_cmd_width_adapter.src/RAM_s1_burst_adapter.sink0} {qsys_mm.command};add_connection {hps_0_h2f_lw_axi_master_wr_limiter.cmd_valid} {cmd_demux.sink_valid} {avalon_streaming};add_connection {hps_0_h2f_lw_axi_master_rd_limiter.cmd_valid} {cmd_demux_001.sink_valid} {avalon_streaming};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {admm_solver_0_avalon_slave_0_translator.reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_translator.reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {admm_solver_0_avalon_slave_0_agent.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {admm_solver_0_avalon_slave_0_agent_rsp_fifo.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {admm_solver_0_avalon_slave_0_agent_rdata_fifo.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_agent.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_agent_rdata_fifo.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {admm_solver_0_avalon_slave_0_burst_adapter.cr0_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_burst_adapter.cr0_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_rsp_width_adapter.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_cmd_width_adapter.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {hps_0_h2f_lw_axi_master_agent.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {hps_0_h2f_lw_axi_master_wr_limiter.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {hps_0_h2f_lw_axi_master_rd_limiter.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_avalon_slave_0_translator.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_translator.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {hps_0_h2f_lw_axi_master_agent.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_avalon_slave_0_agent.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_avalon_slave_0_agent_rsp_fifo.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_avalon_slave_0_agent_rdata_fifo.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_agent.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_agent_rdata_fifo.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {hps_0_h2f_lw_axi_master_wr_limiter.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {hps_0_h2f_lw_axi_master_rd_limiter.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_avalon_slave_0_burst_adapter.cr0} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_burst_adapter.cr0} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_rsp_width_adapter.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_cmd_width_adapter.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_reset_reset_bridge.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.clk} {clock};add_interface {hps_0_h2f_lw_axi_master} {axi} {slave};set_interface_property {hps_0_h2f_lw_axi_master} {EXPORT_OF} {hps_0_h2f_lw_axi_master_agent.altera_axi_slave};add_interface {clk_0_clk} {clock} {slave};set_interface_property {clk_0_clk} {EXPORT_OF} {clk_0_clk_clock_bridge.in_clk};add_interface {admm_solver_0_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {admm_solver_0_reset_reset_bridge_in_reset} {EXPORT_OF} {admm_solver_0_reset_reset_bridge.in_reset};add_interface {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset} {EXPORT_OF} {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.in_reset};add_interface {admm_solver_0_avalon_slave_0} {avalon} {master};set_interface_property {admm_solver_0_avalon_slave_0} {EXPORT_OF} {admm_solver_0_avalon_slave_0_translator.avalon_anti_slave_0};add_interface {RAM_s1} {avalon} {master};set_interface_property {RAM_s1} {EXPORT_OF} {RAM_s1_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.RAM.s1} {0};set_module_assignment {interconnect_id.admm_solver_0.avalon_slave_0} {1};set_module_assignment {interconnect_id.hps_0.h2f_lw_axi_master} {0};(altera_merlin_slave_translator:21.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=16,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=21,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=0,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_slave_translator:21.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=12,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=2,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=16,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=1,AV_READ_WAIT=0,AV_READ_WAIT_CYCLES=0,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=2,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=21,UAV_BURSTCOUNT_W=2,UAV_BYTEENABLE_W=2,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=16,USE_ADDRESS=1,USE_AV_CLKEN=1,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=1,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=1,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0)(altera_merlin_axi_master_ni:21.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;1&quot;
   name=&quot;admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000040000&quot;
   responds=&quot;0&quot;
   user_default=&quot;0&quot; /&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;RAM_s1_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000040000&quot;
   end=&quot;0x00000000000042000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
,ADDR_USER_WIDTH=1,ADDR_WIDTH=21,AXI_BURST_LENGTH_WIDTH=4,AXI_LOCK_WIDTH=2,AXI_VERSION=AXI3,DATA_USER_WIDTH=1,ID=0,ID_WIDTH=12,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),PKT_ADDR_H=56,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=82,PKT_ADDR_SIDEBAND_L=82,PKT_BEGIN_BURST=84,PKT_BURSTWRAP_H=76,PKT_BURSTWRAP_L=70,PKT_BURST_SIZE_H=79,PKT_BURST_SIZE_L=77,PKT_BURST_TYPE_H=81,PKT_BURST_TYPE_L=80,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=69,PKT_BYTE_CNT_L=63,PKT_CACHE_H=106,PKT_CACHE_L=103,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=83,PKT_DATA_SIDEBAND_L=83,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_ORI_BURST_SIZE_H=111,PKT_ORI_BURST_SIZE_L=109,PKT_PROTECTION_H=102,PKT_PROTECTION_L=100,PKT_QOS_H=85,PKT_QOS_L=85,PKT_RESPONSE_STATUS_H=108,PKT_RESPONSE_STATUS_L=107,PKT_SRC_ID_H=86,PKT_SRC_ID_L=86,PKT_THREAD_ID_H=99,PKT_THREAD_ID_L=88,PKT_TRANS_COMPRESSED_READ=57,PKT_TRANS_EXCLUSIVE=62,PKT_TRANS_LOCK=61,PKT_TRANS_POSTED=58,PKT_TRANS_READ=60,PKT_TRANS_WRITE=59,RDATA_WIDTH=32,READ_ISSUING_CAPABILITY=8,ST_CHANNEL_W=2,ST_DATA_W=112,USE_ADDR_USER=0,WDATA_WIDTH=32,WRITE_ISSUING_CAPABILITY=8)(altera_merlin_slave_agent:21.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=1,MAX_BURSTWRAP=127,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),PKT_ADDR_H=56,PKT_ADDR_L=36,PKT_BEGIN_BURST=84,PKT_BURSTWRAP_H=76,PKT_BURSTWRAP_L=70,PKT_BURST_SIZE_H=79,PKT_BURST_SIZE_L=77,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=69,PKT_BYTE_CNT_L=63,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_ORI_BURST_SIZE_H=111,PKT_ORI_BURST_SIZE_L=109,PKT_PROTECTION_H=102,PKT_PROTECTION_L=100,PKT_RESPONSE_STATUS_H=108,PKT_RESPONSE_STATUS_L=107,PKT_SRC_ID_H=86,PKT_SRC_ID_L=86,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=57,PKT_TRANS_LOCK=61,PKT_TRANS_POSTED=58,PKT_TRANS_READ=60,PKT_TRANS_WRITE=59,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=2,ST_DATA_W=112,SUPPRESS_0_BYTEEN_CMD=1,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:21.1:BITS_PER_SYMBOL=113,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_avalon_sc_fifo:21.1:BITS_PER_SYMBOL=34,CHANNEL_WIDTH=0,EMPTY_LATENCY=0,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=0,USE_STORE_FORWARD=0)(altera_merlin_slave_agent:21.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=2,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=0,MAX_BURSTWRAP=127,MAX_BYTE_CNT=2,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0),PKT_ADDR_H=38,PKT_ADDR_L=18,PKT_BEGIN_BURST=66,PKT_BURSTWRAP_H=58,PKT_BURSTWRAP_L=52,PKT_BURST_SIZE_H=61,PKT_BURST_SIZE_L=59,PKT_BYTEEN_H=17,PKT_BYTEEN_L=16,PKT_BYTE_CNT_H=51,PKT_BYTE_CNT_L=45,PKT_DATA_H=15,PKT_DATA_L=0,PKT_DEST_ID_H=69,PKT_DEST_ID_L=69,PKT_ORI_BURST_SIZE_H=93,PKT_ORI_BURST_SIZE_L=91,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_RESPONSE_STATUS_H=90,PKT_RESPONSE_STATUS_L=89,PKT_SRC_ID_H=68,PKT_SRC_ID_L=68,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=39,PKT_TRANS_LOCK=43,PKT_TRANS_POSTED=40,PKT_TRANS_READ=42,PKT_TRANS_WRITE=41,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=2,ST_DATA_W=94,SUPPRESS_0_BYTEEN_CMD=1,USE_READRESPONSE=0,USE_WRITERESPONSE=0)(altera_avalon_sc_fifo:21.1:BITS_PER_SYMBOL=95,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0)(altera_avalon_sc_fifo:21.1:BITS_PER_SYMBOL=18,CHANNEL_WIDTH=0,EMPTY_LATENCY=0,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=0,USE_STORE_FORWARD=0)(altera_merlin_router:21.1:CHANNEL_ID=01,10,DECODER_TYPE=0,DEFAULT_CHANNEL=1,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=1,0,END_ADDRESS=0x40000,0x42000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=56,PKT_ADDR_L=36,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_PROTECTION_H=102,PKT_PROTECTION_L=100,PKT_TRANS_READ=60,PKT_TRANS_WRITE=59,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=1:01:0x0:0x40000:write:1:0:0:1,0:10:0x40000:0x42000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x40000,ST_CHANNEL_W=2,ST_DATA_W=112,TYPE_OF_TRANSACTION=write,both)(altera_merlin_router:21.1:CHANNEL_ID=01,10,DECODER_TYPE=0,DEFAULT_CHANNEL=1,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=1,0,END_ADDRESS=0x40000,0x42000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=56,PKT_ADDR_L=36,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_PROTECTION_H=102,PKT_PROTECTION_L=100,PKT_TRANS_READ=60,PKT_TRANS_WRITE=59,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=1:01:0x0:0x40000:write:1:0:0:1,0:10:0x40000:0x42000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x40000,ST_CHANNEL_W=2,ST_DATA_W=112,TYPE_OF_TRANSACTION=write,both)(altera_merlin_router:21.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=-1,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=1,DEFAULT_WR_CHANNEL=0,DESTINATION_ID=0,0,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=56,PKT_ADDR_L=36,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_PROTECTION_H=102,PKT_PROTECTION_L=100,PKT_TRANS_READ=60,PKT_TRANS_WRITE=59,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=2,ST_DATA_W=112,TYPE_OF_TRANSACTION=write,read)(altera_merlin_router:21.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=-1,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=1,DEFAULT_WR_CHANNEL=0,DESTINATION_ID=0,0,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=38,PKT_ADDR_L=18,PKT_DEST_ID_H=69,PKT_DEST_ID_L=69,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_TRANS_READ=42,PKT_TRANS_WRITE=41,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=2,ST_DATA_W=94,TYPE_OF_TRANSACTION=write,read)(altera_merlin_traffic_limiter:21.1:ENFORCE_ORDER=1,MAX_BURST_LENGTH=16,MAX_OUTSTANDING_RESPONSES=3,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),PIPELINED=0,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=69,PKT_BYTE_CNT_L=63,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_SRC_ID_H=86,PKT_SRC_ID_L=86,PKT_THREAD_ID_H=99,PKT_THREAD_ID_L=88,PKT_TRANS_POSTED=58,PKT_TRANS_WRITE=59,PREVENT_HAZARDS=0,REORDER=0,ST_CHANNEL_W=2,ST_DATA_W=112,SUPPORTS_NONPOSTED_WRITES=0,SUPPORTS_POSTED_WRITES=1,VALID_WIDTH=2)(altera_merlin_traffic_limiter:21.1:ENFORCE_ORDER=1,MAX_BURST_LENGTH=16,MAX_OUTSTANDING_RESPONSES=3,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),PIPELINED=0,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=69,PKT_BYTE_CNT_L=63,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_SRC_ID_H=86,PKT_SRC_ID_L=86,PKT_THREAD_ID_H=99,PKT_THREAD_ID_L=88,PKT_TRANS_POSTED=58,PKT_TRANS_WRITE=59,PREVENT_HAZARDS=0,REORDER=0,ST_CHANNEL_W=2,ST_DATA_W=112,SUPPORTS_NONPOSTED_WRITES=0,SUPPORTS_POSTED_WRITES=1,VALID_WIDTH=2)(altera_merlin_burst_adapter:21.1:ADAPTER_VERSION=13.1,BURSTWRAP_CONST_MASK=0,BURSTWRAP_CONST_VALUE=0,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=1,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=1,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=76,OUT_BYTE_CNT_H=65,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=56,PKT_ADDR_L=36,PKT_BEGIN_BURST=84,PKT_BURSTWRAP_H=76,PKT_BURSTWRAP_L=70,PKT_BURST_SIZE_H=79,PKT_BURST_SIZE_L=77,PKT_BURST_TYPE_H=81,PKT_BURST_TYPE_L=80,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=69,PKT_BYTE_CNT_L=63,PKT_TRANS_COMPRESSED_READ=57,PKT_TRANS_READ=60,PKT_TRANS_WRITE=59,ST_CHANNEL_W=2,ST_DATA_W=112)(altera_merlin_burst_adapter:21.1:ADAPTER_VERSION=13.1,BURSTWRAP_CONST_MASK=0,BURSTWRAP_CONST_VALUE=0,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=1,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=1,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=58,OUT_BYTE_CNT_H=46,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=38,PKT_ADDR_L=18,PKT_BEGIN_BURST=66,PKT_BURSTWRAP_H=58,PKT_BURSTWRAP_L=52,PKT_BURST_SIZE_H=61,PKT_BURST_SIZE_L=59,PKT_BURST_TYPE_H=63,PKT_BURST_TYPE_L=62,PKT_BYTEEN_H=17,PKT_BYTEEN_L=16,PKT_BYTE_CNT_H=51,PKT_BYTE_CNT_L=45,PKT_TRANS_COMPRESSED_READ=39,PKT_TRANS_READ=42,PKT_TRANS_WRITE=41,ST_CHANNEL_W=2,ST_DATA_W=94)(altera_merlin_demultiplexer:21.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone V,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=2,ST_DATA_W=112,VALID_WIDTH=2)(altera_merlin_demultiplexer:21.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone V,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=2,ST_DATA_W=112,VALID_WIDTH=2)(altera_merlin_multiplexer:21.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=1,PKT_TRANS_LOCK=61,ST_CHANNEL_W=2,ST_DATA_W=112,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:21.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=1,PKT_TRANS_LOCK=61,ST_CHANNEL_W=2,ST_DATA_W=112,USE_EXTERNAL_ARB=0)(altera_merlin_demultiplexer:21.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone V,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=2,ST_DATA_W=112,VALID_WIDTH=1)(altera_merlin_demultiplexer:21.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone V,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=2,ST_DATA_W=112,VALID_WIDTH=1)(altera_merlin_multiplexer:21.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=61,ST_CHANNEL_W=2,ST_DATA_W=112,USE_EXTERNAL_ARB=0)(altera_merlin_multiplexer:21.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=61,ST_CHANNEL_W=2,ST_DATA_W=112,USE_EXTERNAL_ARB=0)(altera_merlin_width_adapter:21.1:COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=0,ENABLE_ADDRESS_ALIGNMENT=1,IN_MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0),IN_PKT_ADDR_H=38,IN_PKT_ADDR_L=18,IN_PKT_BURSTWRAP_H=58,IN_PKT_BURSTWRAP_L=52,IN_PKT_BURST_SIZE_H=61,IN_PKT_BURST_SIZE_L=59,IN_PKT_BURST_TYPE_H=63,IN_PKT_BURST_TYPE_L=62,IN_PKT_BYTEEN_H=17,IN_PKT_BYTEEN_L=16,IN_PKT_BYTE_CNT_H=51,IN_PKT_BYTE_CNT_L=45,IN_PKT_DATA_H=15,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=93,IN_PKT_ORI_BURST_SIZE_L=91,IN_PKT_RESPONSE_STATUS_H=90,IN_PKT_RESPONSE_STATUS_L=89,IN_PKT_TRANS_COMPRESSED_READ=39,IN_PKT_TRANS_EXCLUSIVE=44,IN_PKT_TRANS_WRITE=41,IN_ST_DATA_W=94,OPTIMIZE_FOR_RSP=0,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),OUT_PKT_ADDR_H=56,OUT_PKT_ADDR_L=36,OUT_PKT_BURST_SIZE_H=79,OUT_PKT_BURST_SIZE_L=77,OUT_PKT_BURST_TYPE_H=81,OUT_PKT_BURST_TYPE_L=80,OUT_PKT_BYTEEN_H=35,OUT_PKT_BYTEEN_L=32,OUT_PKT_BYTE_CNT_H=69,OUT_PKT_BYTE_CNT_L=63,OUT_PKT_DATA_H=31,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=111,OUT_PKT_ORI_BURST_SIZE_L=109,OUT_PKT_RESPONSE_STATUS_H=108,OUT_PKT_RESPONSE_STATUS_L=107,OUT_PKT_TRANS_COMPRESSED_READ=57,OUT_PKT_TRANS_EXCLUSIVE=62,OUT_ST_DATA_W=112,PACKING=1,RESPONSE_PATH=1,ST_CHANNEL_W=2)(altera_merlin_width_adapter:21.1:COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=0,ENABLE_ADDRESS_ALIGNMENT=1,IN_MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),IN_PKT_ADDR_H=56,IN_PKT_ADDR_L=36,IN_PKT_BURSTWRAP_H=76,IN_PKT_BURSTWRAP_L=70,IN_PKT_BURST_SIZE_H=79,IN_PKT_BURST_SIZE_L=77,IN_PKT_BURST_TYPE_H=81,IN_PKT_BURST_TYPE_L=80,IN_PKT_BYTEEN_H=35,IN_PKT_BYTEEN_L=32,IN_PKT_BYTE_CNT_H=69,IN_PKT_BYTE_CNT_L=63,IN_PKT_DATA_H=31,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=111,IN_PKT_ORI_BURST_SIZE_L=109,IN_PKT_RESPONSE_STATUS_H=108,IN_PKT_RESPONSE_STATUS_L=107,IN_PKT_TRANS_COMPRESSED_READ=57,IN_PKT_TRANS_EXCLUSIVE=62,IN_PKT_TRANS_WRITE=59,IN_ST_DATA_W=112,OPTIMIZE_FOR_RSP=0,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0),OUT_PKT_ADDR_H=38,OUT_PKT_ADDR_L=18,OUT_PKT_BURST_SIZE_H=61,OUT_PKT_BURST_SIZE_L=59,OUT_PKT_BURST_TYPE_H=63,OUT_PKT_BURST_TYPE_L=62,OUT_PKT_BYTEEN_H=17,OUT_PKT_BYTEEN_L=16,OUT_PKT_BYTE_CNT_H=51,OUT_PKT_BYTE_CNT_L=45,OUT_PKT_DATA_H=15,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=93,OUT_PKT_ORI_BURST_SIZE_L=91,OUT_PKT_RESPONSE_STATUS_H=90,OUT_PKT_RESPONSE_STATUS_L=89,OUT_PKT_TRANS_COMPRESSED_READ=39,OUT_PKT_TRANS_EXCLUSIVE=44,OUT_ST_DATA_W=94,PACKING=0,RESPONSE_PATH=0,ST_CHANNEL_W=2)(altera_reset_bridge:21.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_reset_bridge:21.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=50000000,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(altera_clock_bridge:21.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=50000000,NUM_CLOCK_OUTPUTS=1)(avalon:21.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon:21.1:arbitrationPriority=1,baseAddress=0x0000,defaultConnection=false)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(avalon_streaming:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(reset:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)(clock:21.1:)"
   instancePathKey="soc_system:.:mm_interconnect_0"
   kind="altera_mm_interconnect"
   version="21.1"
   name="soc_system_mm_interconnect_0">
  <parameter name="AUTO_DEVICE" value="5CSEMA5F31C6" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
  <parameter
     name="COMPOSE_CONTENTS"
     value="add_instance {admm_solver_0_avalon_slave_0_translator} {altera_merlin_slave_translator};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_ADDRESS_W} {16};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_DATA_W} {32};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_DATA_W} {32};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_ADDRESS_W} {21};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_READLATENCY} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_READ_WAIT} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_READDATA} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_READ} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_WRITE} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_BYTEENABLE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_ADDRESS} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_LOCK} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {RAM_s1_translator} {altera_merlin_slave_translator};set_instance_parameter_value {RAM_s1_translator} {AV_ADDRESS_W} {12};set_instance_parameter_value {RAM_s1_translator} {AV_DATA_W} {16};set_instance_parameter_value {RAM_s1_translator} {UAV_DATA_W} {16};set_instance_parameter_value {RAM_s1_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {RAM_s1_translator} {AV_BYTEENABLE_W} {2};set_instance_parameter_value {RAM_s1_translator} {UAV_BYTEENABLE_W} {2};set_instance_parameter_value {RAM_s1_translator} {UAV_ADDRESS_W} {21};set_instance_parameter_value {RAM_s1_translator} {UAV_BURSTCOUNT_W} {2};set_instance_parameter_value {RAM_s1_translator} {AV_READLATENCY} {1};set_instance_parameter_value {RAM_s1_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {RAM_s1_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {RAM_s1_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {RAM_s1_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {RAM_s1_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {RAM_s1_translator} {USE_READDATA} {1};set_instance_parameter_value {RAM_s1_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {RAM_s1_translator} {USE_READ} {0};set_instance_parameter_value {RAM_s1_translator} {USE_WRITE} {1};set_instance_parameter_value {RAM_s1_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {RAM_s1_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {RAM_s1_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {RAM_s1_translator} {USE_CHIPSELECT} {1};set_instance_parameter_value {RAM_s1_translator} {USE_ADDRESS} {1};set_instance_parameter_value {RAM_s1_translator} {USE_BURSTCOUNT} {0};set_instance_parameter_value {RAM_s1_translator} {USE_READDATAVALID} {0};set_instance_parameter_value {RAM_s1_translator} {USE_WAITREQUEST} {0};set_instance_parameter_value {RAM_s1_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {RAM_s1_translator} {USE_LOCK} {0};set_instance_parameter_value {RAM_s1_translator} {USE_AV_CLKEN} {1};set_instance_parameter_value {RAM_s1_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {RAM_s1_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {RAM_s1_translator} {USE_DEBUGACCESS} {0};set_instance_parameter_value {RAM_s1_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {RAM_s1_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {RAM_s1_translator} {AV_SYMBOLS_PER_WORD} {2};set_instance_parameter_value {RAM_s1_translator} {AV_ADDRESS_SYMBOLS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {RAM_s1_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {RAM_s1_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {RAM_s1_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {RAM_s1_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {RAM_s1_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {RAM_s1_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {RAM_s1_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {RAM_s1_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {RAM_s1_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {RAM_s1_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {RAM_s1_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};add_instance {hps_0_h2f_lw_axi_master_agent} {altera_merlin_axi_master_ni};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ID_WIDTH} {12};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ADDR_WIDTH} {21};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {RDATA_WIDTH} {32};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {WDATA_WIDTH} {32};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ADDR_USER_WIDTH} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {DATA_USER_WIDTH} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {USE_ADDR_USER} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {AXI_VERSION} {AXI3};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {WRITE_ISSUING_CAPABILITY} {8};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {READ_ISSUING_CAPABILITY} {8};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BEGIN_BURST} {84};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_CACHE_H} {106};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_CACHE_L} {103};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ADDR_SIDEBAND_H} {82};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ADDR_SIDEBAND_L} {82};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_PROTECTION_H} {102};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_PROTECTION_L} {100};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURST_SIZE_H} {79};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURST_SIZE_L} {77};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURST_TYPE_H} {81};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURST_TYPE_L} {80};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_RESPONSE_STATUS_L} {107};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_RESPONSE_STATUS_H} {108};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURSTWRAP_H} {76};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BURSTWRAP_L} {70};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BYTE_CNT_H} {69};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BYTE_CNT_L} {63};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ADDR_H} {56};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_EXCLUSIVE} {62};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_COMPRESSED_READ} {57};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_POSTED} {58};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_TRANS_READ} {60};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DATA_H} {31};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DATA_L} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_SRC_ID_H} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_SRC_ID_L} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DEST_ID_H} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DEST_ID_L} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_THREAD_ID_H} {99};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_THREAD_ID_L} {88};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_QOS_L} {85};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_QOS_H} {85};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ORI_BURST_SIZE_L} {109};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_ORI_BURST_SIZE_H} {111};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DATA_SIDEBAND_H} {83};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {PKT_DATA_SIDEBAND_L} {83};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ST_DATA_W} {112};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ID} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;1&quot;
   name=&quot;admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000040000&quot;
   responds=&quot;0&quot;
   user_default=&quot;0&quot; /&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;RAM_s1_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000040000&quot;
   end=&quot;0x00000000000042000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {admm_solver_0_avalon_slave_0_agent} {altera_merlin_slave_agent};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_ORI_BURST_SIZE_H} {111};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_ORI_BURST_SIZE_L} {109};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_RESPONSE_STATUS_H} {108};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_RESPONSE_STATUS_L} {107};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BURST_SIZE_H} {79};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BURST_SIZE_L} {77};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BEGIN_BURST} {84};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_PROTECTION_H} {102};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_PROTECTION_L} {100};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BURSTWRAP_H} {76};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BURSTWRAP_L} {70};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BYTE_CNT_H} {69};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BYTE_CNT_L} {63};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_ADDR_H} {56};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_TRANS_COMPRESSED_READ} {57};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_TRANS_POSTED} {58};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_TRANS_READ} {60};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_DATA_H} {31};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_DATA_L} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_SRC_ID_H} {86};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_SRC_ID_L} {86};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_DEST_ID_H} {87};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_DEST_ID_L} {87};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {ST_DATA_W} {112};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {MAX_BURSTWRAP} {127};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {ID} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent} {ECC_ENABLE} {0};add_instance {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {BITS_PER_SYMBOL} {113};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {admm_solver_0_avalon_slave_0_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {RAM_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {RAM_s1_agent} {PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {RAM_s1_agent} {PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {RAM_s1_agent} {PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {RAM_s1_agent} {PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {RAM_s1_agent} {PKT_BURST_SIZE_H} {61};set_instance_parameter_value {RAM_s1_agent} {PKT_BURST_SIZE_L} {59};set_instance_parameter_value {RAM_s1_agent} {PKT_TRANS_LOCK} {43};set_instance_parameter_value {RAM_s1_agent} {PKT_BEGIN_BURST} {66};set_instance_parameter_value {RAM_s1_agent} {PKT_PROTECTION_H} {84};set_instance_parameter_value {RAM_s1_agent} {PKT_PROTECTION_L} {82};set_instance_parameter_value {RAM_s1_agent} {PKT_BURSTWRAP_H} {58};set_instance_parameter_value {RAM_s1_agent} {PKT_BURSTWRAP_L} {52};set_instance_parameter_value {RAM_s1_agent} {PKT_BYTE_CNT_H} {51};set_instance_parameter_value {RAM_s1_agent} {PKT_BYTE_CNT_L} {45};set_instance_parameter_value {RAM_s1_agent} {PKT_ADDR_H} {38};set_instance_parameter_value {RAM_s1_agent} {PKT_ADDR_L} {18};set_instance_parameter_value {RAM_s1_agent} {PKT_TRANS_COMPRESSED_READ} {39};set_instance_parameter_value {RAM_s1_agent} {PKT_TRANS_POSTED} {40};set_instance_parameter_value {RAM_s1_agent} {PKT_TRANS_WRITE} {41};set_instance_parameter_value {RAM_s1_agent} {PKT_TRANS_READ} {42};set_instance_parameter_value {RAM_s1_agent} {PKT_DATA_H} {15};set_instance_parameter_value {RAM_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {RAM_s1_agent} {PKT_BYTEEN_H} {17};set_instance_parameter_value {RAM_s1_agent} {PKT_BYTEEN_L} {16};set_instance_parameter_value {RAM_s1_agent} {PKT_SRC_ID_H} {68};set_instance_parameter_value {RAM_s1_agent} {PKT_SRC_ID_L} {68};set_instance_parameter_value {RAM_s1_agent} {PKT_DEST_ID_H} {69};set_instance_parameter_value {RAM_s1_agent} {PKT_DEST_ID_L} {69};set_instance_parameter_value {RAM_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {RAM_s1_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {RAM_s1_agent} {ST_DATA_W} {94};set_instance_parameter_value {RAM_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {RAM_s1_agent} {AVS_BURSTCOUNT_W} {2};set_instance_parameter_value {RAM_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {RAM_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)};set_instance_parameter_value {RAM_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {RAM_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {RAM_s1_agent} {MAX_BYTE_CNT} {2};set_instance_parameter_value {RAM_s1_agent} {MAX_BURSTWRAP} {127};set_instance_parameter_value {RAM_s1_agent} {ID} {0};set_instance_parameter_value {RAM_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {RAM_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {RAM_s1_agent} {ECC_ENABLE} {0};add_instance {RAM_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {95};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {RAM_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {RAM_s1_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {BITS_PER_SYMBOL} {18};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {RAM_s1_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {1 0 };set_instance_parameter_value {router} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {write both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 0x40000 };set_instance_parameter_value {router} {END_ADDRESS} {0x40000 0x42000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {56};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {102};set_instance_parameter_value {router} {PKT_PROTECTION_L} {100};set_instance_parameter_value {router} {PKT_DEST_ID_H} {87};set_instance_parameter_value {router} {PKT_DEST_ID_L} {87};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {router} {PKT_TRANS_READ} {60};set_instance_parameter_value {router} {ST_DATA_W} {112};set_instance_parameter_value {router} {ST_CHANNEL_W} {2};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {1};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {1 0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {write both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 0x40000 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x40000 0x42000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {56};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {102};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {100};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {87};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {87};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {60};set_instance_parameter_value {router_001} {ST_DATA_W} {112};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {1};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {write read };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {56};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {102};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {100};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {87};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {87};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {60};set_instance_parameter_value {router_002} {ST_DATA_W} {112};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {0 0 };set_instance_parameter_value {router_003} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {write read };set_instance_parameter_value {router_003} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {38};set_instance_parameter_value {router_003} {PKT_ADDR_L} {18};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {84};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {82};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {69};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {69};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {41};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {42};set_instance_parameter_value {router_003} {ST_DATA_W} {94};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_003} {DECODER_TYPE} {1};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {hps_0_h2f_lw_axi_master_wr_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_DEST_ID_H} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_DEST_ID_L} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_SRC_ID_H} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_SRC_ID_L} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_BYTE_CNT_H} {69};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_BYTE_CNT_L} {63};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_TRANS_POSTED} {58};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_THREAD_ID_H} {99};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PKT_THREAD_ID_L} {88};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {MAX_BURST_LENGTH} {16};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {MAX_OUTSTANDING_RESPONSES} {3};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PIPELINED} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {ST_DATA_W} {112};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {ST_CHANNEL_W} {2};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {VALID_WIDTH} {2};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {hps_0_h2f_lw_axi_master_wr_limiter} {REORDER} {0};add_instance {hps_0_h2f_lw_axi_master_rd_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_DEST_ID_H} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_DEST_ID_L} {87};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_SRC_ID_H} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_SRC_ID_L} {86};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_BYTE_CNT_H} {69};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_BYTE_CNT_L} {63};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_TRANS_POSTED} {58};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_THREAD_ID_H} {99};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PKT_THREAD_ID_L} {88};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {MAX_BURST_LENGTH} {16};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {MAX_OUTSTANDING_RESPONSES} {3};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PIPELINED} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {ST_DATA_W} {112};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {ST_CHANNEL_W} {2};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {VALID_WIDTH} {2};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {hps_0_h2f_lw_axi_master_rd_limiter} {REORDER} {0};add_instance {admm_solver_0_avalon_slave_0_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_ADDR_H} {56};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_ADDR_L} {36};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BEGIN_BURST} {84};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BYTE_CNT_H} {69};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BYTE_CNT_L} {63};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURST_SIZE_H} {79};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURST_SIZE_L} {77};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURST_TYPE_H} {81};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURST_TYPE_L} {80};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURSTWRAP_H} {76};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_BURSTWRAP_L} {70};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {57};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_TRANS_WRITE} {59};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PKT_TRANS_READ} {60};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {IN_NARROW_SIZE} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {ST_DATA_W} {112};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {OUT_BYTE_CNT_H} {65};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {OUT_BURSTWRAP_H} {76};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {BURSTWRAP_CONST_MASK} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {BURSTWRAP_CONST_VALUE} {0};set_instance_parameter_value {admm_solver_0_avalon_slave_0_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {RAM_s1_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_ADDR_H} {38};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_ADDR_L} {18};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BEGIN_BURST} {66};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BYTE_CNT_H} {51};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BYTE_CNT_L} {45};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BYTEEN_H} {17};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BYTEEN_L} {16};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURST_SIZE_H} {61};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURST_SIZE_L} {59};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURST_TYPE_H} {63};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURST_TYPE_L} {62};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURSTWRAP_H} {58};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_BURSTWRAP_L} {52};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {39};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_TRANS_WRITE} {41};set_instance_parameter_value {RAM_s1_burst_adapter} {PKT_TRANS_READ} {42};set_instance_parameter_value {RAM_s1_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {IN_NARROW_SIZE} {1};set_instance_parameter_value {RAM_s1_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {ST_DATA_W} {94};set_instance_parameter_value {RAM_s1_burst_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {RAM_s1_burst_adapter} {OUT_BYTE_CNT_H} {46};set_instance_parameter_value {RAM_s1_burst_adapter} {OUT_BURSTWRAP_H} {58};set_instance_parameter_value {RAM_s1_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)};set_instance_parameter_value {RAM_s1_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {RAM_s1_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {RAM_s1_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {BURSTWRAP_CONST_MASK} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {BURSTWRAP_CONST_VALUE} {0};set_instance_parameter_value {RAM_s1_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {112};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {2};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {112};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {2};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {2};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {112};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {112};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {112};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {112};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {112};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {2};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {112};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {2};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {61};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};add_instance {RAM_s1_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_ADDR_H} {38};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_ADDR_L} {18};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_DATA_H} {15};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BYTEEN_H} {17};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BYTEEN_L} {16};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {51};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {45};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {39};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_TRANS_WRITE} {41};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {58};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {52};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {61};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {59};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {44};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {63};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {62};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_ST_DATA_W} {94};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_ADDR_H} {56};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_ADDR_L} {36};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_DATA_H} {31};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {35};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {32};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {69};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {63};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {57};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {79};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {77};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {108};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {107};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {62};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {81};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {80};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {109};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {111};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_ST_DATA_W} {112};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {CONSTANT_BURST_SIZE} {0};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {RAM_s1_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {1};add_instance {RAM_s1_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_ADDR_H} {56};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_ADDR_L} {36};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_DATA_H} {31};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BYTEEN_H} {35};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BYTEEN_L} {32};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {69};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {63};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {57};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_TRANS_WRITE} {59};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {76};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {70};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {79};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {77};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {108};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {107};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {62};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {81};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {80};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {109};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {111};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_ST_DATA_W} {112};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_ADDR_H} {38};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_ADDR_L} {18};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_DATA_H} {15};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {17};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {16};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {51};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {45};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {39};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {61};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {59};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {90};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {89};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {44};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {63};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {62};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {91};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {93};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_ST_DATA_W} {94};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {CONSTANT_BURST_SIZE} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {PACKING} {0};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {RAM_s1_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {1};add_instance {admm_solver_0_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {admm_solver_0_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {admm_solver_0_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {admm_solver_0_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {admm_solver_0_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {clk_0_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {clk_0_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {clk_0_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {admm_solver_0_avalon_slave_0_agent.m0} {admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {admm_solver_0_avalon_slave_0_agent.m0/admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {admm_solver_0_avalon_slave_0_agent.m0/admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {admm_solver_0_avalon_slave_0_agent.m0/admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {admm_solver_0_avalon_slave_0_agent.rf_source} {admm_solver_0_avalon_slave_0_agent_rsp_fifo.in} {avalon_streaming};add_connection {admm_solver_0_avalon_slave_0_agent_rsp_fifo.out} {admm_solver_0_avalon_slave_0_agent.rf_sink} {avalon_streaming};add_connection {admm_solver_0_avalon_slave_0_agent.rdata_fifo_src} {admm_solver_0_avalon_slave_0_agent_rdata_fifo.in} {avalon_streaming};add_connection {admm_solver_0_avalon_slave_0_agent_rdata_fifo.out} {admm_solver_0_avalon_slave_0_agent.rdata_fifo_sink} {avalon_streaming};add_connection {RAM_s1_agent.m0} {RAM_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {RAM_s1_agent.m0/RAM_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {RAM_s1_agent.m0/RAM_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {RAM_s1_agent.m0/RAM_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {RAM_s1_agent.rf_source} {RAM_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {RAM_s1_agent_rsp_fifo.out} {RAM_s1_agent.rf_sink} {avalon_streaming};add_connection {RAM_s1_agent.rdata_fifo_src} {RAM_s1_agent_rdata_fifo.in} {avalon_streaming};add_connection {RAM_s1_agent_rdata_fifo.out} {RAM_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {hps_0_h2f_lw_axi_master_agent.write_cp} {router.sink} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_agent.write_cp/router.sink} {qsys_mm.command};add_connection {hps_0_h2f_lw_axi_master_agent.read_cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_agent.read_cp/router_001.sink} {qsys_mm.command};add_connection {admm_solver_0_avalon_slave_0_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {admm_solver_0_avalon_slave_0_agent.rp/router_002.sink} {qsys_mm.response};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {RAM_s1_agent.rp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {RAM_s1_agent.rp/router_003.sink} {qsys_mm.response};add_connection {router.src} {hps_0_h2f_lw_axi_master_wr_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router.src/hps_0_h2f_lw_axi_master_wr_limiter.cmd_sink} {qsys_mm.command};add_connection {hps_0_h2f_lw_axi_master_wr_limiter.cmd_src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_wr_limiter.cmd_src/cmd_demux.sink} {qsys_mm.command};add_connection {rsp_mux.src} {hps_0_h2f_lw_axi_master_wr_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/hps_0_h2f_lw_axi_master_wr_limiter.rsp_sink} {qsys_mm.response};add_connection {hps_0_h2f_lw_axi_master_wr_limiter.rsp_src} {hps_0_h2f_lw_axi_master_agent.write_rp} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_wr_limiter.rsp_src/hps_0_h2f_lw_axi_master_agent.write_rp} {qsys_mm.response};add_connection {router_001.src} {hps_0_h2f_lw_axi_master_rd_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router_001.src/hps_0_h2f_lw_axi_master_rd_limiter.cmd_sink} {qsys_mm.command};add_connection {hps_0_h2f_lw_axi_master_rd_limiter.cmd_src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_rd_limiter.cmd_src/cmd_demux_001.sink} {qsys_mm.command};add_connection {rsp_mux_001.src} {hps_0_h2f_lw_axi_master_rd_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/hps_0_h2f_lw_axi_master_rd_limiter.rsp_sink} {qsys_mm.response};add_connection {hps_0_h2f_lw_axi_master_rd_limiter.rsp_src} {hps_0_h2f_lw_axi_master_agent.read_rp} {avalon_streaming};preview_set_connection_tag {hps_0_h2f_lw_axi_master_rd_limiter.rsp_src/hps_0_h2f_lw_axi_master_agent.read_rp} {qsys_mm.response};add_connection {cmd_mux.src} {admm_solver_0_avalon_slave_0_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/admm_solver_0_avalon_slave_0_burst_adapter.sink0} {qsys_mm.command};add_connection {admm_solver_0_avalon_slave_0_burst_adapter.source0} {admm_solver_0_avalon_slave_0_agent.cp} {avalon_streaming};preview_set_connection_tag {admm_solver_0_avalon_slave_0_burst_adapter.source0/admm_solver_0_avalon_slave_0_agent.cp} {qsys_mm.command};add_connection {RAM_s1_burst_adapter.source0} {RAM_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {RAM_s1_burst_adapter.source0/RAM_s1_agent.cp} {qsys_mm.command};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {cmd_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/cmd_mux_001.sink1} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_001.src1} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src1/rsp_mux_001.sink1} {qsys_mm.response};add_connection {router_003.src} {RAM_s1_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/RAM_s1_rsp_width_adapter.sink} {qsys_mm.response};add_connection {RAM_s1_rsp_width_adapter.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {RAM_s1_rsp_width_adapter.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {cmd_mux_001.src} {RAM_s1_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/RAM_s1_cmd_width_adapter.sink} {qsys_mm.command};add_connection {RAM_s1_cmd_width_adapter.src} {RAM_s1_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {RAM_s1_cmd_width_adapter.src/RAM_s1_burst_adapter.sink0} {qsys_mm.command};add_connection {hps_0_h2f_lw_axi_master_wr_limiter.cmd_valid} {cmd_demux.sink_valid} {avalon_streaming};add_connection {hps_0_h2f_lw_axi_master_rd_limiter.cmd_valid} {cmd_demux_001.sink_valid} {avalon_streaming};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {admm_solver_0_avalon_slave_0_translator.reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_translator.reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {admm_solver_0_avalon_slave_0_agent.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {admm_solver_0_avalon_slave_0_agent_rsp_fifo.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {admm_solver_0_avalon_slave_0_agent_rdata_fifo.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_agent.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_agent_rdata_fifo.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {admm_solver_0_avalon_slave_0_burst_adapter.cr0_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_burst_adapter.cr0_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_rsp_width_adapter.clk_reset} {reset};add_connection {admm_solver_0_reset_reset_bridge.out_reset} {RAM_s1_cmd_width_adapter.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {hps_0_h2f_lw_axi_master_agent.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {hps_0_h2f_lw_axi_master_wr_limiter.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {hps_0_h2f_lw_axi_master_rd_limiter.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_avalon_slave_0_translator.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_translator.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {hps_0_h2f_lw_axi_master_agent.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_avalon_slave_0_agent.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_avalon_slave_0_agent_rsp_fifo.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_avalon_slave_0_agent_rdata_fifo.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_agent.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_agent_rdata_fifo.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {hps_0_h2f_lw_axi_master_wr_limiter.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {hps_0_h2f_lw_axi_master_rd_limiter.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_avalon_slave_0_burst_adapter.cr0} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_burst_adapter.cr0} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_rsp_width_adapter.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {RAM_s1_cmd_width_adapter.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {admm_solver_0_reset_reset_bridge.clk} {clock};add_connection {clk_0_clk_clock_bridge.out_clk} {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.clk} {clock};add_interface {hps_0_h2f_lw_axi_master} {axi} {slave};set_interface_property {hps_0_h2f_lw_axi_master} {EXPORT_OF} {hps_0_h2f_lw_axi_master_agent.altera_axi_slave};add_interface {clk_0_clk} {clock} {slave};set_interface_property {clk_0_clk} {EXPORT_OF} {clk_0_clk_clock_bridge.in_clk};add_interface {admm_solver_0_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {admm_solver_0_reset_reset_bridge_in_reset} {EXPORT_OF} {admm_solver_0_reset_reset_bridge.in_reset};add_interface {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset} {EXPORT_OF} {hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge.in_reset};add_interface {admm_solver_0_avalon_slave_0} {avalon} {master};set_interface_property {admm_solver_0_avalon_slave_0} {EXPORT_OF} {admm_solver_0_avalon_slave_0_translator.avalon_anti_slave_0};add_interface {RAM_s1} {avalon} {master};set_interface_property {RAM_s1} {EXPORT_OF} {RAM_s1_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.RAM.s1} {0};set_module_assignment {interconnect_id.admm_solver_0.avalon_slave_0} {1};set_module_assignment {interconnect_id.hps_0.h2f_lw_axi_master} {0};" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_slave_translator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_slave_agent.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_incr_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_wrap_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_default_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_width_adapter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v"
       type="VERILOG" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v"
       type="VERILOG" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_axi_master_ni/altera_merlin_axi_master_ni_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
  </childSourceFiles>
  <instantiator instantiator="soc_system" as="mm_interconnect_0" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 4 starting:altera_mm_interconnect "submodules/soc_system_mm_interconnect_0"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>30</b> modules, <b>96</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>30</b> modules, <b>96</b> connections]]></message>
   <message level="Debug">Transform: InitialInterconnectTransform</message>
   <message level="Debug" culprit="merlin_initial_interconnect_transform"><![CDATA[After transform: <b>0</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: TerminalIdAssignmentUpdateTransform</message>
   <message level="Debug">Transform: DefaultSlaveTransform</message>
   <message level="Debug">Transform: TranslatorTransform</message>
   <message level="Debug">No Avalon connections, skipping transform </message>
   <message level="Debug">Transform: IDPadTransform</message>
   <message level="Debug">Transform: DomainTransform</message>
   <message level="Debug">Transform: RouterTransform</message>
   <message level="Debug">Transform: TrafficLimiterTransform</message>
   <message level="Debug">Transform: BurstTransform</message>
   <message level="Debug">Transform: TreeTransform</message>
   <message level="Debug">Transform: NetworkToSwitchTransform</message>
   <message level="Debug">Transform: WidthTransform</message>
   <message level="Debug">Transform: RouterTableTransform</message>
   <message level="Debug">Transform: ThreadIDMappingTableTransform</message>
   <message level="Debug">Transform: ClockCrossingTransform</message>
   <message level="Debug">Transform: PipelineTransform</message>
   <message level="Debug">Transform: SpotPipelineTransform</message>
   <message level="Debug">Transform: PerformanceMonitorTransform</message>
   <message level="Debug">Transform: TrafficLimiterUpdateTransform</message>
   <message level="Debug">Transform: InsertClockAndResetBridgesTransform</message>
   <message level="Debug">Transform: InterconnectConnectionsTagger</message>
   <message level="Debug">Transform: HierarchyTransform</message>
   <message level="Debug" culprit="merlin_hierarchy_transform"><![CDATA[After transform: <b>30</b> modules, <b>96</b> connections]]></message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Info" culprit="avalon_st_adapter">Inserting error_adapter: error_adapter_0</message>
   <message level="Debug" culprit="avalon_st_adapter.clk_bridge_0">Timing: ELA:1/0.000s</message>
   <message level="Debug" culprit="avalon_st_adapter.rst_bridge_0">Timing: ELA:2/0.000s/0.001s</message>
   <message level="Debug" culprit="avalon_st_adapter.error_adapter_0">Timing: ELA:1/0.006s</message>
   <message level="Debug" culprit="avalon_st_adapter">Timing: COM:3/0.034s/0.048s</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Info" culprit="avalon_st_adapter_001">Inserting error_adapter: error_adapter_0</message>
   <message level="Debug" culprit="avalon_st_adapter_001.clk_bridge_0">Timing: ELA:1/0.000s</message>
   <message level="Debug" culprit="avalon_st_adapter_001.rst_bridge_0">Timing: ELA:2/0.000s/0.000s</message>
   <message level="Debug" culprit="avalon_st_adapter_001.error_adapter_0">Timing: ELA:1/0.006s</message>
   <message level="Debug" culprit="avalon_st_adapter_001">Timing: COM:3/0.018s/0.029s</message>
   <message
       level="Debug"
       culprit="com_altera_sopcmodel_transforms_avalonst_AvalonStreamingTransform"><![CDATA[After transform: <b>32</b> modules, <b>102</b> connections]]></message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_axi_master_ni</b> "<b>submodules/altera_merlin_axi_master_ni</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/soc_system_mm_interconnect_0_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/soc_system_mm_interconnect_0_router</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/soc_system_mm_interconnect_0_router_002</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/soc_system_mm_interconnect_0_router_003</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_burst_adapter</b> "<b>submodules/altera_merlin_burst_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_cmd_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_cmd_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_cmd_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_rsp_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_rsp_demux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_rsp_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/soc_system_mm_interconnect_0_rsp_mux</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_merlin_width_adapter</b> "<b>submodules/altera_merlin_width_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/soc_system_mm_interconnect_0_avalon_st_adapter</b>"]]></message>
   <message level="Debug" culprit="mm_interconnect_0"><![CDATA["<b>mm_interconnect_0</b>" reuses <b>altera_avalon_st_adapter</b> "<b>submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001</b>"]]></message>
   <message level="Info" culprit="mm_interconnect_0"><![CDATA["<b>soc_system</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 29 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>admm_solver_0_avalon_slave_0_translator</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 27 starting:altera_merlin_axi_master_ni "submodules/altera_merlin_axi_master_ni"</message>
   <message level="Info" culprit="hps_0_h2f_lw_axi_master_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_axi_master_ni</b> "<b>hps_0_h2f_lw_axi_master_agent</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 26 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>admm_solver_0_avalon_slave_0_agent</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 25 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>admm_solver_0_avalon_slave_0_agent_rsp_fifo</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 20 starting:altera_merlin_router "submodules/soc_system_mm_interconnect_0_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 18 starting:altera_merlin_router "submodules/soc_system_mm_interconnect_0_router_002"</message>
   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 17 starting:altera_merlin_router "submodules/soc_system_mm_interconnect_0_router_003"</message>
   <message level="Info" culprit="router_003"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_003</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 16 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"</message>
   <message level="Info" culprit="hps_0_h2f_lw_axi_master_wr_limiter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>hps_0_h2f_lw_axi_master_wr_limiter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
   <message level="Debug" culprit="soc_system">queue size: 14 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_burst_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>admm_solver_0_avalon_slave_0_burst_adapter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
   <message level="Debug" culprit="soc_system">queue size: 12 starting:altera_merlin_demultiplexer "submodules/soc_system_mm_interconnect_0_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 10 starting:altera_merlin_multiplexer "submodules/soc_system_mm_interconnect_0_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 8 starting:altera_merlin_demultiplexer "submodules/soc_system_mm_interconnect_0_rsp_demux"</message>
   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 6 starting:altera_merlin_multiplexer "submodules/soc_system_mm_interconnect_0_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
   <message level="Debug" culprit="soc_system">queue size: 4 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
   <message level="Info" culprit="RAM_s1_rsp_width_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>RAM_s1_rsp_width_adapter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
   <message level="Debug" culprit="soc_system">queue size: 2 starting:altera_avalon_st_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0</b>"]]></message>
   <message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 1 starting:error_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0"</message>
   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 2 starting:altera_avalon_st_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="avalon_st_adapter_001"><![CDATA["<b>avalon_st_adapter_001</b>" reuses <b>error_adapter</b> "<b>submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0</b>"]]></message>
   <message level="Info" culprit="avalon_st_adapter_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_001</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 0 starting:error_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0"</message>
   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_001</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_reset_controller:21.1:ADAPT_RESET_REQUEST=0,MIN_RST_ASSERTION_TIME=3,NUM_RESET_INPUTS=1,OUTPUT_RESET_SYNC_EDGES=deassert,RESET_REQUEST_PRESENT=1,RESET_REQ_EARLY_DSRT_TIME=1,RESET_REQ_WAIT_TIME=1,SYNC_DEPTH=2,USE_RESET_REQUEST_IN0=0,USE_RESET_REQUEST_IN1=0,USE_RESET_REQUEST_IN10=0,USE_RESET_REQUEST_IN11=0,USE_RESET_REQUEST_IN12=0,USE_RESET_REQUEST_IN13=0,USE_RESET_REQUEST_IN14=0,USE_RESET_REQUEST_IN15=0,USE_RESET_REQUEST_IN2=0,USE_RESET_REQUEST_IN3=0,USE_RESET_REQUEST_IN4=0,USE_RESET_REQUEST_IN5=0,USE_RESET_REQUEST_IN6=0,USE_RESET_REQUEST_IN7=0,USE_RESET_REQUEST_IN8=0,USE_RESET_REQUEST_IN9=0,USE_RESET_REQUEST_INPUT=0"
   instancePathKey="soc_system:.:rst_controller"
   kind="altera_reset_controller"
   version="21.1"
   name="altera_reset_controller">
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_reset_controller.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_reset_synchronizer.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_reset_controller.sdc"
       type="SDC"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="soc_system" as="rst_controller,rst_controller_001" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 32 starting:altera_reset_controller "submodules/altera_reset_controller"</message>
   <message level="Info" culprit="rst_controller"><![CDATA["<b>soc_system</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_interface_generator:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=,AC_ROM_MR0_DLL_RESET_MIRR=,AC_ROM_MR0_MIRR=,AC_ROM_MR1=,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=,AC_ROM_MR2_MIRR=,AC_ROM_MR3=,AC_ROM_MR3_MIRR=,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=0,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=0,AFI_BANKADDR_WIDTH=0,AFI_CLK_EN_WIDTH=0,AFI_CLK_PAIR_COUNT=0,AFI_CONTROL_WIDTH=0,AFI_CS_WIDTH=0,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=0,AFI_DQ_WIDTH=0,AFI_ODT_WIDTH=0,AFI_RATE_RATIO=0,AFI_RLAT_WIDTH=0,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=0,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=0,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=0,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=0,AVL_DATA_WIDTH=0,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=2,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=0,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=-1,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=-1,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=0,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=0,CFG_MEM_CLK_ENTRY_CYCLES=0,CFG_PDN_EXIT_CYCLES=0,CFG_PORT_WIDTH_READ_ODT_CHIP=0,CFG_PORT_WIDTH_WRITE_ODT_CHIP=0,CFG_POWER_SAVING_EXIT_CYCLES=0,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=0,CFG_STARVE_LIMIT=0,CFG_TCCD=0,CFG_TCCD_NS=2.5,CFG_TYPE=0,CFG_WRITE_ODT_CHIP=0,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=0,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=0,CTL_ECC_MULTIPLES_40_72=0,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=0,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=0,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=0,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=-1,DELAY_PER_DQS_EN_DCHAIN_TAP=-1,DELAY_PER_OPA_TAP=-1,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=false,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=-1,DQS_IN_DELAY_MAX=-1,DQS_PHASE_SHIFT=9000,DQ_DDR=0,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=true,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=true,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=0,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=-1,IO_OUT1_DELAY_MAX=-1,IO_OUT2_DELAY_MAX=-1,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=6,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=2.5,MEM_CLK_MAX_PS=2500.0,MEM_CLK_NS=0.0,MEM_CLK_PS=0.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=0,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=0,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=0,MEM_IF_ADDR_WIDTH_MIN=10,MEM_IF_BANKADDR_WIDTH=0,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=-1,MEM_IF_CK_WIDTH=0,MEM_IF_CLK_EN_WIDTH=0,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=0,MEM_IF_CONTROL_WIDTH=0,MEM_IF_CS_PER_DIMM=0,MEM_IF_CS_PER_RANK=0,MEM_IF_CS_WIDTH=0,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=0,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=0,MEM_IF_DQ_WIDTH=0,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=0,MEM_IF_ODT_WIDTH=0,MEM_IF_RD_TO_WR_TURNAROUND_OCT=0,MEM_IF_READ_DQS_WIDTH=0,MEM_IF_ROW_ADDR_WIDTH=0,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=0,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=2,MEM_TFAW=0,MEM_TFAW_NS=30.0,MEM_TINIT_CK=499,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=0,MEM_TRAS_NS=35.0,MEM_TRC=0,MEM_TRCD=0,MEM_TRCD_NS=13.75,MEM_TREFI=0,MEM_TREFI_US=7.8,MEM_TRFC=0,MEM_TRFC_NS=260.0,MEM_TRP=0,MEM_TRP_NS=13.75,MEM_TRRD=0,MEM_TRRD_NS=7.7,MEM_TRTP=0,MEM_TRTP_NS=7.5,MEM_TWR=0,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=,MEM_T_RL=0,MEM_T_WL=0,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=6,MR0_BL=2,MR0_BT=0,MR0_CAS_LATENCY=3,MR0_DLL=1,MR0_PD=0,MR0_WR=4,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=1,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=false,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=0,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=0,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=false,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=0,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=0,PLL_ADDR_CMD_CLK_DIV_CACHE=0,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=0.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=0.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=,PLL_ADDR_CMD_CLK_MULT=0,PLL_ADDR_CMD_CLK_MULT_CACHE=0,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=,PLL_AFI_CLK_DIV=0,PLL_AFI_CLK_DIV_CACHE=0,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=0.0,PLL_AFI_CLK_FREQ_CACHE=0.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=,PLL_AFI_CLK_MULT=0,PLL_AFI_CLK_MULT_CACHE=0,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=,PLL_AFI_HALF_CLK_DIV=0,PLL_AFI_HALF_CLK_DIV_CACHE=0,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=0.0,PLL_AFI_HALF_CLK_FREQ_CACHE=0.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=,PLL_AFI_HALF_CLK_MULT=0,PLL_AFI_HALF_CLK_MULT_CACHE=0,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=false,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=false,PLL_MEM_CLK_DIV=0,PLL_MEM_CLK_DIV_CACHE=0,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=0.0,PLL_MEM_CLK_FREQ_CACHE=0.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=,PLL_MEM_CLK_MULT=0,PLL_MEM_CLK_MULT_CACHE=0,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=0,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=0,PLL_WRITE_CLK_DIV_CACHE=0,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=0.0,PLL_WRITE_CLK_FREQ_CACHE=0.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=,PLL_WRITE_CLK_MULT=0,PLL_WRITE_CLK_MULT_CACHE=0,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=0.0,PLL_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_WRITE_CLK_PHASE_PS=0,PLL_WRITE_CLK_PHASE_PS_CACHE=0,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=0,PLL_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=0,RATE=Full,RATE_CACHE=Unknown,RDBUFFER_ADDR_WIDTH=6,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=false,REF_CLK_FREQ_MAX_CACHE=0.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=0.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=,REF_CLK_NS=0.0,REF_CLK_PS=0.0,REGISTER_C2P=false,SCC_DATA_WIDTH=0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=0,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=0.0,TB_MEM_IF_DQ_WIDTH=0,TB_MEM_IF_READ_DQS_WIDTH=0,TB_PLL_DLL_MASTER=true,TB_RATE=,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.05,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.01,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=-0.01,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.0,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.0,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.0,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.0,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=0,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=false,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,device=5CSEMA5F31C6,hps_parameter_map=,ignoreSimulation=false,interfaceDefinition=instances {clocks_resets {entity_name cyclonev_hps_interface_clocks_resets location HPSINTERFACECLOCKSRESETS_X52_Y78_N111 signal_widths {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 1 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 1} signal_terminations {f2h_warm_rst_req_n {0:0 1} f2h_pending_rst_ack {0:0 1} f2h_sdram_ref_clk {} f2h_dbg_rst_req_n {0:0 1} f2h_cold_rst_req_n {0:0 1} f2h_periph_ref_clk {}} parameters {} signal_default_terminations {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 0 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 0}} debug_apb {entity_name cyclonev_hps_interface_dbg_apb location HPSINTERFACEDBGAPB_X52_Y80_N111 signal_widths {DBG_APB_DISABLE 1 P_CLK_EN 1} signal_terminations {DBG_APB_DISABLE {0:0 0} P_CLK_EN {0:0 0}} parameters {} signal_default_terminations {DBG_APB_DISABLE 0 P_CLK_EN 0}} fpga2hps {entity_name cyclonev_hps_interface_fpga2hps location HPSINTERFACEFPGA2HPS_X52_Y45_N111 signal_widths {port_size_config 2} parameters {} signal_terminations {port_size_config {1:0 1}} signal_default_terminations {port_size_config 0}} @orderednames {clocks_resets debug_apb tpiu boot_from_fpga fpga2hps hps2fpga_light_weight hps2fpga f2sdram} boot_from_fpga {entity_name cyclonev_hps_interface_boot_from_fpga location HPSINTERFACEBOOTFROMFPGA_X52_Y74_N111 signal_widths {boot_from_fpga_ready 1 boot_from_fpga_on_failure 1 bsel_en 1 csel_en 1 csel 2 bsel 3} signal_terminations {boot_from_fpga_ready {0:0 0} boot_from_fpga_on_failure {0:0 0} bsel_en {0:0 0} csel_en {0:0 0} csel {1:0 1} bsel {2:0 1}} parameters {} signal_default_terminations {boot_from_fpga_ready 0 boot_from_fpga_on_failure 0 bsel_en 0 csel_en 0 csel 0 bsel 0}} tpiu {entity_name cyclonev_hps_interface_tpiu_trace location HPSINTERFACETPIUTRACE_X52_Y39_N111 signal_widths {traceclk_ctl 1} parameters {} signal_terminations {traceclk_ctl {0:0 1}} signal_default_terminations {traceclk_ctl 1}} f2sdram {entity_name cyclonev_hps_interface_fpga2sdram location HPSINTERFACEFPGA2SDRAM_X52_Y53_N111 signal_widths {cfg_axi_mm_select 6 cfg_wfifo_cport_map 16 cfg_cport_rfifo_map 18 cfg_cport_type 12 cfg_port_width 12 cfg_cport_wfifo_map 18 cfg_rfifo_cport_map 16} parameters {} signal_terminations {cfg_axi_mm_select {5:0 0} cfg_wfifo_cport_map {15:0 0} cfg_cport_rfifo_map {17:0 0} cfg_cport_type {11:0 0} cfg_port_width {11:0 0} cfg_cport_wfifo_map {17:0 0} cfg_rfifo_cport_map {15:0 0}} signal_default_terminations {cfg_axi_mm_select 0 cfg_wfifo_cport_map 0 cfg_cport_rfifo_map 0 cfg_cport_type 0 cfg_port_width 0 cfg_cport_wfifo_map 0 cfg_rfifo_cport_map 0}} hps2fpga_light_weight {entity_name cyclonev_hps_interface_hps2fpga_light_weight location HPSINTERFACEHPS2FPGALIGHTWEIGHT_X52_Y43_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps2fpga {entity_name cyclonev_hps_interface_hps2fpga location HPSINTERFACEHPS2FPGA_X52_Y47_N111 signal_widths {port_size_config 2} parameters {} signal_terminations {port_size_config {1:0 1}} signal_default_terminations {port_size_config 0}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{create_clock -period 10.0 [get_pins -compatibility_mode *|fpga_interfaces|clocks_resets|h2f_user1_clk]}} properties {} bfm_types {} intermediate_wire_count 0 wires_to_fragments {} interfaces {@orderednames {h2f_reset h2f_user1_clock f2h_axi_clock f2h_axi_slave h2f_lw_axi_clock h2f_lw_axi_master h2f_axi_clock h2f_axi_master} h2f_reset {properties {associatedResetSinks none synchronousEdges none} type reset direction Output signals {@orderednames h2f_rst_n h2f_rst_n {fragments {} properties {} internal_name h2f_rst_n width 1 instance_name clocks_resets direction Output role reset_n}}} h2f_user1_clock {properties {clockRate 100000000.0 clockRateKnown true} type clock direction Output signals {@orderednames h2f_user1_clk h2f_user1_clk {fragments {} properties {} internal_name h2f_user1_clk width 1 instance_name clocks_resets direction Output role clk}}} f2h_axi_clock {properties {} type clock direction Input signals {@orderednames f2h_axi_clk f2h_axi_clk {fragments {} properties {} internal_name clk width 1 instance_name fpga2hps direction Input role clk}}} f2h_axi_slave {data_width 64 properties {readDataReorderingDepth 16 associatedClock f2h_axi_clock associatedReset h2f_reset writeAcceptanceCapability 8 readAcceptanceCapability 8 combinedAcceptanceCapability 16} type axi address_width 32 direction slave signals {@orderednames {f2h_AWID f2h_AWADDR f2h_AWLEN f2h_AWSIZE f2h_AWBURST f2h_AWLOCK f2h_AWCACHE f2h_AWPROT f2h_AWVALID f2h_AWREADY f2h_AWUSER f2h_WID f2h_WDATA f2h_WSTRB f2h_WLAST f2h_WVALID f2h_WREADY f2h_BID f2h_BRESP f2h_BVALID f2h_BREADY f2h_ARID f2h_ARADDR f2h_ARLEN f2h_ARSIZE f2h_ARBURST f2h_ARLOCK f2h_ARCACHE f2h_ARPROT f2h_ARVALID f2h_ARREADY f2h_ARUSER f2h_RID f2h_RDATA f2h_RRESP f2h_RLAST f2h_RVALID f2h_RREADY} f2h_AWID {fragments {} properties {} internal_name awid width 8 instance_name fpga2hps direction Input role awid} f2h_AWADDR {fragments {} properties {} internal_name awaddr width 32 instance_name fpga2hps direction Input role awaddr} f2h_AWLEN {fragments {} properties {} internal_name awlen width 4 instance_name fpga2hps direction Input role awlen} f2h_AWSIZE {fragments {} properties {} internal_name awsize width 3 instance_name fpga2hps direction Input role awsize} f2h_AWBURST {fragments {} properties {} internal_name awburst width 2 instance_name fpga2hps direction Input role awburst} f2h_AWLOCK {fragments {} properties {} internal_name awlock width 2 instance_name fpga2hps direction Input role awlock} f2h_AWCACHE {fragments {} properties {} internal_name awcache width 4 instance_name fpga2hps direction Input role awcache} f2h_AWPROT {fragments {} properties {} internal_name awprot width 3 instance_name fpga2hps direction Input role awprot} f2h_AWVALID {fragments {} properties {} internal_name awvalid width 1 instance_name fpga2hps direction Input role awvalid} f2h_AWREADY {fragments {} properties {} internal_name awready width 1 instance_name fpga2hps direction Output role awready} f2h_AWUSER {fragments {} properties {} internal_name awuser width 5 instance_name fpga2hps direction Input role awuser} f2h_WID {fragments {} properties {} internal_name wid width 8 instance_name fpga2hps direction Input role wid} f2h_WDATA {fragments {} properties {} internal_name wdata width 64 instance_name fpga2hps direction Input role wdata} f2h_WSTRB {fragments {} properties {} internal_name wstrb width 8 instance_name fpga2hps direction Input role wstrb} f2h_WLAST {fragments {} properties {} internal_name wlast width 1 instance_name fpga2hps direction Input role wlast} f2h_WVALID {fragments {} properties {} internal_name wvalid width 1 instance_name fpga2hps direction Input role wvalid} f2h_WREADY {fragments {} properties {} internal_name wready width 1 instance_name fpga2hps direction Output role wready} f2h_BID {fragments {} properties {} internal_name bid width 8 instance_name fpga2hps direction Output role bid} f2h_BRESP {fragments {} properties {} internal_name bresp width 2 instance_name fpga2hps direction Output role bresp} f2h_BVALID {fragments {} properties {} internal_name bvalid width 1 instance_name fpga2hps direction Output role bvalid} f2h_BREADY {fragments {} properties {} internal_name bready width 1 instance_name fpga2hps direction Input role bready} f2h_ARID {fragments {} properties {} internal_name arid width 8 instance_name fpga2hps direction Input role arid} f2h_ARADDR {fragments {} properties {} internal_name araddr width 32 instance_name fpga2hps direction Input role araddr} f2h_ARLEN {fragments {} properties {} internal_name arlen width 4 instance_name fpga2hps direction Input role arlen} f2h_ARSIZE {fragments {} properties {} internal_name arsize width 3 instance_name fpga2hps direction Input role arsize} f2h_ARBURST {fragments {} properties {} internal_name arburst width 2 instance_name fpga2hps direction Input role arburst} f2h_ARLOCK {fragments {} properties {} internal_name arlock width 2 instance_name fpga2hps direction Input role arlock} f2h_ARCACHE {fragments {} properties {} internal_name arcache width 4 instance_name fpga2hps direction Input role arcache} f2h_ARPROT {fragments {} properties {} internal_name arprot width 3 instance_name fpga2hps direction Input role arprot} f2h_ARVALID {fragments {} properties {} internal_name arvalid width 1 instance_name fpga2hps direction Input role arvalid} f2h_ARREADY {fragments {} properties {} internal_name arready width 1 instance_name fpga2hps direction Output role arready} f2h_ARUSER {fragments {} properties {} internal_name aruser width 5 instance_name fpga2hps direction Input role aruser} f2h_RID {fragments {} properties {} internal_name rid width 8 instance_name fpga2hps direction Output role rid} f2h_RDATA {fragments {} properties {} internal_name rdata width 64 instance_name fpga2hps direction Output role rdata} f2h_RRESP {fragments {} properties {} internal_name rresp width 2 instance_name fpga2hps direction Output role rresp} f2h_RLAST {fragments {} properties {} internal_name rlast width 1 instance_name fpga2hps direction Output role rlast} f2h_RVALID {fragments {} properties {} internal_name rvalid width 1 instance_name fpga2hps direction Output role rvalid} f2h_RREADY {fragments {} properties {} internal_name rready width 1 instance_name fpga2hps direction Input role rready}}} h2f_lw_axi_clock {properties {} type clock direction Input signals {@orderednames h2f_lw_axi_clk h2f_lw_axi_clk {fragments {} properties {} internal_name clk width 1 instance_name hps2fpga_light_weight direction Input role clk}}} h2f_lw_axi_master {id_width 12 data_width 32 properties {associatedClock h2f_lw_axi_clock associatedReset h2f_reset writeIssuingCapability 8 readIssuingCapability 8 combinedIssuingCapability 16} type axi address_width 21 direction master signals {@orderednames {h2f_lw_AWID h2f_lw_AWADDR h2f_lw_AWLEN h2f_lw_AWSIZE h2f_lw_AWBURST h2f_lw_AWLOCK h2f_lw_AWCACHE h2f_lw_AWPROT h2f_lw_AWVALID h2f_lw_AWREADY h2f_lw_WID h2f_lw_WDATA h2f_lw_WSTRB h2f_lw_WLAST h2f_lw_WVALID h2f_lw_WREADY h2f_lw_BID h2f_lw_BRESP h2f_lw_BVALID h2f_lw_BREADY h2f_lw_ARID h2f_lw_ARADDR h2f_lw_ARLEN h2f_lw_ARSIZE h2f_lw_ARBURST h2f_lw_ARLOCK h2f_lw_ARCACHE h2f_lw_ARPROT h2f_lw_ARVALID h2f_lw_ARREADY h2f_lw_RID h2f_lw_RDATA h2f_lw_RRESP h2f_lw_RLAST h2f_lw_RVALID h2f_lw_RREADY} h2f_lw_AWID {fragments {} properties {} internal_name awid width 12 instance_name hps2fpga_light_weight direction Output role awid} h2f_lw_AWADDR {fragments {} properties {} internal_name awaddr width 21 instance_name hps2fpga_light_weight direction Output role awaddr} h2f_lw_AWLEN {fragments {} properties {} internal_name awlen width 4 instance_name hps2fpga_light_weight direction Output role awlen} h2f_lw_AWSIZE {fragments {} properties {} internal_name awsize width 3 instance_name hps2fpga_light_weight direction Output role awsize} h2f_lw_AWBURST {fragments {} properties {} internal_name awburst width 2 instance_name hps2fpga_light_weight direction Output role awburst} h2f_lw_AWLOCK {fragments {} properties {} internal_name awlock width 2 instance_name hps2fpga_light_weight direction Output role awlock} h2f_lw_AWCACHE {fragments {} properties {} internal_name awcache width 4 instance_name hps2fpga_light_weight direction Output role awcache} h2f_lw_AWPROT {fragments {} properties {} internal_name awprot width 3 instance_name hps2fpga_light_weight direction Output role awprot} h2f_lw_AWVALID {fragments {} properties {} internal_name awvalid width 1 instance_name hps2fpga_light_weight direction Output role awvalid} h2f_lw_AWREADY {fragments {} properties {} internal_name awready width 1 instance_name hps2fpga_light_weight direction Input role awready} h2f_lw_WID {fragments {} properties {} internal_name wid width 12 instance_name hps2fpga_light_weight direction Output role wid} h2f_lw_WDATA {fragments {} properties {} internal_name wdata width 32 instance_name hps2fpga_light_weight direction Output role wdata} h2f_lw_WSTRB {fragments {} properties {} internal_name wstrb width 4 instance_name hps2fpga_light_weight direction Output role wstrb} h2f_lw_WLAST {fragments {} properties {} internal_name wlast width 1 instance_name hps2fpga_light_weight direction Output role wlast} h2f_lw_WVALID {fragments {} properties {} internal_name wvalid width 1 instance_name hps2fpga_light_weight direction Output role wvalid} h2f_lw_WREADY {fragments {} properties {} internal_name wready width 1 instance_name hps2fpga_light_weight direction Input role wready} h2f_lw_BID {fragments {} properties {} internal_name bid width 12 instance_name hps2fpga_light_weight direction Input role bid} h2f_lw_BRESP {fragments {} properties {} internal_name bresp width 2 instance_name hps2fpga_light_weight direction Input role bresp} h2f_lw_BVALID {fragments {} properties {} internal_name bvalid width 1 instance_name hps2fpga_light_weight direction Input role bvalid} h2f_lw_BREADY {fragments {} properties {} internal_name bready width 1 instance_name hps2fpga_light_weight direction Output role bready} h2f_lw_ARID {fragments {} properties {} internal_name arid width 12 instance_name hps2fpga_light_weight direction Output role arid} h2f_lw_ARADDR {fragments {} properties {} internal_name araddr width 21 instance_name hps2fpga_light_weight direction Output role araddr} h2f_lw_ARLEN {fragments {} properties {} internal_name arlen width 4 instance_name hps2fpga_light_weight direction Output role arlen} h2f_lw_ARSIZE {fragments {} properties {} internal_name arsize width 3 instance_name hps2fpga_light_weight direction Output role arsize} h2f_lw_ARBURST {fragments {} properties {} internal_name arburst width 2 instance_name hps2fpga_light_weight direction Output role arburst} h2f_lw_ARLOCK {fragments {} properties {} internal_name arlock width 2 instance_name hps2fpga_light_weight direction Output role arlock} h2f_lw_ARCACHE {fragments {} properties {} internal_name arcache width 4 instance_name hps2fpga_light_weight direction Output role arcache} h2f_lw_ARPROT {fragments {} properties {} internal_name arprot width 3 instance_name hps2fpga_light_weight direction Output role arprot} h2f_lw_ARVALID {fragments {} properties {} internal_name arvalid width 1 instance_name hps2fpga_light_weight direction Output role arvalid} h2f_lw_ARREADY {fragments {} properties {} internal_name arready width 1 instance_name hps2fpga_light_weight direction Input role arready} h2f_lw_RID {fragments {} properties {} internal_name rid width 12 instance_name hps2fpga_light_weight direction Input role rid} h2f_lw_RDATA {fragments {} properties {} internal_name rdata width 32 instance_name hps2fpga_light_weight direction Input role rdata} h2f_lw_RRESP {fragments {} properties {} internal_name rresp width 2 instance_name hps2fpga_light_weight direction Input role rresp} h2f_lw_RLAST {fragments {} properties {} internal_name rlast width 1 instance_name hps2fpga_light_weight direction Input role rlast} h2f_lw_RVALID {fragments {} properties {} internal_name rvalid width 1 instance_name hps2fpga_light_weight direction Input role rvalid} h2f_lw_RREADY {fragments {} properties {} internal_name rready width 1 instance_name hps2fpga_light_weight direction Output role rready}}} h2f_axi_clock {properties {} type clock direction Input signals {@orderednames h2f_axi_clk h2f_axi_clk {fragments {} properties {} internal_name clk width 1 instance_name hps2fpga direction Input role clk}}} h2f_axi_master {id_width 12 data_width 64 properties {associatedClock h2f_axi_clock associatedReset h2f_reset writeIssuingCapability 8 readIssuingCapability 8 combinedIssuingCapability 16} type axi address_width 30 direction master signals {@orderednames {h2f_AWID h2f_AWADDR h2f_AWLEN h2f_AWSIZE h2f_AWBURST h2f_AWLOCK h2f_AWCACHE h2f_AWPROT h2f_AWVALID h2f_AWREADY h2f_WID h2f_WDATA h2f_WSTRB h2f_WLAST h2f_WVALID h2f_WREADY h2f_BID h2f_BRESP h2f_BVALID h2f_BREADY h2f_ARID h2f_ARADDR h2f_ARLEN h2f_ARSIZE h2f_ARBURST h2f_ARLOCK h2f_ARCACHE h2f_ARPROT h2f_ARVALID h2f_ARREADY h2f_RID h2f_RDATA h2f_RRESP h2f_RLAST h2f_RVALID h2f_RREADY} h2f_AWID {fragments {} properties {} internal_name awid width 12 instance_name hps2fpga direction Output role awid} h2f_AWADDR {fragments {} properties {} internal_name awaddr width 30 instance_name hps2fpga direction Output role awaddr} h2f_AWLEN {fragments {} properties {} internal_name awlen width 4 instance_name hps2fpga direction Output role awlen} h2f_AWSIZE {fragments {} properties {} internal_name awsize width 3 instance_name hps2fpga direction Output role awsize} h2f_AWBURST {fragments {} properties {} internal_name awburst width 2 instance_name hps2fpga direction Output role awburst} h2f_AWLOCK {fragments {} properties {} internal_name awlock width 2 instance_name hps2fpga direction Output role awlock} h2f_AWCACHE {fragments {} properties {} internal_name awcache width 4 instance_name hps2fpga direction Output role awcache} h2f_AWPROT {fragments {} properties {} internal_name awprot width 3 instance_name hps2fpga direction Output role awprot} h2f_AWVALID {fragments {} properties {} internal_name awvalid width 1 instance_name hps2fpga direction Output role awvalid} h2f_AWREADY {fragments {} properties {} internal_name awready width 1 instance_name hps2fpga direction Input role awready} h2f_WID {fragments {} properties {} internal_name wid width 12 instance_name hps2fpga direction Output role wid} h2f_WDATA {fragments {} properties {} internal_name wdata width 64 instance_name hps2fpga direction Output role wdata} h2f_WSTRB {fragments {} properties {} internal_name wstrb width 8 instance_name hps2fpga direction Output role wstrb} h2f_WLAST {fragments {} properties {} internal_name wlast width 1 instance_name hps2fpga direction Output role wlast} h2f_WVALID {fragments {} properties {} internal_name wvalid width 1 instance_name hps2fpga direction Output role wvalid} h2f_WREADY {fragments {} properties {} internal_name wready width 1 instance_name hps2fpga direction Input role wready} h2f_BID {fragments {} properties {} internal_name bid width 12 instance_name hps2fpga direction Input role bid} h2f_BRESP {fragments {} properties {} internal_name bresp width 2 instance_name hps2fpga direction Input role bresp} h2f_BVALID {fragments {} properties {} internal_name bvalid width 1 instance_name hps2fpga direction Input role bvalid} h2f_BREADY {fragments {} properties {} internal_name bready width 1 instance_name hps2fpga direction Output role bready} h2f_ARID {fragments {} properties {} internal_name arid width 12 instance_name hps2fpga direction Output role arid} h2f_ARADDR {fragments {} properties {} internal_name araddr width 30 instance_name hps2fpga direction Output role araddr} h2f_ARLEN {fragments {} properties {} internal_name arlen width 4 instance_name hps2fpga direction Output role arlen} h2f_ARSIZE {fragments {} properties {} internal_name arsize width 3 instance_name hps2fpga direction Output role arsize} h2f_ARBURST {fragments {} properties {} internal_name arburst width 2 instance_name hps2fpga direction Output role arburst} h2f_ARLOCK {fragments {} properties {} internal_name arlock width 2 instance_name hps2fpga direction Output role arlock} h2f_ARCACHE {fragments {} properties {} internal_name arcache width 4 instance_name hps2fpga direction Output role arcache} h2f_ARPROT {fragments {} properties {} internal_name arprot width 3 instance_name hps2fpga direction Output role arprot} h2f_ARVALID {fragments {} properties {} internal_name arvalid width 1 instance_name hps2fpga direction Output role arvalid} h2f_ARREADY {fragments {} properties {} internal_name arready width 1 instance_name hps2fpga direction Input role arready} h2f_RID {fragments {} properties {} internal_name rid width 12 instance_name hps2fpga direction Input role rid} h2f_RDATA {fragments {} properties {} internal_name rdata width 64 instance_name hps2fpga direction Input role rdata} h2f_RRESP {fragments {} properties {} internal_name rresp width 2 instance_name hps2fpga direction Input role rresp} h2f_RLAST {fragments {} properties {} internal_name rlast width 1 instance_name hps2fpga direction Input role rlast} h2f_RVALID {fragments {} properties {} internal_name rvalid width 1 instance_name hps2fpga direction Input role rvalid} h2f_RREADY {fragments {} properties {} internal_name rready width 1 instance_name hps2fpga direction Output role rready}}}} raw_assign_sim_style {},qipEntries="
   instancePathKey="soc_system:.:hps_0:.:fpga_interfaces"
   kind="altera_interface_generator"
   version="21.1"
   name="soc_system_hps_0_fpga_interfaces">
  <parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
  <parameter name="VECT_ATTR_COUNTER_ZERO_MATCH" value="0" />
  <parameter name="ENUM_GANGED_ARF" value="DISABLED" />
  <parameter name="LRDIMM_INT" value="0" />
  <parameter name="ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
  <parameter name="MAX_LATENCY_COUNT_WIDTH" value="6" />
  <parameter name="MEM_IF_ADDR_WIDTH_MIN" value="10" />
  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="0" />
  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
  <parameter name="MEM_LEVELING" value="true" />
  <parameter name="CV_ENUM_PRIORITY_1_0" value="WEIGHT_0" />
  <parameter name="ENUM_MEM_IF_TRRD" value="TRRD_4" />
  <parameter name="CV_ENUM_PRIORITY_1_2" value="WEIGHT_0" />
  <parameter name="ENUM_ATTR_COUNTER_ZERO_RESET" value="DISABLED" />
  <parameter name="CV_ENUM_PRIORITY_1_1" value="WEIGHT_0" />
  <parameter name="PLL_AFI_HALF_CLK_DIV" value="0" />
  <parameter name="MEM_ADD_LAT" value="0" />
  <parameter name="CV_ENUM_PRIORITY_1_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_1_3" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR" value="0" />
  <parameter name="CV_ENUM_PRIORITY_1_5" value="WEIGHT_0" />
  <parameter name="ignoreSimulation" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT" value="0" />
  <parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
  <parameter name="ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
  <parameter name="INTG_MEM_IF_TRFC" value="34" />
  <parameter name="MEM_REGDIMM_ENABLED" value="false" />
  <parameter name="PLL_HR_CLK_FREQ" value="0.0" />
  <parameter name="AFI_DQ_WIDTH" value="0" />
  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
  <parameter name="AP_MODE_EN" value="0" />
  <parameter name="ENUM_CPORT5_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CALIB_LFIFO_OFFSET" value="-1" />
  <parameter name="INTG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="ENUM_CPORT2_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="VECT_ATTR_COUNTER_ZERO_MASK" value="0" />
  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ALLOCATED_WFIFO_PORT" value="0,None,None,None,None,None" />
  <parameter name="MEM_TRAS_NS" value="35.0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
  <parameter name="IO_DQ_OUT_RESERVE" value="0" />
  <parameter name="IO_DM_OUT_RESERVE" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="CV_ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
  <parameter name="INTG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="DELAY_PER_OPA_TAP" value="-1" />
  <parameter name="INTG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="ENABLE_BONDING" value="false" />
  <parameter name="HHP_HPS_VERIFICATION" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC" value="0" />
  <parameter name="CV_ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP" value="0" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="CV_ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_ENABLE_INTR" value="DISABLED" />
  <parameter name="INTG_MEM_AUTO_PD_CYCLES" value="0" />
  <parameter name="AVL_DATA_WIDTH" value="0" />
  <parameter name="PLL_AFI_CLK_MULT_CACHE" value="0" />
  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
  <parameter name="MR1_RDQS" value="0" />
  <parameter name="ENUM_MEM_IF_ROWADDR_WIDTH" value="ADDR_WIDTH_16" />
  <parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
  <parameter name="MR0_PD" value="0" />
  <parameter name="MEM_VENDOR" value="JEDEC" />
  <parameter name="MEM_IF_CS_PER_RANK" value="0" />
  <parameter name="CV_PORT_1_CONNECT_TO_AV_PORT" value="1" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
  <parameter name="CV_ENUM_CPORT1_TYPE" value="DISABLE" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="" />
  <parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
  <parameter name="USE_MEM_CLK_FREQ" value="false" />
  <parameter name="CV_MSB_WFIFO_PORT_5" value="5" />
  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
  <parameter name="CFG_READ_ODT_CHIP" value="0" />
  <parameter name="CV_MSB_WFIFO_PORT_4" value="5" />
  <parameter name="CV_MSB_WFIFO_PORT_3" value="5" />
  <parameter name="IO_DQS_EN_PHASE_MAX" value="0" />
  <parameter name="RDIMM" value="false" />
  <parameter name="ENUM_MEM_IF_COLADDR_WIDTH" value="ADDR_WIDTH_12" />
  <parameter name="PLL_CONFIG_CLK_FREQ" value="0.0" />
  <parameter name="ENABLE_USER_ECC" value="false" />
  <parameter name="PLL_PHASE_COUNTER_WIDTH" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD" value="0" />
  <parameter name="MEM_TRC" value="0" />
  <parameter name="AVL_ADDR_WIDTH_PORT_2" value="0" />
  <parameter name="ENUM_PRIORITY_6_4" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID" value="0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_3" value="USE_NO" />
  <parameter name="AVL_ADDR_WIDTH_PORT_1" value="0" />
  <parameter name="ENUM_PRIORITY_6_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_2" value="USE_NO" />
  <parameter name="AVL_ADDR_WIDTH_PORT_0" value="0" />
  <parameter name="ENUM_PRIORITY_6_2" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_5" value="USE_NO" />
  <parameter name="ENUM_PRIORITY_6_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_4" value="USE_NO" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_PRIORITY_6_0" value="WEIGHT_0" />
  <parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
  <parameter name="AFI_CS_WIDTH" value="0" />
  <parameter name="AVL_ADDR_WIDTH_PORT_5" value="0" />
  <parameter name="ENUM_PRIORITY_6_1" value="WEIGHT_0" />
  <parameter name="AVL_ADDR_WIDTH_PORT_4" value="0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_1" value="USE_NO" />
  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
  <parameter name="AVL_ADDR_WIDTH_PORT_3" value="0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_0" value="USE_NO" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="CV_MSB_WFIFO_PORT_2" value="5" />
  <parameter name="CV_MSB_WFIFO_PORT_1" value="5" />
  <parameter name="PLL_NIOS_CLK_MULT" value="0" />
  <parameter name="ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_MSB_WFIFO_PORT_0" value="5" />
  <parameter name="TG_TEMP_PORT_5" value="0" />
  <parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
  <parameter name="TG_TEMP_PORT_3" value="0" />
  <parameter name="TG_TEMP_PORT_4" value="0" />
  <parameter name="TG_TEMP_PORT_1" value="0" />
  <parameter name="TG_TEMP_PORT_2" value="0" />
  <parameter name="MEM_CLK_NS" value="0.0" />
  <parameter name="TG_TEMP_PORT_0" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
  <parameter name="ENUM_MEM_IF_BURSTLENGTH" value="MEM_IF_BURSTLENGTH_8" />
  <parameter name="PLL_AFI_CLK_MULT" value="0" />
  <parameter name="SKIP_MEM_INIT" value="true" />
  <parameter name="CFG_ENABLE_NO_DM" value="0" />
  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
  <parameter name="MR1_TDQS" value="0" />
  <parameter name="INTG_MEM_CLK_ENTRY_CYCLES" value="10" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
  <parameter name="CTL_ECC_MULTIPLES_16_24_40_72" value="0" />
  <parameter name="CV_ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="ENUM_MEM_IF_TCWL" value="TCWL_5" />
  <parameter name="DEVICE_FAMILY" value="" />
  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
  <parameter name="DEVICE_FAMILY_PARAM" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID" value="0" />
  <parameter name="ENUM_MEM_IF_TRTP" value="TRTP_4" />
  <parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="INTG_POWER_SAVING_EXIT_CYCLES" value="5" />
  <parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="-1" />
  <parameter name="MEM_IF_ADDR_WIDTH" value="0" />
  <parameter name="PLL_DR_CLK_DIV" value="0" />
  <parameter name="USE_SEQUENCER_BFM" value="false" />
  <parameter name="DELAY_PER_DCHAIN_TAP" value="-1" />
  <parameter name="CSR_ADDR_WIDTH" value="8" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID" value="0" />
  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
  <parameter name="CV_ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="CV_ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="RDIMM_INT" value="0" />
  <parameter name="CV_ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="CTL_CSR_READ_ONLY" value="1" />
  <parameter name="ENUM_MASK_DBE_INTR" value="DISABLED" />
  <parameter name="CV_ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="CV_ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
  <parameter name="CV_ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="READ_VALID_FIFO_SIZE" value="16" />
  <parameter name="DLL_MASTER" value="false" />
  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="AC_ROM_MR0_MIRR" value="" />
  <parameter name="MEM_TWTR" value="4" />
  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
  <parameter name="ENUM_ENABLE_BURST_INTERRUPT" value="DISABLED" />
  <parameter name="CV_ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="WEIGHT_PORT_2" value="0" />
  <parameter name="WEIGHT_PORT_1" value="0" />
  <parameter name="WEIGHT_PORT_0" value="0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="Unknown" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="WEIGHT_PORT_5" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="" />
  <parameter name="WEIGHT_PORT_4" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
  <parameter name="WEIGHT_PORT_3" value="0" />
  <parameter name="ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_2" value="DISABLED" />
  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
  <parameter name="CV_ENUM_ENABLE_BONDING_3" value="DISABLED" />
  <parameter name="MEM_TRFC_NS" value="260.0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_4" value="DISABLED" />
  <parameter name="CV_ENUM_ENABLE_BONDING_5" value="DISABLED" />
  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="ENABLE_ISS_PROBES" value="false" />
  <parameter name="MR2_RTT_WR" value="1" />
  <parameter name="ENUM_MEM_IF_TFAW" value="TFAW_16" />
  <parameter name="TIMING_BOARD_TDS_APPLIED" value="0.0" />
  <parameter name="AFI_ODT_WIDTH" value="0" />
  <parameter name="PLL_MASTER" value="false" />
  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_0" value="DISABLED" />
  <parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_1" value="DISABLED" />
  <parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="DISCRETE_FLY_BY" value="true" />
  <parameter name="QVLD_WR_ADDRESS_OFFSET" value="0" />
  <parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="0" />
  <parameter name="AVL_SYMBOL_WIDTH" value="8" />
  <parameter name="TB_PLL_DLL_MASTER" value="true" />
  <parameter name="MEM_IF_DM_WIDTH" value="0" />
  <parameter name="LOCAL_CS_WIDTH" value="0" />
  <parameter name="CTL_ECC_ENABLED" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="AUTO_POWERDN_EN" value="false" />
  <parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
  <parameter name="PHY_CLKBUF" value="false" />
  <parameter name="ENABLE_ABS_RAM_INTERNAL" value="false" />
  <parameter name="MAX_PENDING_WR_CMD" value="16" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_ATTR_COUNTER_ONE_RESET" value="DISABLED" />
  <parameter name="ENUM_WRITE_ODT_CHIP" value="ODT_DISABLED" />
  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
  <parameter name="MEM_IF_CHIP_BITS" value="-1" />
  <parameter name="ENUM_MEM_IF_CS_PER_RANK" value="MEM_IF_CS_PER_RANK_1" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MEM_IF_CK_WIDTH" value="0" />
  <parameter name="MEM_TCL" value="11" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="0" />
  <parameter name="ENUM_LOCAL_IF_CS_WIDTH" value="ADDR_WIDTH_2" />
  <parameter name="TIMING_TDQSCK" value="255" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="CTL_USR_REFRESH_EN" value="false" />
  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
  <parameter name="ENUM_WR_FIFO_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_WR_FIFO_IN_USE_2" value="FALSE" />
  <parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP" value="0" />
  <parameter name="ENUM_WR_FIFO_IN_USE_1" value="FALSE" />
  <parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_WR_FIFO_IN_USE_0" value="FALSE" />
  <parameter name="ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="AFI_RATE_RATIO" value="0" />
  <parameter name="ENUM_THLD_JAR2_3" value="THRESHOLD_16" />
  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
  <parameter name="ENUM_THLD_JAR2_4" value="THRESHOLD_16" />
  <parameter name="ENUM_THLD_JAR2_5" value="THRESHOLD_16" />
  <parameter name="AV_PORT_0_CONNECT_TO_CV_PORT" value="0" />
  <parameter name="PLL_MEM_CLK_DIV_CACHE" value="0" />
  <parameter name="ENUM_CTL_ECC_RMW_ENABLED" value="CTL_ECC_RMW_DISABLED" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="0" />
  <parameter name="CFG_TCCD_NS" value="2.5" />
  <parameter name="IO_DQS_IN_RESERVE" value="3" />
  <parameter name="AVL_NUM_SYMBOLS" value="2" />
  <parameter name="ENABLE_NIOS_OCI" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="FIX_READ_LATENCY" value="8" />
  <parameter name="CTL_OUTPUT_REGD" value="false" />
  <parameter name="CV_PORT_0_CONNECT_TO_AV_PORT" value="0" />
  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
  <parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
  <parameter name="CTL_CSR_ENABLED" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH" value="0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PHY_CSR_ENABLED" value="false" />
  <parameter name="DQ_DDR" value="0" />
  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_WRITE_CLK_PHASE_DEG" value="0.0" />
  <parameter name="MEM_INIT_FILE" value="" />
  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
  <parameter name="AVL_PORT" value="" />
  <parameter name="TB_RATE" value="" />
  <parameter name="REF_CLK_FREQ_CACHE_VALID" value="false" />
  <parameter name="ALLOCATED_RFIFO_PORT" value="0,None,None,None,None,None" />
  <parameter name="MEM_CK_WIDTH" value="1" />
  <parameter name="MEM_ATCL" value="Disabled" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="AC_ROM_MR0_DLL_RESET" value="" />
  <parameter name="MEM_TDQSCK" value="2" />
  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
  <parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD" value="0" />
  <parameter name="MEM_WTCL" value="8" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP" value="0" />
  <parameter name="CV_ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_MEM_CLK_MULT" value="0" />
  <parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="MEM_IF_CS_PER_DIMM" value="0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="" />
  <parameter name="CTL_ECC_CSR_ENABLED" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP" value="0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
  <parameter name="MEM_AUTO_PD_CYCLES" value="0" />
  <parameter name="CV_ENUM_CPORT3_TYPE" value="DISABLE" />
  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
  <parameter name="PLL_WRITE_CLK_DIV" value="0" />
  <parameter name="CALIB_VFIFO_OFFSET" value="-1" />
  <parameter name="CTL_ECC_MULTIPLES_40_72" value="0" />
  <parameter name="MSB_RFIFO_PORT_2" value="5" />
  <parameter name="MSB_RFIFO_PORT_3" value="5" />
  <parameter name="MSB_RFIFO_PORT_4" value="5" />
  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
  <parameter name="MSB_RFIFO_PORT_5" value="5" />
  <parameter name="CV_ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
  <parameter name="MEM_DRV_STR" value="RZQ/7" />
  <parameter name="MEM_TREFI" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="NUM_SUBGROUP_PER_READ_DQS" value="0" />
  <parameter name="TIMING_BOARD_AC_SKEW" value="0.03" />
  <parameter name="MSB_RFIFO_PORT_0" value="5" />
  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="MEM_TRP_NS" value="13.75" />
  <parameter name="MSB_RFIFO_PORT_1" value="5" />
  <parameter name="QVLD_EXTRA_FLOP_STAGES" value="0" />
  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="CTL_HRB_ENABLED" value="false" />
  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
  <parameter name="PLL_WRITE_CLK_FREQ" value="0.0" />
  <parameter name="EXTRA_SETTINGS" value="" />
  <parameter name="ENUM_MMR_CFG_MEM_BL" value="MP_BL_8" />
  <parameter name="PLL_DR_CLK_FREQ_STR" value="" />
  <parameter name="MEM_IF_CS_WIDTH" value="0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_1" value="USE_NO" />
  <parameter name="STARVE_LIMIT" value="10" />
  <parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_2" value="USE_NO" />
  <parameter name="CV_ENUM_WR_PORT_INFO_3" value="USE_NO" />
  <parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP" value="0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_4" value="USE_NO" />
  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_0" value="USE_NO" />
  <parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="false" />
  <parameter name="SEQUENCER_TYPE_CACHE" value="Unknown" />
  <parameter name="CTL_USR_REFRESH" value="0" />
  <parameter name="AV_PORT_2_CONNECT_TO_CV_PORT" value="2" />
  <parameter name="PLL_MEM_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_5" value="USE_NO" />
  <parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
  <parameter name="MR0_BT" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL" value="0" />
  <parameter name="MR1_AL" value="0" />
  <parameter name="DQS_PHASE_SHIFT" value="9000" />
  <parameter name="MR0_BL" value="2" />
  <parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.09" />
  <parameter name="MEM_TRCD" value="0" />
  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
  <parameter name="MAX_PENDING_RD_CMD" value="32" />
  <parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
  <parameter name="REGISTER_C2P" value="false" />
  <parameter name="MEM_WTCL_INT" value="6" />
  <parameter name="MEM_IF_ROW_ADDR_WIDTH" value="0" />
  <parameter name="DQS_EN_DELAY_MAX" value="-1" />
  <parameter name="ENUM_CPORT1_TYPE" value="DISABLE" />
  <parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
  <parameter name="MR1_BL" value="2" />
  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
  <parameter name="MR1_BT" value="0" />
  <parameter name="REF_CLK_FREQ" value="25.0" />
  <parameter name="AV_PORT_5_CONNECT_TO_CV_PORT" value="5" />
  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
  <parameter name="PLL_NIOS_CLK_DIV" value="0" />
  <parameter name="MR0_DLL" value="1" />
  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
  <parameter name="PINGPONGPHY_EN" value="false" />
  <parameter name="CFG_WRITE_ODT_CHIP" value="0" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_5" value="2" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="" />
  <parameter name="MR2_ASR" value="0" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_3" value="2" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_4" value="2" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_1" value="2" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_2" value="2" />
  <parameter name="MR2_CWL" value="1" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_0" value="2" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV" value="0" />
  <parameter name="HPS_PROTOCOL" value="DDR3" />
  <parameter name="MEM_IF_LRDIMM_RM" value="0" />
  <parameter name="VECT_ATTR_COUNTER_ONE_MATCH" value="0" />
  <parameter name="ENUM_PRIORITY_1_5" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_1" value="WEIGHT_0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ENUM_PRIORITY_1_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="DUPLICATE_AC" value="false" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_5" value="2" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_1" value="2" />
  <parameter name="DUAL_WRITE_CLOCK" value="false" />
  <parameter
     name="interfaceDefinition"
     value="instances {clocks_resets {entity_name cyclonev_hps_interface_clocks_resets location HPSINTERFACECLOCKSRESETS_X52_Y78_N111 signal_widths {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 1 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 1} signal_terminations {f2h_warm_rst_req_n {0:0 1} f2h_pending_rst_ack {0:0 1} f2h_sdram_ref_clk {} f2h_dbg_rst_req_n {0:0 1} f2h_cold_rst_req_n {0:0 1} f2h_periph_ref_clk {}} parameters {} signal_default_terminations {f2h_warm_rst_req_n 1 f2h_pending_rst_ack 1 f2h_sdram_ref_clk 0 f2h_dbg_rst_req_n 1 f2h_cold_rst_req_n 1 f2h_periph_ref_clk 0}} debug_apb {entity_name cyclonev_hps_interface_dbg_apb location HPSINTERFACEDBGAPB_X52_Y80_N111 signal_widths {DBG_APB_DISABLE 1 P_CLK_EN 1} signal_terminations {DBG_APB_DISABLE {0:0 0} P_CLK_EN {0:0 0}} parameters {} signal_default_terminations {DBG_APB_DISABLE 0 P_CLK_EN 0}} fpga2hps {entity_name cyclonev_hps_interface_fpga2hps location HPSINTERFACEFPGA2HPS_X52_Y45_N111 signal_widths {port_size_config 2} parameters {} signal_terminations {port_size_config {1:0 1}} signal_default_terminations {port_size_config 0}} @orderednames {clocks_resets debug_apb tpiu boot_from_fpga fpga2hps hps2fpga_light_weight hps2fpga f2sdram} boot_from_fpga {entity_name cyclonev_hps_interface_boot_from_fpga location HPSINTERFACEBOOTFROMFPGA_X52_Y74_N111 signal_widths {boot_from_fpga_ready 1 boot_from_fpga_on_failure 1 bsel_en 1 csel_en 1 csel 2 bsel 3} signal_terminations {boot_from_fpga_ready {0:0 0} boot_from_fpga_on_failure {0:0 0} bsel_en {0:0 0} csel_en {0:0 0} csel {1:0 1} bsel {2:0 1}} parameters {} signal_default_terminations {boot_from_fpga_ready 0 boot_from_fpga_on_failure 0 bsel_en 0 csel_en 0 csel 0 bsel 0}} tpiu {entity_name cyclonev_hps_interface_tpiu_trace location HPSINTERFACETPIUTRACE_X52_Y39_N111 signal_widths {traceclk_ctl 1} parameters {} signal_terminations {traceclk_ctl {0:0 1}} signal_default_terminations {traceclk_ctl 1}} f2sdram {entity_name cyclonev_hps_interface_fpga2sdram location HPSINTERFACEFPGA2SDRAM_X52_Y53_N111 signal_widths {cfg_axi_mm_select 6 cfg_wfifo_cport_map 16 cfg_cport_rfifo_map 18 cfg_cport_type 12 cfg_port_width 12 cfg_cport_wfifo_map 18 cfg_rfifo_cport_map 16} parameters {} signal_terminations {cfg_axi_mm_select {5:0 0} cfg_wfifo_cport_map {15:0 0} cfg_cport_rfifo_map {17:0 0} cfg_cport_type {11:0 0} cfg_port_width {11:0 0} cfg_cport_wfifo_map {17:0 0} cfg_rfifo_cport_map {15:0 0}} signal_default_terminations {cfg_axi_mm_select 0 cfg_wfifo_cport_map 0 cfg_cport_rfifo_map 0 cfg_cport_type 0 cfg_port_width 0 cfg_cport_wfifo_map 0 cfg_rfifo_cport_map 0}} hps2fpga_light_weight {entity_name cyclonev_hps_interface_hps2fpga_light_weight location HPSINTERFACEHPS2FPGALIGHTWEIGHT_X52_Y43_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps2fpga {entity_name cyclonev_hps_interface_hps2fpga location HPSINTERFACEHPS2FPGA_X52_Y47_N111 signal_widths {port_size_config 2} parameters {} signal_terminations {port_size_config {1:0 1}} signal_default_terminations {port_size_config 0}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{create_clock -period 10.0 [get_pins -compatibility_mode *|fpga_interfaces|clocks_resets|h2f_user1_clk]}} properties {} bfm_types {} intermediate_wire_count 0 wires_to_fragments {} interfaces {@orderednames {h2f_reset h2f_user1_clock f2h_axi_clock f2h_axi_slave h2f_lw_axi_clock h2f_lw_axi_master h2f_axi_clock h2f_axi_master} h2f_reset {properties {associatedResetSinks none synchronousEdges none} type reset direction Output signals {@orderednames h2f_rst_n h2f_rst_n {fragments {} properties {} internal_name h2f_rst_n width 1 instance_name clocks_resets direction Output role reset_n}}} h2f_user1_clock {properties {clockRate 100000000.0 clockRateKnown true} type clock direction Output signals {@orderednames h2f_user1_clk h2f_user1_clk {fragments {} properties {} internal_name h2f_user1_clk width 1 instance_name clocks_resets direction Output role clk}}} f2h_axi_clock {properties {} type clock direction Input signals {@orderednames f2h_axi_clk f2h_axi_clk {fragments {} properties {} internal_name clk width 1 instance_name fpga2hps direction Input role clk}}} f2h_axi_slave {data_width 64 properties {readDataReorderingDepth 16 associatedClock f2h_axi_clock associatedReset h2f_reset writeAcceptanceCapability 8 readAcceptanceCapability 8 combinedAcceptanceCapability 16} type axi address_width 32 direction slave signals {@orderednames {f2h_AWID f2h_AWADDR f2h_AWLEN f2h_AWSIZE f2h_AWBURST f2h_AWLOCK f2h_AWCACHE f2h_AWPROT f2h_AWVALID f2h_AWREADY f2h_AWUSER f2h_WID f2h_WDATA f2h_WSTRB f2h_WLAST f2h_WVALID f2h_WREADY f2h_BID f2h_BRESP f2h_BVALID f2h_BREADY f2h_ARID f2h_ARADDR f2h_ARLEN f2h_ARSIZE f2h_ARBURST f2h_ARLOCK f2h_ARCACHE f2h_ARPROT f2h_ARVALID f2h_ARREADY f2h_ARUSER f2h_RID f2h_RDATA f2h_RRESP f2h_RLAST f2h_RVALID f2h_RREADY} f2h_AWID {fragments {} properties {} internal_name awid width 8 instance_name fpga2hps direction Input role awid} f2h_AWADDR {fragments {} properties {} internal_name awaddr width 32 instance_name fpga2hps direction Input role awaddr} f2h_AWLEN {fragments {} properties {} internal_name awlen width 4 instance_name fpga2hps direction Input role awlen} f2h_AWSIZE {fragments {} properties {} internal_name awsize width 3 instance_name fpga2hps direction Input role awsize} f2h_AWBURST {fragments {} properties {} internal_name awburst width 2 instance_name fpga2hps direction Input role awburst} f2h_AWLOCK {fragments {} properties {} internal_name awlock width 2 instance_name fpga2hps direction Input role awlock} f2h_AWCACHE {fragments {} properties {} internal_name awcache width 4 instance_name fpga2hps direction Input role awcache} f2h_AWPROT {fragments {} properties {} internal_name awprot width 3 instance_name fpga2hps direction Input role awprot} f2h_AWVALID {fragments {} properties {} internal_name awvalid width 1 instance_name fpga2hps direction Input role awvalid} f2h_AWREADY {fragments {} properties {} internal_name awready width 1 instance_name fpga2hps direction Output role awready} f2h_AWUSER {fragments {} properties {} internal_name awuser width 5 instance_name fpga2hps direction Input role awuser} f2h_WID {fragments {} properties {} internal_name wid width 8 instance_name fpga2hps direction Input role wid} f2h_WDATA {fragments {} properties {} internal_name wdata width 64 instance_name fpga2hps direction Input role wdata} f2h_WSTRB {fragments {} properties {} internal_name wstrb width 8 instance_name fpga2hps direction Input role wstrb} f2h_WLAST {fragments {} properties {} internal_name wlast width 1 instance_name fpga2hps direction Input role wlast} f2h_WVALID {fragments {} properties {} internal_name wvalid width 1 instance_name fpga2hps direction Input role wvalid} f2h_WREADY {fragments {} properties {} internal_name wready width 1 instance_name fpga2hps direction Output role wready} f2h_BID {fragments {} properties {} internal_name bid width 8 instance_name fpga2hps direction Output role bid} f2h_BRESP {fragments {} properties {} internal_name bresp width 2 instance_name fpga2hps direction Output role bresp} f2h_BVALID {fragments {} properties {} internal_name bvalid width 1 instance_name fpga2hps direction Output role bvalid} f2h_BREADY {fragments {} properties {} internal_name bready width 1 instance_name fpga2hps direction Input role bready} f2h_ARID {fragments {} properties {} internal_name arid width 8 instance_name fpga2hps direction Input role arid} f2h_ARADDR {fragments {} properties {} internal_name araddr width 32 instance_name fpga2hps direction Input role araddr} f2h_ARLEN {fragments {} properties {} internal_name arlen width 4 instance_name fpga2hps direction Input role arlen} f2h_ARSIZE {fragments {} properties {} internal_name arsize width 3 instance_name fpga2hps direction Input role arsize} f2h_ARBURST {fragments {} properties {} internal_name arburst width 2 instance_name fpga2hps direction Input role arburst} f2h_ARLOCK {fragments {} properties {} internal_name arlock width 2 instance_name fpga2hps direction Input role arlock} f2h_ARCACHE {fragments {} properties {} internal_name arcache width 4 instance_name fpga2hps direction Input role arcache} f2h_ARPROT {fragments {} properties {} internal_name arprot width 3 instance_name fpga2hps direction Input role arprot} f2h_ARVALID {fragments {} properties {} internal_name arvalid width 1 instance_name fpga2hps direction Input role arvalid} f2h_ARREADY {fragments {} properties {} internal_name arready width 1 instance_name fpga2hps direction Output role arready} f2h_ARUSER {fragments {} properties {} internal_name aruser width 5 instance_name fpga2hps direction Input role aruser} f2h_RID {fragments {} properties {} internal_name rid width 8 instance_name fpga2hps direction Output role rid} f2h_RDATA {fragments {} properties {} internal_name rdata width 64 instance_name fpga2hps direction Output role rdata} f2h_RRESP {fragments {} properties {} internal_name rresp width 2 instance_name fpga2hps direction Output role rresp} f2h_RLAST {fragments {} properties {} internal_name rlast width 1 instance_name fpga2hps direction Output role rlast} f2h_RVALID {fragments {} properties {} internal_name rvalid width 1 instance_name fpga2hps direction Output role rvalid} f2h_RREADY {fragments {} properties {} internal_name rready width 1 instance_name fpga2hps direction Input role rready}}} h2f_lw_axi_clock {properties {} type clock direction Input signals {@orderednames h2f_lw_axi_clk h2f_lw_axi_clk {fragments {} properties {} internal_name clk width 1 instance_name hps2fpga_light_weight direction Input role clk}}} h2f_lw_axi_master {id_width 12 data_width 32 properties {associatedClock h2f_lw_axi_clock associatedReset h2f_reset writeIssuingCapability 8 readIssuingCapability 8 combinedIssuingCapability 16} type axi address_width 21 direction master signals {@orderednames {h2f_lw_AWID h2f_lw_AWADDR h2f_lw_AWLEN h2f_lw_AWSIZE h2f_lw_AWBURST h2f_lw_AWLOCK h2f_lw_AWCACHE h2f_lw_AWPROT h2f_lw_AWVALID h2f_lw_AWREADY h2f_lw_WID h2f_lw_WDATA h2f_lw_WSTRB h2f_lw_WLAST h2f_lw_WVALID h2f_lw_WREADY h2f_lw_BID h2f_lw_BRESP h2f_lw_BVALID h2f_lw_BREADY h2f_lw_ARID h2f_lw_ARADDR h2f_lw_ARLEN h2f_lw_ARSIZE h2f_lw_ARBURST h2f_lw_ARLOCK h2f_lw_ARCACHE h2f_lw_ARPROT h2f_lw_ARVALID h2f_lw_ARREADY h2f_lw_RID h2f_lw_RDATA h2f_lw_RRESP h2f_lw_RLAST h2f_lw_RVALID h2f_lw_RREADY} h2f_lw_AWID {fragments {} properties {} internal_name awid width 12 instance_name hps2fpga_light_weight direction Output role awid} h2f_lw_AWADDR {fragments {} properties {} internal_name awaddr width 21 instance_name hps2fpga_light_weight direction Output role awaddr} h2f_lw_AWLEN {fragments {} properties {} internal_name awlen width 4 instance_name hps2fpga_light_weight direction Output role awlen} h2f_lw_AWSIZE {fragments {} properties {} internal_name awsize width 3 instance_name hps2fpga_light_weight direction Output role awsize} h2f_lw_AWBURST {fragments {} properties {} internal_name awburst width 2 instance_name hps2fpga_light_weight direction Output role awburst} h2f_lw_AWLOCK {fragments {} properties {} internal_name awlock width 2 instance_name hps2fpga_light_weight direction Output role awlock} h2f_lw_AWCACHE {fragments {} properties {} internal_name awcache width 4 instance_name hps2fpga_light_weight direction Output role awcache} h2f_lw_AWPROT {fragments {} properties {} internal_name awprot width 3 instance_name hps2fpga_light_weight direction Output role awprot} h2f_lw_AWVALID {fragments {} properties {} internal_name awvalid width 1 instance_name hps2fpga_light_weight direction Output role awvalid} h2f_lw_AWREADY {fragments {} properties {} internal_name awready width 1 instance_name hps2fpga_light_weight direction Input role awready} h2f_lw_WID {fragments {} properties {} internal_name wid width 12 instance_name hps2fpga_light_weight direction Output role wid} h2f_lw_WDATA {fragments {} properties {} internal_name wdata width 32 instance_name hps2fpga_light_weight direction Output role wdata} h2f_lw_WSTRB {fragments {} properties {} internal_name wstrb width 4 instance_name hps2fpga_light_weight direction Output role wstrb} h2f_lw_WLAST {fragments {} properties {} internal_name wlast width 1 instance_name hps2fpga_light_weight direction Output role wlast} h2f_lw_WVALID {fragments {} properties {} internal_name wvalid width 1 instance_name hps2fpga_light_weight direction Output role wvalid} h2f_lw_WREADY {fragments {} properties {} internal_name wready width 1 instance_name hps2fpga_light_weight direction Input role wready} h2f_lw_BID {fragments {} properties {} internal_name bid width 12 instance_name hps2fpga_light_weight direction Input role bid} h2f_lw_BRESP {fragments {} properties {} internal_name bresp width 2 instance_name hps2fpga_light_weight direction Input role bresp} h2f_lw_BVALID {fragments {} properties {} internal_name bvalid width 1 instance_name hps2fpga_light_weight direction Input role bvalid} h2f_lw_BREADY {fragments {} properties {} internal_name bready width 1 instance_name hps2fpga_light_weight direction Output role bready} h2f_lw_ARID {fragments {} properties {} internal_name arid width 12 instance_name hps2fpga_light_weight direction Output role arid} h2f_lw_ARADDR {fragments {} properties {} internal_name araddr width 21 instance_name hps2fpga_light_weight direction Output role araddr} h2f_lw_ARLEN {fragments {} properties {} internal_name arlen width 4 instance_name hps2fpga_light_weight direction Output role arlen} h2f_lw_ARSIZE {fragments {} properties {} internal_name arsize width 3 instance_name hps2fpga_light_weight direction Output role arsize} h2f_lw_ARBURST {fragments {} properties {} internal_name arburst width 2 instance_name hps2fpga_light_weight direction Output role arburst} h2f_lw_ARLOCK {fragments {} properties {} internal_name arlock width 2 instance_name hps2fpga_light_weight direction Output role arlock} h2f_lw_ARCACHE {fragments {} properties {} internal_name arcache width 4 instance_name hps2fpga_light_weight direction Output role arcache} h2f_lw_ARPROT {fragments {} properties {} internal_name arprot width 3 instance_name hps2fpga_light_weight direction Output role arprot} h2f_lw_ARVALID {fragments {} properties {} internal_name arvalid width 1 instance_name hps2fpga_light_weight direction Output role arvalid} h2f_lw_ARREADY {fragments {} properties {} internal_name arready width 1 instance_name hps2fpga_light_weight direction Input role arready} h2f_lw_RID {fragments {} properties {} internal_name rid width 12 instance_name hps2fpga_light_weight direction Input role rid} h2f_lw_RDATA {fragments {} properties {} internal_name rdata width 32 instance_name hps2fpga_light_weight direction Input role rdata} h2f_lw_RRESP {fragments {} properties {} internal_name rresp width 2 instance_name hps2fpga_light_weight direction Input role rresp} h2f_lw_RLAST {fragments {} properties {} internal_name rlast width 1 instance_name hps2fpga_light_weight direction Input role rlast} h2f_lw_RVALID {fragments {} properties {} internal_name rvalid width 1 instance_name hps2fpga_light_weight direction Input role rvalid} h2f_lw_RREADY {fragments {} properties {} internal_name rready width 1 instance_name hps2fpga_light_weight direction Output role rready}}} h2f_axi_clock {properties {} type clock direction Input signals {@orderednames h2f_axi_clk h2f_axi_clk {fragments {} properties {} internal_name clk width 1 instance_name hps2fpga direction Input role clk}}} h2f_axi_master {id_width 12 data_width 64 properties {associatedClock h2f_axi_clock associatedReset h2f_reset writeIssuingCapability 8 readIssuingCapability 8 combinedIssuingCapability 16} type axi address_width 30 direction master signals {@orderednames {h2f_AWID h2f_AWADDR h2f_AWLEN h2f_AWSIZE h2f_AWBURST h2f_AWLOCK h2f_AWCACHE h2f_AWPROT h2f_AWVALID h2f_AWREADY h2f_WID h2f_WDATA h2f_WSTRB h2f_WLAST h2f_WVALID h2f_WREADY h2f_BID h2f_BRESP h2f_BVALID h2f_BREADY h2f_ARID h2f_ARADDR h2f_ARLEN h2f_ARSIZE h2f_ARBURST h2f_ARLOCK h2f_ARCACHE h2f_ARPROT h2f_ARVALID h2f_ARREADY h2f_RID h2f_RDATA h2f_RRESP h2f_RLAST h2f_RVALID h2f_RREADY} h2f_AWID {fragments {} properties {} internal_name awid width 12 instance_name hps2fpga direction Output role awid} h2f_AWADDR {fragments {} properties {} internal_name awaddr width 30 instance_name hps2fpga direction Output role awaddr} h2f_AWLEN {fragments {} properties {} internal_name awlen width 4 instance_name hps2fpga direction Output role awlen} h2f_AWSIZE {fragments {} properties {} internal_name awsize width 3 instance_name hps2fpga direction Output role awsize} h2f_AWBURST {fragments {} properties {} internal_name awburst width 2 instance_name hps2fpga direction Output role awburst} h2f_AWLOCK {fragments {} properties {} internal_name awlock width 2 instance_name hps2fpga direction Output role awlock} h2f_AWCACHE {fragments {} properties {} internal_name awcache width 4 instance_name hps2fpga direction Output role awcache} h2f_AWPROT {fragments {} properties {} internal_name awprot width 3 instance_name hps2fpga direction Output role awprot} h2f_AWVALID {fragments {} properties {} internal_name awvalid width 1 instance_name hps2fpga direction Output role awvalid} h2f_AWREADY {fragments {} properties {} internal_name awready width 1 instance_name hps2fpga direction Input role awready} h2f_WID {fragments {} properties {} internal_name wid width 12 instance_name hps2fpga direction Output role wid} h2f_WDATA {fragments {} properties {} internal_name wdata width 64 instance_name hps2fpga direction Output role wdata} h2f_WSTRB {fragments {} properties {} internal_name wstrb width 8 instance_name hps2fpga direction Output role wstrb} h2f_WLAST {fragments {} properties {} internal_name wlast width 1 instance_name hps2fpga direction Output role wlast} h2f_WVALID {fragments {} properties {} internal_name wvalid width 1 instance_name hps2fpga direction Output role wvalid} h2f_WREADY {fragments {} properties {} internal_name wready width 1 instance_name hps2fpga direction Input role wready} h2f_BID {fragments {} properties {} internal_name bid width 12 instance_name hps2fpga direction Input role bid} h2f_BRESP {fragments {} properties {} internal_name bresp width 2 instance_name hps2fpga direction Input role bresp} h2f_BVALID {fragments {} properties {} internal_name bvalid width 1 instance_name hps2fpga direction Input role bvalid} h2f_BREADY {fragments {} properties {} internal_name bready width 1 instance_name hps2fpga direction Output role bready} h2f_ARID {fragments {} properties {} internal_name arid width 12 instance_name hps2fpga direction Output role arid} h2f_ARADDR {fragments {} properties {} internal_name araddr width 30 instance_name hps2fpga direction Output role araddr} h2f_ARLEN {fragments {} properties {} internal_name arlen width 4 instance_name hps2fpga direction Output role arlen} h2f_ARSIZE {fragments {} properties {} internal_name arsize width 3 instance_name hps2fpga direction Output role arsize} h2f_ARBURST {fragments {} properties {} internal_name arburst width 2 instance_name hps2fpga direction Output role arburst} h2f_ARLOCK {fragments {} properties {} internal_name arlock width 2 instance_name hps2fpga direction Output role arlock} h2f_ARCACHE {fragments {} properties {} internal_name arcache width 4 instance_name hps2fpga direction Output role arcache} h2f_ARPROT {fragments {} properties {} internal_name arprot width 3 instance_name hps2fpga direction Output role arprot} h2f_ARVALID {fragments {} properties {} internal_name arvalid width 1 instance_name hps2fpga direction Output role arvalid} h2f_ARREADY {fragments {} properties {} internal_name arready width 1 instance_name hps2fpga direction Input role arready} h2f_RID {fragments {} properties {} internal_name rid width 12 instance_name hps2fpga direction Input role rid} h2f_RDATA {fragments {} properties {} internal_name rdata width 64 instance_name hps2fpga direction Input role rdata} h2f_RRESP {fragments {} properties {} internal_name rresp width 2 instance_name hps2fpga direction Input role rresp} h2f_RLAST {fragments {} properties {} internal_name rlast width 1 instance_name hps2fpga direction Input role rlast} h2f_RVALID {fragments {} properties {} internal_name rvalid width 1 instance_name hps2fpga direction Input role rvalid} h2f_RREADY {fragments {} properties {} internal_name rready width 1 instance_name hps2fpga direction Output role rready}}}} raw_assign_sim_style {}" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_2" value="2" />
  <parameter name="AC_ROM_MR1_MIRR" value="" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_3" value="2" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_4" value="2" />
  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
  <parameter name="CFG_POWER_SAVING_EXIT_CYCLES" value="0" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_0" value="2" />
  <parameter name="CV_PORT_2_CONNECT_TO_AV_PORT" value="2" />
  <parameter name="MR1_DS" value="0" />
  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="AUTO_PD_CYCLES" value="0" />
  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
  <parameter name="ENUM_CPORT5_TYPE" value="DISABLE" />
  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD" value="0" />
  <parameter name="AFI_BANKADDR_WIDTH" value="0" />
  <parameter name="CV_ENUM_CPORT0_TYPE" value="DISABLE" />
  <parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_THLD_JAR2_0" value="THRESHOLD_16" />
  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
  <parameter name="CTL_TBP_NUM" value="4" />
  <parameter name="ENUM_THLD_JAR2_1" value="THRESHOLD_16" />
  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
  <parameter name="ENUM_THLD_JAR2_2" value="THRESHOLD_16" />
  <parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
  <parameter name="CTL_ENABLE_BURST_TERMINATE_INT" value="false" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CFG_ECC_DECODER_REG" value="0" />
  <parameter name="CTL_ENABLE_BURST_INTERRUPT_INT" value="false" />
  <parameter name="REF_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="TRACKING_ERROR_TEST" value="false" />
  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="REF_CLK_FREQ_STR" value="" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
  <parameter name="PLL_MEM_CLK_FREQ" value="0.0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
  <parameter name="MR1_RTT" value="1" />
  <parameter name="READ_FIFO_HALF_RATE" value="false" />
  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="" />
  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
  <parameter name="CSR_DATA_WIDTH" value="32" />
  <parameter name="MEM_DLL_EN" value="true" />
  <parameter name="IS_ES_DEVICE" value="false" />
  <parameter name="PRE_V_SERIES_FAMILY" value="false" />
  <parameter name="USE_MM_ADAPTOR" value="true" />
  <parameter name="HHP_HPS_SIMULATION" value="true" />
  <parameter name="CV_ENUM_PRIORITY_6_1" value="WEIGHT_0" />
  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
  <parameter name="CV_ENUM_PRIORITY_6_0" value="WEIGHT_0" />
  <parameter name="IO_OUT2_DELAY_MAX" value="-1" />
  <parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
  <parameter name="PLL_MEM_CLK_MULT_CACHE" value="0" />
  <parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
  <parameter name="HCX_COMPAT_MODE" value="false" />
  <parameter name="MEM_IF_DQSN_EN" value="true" />
  <parameter name="ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="AC_ROM_MR0" value="" />
  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MEM_TRAS" value="0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_ECC_DQ_WIDTH" value="ECC_DQ_WIDTH_0" />
  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP" value="0" />
  <parameter name="MEM_TINIT_US" value="500" />
  <parameter name="CTL_SELF_REFRESH" value="0" />
  <parameter name="ENUM_MEM_IF_TWTR" value="TWTR_4" />
  <parameter name="CALIBRATION_MODE" value="Skip" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
  <parameter name="ENUM_USER_ECC_EN" value="DISABLE" />
  <parameter name="PLL_MEM_CLK_DIV" value="0" />
  <parameter name="OCT_SHARING_MODE" value="None" />
  <parameter name="AC_ROM_MR2" value="" />
  <parameter name="AC_ROM_MR1" value="" />
  <parameter name="PLL_AFI_PHY_CLK_DIV" value="0" />
  <parameter name="AC_ROM_MR3" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH" value="0" />
  <parameter name="USE_HARD_READ_FIFO" value="false" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID" value="0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
  <parameter name="ENUM_CFG_BURST_LENGTH" value="BL_8" />
  <parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
  <parameter name="CV_ENUM_PRIORITY_6_3" value="WEIGHT_0" />
  <parameter name="PHY_VERSION_NUMBER" value="0" />
  <parameter name="CV_ENUM_PRIORITY_6_2" value="WEIGHT_0" />
  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
  <parameter name="CV_ENUM_PRIORITY_6_5" value="WEIGHT_0" />
  <parameter name="TIMING_BOARD_TIH_APPLIED" value="0.0" />
  <parameter name="CV_ENUM_PRIORITY_6_4" value="WEIGHT_0" />
  <parameter name="MEM_SRT" value="Normal" />
  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
  <parameter name="MEM_IF_READ_DQS_WIDTH" value="0" />
  <parameter name="PLL_WRITE_CLK_MULT_CACHE" value="0" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
  <parameter name="EXTRA_VFIFO_SHIFT" value="0" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
  <parameter name="CFG_TYPE" value="0" />
  <parameter name="ENUM_CLR_INTR" value="NO_CLR_INTR" />
  <parameter name="ENUM_CPORT3_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
  <parameter name="MR3_DS" value="2" />
  <parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
  <parameter name="MR2_RLWL" value="1" />
  <parameter name="DELAY_CHAIN_LENGTH" value="8" />
  <parameter name="PLL_WRITE_CLK_DIV_CACHE" value="0" />
  <parameter name="CV_ENUM_PRIORITY_4_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_2" value="WEIGHT_0" />
  <parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID" value="0" />
  <parameter name="ENUM_PRIORITY_5_5" value="WEIGHT_0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_PRIORITY_5_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_2" value="WEIGHT_0" />
  <parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="ENUM_PRIORITY_5_0" value="WEIGHT_0" />
  <parameter name="TIMING_TQHS" value="300" />
  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="0" />
  <parameter name="AV_PORT_1_CONNECT_TO_CV_PORT" value="1" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="CV_PORT_5_CONNECT_TO_AV_PORT" value="5" />
  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="0" />
  <parameter name="MEM_TMRD_CK" value="4" />
  <parameter name="CFG_INTERFACE_WIDTH" value="0" />
  <parameter name="IO_OUT1_DELAY_MAX" value="-1" />
  <parameter name="DEVICE_DEPTH" value="1" />
  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
  <parameter name="CV_ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="ENUM_MASK_CORR_DROPPED_INTR" value="DISABLED" />
  <parameter name="AC_PACKAGE_DESKEW" value="false" />
  <parameter name="ENUM_ATTR_STATIC_CONFIG_VALID" value="DISABLED" />
  <parameter name="CTL_ENABLE_WDATA_PATH_LATENCY" value="false" />
  <parameter name="ENUM_CLOCK_OFF_2" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_1" value="DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
  <parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="ENUM_CLOCK_OFF_0" value="DISABLED" />
  <parameter name="SEQ_BURST_COUNT_WIDTH" value="0" />
  <parameter name="CFG_BURST_LENGTH" value="0" />
  <parameter name="ENUM_CLOCK_OFF_5" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_4" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_3" value="DISABLED" />
  <parameter name="PHY_ONLY" value="false" />
  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="false" />
  <parameter name="TRFC" value="350" />
  <parameter name="IO_STANDARD" value="" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
  <parameter name="CV_ENUM_PRIORITY_4_5" value="WEIGHT_0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="SPEED_GRADE_CACHE" value="" />
  <parameter name="CV_ENUM_PRIORITY_4_4" value="WEIGHT_0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_AFI_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="READ_FIFO_SIZE" value="8" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="TB_MEM_IF_DQ_WIDTH" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="NEGATIVE_WRITE_CK_PHASE" value="false" />
  <parameter name="CFG_MEM_CLK_ENTRY_CYCLES" value="0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
  <parameter name="CV_ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
  <parameter name="ENUM_CFG_INTERFACE_WIDTH" value="DWIDTH_32" />
  <parameter name="ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="MEM_ATCL_INT" value="0" />
  <parameter name="ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
  <parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
  <parameter name="CV_ENUM_CPORT4_TYPE" value="DISABLE" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="TIMING_TDSS" value="0.2" />
  <parameter name="CV_ENUM_PRIORITY_2_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_0" value="WEIGHT_0" />
  <parameter name="CSR_BE_WIDTH" value="4" />
  <parameter name="CV_ENUM_PRIORITY_2_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_2" value="WEIGHT_0" />
  <parameter name="PLL_LOCATION" value="Top_Bottom" />
  <parameter name="CV_ENUM_PRIORITY_2_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_4" value="WEIGHT_0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="" />
  <parameter name="MEM_TRTP_NS" value="7.5" />
  <parameter name="CV_CPORT_TYPE_PORT_2" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_3" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_0" value="0" />
  <parameter name="PLL_SHARING_MODE" value="None" />
  <parameter name="CV_CPORT_TYPE_PORT_1" value="0" />
  <parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_4" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_5" value="0" />
  <parameter name="ENUM_PRIORITY_3_5" value="WEIGHT_0" />
  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="AP_MODE" value="false" />
  <parameter name="ENUM_PRIORITY_3_3" value="WEIGHT_0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="ENUM_PRIORITY_3_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_3_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_3_2" value="WEIGHT_0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="" />
  <parameter name="ENUM_PRIORITY_3_0" value="WEIGHT_0" />
  <parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="false" />
  <parameter name="ENUM_MEM_IF_MEMTYPE" value="DDR3_SDRAM" />
  <parameter name="MEM_PD" value="DLL off" />
  <parameter name="MAX10_RTL_SEQ" value="false" />
  <parameter name="TIMING_TDSH" value="0.2" />
  <parameter name="CTL_AUTOPCH_EN" value="false" />
  <parameter name="ENUM_PDN_EXIT_CYCLES" value="SLOW_EXIT" />
  <parameter name="REF_CLK_FREQ_MAX_CACHE" value="0.0" />
  <parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID" value="0" />
  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
  <parameter name="MEM_DQ_WIDTH" value="32" />
  <parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
  <parameter name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES" value="" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="FLY_BY" value="true" />
  <parameter name="ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="TIMING_TQSH" value="0.4" />
  <parameter name="CV_ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
  <parameter name="LSB_RFIFO_PORT_0" value="5" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ" value="0.0" />
  <parameter name="AFI_CLK_PAIR_COUNT" value="0" />
  <parameter name="HARD_EMIF" value="true" />
  <parameter name="LSB_RFIFO_PORT_5" value="5" />
  <parameter name="LSB_RFIFO_PORT_3" value="5" />
  <parameter name="LSB_RFIFO_PORT_4" value="5" />
  <parameter name="LSB_RFIFO_PORT_1" value="5" />
  <parameter name="CV_ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
  <parameter name="LSB_RFIFO_PORT_2" value="5" />
  <parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
  <parameter name="MEM_CLK_MAX_NS" value="2.5" />
  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
  <parameter name="CALIB_REG_WIDTH" value="8" />
  <parameter name="DWIDTH_RATIO" value="4" />
  <parameter name="INTG_MEM_IF_TREFI" value="3120" />
  <parameter name="CFG_CLR_INTR" value="0" />
  <parameter name="ENABLE_ABSTRACT_RAM" value="false" />
  <parameter name="ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
  <parameter name="ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_ENABLE_NO_DM" value="DISABLED" />
  <parameter name="ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="MEM_TINIT_CK" value="499" />
  <parameter name="ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
  <parameter name="MR1_PASR" value="0" />
  <parameter name="IO_DQS_OUT_RESERVE" value="3" />
  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
  <parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
  <parameter name="MEM_BL" value="OTF" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
  <parameter name="MEM_BT" value="Sequential" />
  <parameter name="ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="CONTROLLER_LATENCY" value="5" />
  <parameter name="MEM_TRTP" value="0" />
  <parameter name="ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="TREFI" value="35100" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="PLL_AFI_CLK_DIV_CACHE" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="0" />
  <parameter name="MEM_DQ_PER_DQS" value="8" />
  <parameter name="CV_ENUM_PRIORITY_0_1" value="WEIGHT_0" />
  <parameter name="ENUM_CTL_REGDIMM_ENABLED" value="REGDIMM_DISABLED" />
  <parameter name="CV_ENUM_PRIORITY_0_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_0_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_0_2" value="WEIGHT_0" />
  <parameter name="ENABLE_BURST_MERGE" value="false" />
  <parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="2" />
  <parameter name="CV_ENUM_PRIORITY_0_5" value="WEIGHT_0" />
  <parameter name="ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="CV_ENUM_PRIORITY_0_4" value="WEIGHT_0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
  <parameter name="ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.08" />
  <parameter name="CV_ENUM_CPORT5_TYPE" value="DISABLE" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="ENUM_ENABLE_BURST_TERMINATE" value="DISABLED" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
  <parameter name="VECT_ATTR_DEBUG_SELECT_BYTE" value="0" />
  <parameter name="CV_PORT_4_CONNECT_TO_AV_PORT" value="4" />
  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
  <parameter name="DEVICE_WIDTH" value="1" />
  <parameter name="SOPC_COMPAT_RESET" value="false" />
  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
  <parameter name="PLL_HR_CLK_FREQ_STR" value="" />
  <parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
  <parameter name="ENUM_ENABLE_PIPELINEGLOBAL" value="DISABLED" />
  <parameter name="COMMAND_PHASE_CACHE" value="0.0" />
  <parameter name="AFI_CONTROL_WIDTH" value="0" />
  <parameter name="PLL_HR_CLK_DIV" value="0" />
  <parameter name="REF_CLK_FREQ_MIN_CACHE" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="USER_DEBUG_LEVEL" value="1" />
  <parameter name="ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="ENUM_SINGLE_READY_3" value="CONCATENATE_RDY" />
  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
  <parameter name="ENUM_SINGLE_READY_1" value="CONCATENATE_RDY" />
  <parameter name="ENUM_SINGLE_READY_2" value="CONCATENATE_RDY" />
  <parameter name="ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="ENUM_GEN_DBE" value="GEN_DBE_DISABLED" />
  <parameter name="ENUM_SINGLE_READY_0" value="CONCATENATE_RDY" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="DATA_RATE_RATIO" value="0" />
  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
  <parameter name="ENUM_ENABLE_DQS_TRACKING" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_3" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_2" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_5" value="DISABLED" />
  <parameter name="ENUM_MEM_IF_TCL" value="TCL_6" />
  <parameter name="ENUM_ENABLE_BONDING_4" value="DISABLED" />
  <parameter name="CV_ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="CV_ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="CV_ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
  <parameter name="LOW_LATENCY" value="false" />
  <parameter name="ENUM_ENABLE_BONDING_1" value="DISABLED" />
  <parameter name="CV_ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="ENUM_ENABLE_BONDING_0" value="DISABLED" />
  <parameter name="CV_ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="CV_ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="0.0" />
  <parameter name="ENUM_MEM_IF_DQ_PER_CHIP" value="MEM_IF_DQ_PER_CHIP_8" />
  <parameter name="MR1_WC" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="" />
  <parameter name="ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_WRITE_CLK_FREQ_STR" value="" />
  <parameter name="RATE" value="Full" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MR1_WL" value="0" />
  <parameter name="POWER_OF_TWO_BUS" value="false" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="MR1_WR" value="1" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="MR3_MPR_RF" value="0" />
  <parameter name="MEM_IF_CONTROL_WIDTH" value="0" />
  <parameter name="DEBUG_MODE" value="false" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="MEM_RTT_WR" value="RZQ/4" />
  <parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="0" />
  <parameter name="CFG_STARVE_LIMIT" value="0" />
  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT" value="0" />
  <parameter name="ENUM_PRIORITY_7_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_4" value="WEIGHT_0" />
  <parameter name="MEM_CLK_MAX_PS" value="2500.0" />
  <parameter name="ENUM_PRIORITY_7_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_0" value="WEIGHT_0" />
  <parameter name="MEM_IF_NUMBER_OF_RANKS" value="0" />
  <parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
  <parameter name="ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="MEM_BURST_LENGTH" value="8" />
  <parameter name="ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="PLL_AFI_CLK_FREQ_STR" value="" />
  <parameter name="IO_DQDQS_OUT_PHASE_MAX" value="0" />
  <parameter name="MEM_TRRD" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="REFRESH_INTERVAL" value="15000" />
  <parameter name="ENUM_PRIORITY_7_5" value="WEIGHT_0" />
  <parameter name="MEM_INIT_EN" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH" value="0" />
  <parameter name="TIMING_BOARD_TDH_APPLIED" value="0.0" />
  <parameter name="ADDR_RATE_RATIO" value="0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CFG_SELF_RFSH_EXIT_CYCLES" value="0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="CTL_REGDIMM_ENABLED" value="false" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="CV_LSB_WFIFO_PORT_1" value="5" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="CV_LSB_WFIFO_PORT_0" value="5" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_0" value="0" />
  <parameter name="CV_ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="ENUM_GEN_SBE" value="GEN_SBE_DISABLED" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="ENUM_ENABLE_BONDING_WRAPBACK" value="DISABLED" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_2" value="0" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_1" value="0" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
  <parameter name="ENUM_THLD_JAR1_4" value="THRESHOLD_32" />
  <parameter name="MEM_RTT_NOM" value="RZQ/4" />
  <parameter name="ENUM_THLD_JAR1_5" value="THRESHOLD_32" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_4" value="0" />
  <parameter name="PLL_CONFIG_CLK_MULT" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_3" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_5" value="0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.16" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="AFI_WRANK_WIDTH" value="0" />
  <parameter name="LRDIMM" value="false" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MR1_DLL" value="0" />
  <parameter name="CFG_ADDR_ORDER" value="0" />
  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
  <parameter name="ENUM_WR_PORT_INFO_0" value="USE_NO" />
  <parameter name="CTL_ODT_ENABLED" value="false" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="SEQUENCER_TYPE" value="NIOS" />
  <parameter name="ENUM_WR_PORT_INFO_5" value="USE_NO" />
  <parameter name="MEM_IF_CLK_EN_WIDTH" value="0" />
  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="ENUM_WR_PORT_INFO_1" value="USE_NO" />
  <parameter name="ENUM_WR_PORT_INFO_2" value="USE_NO" />
  <parameter name="ENUM_WR_PORT_INFO_3" value="USE_NO" />
  <parameter name="VFIFO_AS_SHIFT_REG" value="false" />
  <parameter name="ENUM_WR_PORT_INFO_4" value="USE_NO" />
  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
  <parameter name="ENUM_THLD_JAR1_0" value="THRESHOLD_32" />
  <parameter name="ENUM_THLD_JAR1_1" value="THRESHOLD_32" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
  <parameter name="ENUM_THLD_JAR1_2" value="THRESHOLD_32" />
  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
  <parameter name="ENUM_THLD_JAR1_3" value="THRESHOLD_32" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="DLL_SHARING_MODE" value="None" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="ENUM_CPORT2_TYPE" value="DISABLE" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_ENABLE_ATPG" value="DISABLED" />
  <parameter name="PLL_DR_CLK_MULT" value="0" />
  <parameter name="USE_USER_RDIMM_VALUE" value="false" />
  <parameter name="MEM_FORMAT" value="DISCRETE" />
  <parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
  <parameter name="CONTROLLER_TYPE" value="nextgen_v110" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="AFI_WLAT_WIDTH" value="0" />
  <parameter name="MEM_IF_WRITE_DQS_WIDTH" value="0" />
  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="RATE_CACHE" value="Unknown" />
  <parameter name="COMMAND_PHASE" value="0.0" />
  <parameter name="CTL_CS_WIDTH" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_MULT" value="0" />
  <parameter name="ENUM_OUTPUT_REGD" value="DISABLED" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MR1_ODS" value="1" />
  <parameter name="MEM_TRFC" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="AV_PORT_4_CONNECT_TO_CV_PORT" value="4" />
  <parameter name="ENUM_SYNC_MODE_1" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="ENUM_SYNC_MODE_0" value="ASYNCHRONOUS" />
  <parameter name="ENUM_SYNC_MODE_3" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_SYNC_MODE_2" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="ENUM_CPORT1_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="ENUM_SYNC_MODE_5" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_CPORT4_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="ENUM_SYNC_MODE_4" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
  <parameter name="MEM_CK_PHASE" value="0.0" />
  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
  <parameter name="ENUM_CFG_TYPE" value="DDR3" />
  <parameter name="CV_ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="-0.01" />
  <parameter name="ADDR_ORDER" value="0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MEM_VERBOSE" value="true" />
  <parameter name="HARD_PHY" value="false" />
  <parameter name="MR2_SRF" value="0" />
  <parameter name="ENUM_CPORT4_TYPE" value="DISABLE" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="false" />
  <parameter name="ENUM_MEM_IF_BANKADDR_WIDTH" value="ADDR_WIDTH_3" />
  <parameter name="ENUM_MASK_SBE_INTR" value="DISABLED" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK" value="0" />
  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
  <parameter name="ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_READ_ODT_CHIP" value="ODT_DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
  <parameter name="VECT_ATTR_COUNTER_ONE_MASK" value="0" />
  <parameter name="MULTICAST_EN" value="false" />
  <parameter name="VCALIB_COUNT_WIDTH" value="0" />
  <parameter name="CV_ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
  <parameter name="OCT_TERM_CONTROL_WIDTH" value="14" />
  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="DLL_USE_DR_CLK" value="false" />
  <parameter name="ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="AC_PARITY" value="false" />
  <parameter name="AC_ROM_MR2_MIRR" value="" />
  <parameter name="MR1_DQS" value="0" />
  <parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES" value="DISABLED" />
  <parameter name="MR2_SRT" value="0" />
  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
  <parameter name="ENUM_MEM_IF_TMRD" value="" />
  <parameter name="CV_LSB_WFIFO_PORT_3" value="5" />
  <parameter name="CV_LSB_WFIFO_PORT_2" value="5" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CV_LSB_WFIFO_PORT_5" value="5" />
  <parameter name="CV_LSB_WFIFO_PORT_4" value="5" />
  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
  <parameter name="MR1_QOFF" value="0" />
  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
  <parameter name="TB_MEM_CLK_FREQ" value="0.0" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="DLL_DELAY_CTRL_WIDTH" value="6" />
  <parameter name="MEM_CLK_FREQ" value="400.0" />
  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
  <parameter name="CV_ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="USE_FAKE_PHY" value="false" />
  <parameter name="ENUM_MEM_IF_TWR" value="TWR_6" />
  <parameter name="SEQ_MODE" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
  <parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
  <parameter name="ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
  <parameter name="MEM_TYPE" value="" />
  <parameter name="REF_CLK_PS" value="0.0" />
  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
  <parameter name="ENUM_MEM_IF_TRAS" value="TRAS_16" />
  <parameter name="ENUM_INC_SYNC" value="FIFO_SET_2" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01" />
  <parameter name="ENUM_MEM_IF_TRCD" value="TRCD_6" />
  <parameter name="MARGIN_VARIATION_TEST" value="false" />
  <parameter name="TIMING_TIS" value="180" />
  <parameter name="ENUM_PRIORITY_0_4" value="WEIGHT_0" />
  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.03" />
  <parameter name="ENUM_PRIORITY_0_5" value="WEIGHT_0" />
  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
  <parameter name="ENUM_PRIORITY_0_2" value="WEIGHT_0" />
  <parameter name="IO_IN_DELAY_MAX" value="-1" />
  <parameter name="ENUM_PRIORITY_0_3" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID" value="0" />
  <parameter name="ENUM_PRIORITY_0_0" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_0_1" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR" value="0" />
  <parameter name="FAST_SIM_CALIBRATION" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="AVL_ADDR_WIDTH" value="0" />
  <parameter name="CV_ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
  <parameter name="MAX10_CFG" value="false" />
  <parameter name="CFG_REORDER_DATA" value="true" />
  <parameter name="device" value="5CSEMA5F31C6" />
  <parameter name="ENUM_ENABLE_FAST_EXIT_PPD" value="DISABLED" />
  <parameter name="DELAY_BUFFER_MODE" value="HIGH" />
  <parameter name="ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="0.0" />
  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
  <parameter name="CONTINUE_AFTER_CAL_FAIL" value="false" />
  <parameter name="AFI_RRANK_WIDTH" value="0" />
  <parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="" />
  <parameter name="MR3_MPR" value="0" />
  <parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
  <parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
  <parameter name="ENUM_CFG_STARVE_LIMIT" value="STARVE_LIMIT_32" />
  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.02" />
  <parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
  <parameter name="MEM_IF_ODT_WIDTH" value="0" />
  <parameter name="TIMING_TDQSCKDL" value="1200" />
  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
  <parameter name="TIMING_TDQSCKDS" value="450" />
  <parameter name="TIMING_TDQSCKDM" value="900" />
  <parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="TIMING_BOARD_TIS" value="0.0" />
  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
  <parameter name="ENUM_MEM_IF_TCCD" value="TCCD_4" />
  <parameter name="CV_ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
  <parameter name="NIOS_HEX_FILE_LOCATION" value="" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="" />
  <parameter name="AVL_BE_WIDTH" value="0" />
  <parameter name="AVL_MAX_SIZE" value="4" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
  <parameter name="TIMING_BOARD_TIH" value="0.0" />
  <parameter name="PLL_WRITE_CLK_MULT" value="0" />
  <parameter name="ENUM_CTL_USR_REFRESH" value="CTL_USR_REFRESH_DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="TIMING_BOARD_TDS" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="CV_ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
  <parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
  <parameter name="CFG_ERRCMD_FIFO_REG" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
  <parameter name="TIMING_BOARD_TDH" value="0.0" />
  <parameter name="PACKAGE_DESKEW" value="false" />
  <parameter name="PLL_NIOS_CLK_PHASE_DEG" value="0.0" />
  <parameter name="TRACKING_WATCH_TEST" value="false" />
  <parameter name="ENUM_DISABLE_MERGING" value="MERGING_ENABLED" />
  <parameter name="CV_ENUM_PRIORITY_7_0" value="WEIGHT_0" />
  <parameter name="ENUM_CTL_ADDR_ORDER" value="CHIP_BANK_ROW_COL" />
  <parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="AFI_DM_WIDTH" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_CONFIG_CLK_DIV" value="0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
  <parameter name="ENUM_CTL_ECC_ENABLED" value="CTL_ECC_DISABLED" />
  <parameter name="BYTE_ENABLE" value="true" />
  <parameter name="USE_SHADOW_REGS" value="false" />
  <parameter name="ENUM_MEM_IF_CS_WIDTH" value="MEM_IF_CS_WIDTH_1" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="MEM_IF_BANKADDR_WIDTH" value="0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="CV_ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
  <parameter name="ENUM_CAL_REQ" value="DISABLED" />
  <parameter name="ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
  <parameter name="MEM_IF_DQ_WIDTH" value="0" />
  <parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
  <parameter name="ADDR_CMD_DDR" value="0" />
  <parameter name="GENERIC_PLL" value="false" />
  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="ENABLE_NON_DES_CAL" value="false" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="MR3_MPR_AA" value="0" />
  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_1" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_0" value="0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_3" value="0" />
  <parameter name="MEM_TFAW_NS" value="30.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_2" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ" value="0.0" />
  <parameter name="AVL_DATA_WIDTH_PORT_5" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_4" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_3" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_2" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_1" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_0" value="0" />
  <parameter name="REF_CLK_NS" value="0.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_5" value="0" />
  <parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_4" value="0" />
  <parameter name="AFI_CLK_EN_WIDTH" value="0" />
  <parameter name="TIMING_TQH" value="0.38" />
  <parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_CLK_CACHE_VALID" value="false" />
  <parameter name="ENUM_MEM_IF_DWIDTH" value="MEM_IF_DWIDTH_32" />
  <parameter name="ENUM_RD_PORT_INFO_2" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="ENUM_RD_PORT_INFO_3" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_RD_PORT_INFO_4" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_MEM_IF_SPEEDBIN" value="DDR3_1066_6_6_6" />
  <parameter name="ENUM_RD_PORT_INFO_5" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="ENUM_CPORT0_TYPE" value="DISABLE" />
  <parameter name="CV_ENUM_PRIORITY_7_2" value="WEIGHT_0" />
  <parameter name="PLL_HR_CLK_MULT" value="0" />
  <parameter name="ENUM_MEM_IF_TRP" value="TRP_6" />
  <parameter name="CV_ENUM_PRIORITY_7_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_7_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_7_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_ENUM_PRIORITY_7_5" value="WEIGHT_0" />
  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="HHP_HPS" value="true" />
  <parameter name="CV_ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
  <parameter name="ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
  <parameter name="AVL_SIZE_WIDTH" value="0" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="" />
  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
  <parameter name="RDBUFFER_ADDR_WIDTH" value="6" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_MEM_IF_TRC" value="TRC_22" />
  <parameter name="ENUM_RD_PORT_INFO_0" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="ENUM_RD_PORT_INFO_1" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
  <parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
  <parameter name="DAT_DATA_WIDTH" value="32" />
  <parameter
     name="CPORT_TYPE_PORT"
     value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
  <parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
  <parameter name="AC_ROM_MR1_CALIB" value="" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="INTG_CYC_TO_RLD_JARS_5" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_4" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_3" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_2" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_1" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_0" value="1" />
  <parameter name="SPEED_GRADE" value="7" />
  <parameter name="CV_ENUM_PRIORITY_5_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_5_2" value="WEIGHT_0" />
  <parameter name="PLL_NIOS_CLK_FREQ" value="0.0" />
  <parameter name="ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
  <parameter name="CV_ENUM_PRIORITY_5_1" value="WEIGHT_0" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="0" />
  <parameter name="MEM_TRCD_NS" value="13.75" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="ENUM_PRIORITY_4_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_5" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_0" value="WEIGHT_0" />
  <parameter name="AFI_ADDR_WIDTH" value="0" />
  <parameter name="ENUM_PRIORITY_4_1" value="WEIGHT_0" />
  <parameter name="USE_HPS_DQS_TRACKING" value="false" />
  <parameter name="MEM_IF_COL_ADDR_WIDTH" value="0" />
  <parameter name="EXPORT_CSR_PORT" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="" />
  <parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
  <parameter name="MSB_WFIFO_PORT_0" value="5" />
  <parameter name="CV_LSB_RFIFO_PORT_5" value="5" />
  <parameter name="MSB_WFIFO_PORT_1" value="5" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="TIMING_TDS" value="30" />
  <parameter name="MSB_WFIFO_PORT_2" value="5" />
  <parameter name="qipEntries" value="" />
  <parameter name="MSB_WFIFO_PORT_3" value="5" />
  <parameter name="MEM_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="MSB_WFIFO_PORT_4" value="5" />
  <parameter name="MSB_WFIFO_PORT_5" value="5" />
  <parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
  <parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
  <parameter name="CFG_TCCD" value="0" />
  <parameter name="ENUM_MEM_IF_AL" value="AL_0" />
  <parameter name="ENUM_TEST_MODE" value="NORMAL_MODE" />
  <parameter name="MEM_CS_WIDTH" value="1" />
  <parameter name="CV_LSB_RFIFO_PORT_0" value="5" />
  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
  <parameter name="ENUM_CPORT0_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="CV_LSB_RFIFO_PORT_2" value="5" />
  <parameter name="CV_LSB_RFIFO_PORT_1" value="5" />
  <parameter name="TIMING_TDH" value="65" />
  <parameter name="AV_PORT_3_CONNECT_TO_CV_PORT" value="3" />
  <parameter name="CV_LSB_RFIFO_PORT_4" value="5" />
  <parameter name="SCC_DATA_WIDTH" value="0" />
  <parameter name="CV_LSB_RFIFO_PORT_3" value="5" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC" value="0" />
  <parameter name="CV_ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ" value="0.0" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="MEM_TREFI_US" value="7.8" />
  <parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
  <parameter name="USE_DQS_TRACKING" value="false" />
  <parameter name="MEM_LRDIMM_ENABLED" value="false" />
  <parameter name="TIMING_BOARD_TIS_APPLIED" value="0.0" />
  <parameter name="ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.01" />
  <parameter name="ENUM_MEM_IF_DQS_WIDTH" value="DQS_WIDTH_4" />
  <parameter name="CTL_ZQCAL_EN" value="false" />
  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
  <parameter name="ENUM_DFX_BYPASS_ENABLE" value="DFX_BYPASS_DISABLED" />
  <parameter name="AC_ROM_MR0_CALIB" value="" />
  <parameter name="MEM_TWR_NS" value="15.0" />
  <parameter name="ENUM_CTRL_WIDTH" value="DATA_WIDTH_64_BIT" />
  <parameter name="MEM_T_WL" value="0" />
  <parameter name="CV_ENUM_PRIORITY_5_4" value="WEIGHT_0" />
  <parameter name="AFI_WRITE_DQS_WIDTH" value="0" />
  <parameter name="CV_ENUM_PRIORITY_5_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_5_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_CPORT2_TYPE" value="DISABLE" />
  <parameter name="AFI_RLAT_WIDTH" value="0" />
  <parameter name="ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
  <parameter name="MEM_TRP" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR" value="0" />
  <parameter name="MEM_CLK_PS" value="0.0" />
  <parameter name="IS_ES_DEVICE_CACHE" value="false" />
  <parameter name="PLL_AFI_CLK_FREQ" value="0.0" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_1" value="EMPTY" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_2" value="EMPTY" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_3" value="EMPTY" />
  <parameter name="MEM_TRRD_NS" value="7.7" />
  <parameter name="CV_PORT_3_CONNECT_TO_AV_PORT" value="3" />
  <parameter name="ENUM_DELAY_BONDING" value="BONDING_LATENCY_0" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_0" value="EMPTY" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="DQS_IN_DELAY_MAX" value="-1" />
  <parameter name="LSB_WFIFO_PORT_4" value="5" />
  <parameter name="LSB_WFIFO_PORT_5" value="5" />
  <parameter name="LSB_WFIFO_PORT_2" value="5" />
  <parameter name="LSB_WFIFO_PORT_3" value="5" />
  <parameter name="MR0_CAS_LATENCY" value="3" />
  <parameter name="LSB_WFIFO_PORT_0" value="5" />
  <parameter name="LSB_WFIFO_PORT_1" value="5" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.05" />
  <parameter name="CFG_PDN_EXIT_CYCLES" value="0" />
  <parameter name="MR0_WR" value="4" />
  <parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="CV_ENUM_PRIORITY_3_0" value="WEIGHT_0" />
  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
  <parameter name="CV_ENUM_PRIORITY_3_2" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_3" value="WEIGHT_0" />
  <parameter name="PLL_MEM_CLK_FREQ_STR" value="" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
  <parameter name="LOCAL_ID_WIDTH" value="8" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="TIMING_TDQSS" value="0.25" />
  <parameter name="TIMING_TDQSQ" value="125" />
  <parameter name="ENUM_PRIORITY_2_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_PRIORITY_2_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_0" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="ENUM_PRIORITY_2_1" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="TIMING_TDQSH" value="0.35" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="USE_2X_FF" value="false" />
  <parameter name="MEM_ASR" value="Manual" />
  <parameter name="ENUM_RD_FIFO_IN_USE_2" value="FALSE" />
  <parameter name="PLL_DR_CLK_FREQ" value="0.0" />
  <parameter name="ENUM_RD_FIFO_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_RD_FIFO_IN_USE_0" value="FALSE" />
  <parameter name="ENUM_RD_FIFO_IN_USE_1" value="FALSE" />
  <parameter name="ADVANCED_CK_PHASES" value="false" />
  <parameter name="ENUM_REORDER_DATA" value="DATA_REORDERING" />
  <parameter name="NEXTGEN" value="true" />
  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
  <parameter name="PRIORITY_PORT_0" value="0" />
  <parameter name="MEM_T_RL" value="0" />
  <parameter name="MEM_TWR" value="0" />
  <parameter name="PRIORITY_PORT_2" value="0" />
  <parameter name="PRIORITY_PORT_1" value="0" />
  <parameter name="USE_DR_CLK" value="false" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="AC_ROM_MR3_MIRR" value="" />
  <parameter name="ENABLE_EMIT_JTAG_MASTER" value="false" />
  <parameter name="CPORT_TYPE_PORT_3" value="0" />
  <parameter name="MEM_IF_DQS_WIDTH" value="0" />
  <parameter name="CPORT_TYPE_PORT_2" value="0" />
  <parameter name="CPORT_TYPE_PORT_1" value="0" />
  <parameter name="TIMING_TIH" value="140" />
  <parameter name="CPORT_TYPE_PORT_0" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD" value="0" />
  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
  <parameter name="USE_AXI_ADAPTOR" value="false" />
  <parameter name="PRIORITY_PORT_4" value="0" />
  <parameter name="PRIORITY_PORT_3" value="0" />
  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
  <parameter name="PRIORITY_PORT_5" value="0" />
  <parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
  <parameter name="ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
  <parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
  <parameter name="ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
  <parameter name="ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
  <parameter name="NUM_OF_PORTS" value="1" />
  <parameter name="CV_ENUM_PRIORITY_3_5" value="WEIGHT_0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="false" />
  <parameter name="ENUM_CPORT3_TYPE" value="DISABLE" />
  <parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
  <parameter name="hps_parameter_map" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="CPORT_TYPE_PORT_5" value="0" />
  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
  <parameter name="CPORT_TYPE_PORT_4" value="0" />
  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="CV_MSB_RFIFO_PORT_1" value="5" />
  <parameter name="CV_MSB_RFIFO_PORT_0" value="5" />
  <parameter name="PLL_AFI_CLK_DIV" value="0" />
  <parameter name="ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
  <parameter name="CV_MSB_RFIFO_PORT_5" value="5" />
  <parameter name="MEM_TFAW" value="0" />
  <parameter name="CV_MSB_RFIFO_PORT_4" value="5" />
  <parameter name="CV_MSB_RFIFO_PORT_3" value="5" />
  <parameter name="CV_ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_MSB_RFIFO_PORT_2" value="5" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sdc"
       type="SDC"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_interface_generator/altera_interface_generator_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="soc_system_hps_0" as="fpga_interfaces" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 30 starting:altera_interface_generator "submodules/soc_system_hps_0_fpga_interfaces"</message>
   <message level="Info" culprit="fpga_interfaces"><![CDATA["<b>hps_0</b>" instantiated <b>altera_interface_generator</b> "<b>fpga_interfaces</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_hps_io:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=,AC_ROM_MR0_DLL_RESET_MIRR=,AC_ROM_MR0_MIRR=,AC_ROM_MR1=,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=,AC_ROM_MR2_MIRR=,AC_ROM_MR3=,AC_ROM_MR3_MIRR=,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=0,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=0,AFI_BANKADDR_WIDTH=0,AFI_CLK_EN_WIDTH=0,AFI_CLK_PAIR_COUNT=0,AFI_CONTROL_WIDTH=0,AFI_CS_WIDTH=0,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=0,AFI_DQ_WIDTH=0,AFI_ODT_WIDTH=0,AFI_RATE_RATIO=0,AFI_RLAT_WIDTH=0,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=0,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=0,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_DEVICE=5CSEMA5F31C6,AUTO_DEVICE_SPEEDGRADE=6,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=0,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=0,AVL_DATA_WIDTH=0,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=2,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=0,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=-1,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=-1,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=0,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=0,CFG_MEM_CLK_ENTRY_CYCLES=0,CFG_PDN_EXIT_CYCLES=0,CFG_PORT_WIDTH_READ_ODT_CHIP=0,CFG_PORT_WIDTH_WRITE_ODT_CHIP=0,CFG_POWER_SAVING_EXIT_CYCLES=0,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=0,CFG_STARVE_LIMIT=0,CFG_TCCD=0,CFG_TCCD_NS=2.5,CFG_TYPE=0,CFG_WRITE_ODT_CHIP=0,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=0,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=0,CTL_ECC_MULTIPLES_40_72=0,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=0,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=0,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=0,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=-1,DELAY_PER_DQS_EN_DCHAIN_TAP=-1,DELAY_PER_OPA_TAP=-1,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=false,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=-1,DQS_IN_DELAY_MAX=-1,DQS_PHASE_SHIFT=9000,DQ_DDR=0,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=true,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=0,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=-1,IO_OUT1_DELAY_MAX=-1,IO_OUT2_DELAY_MAX=-1,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=6,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=2.5,MEM_CLK_MAX_PS=2500.0,MEM_CLK_NS=0.0,MEM_CLK_PS=0.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=0,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=0,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=0,MEM_IF_ADDR_WIDTH_MIN=10,MEM_IF_BANKADDR_WIDTH=0,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=-1,MEM_IF_CK_WIDTH=0,MEM_IF_CLK_EN_WIDTH=0,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=0,MEM_IF_CONTROL_WIDTH=0,MEM_IF_CS_PER_DIMM=0,MEM_IF_CS_PER_RANK=0,MEM_IF_CS_WIDTH=0,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=0,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=0,MEM_IF_DQ_WIDTH=0,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=0,MEM_IF_ODT_WIDTH=0,MEM_IF_RD_TO_WR_TURNAROUND_OCT=0,MEM_IF_READ_DQS_WIDTH=0,MEM_IF_ROW_ADDR_WIDTH=0,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=0,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=2,MEM_TFAW=0,MEM_TFAW_NS=30.0,MEM_TINIT_CK=499,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=0,MEM_TRAS_NS=35.0,MEM_TRC=0,MEM_TRCD=0,MEM_TRCD_NS=13.75,MEM_TREFI=0,MEM_TREFI_US=7.8,MEM_TRFC=0,MEM_TRFC_NS=260.0,MEM_TRP=0,MEM_TRP_NS=13.75,MEM_TRRD=0,MEM_TRRD_NS=7.7,MEM_TRTP=0,MEM_TRTP_NS=7.5,MEM_TWR=0,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=,MEM_T_RL=0,MEM_T_WL=0,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=6,MR0_BL=2,MR0_BT=0,MR0_CAS_LATENCY=3,MR0_DLL=1,MR0_PD=0,MR0_WR=4,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=1,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=false,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=0,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=0,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=false,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=0,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=0,PLL_ADDR_CMD_CLK_DIV_CACHE=0,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=0.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=0.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=,PLL_ADDR_CMD_CLK_MULT=0,PLL_ADDR_CMD_CLK_MULT_CACHE=0,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=,PLL_AFI_CLK_DIV=0,PLL_AFI_CLK_DIV_CACHE=0,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=0.0,PLL_AFI_CLK_FREQ_CACHE=0.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=,PLL_AFI_CLK_MULT=0,PLL_AFI_CLK_MULT_CACHE=0,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=,PLL_AFI_HALF_CLK_DIV=0,PLL_AFI_HALF_CLK_DIV_CACHE=0,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=0.0,PLL_AFI_HALF_CLK_FREQ_CACHE=0.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=,PLL_AFI_HALF_CLK_MULT=0,PLL_AFI_HALF_CLK_MULT_CACHE=0,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=false,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=false,PLL_MEM_CLK_DIV=0,PLL_MEM_CLK_DIV_CACHE=0,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=0.0,PLL_MEM_CLK_FREQ_CACHE=0.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=,PLL_MEM_CLK_MULT=0,PLL_MEM_CLK_MULT_CACHE=0,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=0,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=0,PLL_WRITE_CLK_DIV_CACHE=0,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=0.0,PLL_WRITE_CLK_FREQ_CACHE=0.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=,PLL_WRITE_CLK_MULT=0,PLL_WRITE_CLK_MULT_CACHE=0,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=0.0,PLL_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_WRITE_CLK_PHASE_PS=0,PLL_WRITE_CLK_PHASE_PS_CACHE=0,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=0,PLL_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=0,RATE=Full,RATE_CACHE=Unknown,RDBUFFER_ADDR_WIDTH=6,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=false,REF_CLK_FREQ_MAX_CACHE=0.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=0.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=,REF_CLK_NS=0.0,REF_CLK_PS=0.0,REGISTER_C2P=false,SCC_DATA_WIDTH=0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=0,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=0.0,TB_MEM_IF_DQ_WIDTH=0,TB_MEM_IF_READ_DQS_WIDTH=0,TB_PLL_DLL_MASTER=true,TB_RATE=,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.05,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.01,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=-0.01,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.0,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.0,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.0,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.0,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=0,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=false,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,border_description=instances {sdio_inst {entity_name cyclonev_hps_peripheral_sdmmc location HPSPERIPHERALSDMMC_X87_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} emac1_inst {entity_name cyclonev_hps_peripheral_emac location HPSPERIPHERALEMAC_X77_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c1_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y65_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} spim1_inst {entity_name cyclonev_hps_peripheral_spi_master location HPSPERIPHERALSPIMASTER_X87_Y53_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} uart0_inst {entity_name cyclonev_hps_peripheral_uart location HPSPERIPHERALUART_X87_Y45_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} @orderednames {emac1_inst sdio_inst usb1_inst spim1_inst uart0_inst i2c0_inst i2c1_inst gpio_inst hps_sdram_inst} usb1_inst {entity_name cyclonev_hps_peripheral_usb location HPSPERIPHERALUSB_X55_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} gpio_inst {entity_name cyclonev_hps_peripheral_gpio location HPSPERIPHERALGPIO_X87_Y74_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps_sdram_inst {entity_name hps_sdram location {} signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c0_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y67_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD0]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD1]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD2]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD3]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD0] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_MDIO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDIO]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDC]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CTL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CTL]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CLK] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD1] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD2] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD3] -to *} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1]} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D1]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D4] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D4]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D5] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D5]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D6] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D6]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D7] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D7]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_CLK] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_STP]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_DIR] -to *} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_NXT] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_MOSI]} {set_false_path -from [get_ports hps_io_hps_io_spim1_inst_MISO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_SS0]} {set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO09] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO09]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO35] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO35]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO40] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO40]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO48] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO48]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO53] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO53]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO54] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO54]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO61] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO61]}} properties {SUPPRESS_SDRAM_SYNTH 0 GENERATE_ISW 1} bfm_types {} intermediate_wire_count 48 wires_to_fragments {{intermediate 9} {output sdio_inst:SDMMC_DATA_OE(2:2)} {intermediate 8} {output sdio_inst:SDMMC_DATA_O(2:2)} {intermediate 7} {output sdio_inst:SDMMC_DATA_OE(1:1)} {intermediate 6} {output sdio_inst:SDMMC_DATA_O(1:1)} {intermediate 5} {output sdio_inst:SDMMC_DATA_OE(0:0)} {intermediate 4} {output sdio_inst:SDMMC_DATA_O(0:0)} {intermediate 3} {output sdio_inst:SDMMC_CMD_OE(0:0)} {intermediate 2} {output sdio_inst:SDMMC_CMD_O(0:0)} {intermediate 1} {output emac1_inst:EMAC_GMII_MDO_OE(0:0)} {intermediate 0} {output emac1_inst:EMAC_GMII_MDO_O(0:0)} {intermediate 19} {output usb1_inst:USB_ULPI_DATA_OE(3:3)} {intermediate 18} {output usb1_inst:USB_ULPI_DATA_O(3:3)} {intermediate 17} {output usb1_inst:USB_ULPI_DATA_OE(2:2)} {intermediate 16} {output usb1_inst:USB_ULPI_DATA_O(2:2)} {intermediate 47} {output gpio_inst:GPIO2_PORTA_OE(3:3)} {intermediate 15} {output usb1_inst:USB_ULPI_DATA_OE(1:1)} {intermediate 46} {output gpio_inst:GPIO2_PORTA_O(3:3)} {intermediate 14} {output usb1_inst:USB_ULPI_DATA_O(1:1)} {intermediate 45} {output gpio_inst:GPIO1_PORTA_OE(25:25)} {intermediate 13} {output usb1_inst:USB_ULPI_DATA_OE(0:0)} {intermediate 44} {output gpio_inst:GPIO1_PORTA_O(25:25)} {intermediate 12} {output usb1_inst:USB_ULPI_DATA_O(0:0)} {intermediate 43} {output gpio_inst:GPIO1_PORTA_OE(24:24)} {intermediate 11} {output sdio_inst:SDMMC_DATA_OE(3:3)} {intermediate 42} {output gpio_inst:GPIO1_PORTA_O(24:24)} {intermediate 10} {output sdio_inst:SDMMC_DATA_O(3:3)} {intermediate 41} {output gpio_inst:GPIO1_PORTA_OE(19:19)} {intermediate 40} {output gpio_inst:GPIO1_PORTA_O(19:19)} {intermediate 39} {output gpio_inst:GPIO1_PORTA_OE(11:11)} {intermediate 38} {output gpio_inst:GPIO1_PORTA_O(11:11)} {intermediate 37} {output gpio_inst:GPIO1_PORTA_OE(6:6)} {intermediate 36} {output gpio_inst:GPIO1_PORTA_O(6:6)} {intermediate 35} {output gpio_inst:GPIO0_PORTA_OE(9:9)} {intermediate 34} {output gpio_inst:GPIO0_PORTA_O(9:9)} {intermediate 33} {output i2c1_inst:I2C_CLK_OE(0:0)} {intermediate 32} {output i2c1_inst:I2C_DATA_OE(0:0)} {intermediate 31} {output i2c0_inst:I2C_CLK_OE(0:0)} {intermediate 30} {output i2c0_inst:I2C_DATA_OE(0:0)} {intermediate 29} {output spim1_inst:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 28} {output spim1_inst:SPI_MASTER_TXD(0:0)} {intermediate 27} {output usb1_inst:USB_ULPI_DATA_OE(7:7)} {intermediate 26} {output usb1_inst:USB_ULPI_DATA_O(7:7)} {intermediate 25} {output usb1_inst:USB_ULPI_DATA_OE(6:6)} {intermediate 24} {output usb1_inst:USB_ULPI_DATA_O(6:6)} {intermediate 23} {output usb1_inst:USB_ULPI_DATA_OE(5:5)} {intermediate 22} {output usb1_inst:USB_ULPI_DATA_O(5:5)} {intermediate 21} {output usb1_inst:USB_ULPI_DATA_OE(4:4)} {intermediate 20} {output usb1_inst:USB_ULPI_DATA_O(4:4)}} interfaces {@orderednames {memory hps_io} memory {properties {} type conduit direction end signals {@orderednames {mem_a mem_ba mem_ck mem_ck_n mem_cke mem_cs_n mem_ras_n mem_cas_n mem_we_n mem_reset_n mem_dq mem_dqs mem_dqs_n mem_odt mem_dm oct_rzqin} mem_a {fragments {} properties {} internal_name mem_a width 15 instance_name hps_sdram_inst direction Output role mem_a} mem_ba {fragments {} properties {} internal_name mem_ba width 3 instance_name hps_sdram_inst direction Output role mem_ba} mem_ck {fragments {} properties {} internal_name mem_ck width 1 instance_name hps_sdram_inst direction Output role mem_ck} mem_ck_n {fragments {} properties {} internal_name mem_ck_n width 1 instance_name hps_sdram_inst direction Output role mem_ck_n} mem_cke {fragments {} properties {} internal_name mem_cke width 1 instance_name hps_sdram_inst direction Output role mem_cke} mem_cs_n {fragments {} properties {} internal_name mem_cs_n width 1 instance_name hps_sdram_inst direction Output role mem_cs_n} mem_ras_n {fragments {} properties {} internal_name mem_ras_n width 1 instance_name hps_sdram_inst direction Output role mem_ras_n} mem_cas_n {fragments {} properties {} internal_name mem_cas_n width 1 instance_name hps_sdram_inst direction Output role mem_cas_n} mem_we_n {fragments {} properties {} internal_name mem_we_n width 1 instance_name hps_sdram_inst direction Output role mem_we_n} mem_reset_n {fragments {} properties {} internal_name mem_reset_n width 1 instance_name hps_sdram_inst direction Output role mem_reset_n} mem_dq {fragments {} properties {} internal_name mem_dq width 32 instance_name hps_sdram_inst direction Bidir role mem_dq} mem_dqs {fragments {} properties {} internal_name mem_dqs width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs} mem_dqs_n {fragments {} properties {} internal_name mem_dqs_n width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs_n} mem_odt {fragments {} properties {} internal_name mem_odt width 1 instance_name hps_sdram_inst direction Output role mem_odt} mem_dm {fragments {} properties {} internal_name mem_dm width 4 instance_name hps_sdram_inst direction Output role mem_dm} oct_rzqin {fragments {} properties {} internal_name oct_rzqin width 1 instance_name hps_sdram_inst direction Input role oct_rzqin}}} hps_io {properties {} type conduit direction input signals {@orderednames {hps_io_emac1_inst_TX_CLK hps_io_emac1_inst_TXD0 hps_io_emac1_inst_TXD1 hps_io_emac1_inst_TXD2 hps_io_emac1_inst_TXD3 hps_io_emac1_inst_RXD0 hps_io_emac1_inst_MDIO hps_io_emac1_inst_MDC hps_io_emac1_inst_RX_CTL hps_io_emac1_inst_TX_CTL hps_io_emac1_inst_RX_CLK hps_io_emac1_inst_RXD1 hps_io_emac1_inst_RXD2 hps_io_emac1_inst_RXD3 hps_io_sdio_inst_CMD hps_io_sdio_inst_D0 hps_io_sdio_inst_D1 hps_io_sdio_inst_CLK hps_io_sdio_inst_D2 hps_io_sdio_inst_D3 hps_io_usb1_inst_D0 hps_io_usb1_inst_D1 hps_io_usb1_inst_D2 hps_io_usb1_inst_D3 hps_io_usb1_inst_D4 hps_io_usb1_inst_D5 hps_io_usb1_inst_D6 hps_io_usb1_inst_D7 hps_io_usb1_inst_CLK hps_io_usb1_inst_STP hps_io_usb1_inst_DIR hps_io_usb1_inst_NXT hps_io_spim1_inst_CLK hps_io_spim1_inst_MOSI hps_io_spim1_inst_MISO hps_io_spim1_inst_SS0 hps_io_uart0_inst_RX hps_io_uart0_inst_TX hps_io_i2c0_inst_SDA hps_io_i2c0_inst_SCL hps_io_i2c1_inst_SDA hps_io_i2c1_inst_SCL hps_io_gpio_inst_GPIO09 hps_io_gpio_inst_GPIO35 hps_io_gpio_inst_GPIO40 hps_io_gpio_inst_GPIO48 hps_io_gpio_inst_GPIO53 hps_io_gpio_inst_GPIO54 hps_io_gpio_inst_GPIO61} hps_io_emac1_inst_TX_CLK {fragments emac1_inst:EMAC_CLK_TX(0:0) properties {} internal_name hps_io_emac1_inst_TX_CLK width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CLK} hps_io_emac1_inst_TXD0 {fragments emac1_inst:EMAC_PHY_TXD(0:0) properties {} internal_name hps_io_emac1_inst_TXD0 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD0} hps_io_emac1_inst_TXD1 {fragments emac1_inst:EMAC_PHY_TXD(1:1) properties {} internal_name hps_io_emac1_inst_TXD1 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD1} hps_io_emac1_inst_TXD2 {fragments emac1_inst:EMAC_PHY_TXD(2:2) properties {} internal_name hps_io_emac1_inst_TXD2 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD2} hps_io_emac1_inst_TXD3 {fragments emac1_inst:EMAC_PHY_TXD(3:3) properties {} internal_name hps_io_emac1_inst_TXD3 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD3} hps_io_emac1_inst_RXD0 {fragments emac1_inst:EMAC_PHY_RXD(0:0) properties {} internal_name hps_io_emac1_inst_RXD0 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD0} hps_io_emac1_inst_MDIO {fragments emac1_inst:EMAC_GMII_MDO_I(0:0) properties {} internal_name hps_io_emac1_inst_MDIO width 1 instance_name hps_io tristate_output {{intermediate 1} {intermediate 0}} direction bidir role hps_io_emac1_inst_MDIO} hps_io_emac1_inst_MDC {fragments emac1_inst:EMAC_GMII_MDC(0:0) properties {} internal_name hps_io_emac1_inst_MDC width 1 instance_name hps_io direction output role hps_io_emac1_inst_MDC} hps_io_emac1_inst_RX_CTL {fragments emac1_inst:EMAC_PHY_RXDV(0:0) properties {} internal_name hps_io_emac1_inst_RX_CTL width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CTL} hps_io_emac1_inst_TX_CTL {fragments emac1_inst:EMAC_PHY_TX_OE(0:0) properties {} internal_name hps_io_emac1_inst_TX_CTL width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CTL} hps_io_emac1_inst_RX_CLK {fragments emac1_inst:EMAC_CLK_RX(0:0) properties {} internal_name hps_io_emac1_inst_RX_CLK width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CLK} hps_io_emac1_inst_RXD1 {fragments emac1_inst:EMAC_PHY_RXD(1:1) properties {} internal_name hps_io_emac1_inst_RXD1 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD1} hps_io_emac1_inst_RXD2 {fragments emac1_inst:EMAC_PHY_RXD(2:2) properties {} internal_name hps_io_emac1_inst_RXD2 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD2} hps_io_emac1_inst_RXD3 {fragments emac1_inst:EMAC_PHY_RXD(3:3) properties {} internal_name hps_io_emac1_inst_RXD3 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD3} hps_io_sdio_inst_CMD {fragments sdio_inst:SDMMC_CMD_I(0:0) properties {} internal_name hps_io_sdio_inst_CMD width 1 instance_name hps_io tristate_output {{intermediate 3} {intermediate 2}} direction bidir role hps_io_sdio_inst_CMD} hps_io_sdio_inst_D0 {fragments sdio_inst:SDMMC_DATA_I(0:0) properties {} internal_name hps_io_sdio_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 5} {intermediate 4}} direction bidir role hps_io_sdio_inst_D0} hps_io_sdio_inst_D1 {fragments sdio_inst:SDMMC_DATA_I(1:1) properties {} internal_name hps_io_sdio_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 7} {intermediate 6}} direction bidir role hps_io_sdio_inst_D1} hps_io_sdio_inst_CLK {fragments sdio_inst:SDMMC_CCLK(0:0) properties {} internal_name hps_io_sdio_inst_CLK width 1 instance_name hps_io direction output role hps_io_sdio_inst_CLK} hps_io_sdio_inst_D2 {fragments sdio_inst:SDMMC_DATA_I(2:2) properties {} internal_name hps_io_sdio_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 9} {intermediate 8}} direction bidir role hps_io_sdio_inst_D2} hps_io_sdio_inst_D3 {fragments sdio_inst:SDMMC_DATA_I(3:3) properties {} internal_name hps_io_sdio_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 11} {intermediate 10}} direction bidir role hps_io_sdio_inst_D3} hps_io_usb1_inst_D0 {fragments usb1_inst:USB_ULPI_DATA_I(0:0) properties {} internal_name hps_io_usb1_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 13} {intermediate 12}} direction bidir role hps_io_usb1_inst_D0} hps_io_usb1_inst_D1 {fragments usb1_inst:USB_ULPI_DATA_I(1:1) properties {} internal_name hps_io_usb1_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 15} {intermediate 14}} direction bidir role hps_io_usb1_inst_D1} hps_io_usb1_inst_D2 {fragments usb1_inst:USB_ULPI_DATA_I(2:2) properties {} internal_name hps_io_usb1_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 17} {intermediate 16}} direction bidir role hps_io_usb1_inst_D2} hps_io_usb1_inst_D3 {fragments usb1_inst:USB_ULPI_DATA_I(3:3) properties {} internal_name hps_io_usb1_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 19} {intermediate 18}} direction bidir role hps_io_usb1_inst_D3} hps_io_usb1_inst_D4 {fragments usb1_inst:USB_ULPI_DATA_I(4:4) properties {} internal_name hps_io_usb1_inst_D4 width 1 instance_name hps_io tristate_output {{intermediate 21} {intermediate 20}} direction bidir role hps_io_usb1_inst_D4} hps_io_usb1_inst_D5 {fragments usb1_inst:USB_ULPI_DATA_I(5:5) properties {} internal_name hps_io_usb1_inst_D5 width 1 instance_name hps_io tristate_output {{intermediate 23} {intermediate 22}} direction bidir role hps_io_usb1_inst_D5} hps_io_usb1_inst_D6 {fragments usb1_inst:USB_ULPI_DATA_I(6:6) properties {} internal_name hps_io_usb1_inst_D6 width 1 instance_name hps_io tristate_output {{intermediate 25} {intermediate 24}} direction bidir role hps_io_usb1_inst_D6} hps_io_usb1_inst_D7 {fragments usb1_inst:USB_ULPI_DATA_I(7:7) properties {} internal_name hps_io_usb1_inst_D7 width 1 instance_name hps_io tristate_output {{intermediate 27} {intermediate 26}} direction bidir role hps_io_usb1_inst_D7} hps_io_usb1_inst_CLK {fragments usb1_inst:USB_ULPI_CLK(0:0) properties {} internal_name hps_io_usb1_inst_CLK width 1 instance_name hps_io direction input role hps_io_usb1_inst_CLK} hps_io_usb1_inst_STP {fragments usb1_inst:USB_ULPI_STP(0:0) properties {} internal_name hps_io_usb1_inst_STP width 1 instance_name hps_io direction output role hps_io_usb1_inst_STP} hps_io_usb1_inst_DIR {fragments usb1_inst:USB_ULPI_DIR(0:0) properties {} internal_name hps_io_usb1_inst_DIR width 1 instance_name hps_io direction input role hps_io_usb1_inst_DIR} hps_io_usb1_inst_NXT {fragments usb1_inst:USB_ULPI_NXT(0:0) properties {} internal_name hps_io_usb1_inst_NXT width 1 instance_name hps_io direction input role hps_io_usb1_inst_NXT} hps_io_spim1_inst_CLK {fragments spim1_inst:SPI_MASTER_SCLK(0:0) properties {} internal_name hps_io_spim1_inst_CLK width 1 instance_name hps_io direction output role hps_io_spim1_inst_CLK} hps_io_spim1_inst_MOSI {fragments {} properties {} internal_name hps_io_spim1_inst_MOSI width 1 instance_name hps_io tristate_output {{intermediate 29} {intermediate 28}} direction output role hps_io_spim1_inst_MOSI} hps_io_spim1_inst_MISO {fragments spim1_inst:SPI_MASTER_RXD(0:0) properties {} internal_name hps_io_spim1_inst_MISO width 1 instance_name hps_io direction input role hps_io_spim1_inst_MISO} hps_io_spim1_inst_SS0 {fragments spim1_inst:SPI_MASTER_SS_0_N(0:0) properties {} internal_name hps_io_spim1_inst_SS0 width 1 instance_name hps_io direction output role hps_io_spim1_inst_SS0} hps_io_uart0_inst_RX {fragments uart0_inst:UART_RXD(0:0) properties {} internal_name hps_io_uart0_inst_RX width 1 instance_name hps_io direction input role hps_io_uart0_inst_RX} hps_io_uart0_inst_TX {fragments uart0_inst:UART_TXD(0:0) properties {} internal_name hps_io_uart0_inst_TX width 1 instance_name hps_io direction output role hps_io_uart0_inst_TX} hps_io_i2c0_inst_SDA {fragments i2c0_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c0_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 30} {}} direction bidir role hps_io_i2c0_inst_SDA} hps_io_i2c0_inst_SCL {fragments i2c0_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c0_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 31} {}} direction bidir role hps_io_i2c0_inst_SCL} hps_io_i2c1_inst_SDA {fragments i2c1_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c1_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 32} {}} direction bidir role hps_io_i2c1_inst_SDA} hps_io_i2c1_inst_SCL {fragments i2c1_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c1_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 33} {}} direction bidir role hps_io_i2c1_inst_SCL} hps_io_gpio_inst_GPIO09 {fragments gpio_inst:GPIO0_PORTA_I(9:9) properties {} internal_name hps_io_gpio_inst_GPIO09 width 1 instance_name hps_io tristate_output {{intermediate 35} {intermediate 34}} direction bidir role hps_io_gpio_inst_GPIO09} hps_io_gpio_inst_GPIO35 {fragments gpio_inst:GPIO1_PORTA_I(6:6) properties {} internal_name hps_io_gpio_inst_GPIO35 width 1 instance_name hps_io tristate_output {{intermediate 37} {intermediate 36}} direction bidir role hps_io_gpio_inst_GPIO35} hps_io_gpio_inst_GPIO40 {fragments gpio_inst:GPIO1_PORTA_I(11:11) properties {} internal_name hps_io_gpio_inst_GPIO40 width 1 instance_name hps_io tristate_output {{intermediate 39} {intermediate 38}} direction bidir role hps_io_gpio_inst_GPIO40} hps_io_gpio_inst_GPIO48 {fragments gpio_inst:GPIO1_PORTA_I(19:19) properties {} internal_name hps_io_gpio_inst_GPIO48 width 1 instance_name hps_io tristate_output {{intermediate 41} {intermediate 40}} direction bidir role hps_io_gpio_inst_GPIO48} hps_io_gpio_inst_GPIO53 {fragments gpio_inst:GPIO1_PORTA_I(24:24) properties {} internal_name hps_io_gpio_inst_GPIO53 width 1 instance_name hps_io tristate_output {{intermediate 43} {intermediate 42}} direction bidir role hps_io_gpio_inst_GPIO53} hps_io_gpio_inst_GPIO54 {fragments gpio_inst:GPIO1_PORTA_I(25:25) properties {} internal_name hps_io_gpio_inst_GPIO54 width 1 instance_name hps_io tristate_output {{intermediate 45} {intermediate 44}} direction bidir role hps_io_gpio_inst_GPIO54} hps_io_gpio_inst_GPIO61 {fragments gpio_inst:GPIO2_PORTA_I(3:3) properties {} internal_name hps_io_gpio_inst_GPIO61 width 1 instance_name hps_io tristate_output {{intermediate 47} {intermediate 46}} direction bidir role hps_io_gpio_inst_GPIO61}}}} raw_assign_sim_style {},hps_parameter_map=AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 1.25 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 200000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 32 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 4 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 1000.0 MEM_TRCD 6 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA5F31C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 14 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 25.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 64 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 125 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.02 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 32 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 25.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 25000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 2500.0 periph_pll_vco_hz 1000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 30 PLL_WRITE_CLK_PHASE_PS_CACHE 1875 UART0_PinMuxing {HPS I/O Set 0} sdmmc_clk_hz 200000000 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode RGMII NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz 1600000000 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 2.5 PLL_AFI_CLK_MULT_CACHE 32 PLL_ADDR_CMD_CLK_DIV 2 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 3 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 32 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {45000 ps} PLL_AFI_CLK_DIV 2 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 13.75 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 400.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 2 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.8 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.08 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 25000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 200.0 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 180 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {25.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.03 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 6 TIMING_TIH 140 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 0 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing {HPS I/O Set 0} desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 200000000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_8 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 1875 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 200.0 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 30 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 6 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 65 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {2500 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 20 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 32 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 64 PLL_AFI_PHY_CLK_FREQ 400.0 periph_nand_sdmmc_clk_mhz 200.0 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000110 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No Yes No No No No Yes No No No No No No No Yes No No No No Yes Yes No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 4 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {400.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode I2C IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 12500000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.09 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 200000000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 35.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 2 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {2500 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED true TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode {No Flow Control} S2FCLK_USER0CLK_FREQ_HZ 97368421 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 800.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 4 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 1875 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 8 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 10 dbg_timer_clk_hz 25000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode {Single Slave Select} hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 97.368421 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM RZQ/4 AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 40000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_6 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 13.75 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 8 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.16 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 40.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 2 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 400.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_6 MR2_RTT_WR 1 MEM_TCL 11 GPIO_Pin_Used_DERIVED true JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 104 USE_2X_FF false ENUM_MEM_IF_TRC TRC_20 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 27 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 50000000 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable true desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 2 F2SDRAM_Width {} dbg_clk_hz 12500000 PLL_AFI_CLK_FREQ 400.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.18 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 400.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 66.6666666667 dbg_timer_clk_mhz 25.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {2500 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 9 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 0 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {1875 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 15 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 100.0 PLL_AFI_HALF_CLK_MULT_CACHE 32 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 32 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 400.0 AFI_WRITE_DQS_WIDTH 4 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 200.0 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 25000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.16 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 10 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 200.0 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz 1600.0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.33 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {1875 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {2500 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 15 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {1875 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0010011101000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/7 MEM_IF_DM_WIDTH 4 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.7 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 32 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 32 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 30.0 DELAY_PER_OPA_TAP 312 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing {HPS I/O Set 0} MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {2500 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 12.5 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 6000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 2 ENUM_MEM_IF_TCL TCL_11 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR JEDEC device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing {HPS I/O Set 0} CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_4 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 2 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 97.368421 MR2_CWL 3 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 211 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 39 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 12.5 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 73 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 400.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 15 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 1 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 32000 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 MR0_BT 0 PLL_CONFIG_CLK_FREQ 22.2222222222 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 1 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {400.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 32 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 25.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR RZQ/4 TIMING_TDQSCK 255 REF_CLK_FREQ_CACHE 25.0 AC_ROM_MR0_DLL_RESET 0010101110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {15000 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0010001101001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 12 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {400.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing {HPS I/O Set 0} MEM_TREFI 3120 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 32 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 25.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.09 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {2500 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 4 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 10 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_6 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 50000000 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.165 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {2500 ps} emac1_clk_mhz 250.0 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 500 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 32 TIMING_BOARD_SKEW_WITHIN_DQS 0.01 ENUM_MEM_IF_TRAS TRAS_14 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 1 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.03 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 7 H2F_LW_AXI_CLOCK_FREQ 50000000 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {400.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 2 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {1875 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 12500000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 250000000 eosc2_clk_mhz 25.0 PLL_MEM_CLK_DIV_CACHE 2 periph_base_clk_mhz 200.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_32 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 8 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.24 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing {HPS I/O Set 0} INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 400.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 25.0 desired_cfg_clk_hz 97368421 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 2 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 200000000 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 4 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {5000 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 8 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 11 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 200000000 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 6249 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0001000011000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode I2C quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 3120 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 1875 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {400.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 4 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 260.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY true ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 4 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 1 pin_muxing_check {Cyclone V+5CSEMA5F31C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 100000000 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 2 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 200000 PLL_WRITE_CLK_MULT_CACHE 32 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 400.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 4 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 50.0 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} USB1.D0 USB1.D1 USB1.D2 USB1.D3 USB1.D4 USB1.D5 USB1.D6 USB1.D7 {} USB1.CLK USB1.STP USB1.DIR USB1.NXT EMAC1.TX_CLK EMAC1.TXD0 EMAC1.TXD1 EMAC1.TXD2 EMAC1.TXD3 EMAC1.RXD0 EMAC1.MDIO EMAC1.MDC EMAC1.RX_CTL EMAC1.TX_CTL EMAC1.RX_CLK EMAC1.RXD1 EMAC1.RXD2 EMAC1.RXD3 {} {} {} {} {} {} {} {} SDIO.CMD {} SDIO.D0 SDIO.D1 {} {} {} {} {} SDIO.CLK SDIO.D2 SDIO.D3 {} UART0.RX UART0.TX I2C1.SDA I2C1.SCL {} {} I2C0.SDA I2C0.SCL {} {} {} {} {} {} SPIM1.CLK SPIM1.MOSI SPIM1.MISO SPIM1.SS0} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 8 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 400.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 8 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 32 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0001000011000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000000000110 TB_MEM_CLK_FREQ 400.0 AC_ROM_MR0 0010001110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 18000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 400.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {2500 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 12.5 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 5 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_4 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing {HPS I/O Set 0} CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 25000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {5000 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode SDR ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.4 dbg_base_clk_hz 25000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 400.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 2 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 1250.0 S2FCLK_USER1CLK_Enable true SDIO_Mode {4-bit Data} desired_qspi_clk_mhz 400.0 MEM_TRFC 104 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2(altera_interface_generator:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=,AC_ROM_MR0_DLL_RESET_MIRR=,AC_ROM_MR0_MIRR=,AC_ROM_MR1=,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=,AC_ROM_MR2_MIRR=,AC_ROM_MR3=,AC_ROM_MR3_MIRR=,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=0,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=0,AFI_BANKADDR_WIDTH=0,AFI_CLK_EN_WIDTH=0,AFI_CLK_PAIR_COUNT=0,AFI_CONTROL_WIDTH=0,AFI_CS_WIDTH=0,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=0,AFI_DQ_WIDTH=0,AFI_ODT_WIDTH=0,AFI_RATE_RATIO=0,AFI_RLAT_WIDTH=0,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=0,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=0,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=0,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=0,AVL_DATA_WIDTH=0,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=2,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=0,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=-1,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=-1,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=0,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=0,CFG_MEM_CLK_ENTRY_CYCLES=0,CFG_PDN_EXIT_CYCLES=0,CFG_PORT_WIDTH_READ_ODT_CHIP=0,CFG_PORT_WIDTH_WRITE_ODT_CHIP=0,CFG_POWER_SAVING_EXIT_CYCLES=0,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=0,CFG_STARVE_LIMIT=0,CFG_TCCD=0,CFG_TCCD_NS=2.5,CFG_TYPE=0,CFG_WRITE_ODT_CHIP=0,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=0,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=0,CTL_ECC_MULTIPLES_40_72=0,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=0,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=0,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=0,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=-1,DELAY_PER_DQS_EN_DCHAIN_TAP=-1,DELAY_PER_OPA_TAP=-1,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=false,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=-1,DQS_IN_DELAY_MAX=-1,DQS_PHASE_SHIFT=9000,DQ_DDR=0,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=true,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=0,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=-1,IO_OUT1_DELAY_MAX=-1,IO_OUT2_DELAY_MAX=-1,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=6,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=2.5,MEM_CLK_MAX_PS=2500.0,MEM_CLK_NS=0.0,MEM_CLK_PS=0.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=0,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=0,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=0,MEM_IF_ADDR_WIDTH_MIN=10,MEM_IF_BANKADDR_WIDTH=0,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=-1,MEM_IF_CK_WIDTH=0,MEM_IF_CLK_EN_WIDTH=0,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=0,MEM_IF_CONTROL_WIDTH=0,MEM_IF_CS_PER_DIMM=0,MEM_IF_CS_PER_RANK=0,MEM_IF_CS_WIDTH=0,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=0,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=0,MEM_IF_DQ_WIDTH=0,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=0,MEM_IF_ODT_WIDTH=0,MEM_IF_RD_TO_WR_TURNAROUND_OCT=0,MEM_IF_READ_DQS_WIDTH=0,MEM_IF_ROW_ADDR_WIDTH=0,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=0,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=2,MEM_TFAW=0,MEM_TFAW_NS=30.0,MEM_TINIT_CK=499,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=0,MEM_TRAS_NS=35.0,MEM_TRC=0,MEM_TRCD=0,MEM_TRCD_NS=13.75,MEM_TREFI=0,MEM_TREFI_US=7.8,MEM_TRFC=0,MEM_TRFC_NS=260.0,MEM_TRP=0,MEM_TRP_NS=13.75,MEM_TRRD=0,MEM_TRRD_NS=7.7,MEM_TRTP=0,MEM_TRTP_NS=7.5,MEM_TWR=0,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=,MEM_T_RL=0,MEM_T_WL=0,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=6,MR0_BL=2,MR0_BT=0,MR0_CAS_LATENCY=3,MR0_DLL=1,MR0_PD=0,MR0_WR=4,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=1,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=false,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=0,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=0,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=false,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=0,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=0,PLL_ADDR_CMD_CLK_DIV_CACHE=0,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=0.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=0.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=,PLL_ADDR_CMD_CLK_MULT=0,PLL_ADDR_CMD_CLK_MULT_CACHE=0,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=,PLL_AFI_CLK_DIV=0,PLL_AFI_CLK_DIV_CACHE=0,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=0.0,PLL_AFI_CLK_FREQ_CACHE=0.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=,PLL_AFI_CLK_MULT=0,PLL_AFI_CLK_MULT_CACHE=0,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=,PLL_AFI_HALF_CLK_DIV=0,PLL_AFI_HALF_CLK_DIV_CACHE=0,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=0.0,PLL_AFI_HALF_CLK_FREQ_CACHE=0.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=,PLL_AFI_HALF_CLK_MULT=0,PLL_AFI_HALF_CLK_MULT_CACHE=0,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=false,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=false,PLL_MEM_CLK_DIV=0,PLL_MEM_CLK_DIV_CACHE=0,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=0.0,PLL_MEM_CLK_FREQ_CACHE=0.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=,PLL_MEM_CLK_MULT=0,PLL_MEM_CLK_MULT_CACHE=0,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=0,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=0,PLL_WRITE_CLK_DIV_CACHE=0,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=0.0,PLL_WRITE_CLK_FREQ_CACHE=0.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=,PLL_WRITE_CLK_MULT=0,PLL_WRITE_CLK_MULT_CACHE=0,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=0.0,PLL_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_WRITE_CLK_PHASE_PS=0,PLL_WRITE_CLK_PHASE_PS_CACHE=0,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=0,PLL_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=0,RATE=Full,RATE_CACHE=Unknown,RDBUFFER_ADDR_WIDTH=6,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=false,REF_CLK_FREQ_MAX_CACHE=0.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=0.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=,REF_CLK_NS=0.0,REF_CLK_PS=0.0,REGISTER_C2P=false,SCC_DATA_WIDTH=0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=0,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=0.0,TB_MEM_IF_DQ_WIDTH=0,TB_MEM_IF_READ_DQS_WIDTH=0,TB_PLL_DLL_MASTER=true,TB_RATE=,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.05,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.01,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=-0.01,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.0,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.0,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.0,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.0,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=0,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=false,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,device=5CSEMA5F31C6,hps_parameter_map=AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 1.25 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 200000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 32 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 4 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 1000.0 MEM_TRCD 6 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA5F31C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 14 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 25.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 64 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 125 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.02 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 32 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 25.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 25000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 2500.0 periph_pll_vco_hz 1000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 30 PLL_WRITE_CLK_PHASE_PS_CACHE 1875 UART0_PinMuxing {HPS I/O Set 0} sdmmc_clk_hz 200000000 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode RGMII NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz 1600000000 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 2.5 PLL_AFI_CLK_MULT_CACHE 32 PLL_ADDR_CMD_CLK_DIV 2 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 3 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 32 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {45000 ps} PLL_AFI_CLK_DIV 2 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 13.75 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 400.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 2 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.8 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.08 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 25000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 200.0 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 180 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {25.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.03 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 6 TIMING_TIH 140 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 0 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing {HPS I/O Set 0} desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 200000000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_8 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 1875 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 200.0 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 30 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 6 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 65 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {2500 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 20 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 32 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 64 PLL_AFI_PHY_CLK_FREQ 400.0 periph_nand_sdmmc_clk_mhz 200.0 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000110 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No Yes No No No No Yes No No No No No No No Yes No No No No Yes Yes No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 4 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {400.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode I2C IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 12500000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.09 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 200000000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 35.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 2 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {2500 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED true TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode {No Flow Control} S2FCLK_USER0CLK_FREQ_HZ 97368421 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 800.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 4 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 1875 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 8 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 10 dbg_timer_clk_hz 25000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode {Single Slave Select} hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 97.368421 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM RZQ/4 AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 40000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_6 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 13.75 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 8 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.16 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 40.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 2 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 400.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_6 MR2_RTT_WR 1 MEM_TCL 11 GPIO_Pin_Used_DERIVED true JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 104 USE_2X_FF false ENUM_MEM_IF_TRC TRC_20 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 27 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 50000000 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable true desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 2 F2SDRAM_Width {} dbg_clk_hz 12500000 PLL_AFI_CLK_FREQ 400.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.18 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 400.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 66.6666666667 dbg_timer_clk_mhz 25.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {2500 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 9 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 0 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {1875 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 15 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 100.0 PLL_AFI_HALF_CLK_MULT_CACHE 32 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 32 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 400.0 AFI_WRITE_DQS_WIDTH 4 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 200.0 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 25000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.16 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 10 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 200.0 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz 1600.0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.33 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {1875 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {2500 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 15 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {1875 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0010011101000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/7 MEM_IF_DM_WIDTH 4 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.7 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 32 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 32 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 30.0 DELAY_PER_OPA_TAP 312 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing {HPS I/O Set 0} MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {2500 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 12.5 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 6000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 2 ENUM_MEM_IF_TCL TCL_11 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR JEDEC device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing {HPS I/O Set 0} CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_4 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 2 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 97.368421 MR2_CWL 3 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 211 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 39 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 12.5 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 73 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 400.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 15 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 1 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 32000 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 MR0_BT 0 PLL_CONFIG_CLK_FREQ 22.2222222222 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 1 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {400.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 32 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 25.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR RZQ/4 TIMING_TDQSCK 255 REF_CLK_FREQ_CACHE 25.0 AC_ROM_MR0_DLL_RESET 0010101110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {15000 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0010001101001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 12 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {400.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing {HPS I/O Set 0} MEM_TREFI 3120 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 32 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 25.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.09 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {2500 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 4 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 10 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_6 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 50000000 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.165 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {2500 ps} emac1_clk_mhz 250.0 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 500 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 32 TIMING_BOARD_SKEW_WITHIN_DQS 0.01 ENUM_MEM_IF_TRAS TRAS_14 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 1 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.03 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 7 H2F_LW_AXI_CLOCK_FREQ 50000000 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {400.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 2 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {1875 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 12500000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 250000000 eosc2_clk_mhz 25.0 PLL_MEM_CLK_DIV_CACHE 2 periph_base_clk_mhz 200.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_32 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 8 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.24 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing {HPS I/O Set 0} INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 400.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 25.0 desired_cfg_clk_hz 97368421 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 2 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 200000000 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 4 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {5000 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 8 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 11 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 200000000 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 6249 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0001000011000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode I2C quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 3120 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 1875 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {400.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 4 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 260.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY true ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 4 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 1 pin_muxing_check {Cyclone V+5CSEMA5F31C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 100000000 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 2 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 200000 PLL_WRITE_CLK_MULT_CACHE 32 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 400.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 4 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 50.0 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} USB1.D0 USB1.D1 USB1.D2 USB1.D3 USB1.D4 USB1.D5 USB1.D6 USB1.D7 {} USB1.CLK USB1.STP USB1.DIR USB1.NXT EMAC1.TX_CLK EMAC1.TXD0 EMAC1.TXD1 EMAC1.TXD2 EMAC1.TXD3 EMAC1.RXD0 EMAC1.MDIO EMAC1.MDC EMAC1.RX_CTL EMAC1.TX_CTL EMAC1.RX_CLK EMAC1.RXD1 EMAC1.RXD2 EMAC1.RXD3 {} {} {} {} {} {} {} {} SDIO.CMD {} SDIO.D0 SDIO.D1 {} {} {} {} {} SDIO.CLK SDIO.D2 SDIO.D3 {} UART0.RX UART0.TX I2C1.SDA I2C1.SCL {} {} I2C0.SDA I2C0.SCL {} {} {} {} {} {} SPIM1.CLK SPIM1.MOSI SPIM1.MISO SPIM1.SS0} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 8 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 400.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 8 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 32 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0001000011000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000000000110 TB_MEM_CLK_FREQ 400.0 AC_ROM_MR0 0010001110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 18000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 400.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {2500 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 12.5 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 5 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_4 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing {HPS I/O Set 0} CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 25000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {5000 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode SDR ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.4 dbg_base_clk_hz 25000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 400.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 2 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 1250.0 S2FCLK_USER1CLK_Enable true SDIO_Mode {4-bit Data} desired_qspi_clk_mhz 400.0 MEM_TRFC 104 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2,ignoreSimulation=true,interfaceDefinition=instances {sdio_inst {entity_name cyclonev_hps_peripheral_sdmmc location HPSPERIPHERALSDMMC_X87_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} emac1_inst {entity_name cyclonev_hps_peripheral_emac location HPSPERIPHERALEMAC_X77_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c1_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y65_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} spim1_inst {entity_name cyclonev_hps_peripheral_spi_master location HPSPERIPHERALSPIMASTER_X87_Y53_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} uart0_inst {entity_name cyclonev_hps_peripheral_uart location HPSPERIPHERALUART_X87_Y45_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} @orderednames {emac1_inst sdio_inst usb1_inst spim1_inst uart0_inst i2c0_inst i2c1_inst gpio_inst hps_sdram_inst} usb1_inst {entity_name cyclonev_hps_peripheral_usb location HPSPERIPHERALUSB_X55_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} gpio_inst {entity_name cyclonev_hps_peripheral_gpio location HPSPERIPHERALGPIO_X87_Y74_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps_sdram_inst {entity_name hps_sdram location {} signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c0_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y67_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD0]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD1]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD2]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD3]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD0] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_MDIO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDIO]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDC]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CTL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CTL]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CLK] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD1] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD2] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD3] -to *} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1]} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D1]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D4] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D4]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D5] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D5]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D6] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D6]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D7] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D7]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_CLK] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_STP]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_DIR] -to *} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_NXT] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_MOSI]} {set_false_path -from [get_ports hps_io_hps_io_spim1_inst_MISO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_SS0]} {set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO09] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO09]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO35] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO35]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO40] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO40]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO48] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO48]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO53] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO53]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO54] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO54]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO61] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO61]}} properties {SUPPRESS_SDRAM_SYNTH 0 GENERATE_ISW 1} bfm_types {} intermediate_wire_count 48 interfaces {@orderednames {memory hps_io} memory {properties {} type conduit direction end signals {@orderednames {mem_a mem_ba mem_ck mem_ck_n mem_cke mem_cs_n mem_ras_n mem_cas_n mem_we_n mem_reset_n mem_dq mem_dqs mem_dqs_n mem_odt mem_dm oct_rzqin} mem_a {fragments {} properties {} internal_name mem_a width 15 instance_name hps_sdram_inst direction Output role mem_a} mem_ba {fragments {} properties {} internal_name mem_ba width 3 instance_name hps_sdram_inst direction Output role mem_ba} mem_ck {fragments {} properties {} internal_name mem_ck width 1 instance_name hps_sdram_inst direction Output role mem_ck} mem_ck_n {fragments {} properties {} internal_name mem_ck_n width 1 instance_name hps_sdram_inst direction Output role mem_ck_n} mem_cke {fragments {} properties {} internal_name mem_cke width 1 instance_name hps_sdram_inst direction Output role mem_cke} mem_cs_n {fragments {} properties {} internal_name mem_cs_n width 1 instance_name hps_sdram_inst direction Output role mem_cs_n} mem_ras_n {fragments {} properties {} internal_name mem_ras_n width 1 instance_name hps_sdram_inst direction Output role mem_ras_n} mem_cas_n {fragments {} properties {} internal_name mem_cas_n width 1 instance_name hps_sdram_inst direction Output role mem_cas_n} mem_we_n {fragments {} properties {} internal_name mem_we_n width 1 instance_name hps_sdram_inst direction Output role mem_we_n} mem_reset_n {fragments {} properties {} internal_name mem_reset_n width 1 instance_name hps_sdram_inst direction Output role mem_reset_n} mem_dq {fragments {} properties {} internal_name mem_dq width 32 instance_name hps_sdram_inst direction Bidir role mem_dq} mem_dqs {fragments {} properties {} internal_name mem_dqs width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs} mem_dqs_n {fragments {} properties {} internal_name mem_dqs_n width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs_n} mem_odt {fragments {} properties {} internal_name mem_odt width 1 instance_name hps_sdram_inst direction Output role mem_odt} mem_dm {fragments {} properties {} internal_name mem_dm width 4 instance_name hps_sdram_inst direction Output role mem_dm} oct_rzqin {fragments {} properties {} internal_name oct_rzqin width 1 instance_name hps_sdram_inst direction Input role oct_rzqin}}} hps_io {properties {} type conduit direction input signals {@orderednames {hps_io_emac1_inst_TX_CLK hps_io_emac1_inst_TXD0 hps_io_emac1_inst_TXD1 hps_io_emac1_inst_TXD2 hps_io_emac1_inst_TXD3 hps_io_emac1_inst_RXD0 hps_io_emac1_inst_MDIO hps_io_emac1_inst_MDC hps_io_emac1_inst_RX_CTL hps_io_emac1_inst_TX_CTL hps_io_emac1_inst_RX_CLK hps_io_emac1_inst_RXD1 hps_io_emac1_inst_RXD2 hps_io_emac1_inst_RXD3 hps_io_sdio_inst_CMD hps_io_sdio_inst_D0 hps_io_sdio_inst_D1 hps_io_sdio_inst_CLK hps_io_sdio_inst_D2 hps_io_sdio_inst_D3 hps_io_usb1_inst_D0 hps_io_usb1_inst_D1 hps_io_usb1_inst_D2 hps_io_usb1_inst_D3 hps_io_usb1_inst_D4 hps_io_usb1_inst_D5 hps_io_usb1_inst_D6 hps_io_usb1_inst_D7 hps_io_usb1_inst_CLK hps_io_usb1_inst_STP hps_io_usb1_inst_DIR hps_io_usb1_inst_NXT hps_io_spim1_inst_CLK hps_io_spim1_inst_MOSI hps_io_spim1_inst_MISO hps_io_spim1_inst_SS0 hps_io_uart0_inst_RX hps_io_uart0_inst_TX hps_io_i2c0_inst_SDA hps_io_i2c0_inst_SCL hps_io_i2c1_inst_SDA hps_io_i2c1_inst_SCL hps_io_gpio_inst_GPIO09 hps_io_gpio_inst_GPIO35 hps_io_gpio_inst_GPIO40 hps_io_gpio_inst_GPIO48 hps_io_gpio_inst_GPIO53 hps_io_gpio_inst_GPIO54 hps_io_gpio_inst_GPIO61} hps_io_emac1_inst_TX_CLK {fragments emac1_inst:EMAC_CLK_TX(0:0) properties {} internal_name hps_io_emac1_inst_TX_CLK width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CLK} hps_io_emac1_inst_TXD0 {fragments emac1_inst:EMAC_PHY_TXD(0:0) properties {} internal_name hps_io_emac1_inst_TXD0 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD0} hps_io_emac1_inst_TXD1 {fragments emac1_inst:EMAC_PHY_TXD(1:1) properties {} internal_name hps_io_emac1_inst_TXD1 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD1} hps_io_emac1_inst_TXD2 {fragments emac1_inst:EMAC_PHY_TXD(2:2) properties {} internal_name hps_io_emac1_inst_TXD2 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD2} hps_io_emac1_inst_TXD3 {fragments emac1_inst:EMAC_PHY_TXD(3:3) properties {} internal_name hps_io_emac1_inst_TXD3 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD3} hps_io_emac1_inst_RXD0 {fragments emac1_inst:EMAC_PHY_RXD(0:0) properties {} internal_name hps_io_emac1_inst_RXD0 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD0} hps_io_emac1_inst_MDIO {fragments emac1_inst:EMAC_GMII_MDO_I(0:0) properties {} internal_name hps_io_emac1_inst_MDIO width 1 instance_name hps_io tristate_output {{intermediate 1} {intermediate 0}} direction bidir role hps_io_emac1_inst_MDIO} hps_io_emac1_inst_MDC {fragments emac1_inst:EMAC_GMII_MDC(0:0) properties {} internal_name hps_io_emac1_inst_MDC width 1 instance_name hps_io direction output role hps_io_emac1_inst_MDC} hps_io_emac1_inst_RX_CTL {fragments emac1_inst:EMAC_PHY_RXDV(0:0) properties {} internal_name hps_io_emac1_inst_RX_CTL width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CTL} hps_io_emac1_inst_TX_CTL {fragments emac1_inst:EMAC_PHY_TX_OE(0:0) properties {} internal_name hps_io_emac1_inst_TX_CTL width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CTL} hps_io_emac1_inst_RX_CLK {fragments emac1_inst:EMAC_CLK_RX(0:0) properties {} internal_name hps_io_emac1_inst_RX_CLK width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CLK} hps_io_emac1_inst_RXD1 {fragments emac1_inst:EMAC_PHY_RXD(1:1) properties {} internal_name hps_io_emac1_inst_RXD1 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD1} hps_io_emac1_inst_RXD2 {fragments emac1_inst:EMAC_PHY_RXD(2:2) properties {} internal_name hps_io_emac1_inst_RXD2 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD2} hps_io_emac1_inst_RXD3 {fragments emac1_inst:EMAC_PHY_RXD(3:3) properties {} internal_name hps_io_emac1_inst_RXD3 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD3} hps_io_sdio_inst_CMD {fragments sdio_inst:SDMMC_CMD_I(0:0) properties {} internal_name hps_io_sdio_inst_CMD width 1 instance_name hps_io tristate_output {{intermediate 3} {intermediate 2}} direction bidir role hps_io_sdio_inst_CMD} hps_io_sdio_inst_D0 {fragments sdio_inst:SDMMC_DATA_I(0:0) properties {} internal_name hps_io_sdio_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 5} {intermediate 4}} direction bidir role hps_io_sdio_inst_D0} hps_io_sdio_inst_D1 {fragments sdio_inst:SDMMC_DATA_I(1:1) properties {} internal_name hps_io_sdio_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 7} {intermediate 6}} direction bidir role hps_io_sdio_inst_D1} hps_io_sdio_inst_CLK {fragments sdio_inst:SDMMC_CCLK(0:0) properties {} internal_name hps_io_sdio_inst_CLK width 1 instance_name hps_io direction output role hps_io_sdio_inst_CLK} hps_io_sdio_inst_D2 {fragments sdio_inst:SDMMC_DATA_I(2:2) properties {} internal_name hps_io_sdio_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 9} {intermediate 8}} direction bidir role hps_io_sdio_inst_D2} hps_io_sdio_inst_D3 {fragments sdio_inst:SDMMC_DATA_I(3:3) properties {} internal_name hps_io_sdio_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 11} {intermediate 10}} direction bidir role hps_io_sdio_inst_D3} hps_io_usb1_inst_D0 {fragments usb1_inst:USB_ULPI_DATA_I(0:0) properties {} internal_name hps_io_usb1_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 13} {intermediate 12}} direction bidir role hps_io_usb1_inst_D0} hps_io_usb1_inst_D1 {fragments usb1_inst:USB_ULPI_DATA_I(1:1) properties {} internal_name hps_io_usb1_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 15} {intermediate 14}} direction bidir role hps_io_usb1_inst_D1} hps_io_usb1_inst_D2 {fragments usb1_inst:USB_ULPI_DATA_I(2:2) properties {} internal_name hps_io_usb1_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 17} {intermediate 16}} direction bidir role hps_io_usb1_inst_D2} hps_io_usb1_inst_D3 {fragments usb1_inst:USB_ULPI_DATA_I(3:3) properties {} internal_name hps_io_usb1_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 19} {intermediate 18}} direction bidir role hps_io_usb1_inst_D3} hps_io_usb1_inst_D4 {fragments usb1_inst:USB_ULPI_DATA_I(4:4) properties {} internal_name hps_io_usb1_inst_D4 width 1 instance_name hps_io tristate_output {{intermediate 21} {intermediate 20}} direction bidir role hps_io_usb1_inst_D4} hps_io_usb1_inst_D5 {fragments usb1_inst:USB_ULPI_DATA_I(5:5) properties {} internal_name hps_io_usb1_inst_D5 width 1 instance_name hps_io tristate_output {{intermediate 23} {intermediate 22}} direction bidir role hps_io_usb1_inst_D5} hps_io_usb1_inst_D6 {fragments usb1_inst:USB_ULPI_DATA_I(6:6) properties {} internal_name hps_io_usb1_inst_D6 width 1 instance_name hps_io tristate_output {{intermediate 25} {intermediate 24}} direction bidir role hps_io_usb1_inst_D6} hps_io_usb1_inst_D7 {fragments usb1_inst:USB_ULPI_DATA_I(7:7) properties {} internal_name hps_io_usb1_inst_D7 width 1 instance_name hps_io tristate_output {{intermediate 27} {intermediate 26}} direction bidir role hps_io_usb1_inst_D7} hps_io_usb1_inst_CLK {fragments usb1_inst:USB_ULPI_CLK(0:0) properties {} internal_name hps_io_usb1_inst_CLK width 1 instance_name hps_io direction input role hps_io_usb1_inst_CLK} hps_io_usb1_inst_STP {fragments usb1_inst:USB_ULPI_STP(0:0) properties {} internal_name hps_io_usb1_inst_STP width 1 instance_name hps_io direction output role hps_io_usb1_inst_STP} hps_io_usb1_inst_DIR {fragments usb1_inst:USB_ULPI_DIR(0:0) properties {} internal_name hps_io_usb1_inst_DIR width 1 instance_name hps_io direction input role hps_io_usb1_inst_DIR} hps_io_usb1_inst_NXT {fragments usb1_inst:USB_ULPI_NXT(0:0) properties {} internal_name hps_io_usb1_inst_NXT width 1 instance_name hps_io direction input role hps_io_usb1_inst_NXT} hps_io_spim1_inst_CLK {fragments spim1_inst:SPI_MASTER_SCLK(0:0) properties {} internal_name hps_io_spim1_inst_CLK width 1 instance_name hps_io direction output role hps_io_spim1_inst_CLK} hps_io_spim1_inst_MOSI {fragments {} properties {} internal_name hps_io_spim1_inst_MOSI width 1 instance_name hps_io tristate_output {{intermediate 29} {intermediate 28}} direction output role hps_io_spim1_inst_MOSI} hps_io_spim1_inst_MISO {fragments spim1_inst:SPI_MASTER_RXD(0:0) properties {} internal_name hps_io_spim1_inst_MISO width 1 instance_name hps_io direction input role hps_io_spim1_inst_MISO} hps_io_spim1_inst_SS0 {fragments spim1_inst:SPI_MASTER_SS_0_N(0:0) properties {} internal_name hps_io_spim1_inst_SS0 width 1 instance_name hps_io direction output role hps_io_spim1_inst_SS0} hps_io_uart0_inst_RX {fragments uart0_inst:UART_RXD(0:0) properties {} internal_name hps_io_uart0_inst_RX width 1 instance_name hps_io direction input role hps_io_uart0_inst_RX} hps_io_uart0_inst_TX {fragments uart0_inst:UART_TXD(0:0) properties {} internal_name hps_io_uart0_inst_TX width 1 instance_name hps_io direction output role hps_io_uart0_inst_TX} hps_io_i2c0_inst_SDA {fragments i2c0_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c0_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 30} {}} direction bidir role hps_io_i2c0_inst_SDA} hps_io_i2c0_inst_SCL {fragments i2c0_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c0_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 31} {}} direction bidir role hps_io_i2c0_inst_SCL} hps_io_i2c1_inst_SDA {fragments i2c1_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c1_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 32} {}} direction bidir role hps_io_i2c1_inst_SDA} hps_io_i2c1_inst_SCL {fragments i2c1_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c1_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 33} {}} direction bidir role hps_io_i2c1_inst_SCL} hps_io_gpio_inst_GPIO09 {fragments gpio_inst:GPIO0_PORTA_I(9:9) properties {} internal_name hps_io_gpio_inst_GPIO09 width 1 instance_name hps_io tristate_output {{intermediate 35} {intermediate 34}} direction bidir role hps_io_gpio_inst_GPIO09} hps_io_gpio_inst_GPIO35 {fragments gpio_inst:GPIO1_PORTA_I(6:6) properties {} internal_name hps_io_gpio_inst_GPIO35 width 1 instance_name hps_io tristate_output {{intermediate 37} {intermediate 36}} direction bidir role hps_io_gpio_inst_GPIO35} hps_io_gpio_inst_GPIO40 {fragments gpio_inst:GPIO1_PORTA_I(11:11) properties {} internal_name hps_io_gpio_inst_GPIO40 width 1 instance_name hps_io tristate_output {{intermediate 39} {intermediate 38}} direction bidir role hps_io_gpio_inst_GPIO40} hps_io_gpio_inst_GPIO48 {fragments gpio_inst:GPIO1_PORTA_I(19:19) properties {} internal_name hps_io_gpio_inst_GPIO48 width 1 instance_name hps_io tristate_output {{intermediate 41} {intermediate 40}} direction bidir role hps_io_gpio_inst_GPIO48} hps_io_gpio_inst_GPIO53 {fragments gpio_inst:GPIO1_PORTA_I(24:24) properties {} internal_name hps_io_gpio_inst_GPIO53 width 1 instance_name hps_io tristate_output {{intermediate 43} {intermediate 42}} direction bidir role hps_io_gpio_inst_GPIO53} hps_io_gpio_inst_GPIO54 {fragments gpio_inst:GPIO1_PORTA_I(25:25) properties {} internal_name hps_io_gpio_inst_GPIO54 width 1 instance_name hps_io tristate_output {{intermediate 45} {intermediate 44}} direction bidir role hps_io_gpio_inst_GPIO54} hps_io_gpio_inst_GPIO61 {fragments gpio_inst:GPIO2_PORTA_I(3:3) properties {} internal_name hps_io_gpio_inst_GPIO61 width 1 instance_name hps_io tristate_output {{intermediate 47} {intermediate 46}} direction bidir role hps_io_gpio_inst_GPIO61}}}} wires_to_fragments {{intermediate 9} {output sdio_inst:SDMMC_DATA_OE(2:2)} {intermediate 8} {output sdio_inst:SDMMC_DATA_O(2:2)} {intermediate 7} {output sdio_inst:SDMMC_DATA_OE(1:1)} {intermediate 6} {output sdio_inst:SDMMC_DATA_O(1:1)} {intermediate 5} {output sdio_inst:SDMMC_DATA_OE(0:0)} {intermediate 4} {output sdio_inst:SDMMC_DATA_O(0:0)} {intermediate 3} {output sdio_inst:SDMMC_CMD_OE(0:0)} {intermediate 2} {output sdio_inst:SDMMC_CMD_O(0:0)} {intermediate 1} {output emac1_inst:EMAC_GMII_MDO_OE(0:0)} {intermediate 0} {output emac1_inst:EMAC_GMII_MDO_O(0:0)} {intermediate 19} {output usb1_inst:USB_ULPI_DATA_OE(3:3)} {intermediate 18} {output usb1_inst:USB_ULPI_DATA_O(3:3)} {intermediate 17} {output usb1_inst:USB_ULPI_DATA_OE(2:2)} {intermediate 16} {output usb1_inst:USB_ULPI_DATA_O(2:2)} {intermediate 47} {output gpio_inst:GPIO2_PORTA_OE(3:3)} {intermediate 15} {output usb1_inst:USB_ULPI_DATA_OE(1:1)} {intermediate 46} {output gpio_inst:GPIO2_PORTA_O(3:3)} {intermediate 14} {output usb1_inst:USB_ULPI_DATA_O(1:1)} {intermediate 45} {output gpio_inst:GPIO1_PORTA_OE(25:25)} {intermediate 13} {output usb1_inst:USB_ULPI_DATA_OE(0:0)} {intermediate 44} {output gpio_inst:GPIO1_PORTA_O(25:25)} {intermediate 12} {output usb1_inst:USB_ULPI_DATA_O(0:0)} {intermediate 43} {output gpio_inst:GPIO1_PORTA_OE(24:24)} {intermediate 11} {output sdio_inst:SDMMC_DATA_OE(3:3)} {intermediate 42} {output gpio_inst:GPIO1_PORTA_O(24:24)} {intermediate 10} {output sdio_inst:SDMMC_DATA_O(3:3)} {intermediate 41} {output gpio_inst:GPIO1_PORTA_OE(19:19)} {intermediate 40} {output gpio_inst:GPIO1_PORTA_O(19:19)} {intermediate 39} {output gpio_inst:GPIO1_PORTA_OE(11:11)} {intermediate 38} {output gpio_inst:GPIO1_PORTA_O(11:11)} {intermediate 37} {output gpio_inst:GPIO1_PORTA_OE(6:6)} {intermediate 36} {output gpio_inst:GPIO1_PORTA_O(6:6)} {intermediate 35} {output gpio_inst:GPIO0_PORTA_OE(9:9)} {intermediate 34} {output gpio_inst:GPIO0_PORTA_O(9:9)} {intermediate 33} {output i2c1_inst:I2C_CLK_OE(0:0)} {intermediate 32} {output i2c1_inst:I2C_DATA_OE(0:0)} {intermediate 31} {output i2c0_inst:I2C_CLK_OE(0:0)} {intermediate 30} {output i2c0_inst:I2C_DATA_OE(0:0)} {intermediate 29} {output spim1_inst:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 28} {output spim1_inst:SPI_MASTER_TXD(0:0)} {intermediate 27} {output usb1_inst:USB_ULPI_DATA_OE(7:7)} {intermediate 26} {output usb1_inst:USB_ULPI_DATA_O(7:7)} {intermediate 25} {output usb1_inst:USB_ULPI_DATA_OE(6:6)} {intermediate 24} {output usb1_inst:USB_ULPI_DATA_O(6:6)} {intermediate 23} {output usb1_inst:USB_ULPI_DATA_OE(5:5)} {intermediate 22} {output usb1_inst:USB_ULPI_DATA_O(5:5)} {intermediate 21} {output usb1_inst:USB_ULPI_DATA_OE(4:4)} {intermediate 20} {output usb1_inst:USB_ULPI_DATA_O(4:4)}} raw_assign_sim_style {},qipEntries={set_instance_assignment -name hps_partition on -entity %entityName% -library %libraryName%})"
   instancePathKey="soc_system:.:hps_0:.:hps_io"
   kind="altera_hps_io"
   version="21.1"
   name="soc_system_hps_0_hps_io">
  <parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
  <parameter name="VECT_ATTR_COUNTER_ZERO_MATCH" value="0" />
  <parameter name="ENUM_GANGED_ARF" value="DISABLED" />
  <parameter name="LRDIMM_INT" value="0" />
  <parameter name="ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
  <parameter name="MAX_LATENCY_COUNT_WIDTH" value="6" />
  <parameter name="MEM_IF_ADDR_WIDTH_MIN" value="10" />
  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="0" />
  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
  <parameter name="MEM_LEVELING" value="true" />
  <parameter name="CV_ENUM_PRIORITY_1_0" value="WEIGHT_0" />
  <parameter name="ENUM_MEM_IF_TRRD" value="TRRD_4" />
  <parameter name="CV_ENUM_PRIORITY_1_2" value="WEIGHT_0" />
  <parameter name="ENUM_ATTR_COUNTER_ZERO_RESET" value="DISABLED" />
  <parameter name="CV_ENUM_PRIORITY_1_1" value="WEIGHT_0" />
  <parameter name="PLL_AFI_HALF_CLK_DIV" value="0" />
  <parameter name="MEM_ADD_LAT" value="0" />
  <parameter name="CV_ENUM_PRIORITY_1_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_1_3" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR" value="0" />
  <parameter name="CV_ENUM_PRIORITY_1_5" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT" value="0" />
  <parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
  <parameter name="ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
  <parameter name="INTG_MEM_IF_TRFC" value="34" />
  <parameter name="MEM_REGDIMM_ENABLED" value="false" />
  <parameter name="PLL_HR_CLK_FREQ" value="0.0" />
  <parameter name="AFI_DQ_WIDTH" value="0" />
  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
  <parameter name="AP_MODE_EN" value="0" />
  <parameter name="ENUM_CPORT5_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CALIB_LFIFO_OFFSET" value="-1" />
  <parameter name="INTG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="ENUM_CPORT2_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="VECT_ATTR_COUNTER_ZERO_MASK" value="0" />
  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ALLOCATED_WFIFO_PORT" value="0,None,None,None,None,None" />
  <parameter name="MEM_TRAS_NS" value="35.0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
  <parameter name="IO_DQ_OUT_RESERVE" value="0" />
  <parameter name="IO_DM_OUT_RESERVE" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="CV_ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
  <parameter name="INTG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="DELAY_PER_OPA_TAP" value="-1" />
  <parameter name="INTG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="ENABLE_BONDING" value="false" />
  <parameter name="HHP_HPS_VERIFICATION" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC" value="0" />
  <parameter name="CV_ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP" value="0" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="CV_ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_ENABLE_INTR" value="DISABLED" />
  <parameter name="INTG_MEM_AUTO_PD_CYCLES" value="0" />
  <parameter name="AVL_DATA_WIDTH" value="0" />
  <parameter name="PLL_AFI_CLK_MULT_CACHE" value="0" />
  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
  <parameter name="MR1_RDQS" value="0" />
  <parameter name="ENUM_MEM_IF_ROWADDR_WIDTH" value="ADDR_WIDTH_16" />
  <parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
  <parameter name="MR0_PD" value="0" />
  <parameter name="MEM_VENDOR" value="JEDEC" />
  <parameter name="MEM_IF_CS_PER_RANK" value="0" />
  <parameter name="CV_PORT_1_CONNECT_TO_AV_PORT" value="1" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
  <parameter name="CV_ENUM_CPORT1_TYPE" value="DISABLE" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="" />
  <parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
  <parameter name="USE_MEM_CLK_FREQ" value="false" />
  <parameter name="CV_MSB_WFIFO_PORT_5" value="5" />
  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
  <parameter name="CFG_READ_ODT_CHIP" value="0" />
  <parameter name="CV_MSB_WFIFO_PORT_4" value="5" />
  <parameter name="CV_MSB_WFIFO_PORT_3" value="5" />
  <parameter name="IO_DQS_EN_PHASE_MAX" value="0" />
  <parameter name="RDIMM" value="false" />
  <parameter name="ENUM_MEM_IF_COLADDR_WIDTH" value="ADDR_WIDTH_12" />
  <parameter name="PLL_CONFIG_CLK_FREQ" value="0.0" />
  <parameter name="ENABLE_USER_ECC" value="false" />
  <parameter name="PLL_PHASE_COUNTER_WIDTH" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD" value="0" />
  <parameter name="MEM_TRC" value="0" />
  <parameter name="AVL_ADDR_WIDTH_PORT_2" value="0" />
  <parameter name="ENUM_PRIORITY_6_4" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID" value="0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_3" value="USE_NO" />
  <parameter name="AVL_ADDR_WIDTH_PORT_1" value="0" />
  <parameter name="ENUM_PRIORITY_6_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_2" value="USE_NO" />
  <parameter name="AVL_ADDR_WIDTH_PORT_0" value="0" />
  <parameter name="ENUM_PRIORITY_6_2" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_5" value="USE_NO" />
  <parameter name="ENUM_PRIORITY_6_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_4" value="USE_NO" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_PRIORITY_6_0" value="WEIGHT_0" />
  <parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
  <parameter name="AFI_CS_WIDTH" value="0" />
  <parameter name="AVL_ADDR_WIDTH_PORT_5" value="0" />
  <parameter name="ENUM_PRIORITY_6_1" value="WEIGHT_0" />
  <parameter name="AVL_ADDR_WIDTH_PORT_4" value="0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_1" value="USE_NO" />
  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
  <parameter name="AVL_ADDR_WIDTH_PORT_3" value="0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_0" value="USE_NO" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="CV_MSB_WFIFO_PORT_2" value="5" />
  <parameter name="CV_MSB_WFIFO_PORT_1" value="5" />
  <parameter name="PLL_NIOS_CLK_MULT" value="0" />
  <parameter name="ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_MSB_WFIFO_PORT_0" value="5" />
  <parameter name="TG_TEMP_PORT_5" value="0" />
  <parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
  <parameter name="TG_TEMP_PORT_3" value="0" />
  <parameter name="TG_TEMP_PORT_4" value="0" />
  <parameter name="TG_TEMP_PORT_1" value="0" />
  <parameter name="TG_TEMP_PORT_2" value="0" />
  <parameter name="MEM_CLK_NS" value="0.0" />
  <parameter name="TG_TEMP_PORT_0" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
  <parameter name="ENUM_MEM_IF_BURSTLENGTH" value="MEM_IF_BURSTLENGTH_8" />
  <parameter name="PLL_AFI_CLK_MULT" value="0" />
  <parameter name="SKIP_MEM_INIT" value="true" />
  <parameter name="CFG_ENABLE_NO_DM" value="0" />
  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
  <parameter name="MR1_TDQS" value="0" />
  <parameter name="INTG_MEM_CLK_ENTRY_CYCLES" value="10" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
  <parameter name="CTL_ECC_MULTIPLES_16_24_40_72" value="0" />
  <parameter name="CV_ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="ENUM_MEM_IF_TCWL" value="TCWL_5" />
  <parameter name="DEVICE_FAMILY" value="" />
  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
  <parameter name="DEVICE_FAMILY_PARAM" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID" value="0" />
  <parameter name="ENUM_MEM_IF_TRTP" value="TRTP_4" />
  <parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="INTG_POWER_SAVING_EXIT_CYCLES" value="5" />
  <parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="-1" />
  <parameter name="MEM_IF_ADDR_WIDTH" value="0" />
  <parameter name="PLL_DR_CLK_DIV" value="0" />
  <parameter name="USE_SEQUENCER_BFM" value="false" />
  <parameter name="DELAY_PER_DCHAIN_TAP" value="-1" />
  <parameter name="CSR_ADDR_WIDTH" value="8" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID" value="0" />
  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
  <parameter name="CV_ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="CV_ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="RDIMM_INT" value="0" />
  <parameter name="CV_ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="CTL_CSR_READ_ONLY" value="1" />
  <parameter name="ENUM_MASK_DBE_INTR" value="DISABLED" />
  <parameter name="CV_ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="CV_ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
  <parameter name="CV_ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="READ_VALID_FIFO_SIZE" value="16" />
  <parameter name="DLL_MASTER" value="false" />
  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="AC_ROM_MR0_MIRR" value="" />
  <parameter name="MEM_TWTR" value="4" />
  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
  <parameter name="ENUM_ENABLE_BURST_INTERRUPT" value="DISABLED" />
  <parameter name="CV_ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="WEIGHT_PORT_2" value="0" />
  <parameter name="WEIGHT_PORT_1" value="0" />
  <parameter name="WEIGHT_PORT_0" value="0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="Unknown" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="WEIGHT_PORT_5" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="" />
  <parameter name="WEIGHT_PORT_4" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
  <parameter name="WEIGHT_PORT_3" value="0" />
  <parameter name="ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_2" value="DISABLED" />
  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
  <parameter name="CV_ENUM_ENABLE_BONDING_3" value="DISABLED" />
  <parameter name="MEM_TRFC_NS" value="260.0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_4" value="DISABLED" />
  <parameter name="CV_ENUM_ENABLE_BONDING_5" value="DISABLED" />
  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="ENABLE_ISS_PROBES" value="false" />
  <parameter name="MR2_RTT_WR" value="1" />
  <parameter name="ENUM_MEM_IF_TFAW" value="TFAW_16" />
  <parameter name="TIMING_BOARD_TDS_APPLIED" value="0.0" />
  <parameter name="AFI_ODT_WIDTH" value="0" />
  <parameter name="PLL_MASTER" value="false" />
  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_0" value="DISABLED" />
  <parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_1" value="DISABLED" />
  <parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="DISCRETE_FLY_BY" value="true" />
  <parameter name="QVLD_WR_ADDRESS_OFFSET" value="0" />
  <parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="0" />
  <parameter name="AVL_SYMBOL_WIDTH" value="8" />
  <parameter name="TB_PLL_DLL_MASTER" value="true" />
  <parameter name="MEM_IF_DM_WIDTH" value="0" />
  <parameter name="LOCAL_CS_WIDTH" value="0" />
  <parameter name="CTL_ECC_ENABLED" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="AUTO_POWERDN_EN" value="false" />
  <parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
  <parameter name="PHY_CLKBUF" value="false" />
  <parameter name="ENABLE_ABS_RAM_INTERNAL" value="false" />
  <parameter name="MAX_PENDING_WR_CMD" value="16" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_ATTR_COUNTER_ONE_RESET" value="DISABLED" />
  <parameter name="ENUM_WRITE_ODT_CHIP" value="ODT_DISABLED" />
  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
  <parameter
     name="border_description"
     value="instances {sdio_inst {entity_name cyclonev_hps_peripheral_sdmmc location HPSPERIPHERALSDMMC_X87_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} emac1_inst {entity_name cyclonev_hps_peripheral_emac location HPSPERIPHERALEMAC_X77_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c1_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y65_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} spim1_inst {entity_name cyclonev_hps_peripheral_spi_master location HPSPERIPHERALSPIMASTER_X87_Y53_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} uart0_inst {entity_name cyclonev_hps_peripheral_uart location HPSPERIPHERALUART_X87_Y45_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} @orderednames {emac1_inst sdio_inst usb1_inst spim1_inst uart0_inst i2c0_inst i2c1_inst gpio_inst hps_sdram_inst} usb1_inst {entity_name cyclonev_hps_peripheral_usb location HPSPERIPHERALUSB_X55_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} gpio_inst {entity_name cyclonev_hps_peripheral_gpio location HPSPERIPHERALGPIO_X87_Y74_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps_sdram_inst {entity_name hps_sdram location {} signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c0_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y67_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD0]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD1]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD2]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD3]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD0] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_MDIO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDIO]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDC]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CTL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CTL]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CLK] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD1] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD2] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD3] -to *} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1]} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D1]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D4] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D4]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D5] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D5]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D6] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D6]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D7] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D7]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_CLK] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_STP]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_DIR] -to *} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_NXT] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_MOSI]} {set_false_path -from [get_ports hps_io_hps_io_spim1_inst_MISO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_SS0]} {set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO09] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO09]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO35] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO35]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO40] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO40]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO48] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO48]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO53] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO53]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO54] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO54]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO61] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO61]}} properties {SUPPRESS_SDRAM_SYNTH 0 GENERATE_ISW 1} bfm_types {} intermediate_wire_count 48 wires_to_fragments {{intermediate 9} {output sdio_inst:SDMMC_DATA_OE(2:2)} {intermediate 8} {output sdio_inst:SDMMC_DATA_O(2:2)} {intermediate 7} {output sdio_inst:SDMMC_DATA_OE(1:1)} {intermediate 6} {output sdio_inst:SDMMC_DATA_O(1:1)} {intermediate 5} {output sdio_inst:SDMMC_DATA_OE(0:0)} {intermediate 4} {output sdio_inst:SDMMC_DATA_O(0:0)} {intermediate 3} {output sdio_inst:SDMMC_CMD_OE(0:0)} {intermediate 2} {output sdio_inst:SDMMC_CMD_O(0:0)} {intermediate 1} {output emac1_inst:EMAC_GMII_MDO_OE(0:0)} {intermediate 0} {output emac1_inst:EMAC_GMII_MDO_O(0:0)} {intermediate 19} {output usb1_inst:USB_ULPI_DATA_OE(3:3)} {intermediate 18} {output usb1_inst:USB_ULPI_DATA_O(3:3)} {intermediate 17} {output usb1_inst:USB_ULPI_DATA_OE(2:2)} {intermediate 16} {output usb1_inst:USB_ULPI_DATA_O(2:2)} {intermediate 47} {output gpio_inst:GPIO2_PORTA_OE(3:3)} {intermediate 15} {output usb1_inst:USB_ULPI_DATA_OE(1:1)} {intermediate 46} {output gpio_inst:GPIO2_PORTA_O(3:3)} {intermediate 14} {output usb1_inst:USB_ULPI_DATA_O(1:1)} {intermediate 45} {output gpio_inst:GPIO1_PORTA_OE(25:25)} {intermediate 13} {output usb1_inst:USB_ULPI_DATA_OE(0:0)} {intermediate 44} {output gpio_inst:GPIO1_PORTA_O(25:25)} {intermediate 12} {output usb1_inst:USB_ULPI_DATA_O(0:0)} {intermediate 43} {output gpio_inst:GPIO1_PORTA_OE(24:24)} {intermediate 11} {output sdio_inst:SDMMC_DATA_OE(3:3)} {intermediate 42} {output gpio_inst:GPIO1_PORTA_O(24:24)} {intermediate 10} {output sdio_inst:SDMMC_DATA_O(3:3)} {intermediate 41} {output gpio_inst:GPIO1_PORTA_OE(19:19)} {intermediate 40} {output gpio_inst:GPIO1_PORTA_O(19:19)} {intermediate 39} {output gpio_inst:GPIO1_PORTA_OE(11:11)} {intermediate 38} {output gpio_inst:GPIO1_PORTA_O(11:11)} {intermediate 37} {output gpio_inst:GPIO1_PORTA_OE(6:6)} {intermediate 36} {output gpio_inst:GPIO1_PORTA_O(6:6)} {intermediate 35} {output gpio_inst:GPIO0_PORTA_OE(9:9)} {intermediate 34} {output gpio_inst:GPIO0_PORTA_O(9:9)} {intermediate 33} {output i2c1_inst:I2C_CLK_OE(0:0)} {intermediate 32} {output i2c1_inst:I2C_DATA_OE(0:0)} {intermediate 31} {output i2c0_inst:I2C_CLK_OE(0:0)} {intermediate 30} {output i2c0_inst:I2C_DATA_OE(0:0)} {intermediate 29} {output spim1_inst:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 28} {output spim1_inst:SPI_MASTER_TXD(0:0)} {intermediate 27} {output usb1_inst:USB_ULPI_DATA_OE(7:7)} {intermediate 26} {output usb1_inst:USB_ULPI_DATA_O(7:7)} {intermediate 25} {output usb1_inst:USB_ULPI_DATA_OE(6:6)} {intermediate 24} {output usb1_inst:USB_ULPI_DATA_O(6:6)} {intermediate 23} {output usb1_inst:USB_ULPI_DATA_OE(5:5)} {intermediate 22} {output usb1_inst:USB_ULPI_DATA_O(5:5)} {intermediate 21} {output usb1_inst:USB_ULPI_DATA_OE(4:4)} {intermediate 20} {output usb1_inst:USB_ULPI_DATA_O(4:4)}} interfaces {@orderednames {memory hps_io} memory {properties {} type conduit direction end signals {@orderednames {mem_a mem_ba mem_ck mem_ck_n mem_cke mem_cs_n mem_ras_n mem_cas_n mem_we_n mem_reset_n mem_dq mem_dqs mem_dqs_n mem_odt mem_dm oct_rzqin} mem_a {fragments {} properties {} internal_name mem_a width 15 instance_name hps_sdram_inst direction Output role mem_a} mem_ba {fragments {} properties {} internal_name mem_ba width 3 instance_name hps_sdram_inst direction Output role mem_ba} mem_ck {fragments {} properties {} internal_name mem_ck width 1 instance_name hps_sdram_inst direction Output role mem_ck} mem_ck_n {fragments {} properties {} internal_name mem_ck_n width 1 instance_name hps_sdram_inst direction Output role mem_ck_n} mem_cke {fragments {} properties {} internal_name mem_cke width 1 instance_name hps_sdram_inst direction Output role mem_cke} mem_cs_n {fragments {} properties {} internal_name mem_cs_n width 1 instance_name hps_sdram_inst direction Output role mem_cs_n} mem_ras_n {fragments {} properties {} internal_name mem_ras_n width 1 instance_name hps_sdram_inst direction Output role mem_ras_n} mem_cas_n {fragments {} properties {} internal_name mem_cas_n width 1 instance_name hps_sdram_inst direction Output role mem_cas_n} mem_we_n {fragments {} properties {} internal_name mem_we_n width 1 instance_name hps_sdram_inst direction Output role mem_we_n} mem_reset_n {fragments {} properties {} internal_name mem_reset_n width 1 instance_name hps_sdram_inst direction Output role mem_reset_n} mem_dq {fragments {} properties {} internal_name mem_dq width 32 instance_name hps_sdram_inst direction Bidir role mem_dq} mem_dqs {fragments {} properties {} internal_name mem_dqs width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs} mem_dqs_n {fragments {} properties {} internal_name mem_dqs_n width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs_n} mem_odt {fragments {} properties {} internal_name mem_odt width 1 instance_name hps_sdram_inst direction Output role mem_odt} mem_dm {fragments {} properties {} internal_name mem_dm width 4 instance_name hps_sdram_inst direction Output role mem_dm} oct_rzqin {fragments {} properties {} internal_name oct_rzqin width 1 instance_name hps_sdram_inst direction Input role oct_rzqin}}} hps_io {properties {} type conduit direction input signals {@orderednames {hps_io_emac1_inst_TX_CLK hps_io_emac1_inst_TXD0 hps_io_emac1_inst_TXD1 hps_io_emac1_inst_TXD2 hps_io_emac1_inst_TXD3 hps_io_emac1_inst_RXD0 hps_io_emac1_inst_MDIO hps_io_emac1_inst_MDC hps_io_emac1_inst_RX_CTL hps_io_emac1_inst_TX_CTL hps_io_emac1_inst_RX_CLK hps_io_emac1_inst_RXD1 hps_io_emac1_inst_RXD2 hps_io_emac1_inst_RXD3 hps_io_sdio_inst_CMD hps_io_sdio_inst_D0 hps_io_sdio_inst_D1 hps_io_sdio_inst_CLK hps_io_sdio_inst_D2 hps_io_sdio_inst_D3 hps_io_usb1_inst_D0 hps_io_usb1_inst_D1 hps_io_usb1_inst_D2 hps_io_usb1_inst_D3 hps_io_usb1_inst_D4 hps_io_usb1_inst_D5 hps_io_usb1_inst_D6 hps_io_usb1_inst_D7 hps_io_usb1_inst_CLK hps_io_usb1_inst_STP hps_io_usb1_inst_DIR hps_io_usb1_inst_NXT hps_io_spim1_inst_CLK hps_io_spim1_inst_MOSI hps_io_spim1_inst_MISO hps_io_spim1_inst_SS0 hps_io_uart0_inst_RX hps_io_uart0_inst_TX hps_io_i2c0_inst_SDA hps_io_i2c0_inst_SCL hps_io_i2c1_inst_SDA hps_io_i2c1_inst_SCL hps_io_gpio_inst_GPIO09 hps_io_gpio_inst_GPIO35 hps_io_gpio_inst_GPIO40 hps_io_gpio_inst_GPIO48 hps_io_gpio_inst_GPIO53 hps_io_gpio_inst_GPIO54 hps_io_gpio_inst_GPIO61} hps_io_emac1_inst_TX_CLK {fragments emac1_inst:EMAC_CLK_TX(0:0) properties {} internal_name hps_io_emac1_inst_TX_CLK width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CLK} hps_io_emac1_inst_TXD0 {fragments emac1_inst:EMAC_PHY_TXD(0:0) properties {} internal_name hps_io_emac1_inst_TXD0 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD0} hps_io_emac1_inst_TXD1 {fragments emac1_inst:EMAC_PHY_TXD(1:1) properties {} internal_name hps_io_emac1_inst_TXD1 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD1} hps_io_emac1_inst_TXD2 {fragments emac1_inst:EMAC_PHY_TXD(2:2) properties {} internal_name hps_io_emac1_inst_TXD2 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD2} hps_io_emac1_inst_TXD3 {fragments emac1_inst:EMAC_PHY_TXD(3:3) properties {} internal_name hps_io_emac1_inst_TXD3 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD3} hps_io_emac1_inst_RXD0 {fragments emac1_inst:EMAC_PHY_RXD(0:0) properties {} internal_name hps_io_emac1_inst_RXD0 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD0} hps_io_emac1_inst_MDIO {fragments emac1_inst:EMAC_GMII_MDO_I(0:0) properties {} internal_name hps_io_emac1_inst_MDIO width 1 instance_name hps_io tristate_output {{intermediate 1} {intermediate 0}} direction bidir role hps_io_emac1_inst_MDIO} hps_io_emac1_inst_MDC {fragments emac1_inst:EMAC_GMII_MDC(0:0) properties {} internal_name hps_io_emac1_inst_MDC width 1 instance_name hps_io direction output role hps_io_emac1_inst_MDC} hps_io_emac1_inst_RX_CTL {fragments emac1_inst:EMAC_PHY_RXDV(0:0) properties {} internal_name hps_io_emac1_inst_RX_CTL width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CTL} hps_io_emac1_inst_TX_CTL {fragments emac1_inst:EMAC_PHY_TX_OE(0:0) properties {} internal_name hps_io_emac1_inst_TX_CTL width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CTL} hps_io_emac1_inst_RX_CLK {fragments emac1_inst:EMAC_CLK_RX(0:0) properties {} internal_name hps_io_emac1_inst_RX_CLK width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CLK} hps_io_emac1_inst_RXD1 {fragments emac1_inst:EMAC_PHY_RXD(1:1) properties {} internal_name hps_io_emac1_inst_RXD1 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD1} hps_io_emac1_inst_RXD2 {fragments emac1_inst:EMAC_PHY_RXD(2:2) properties {} internal_name hps_io_emac1_inst_RXD2 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD2} hps_io_emac1_inst_RXD3 {fragments emac1_inst:EMAC_PHY_RXD(3:3) properties {} internal_name hps_io_emac1_inst_RXD3 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD3} hps_io_sdio_inst_CMD {fragments sdio_inst:SDMMC_CMD_I(0:0) properties {} internal_name hps_io_sdio_inst_CMD width 1 instance_name hps_io tristate_output {{intermediate 3} {intermediate 2}} direction bidir role hps_io_sdio_inst_CMD} hps_io_sdio_inst_D0 {fragments sdio_inst:SDMMC_DATA_I(0:0) properties {} internal_name hps_io_sdio_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 5} {intermediate 4}} direction bidir role hps_io_sdio_inst_D0} hps_io_sdio_inst_D1 {fragments sdio_inst:SDMMC_DATA_I(1:1) properties {} internal_name hps_io_sdio_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 7} {intermediate 6}} direction bidir role hps_io_sdio_inst_D1} hps_io_sdio_inst_CLK {fragments sdio_inst:SDMMC_CCLK(0:0) properties {} internal_name hps_io_sdio_inst_CLK width 1 instance_name hps_io direction output role hps_io_sdio_inst_CLK} hps_io_sdio_inst_D2 {fragments sdio_inst:SDMMC_DATA_I(2:2) properties {} internal_name hps_io_sdio_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 9} {intermediate 8}} direction bidir role hps_io_sdio_inst_D2} hps_io_sdio_inst_D3 {fragments sdio_inst:SDMMC_DATA_I(3:3) properties {} internal_name hps_io_sdio_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 11} {intermediate 10}} direction bidir role hps_io_sdio_inst_D3} hps_io_usb1_inst_D0 {fragments usb1_inst:USB_ULPI_DATA_I(0:0) properties {} internal_name hps_io_usb1_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 13} {intermediate 12}} direction bidir role hps_io_usb1_inst_D0} hps_io_usb1_inst_D1 {fragments usb1_inst:USB_ULPI_DATA_I(1:1) properties {} internal_name hps_io_usb1_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 15} {intermediate 14}} direction bidir role hps_io_usb1_inst_D1} hps_io_usb1_inst_D2 {fragments usb1_inst:USB_ULPI_DATA_I(2:2) properties {} internal_name hps_io_usb1_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 17} {intermediate 16}} direction bidir role hps_io_usb1_inst_D2} hps_io_usb1_inst_D3 {fragments usb1_inst:USB_ULPI_DATA_I(3:3) properties {} internal_name hps_io_usb1_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 19} {intermediate 18}} direction bidir role hps_io_usb1_inst_D3} hps_io_usb1_inst_D4 {fragments usb1_inst:USB_ULPI_DATA_I(4:4) properties {} internal_name hps_io_usb1_inst_D4 width 1 instance_name hps_io tristate_output {{intermediate 21} {intermediate 20}} direction bidir role hps_io_usb1_inst_D4} hps_io_usb1_inst_D5 {fragments usb1_inst:USB_ULPI_DATA_I(5:5) properties {} internal_name hps_io_usb1_inst_D5 width 1 instance_name hps_io tristate_output {{intermediate 23} {intermediate 22}} direction bidir role hps_io_usb1_inst_D5} hps_io_usb1_inst_D6 {fragments usb1_inst:USB_ULPI_DATA_I(6:6) properties {} internal_name hps_io_usb1_inst_D6 width 1 instance_name hps_io tristate_output {{intermediate 25} {intermediate 24}} direction bidir role hps_io_usb1_inst_D6} hps_io_usb1_inst_D7 {fragments usb1_inst:USB_ULPI_DATA_I(7:7) properties {} internal_name hps_io_usb1_inst_D7 width 1 instance_name hps_io tristate_output {{intermediate 27} {intermediate 26}} direction bidir role hps_io_usb1_inst_D7} hps_io_usb1_inst_CLK {fragments usb1_inst:USB_ULPI_CLK(0:0) properties {} internal_name hps_io_usb1_inst_CLK width 1 instance_name hps_io direction input role hps_io_usb1_inst_CLK} hps_io_usb1_inst_STP {fragments usb1_inst:USB_ULPI_STP(0:0) properties {} internal_name hps_io_usb1_inst_STP width 1 instance_name hps_io direction output role hps_io_usb1_inst_STP} hps_io_usb1_inst_DIR {fragments usb1_inst:USB_ULPI_DIR(0:0) properties {} internal_name hps_io_usb1_inst_DIR width 1 instance_name hps_io direction input role hps_io_usb1_inst_DIR} hps_io_usb1_inst_NXT {fragments usb1_inst:USB_ULPI_NXT(0:0) properties {} internal_name hps_io_usb1_inst_NXT width 1 instance_name hps_io direction input role hps_io_usb1_inst_NXT} hps_io_spim1_inst_CLK {fragments spim1_inst:SPI_MASTER_SCLK(0:0) properties {} internal_name hps_io_spim1_inst_CLK width 1 instance_name hps_io direction output role hps_io_spim1_inst_CLK} hps_io_spim1_inst_MOSI {fragments {} properties {} internal_name hps_io_spim1_inst_MOSI width 1 instance_name hps_io tristate_output {{intermediate 29} {intermediate 28}} direction output role hps_io_spim1_inst_MOSI} hps_io_spim1_inst_MISO {fragments spim1_inst:SPI_MASTER_RXD(0:0) properties {} internal_name hps_io_spim1_inst_MISO width 1 instance_name hps_io direction input role hps_io_spim1_inst_MISO} hps_io_spim1_inst_SS0 {fragments spim1_inst:SPI_MASTER_SS_0_N(0:0) properties {} internal_name hps_io_spim1_inst_SS0 width 1 instance_name hps_io direction output role hps_io_spim1_inst_SS0} hps_io_uart0_inst_RX {fragments uart0_inst:UART_RXD(0:0) properties {} internal_name hps_io_uart0_inst_RX width 1 instance_name hps_io direction input role hps_io_uart0_inst_RX} hps_io_uart0_inst_TX {fragments uart0_inst:UART_TXD(0:0) properties {} internal_name hps_io_uart0_inst_TX width 1 instance_name hps_io direction output role hps_io_uart0_inst_TX} hps_io_i2c0_inst_SDA {fragments i2c0_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c0_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 30} {}} direction bidir role hps_io_i2c0_inst_SDA} hps_io_i2c0_inst_SCL {fragments i2c0_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c0_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 31} {}} direction bidir role hps_io_i2c0_inst_SCL} hps_io_i2c1_inst_SDA {fragments i2c1_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c1_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 32} {}} direction bidir role hps_io_i2c1_inst_SDA} hps_io_i2c1_inst_SCL {fragments i2c1_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c1_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 33} {}} direction bidir role hps_io_i2c1_inst_SCL} hps_io_gpio_inst_GPIO09 {fragments gpio_inst:GPIO0_PORTA_I(9:9) properties {} internal_name hps_io_gpio_inst_GPIO09 width 1 instance_name hps_io tristate_output {{intermediate 35} {intermediate 34}} direction bidir role hps_io_gpio_inst_GPIO09} hps_io_gpio_inst_GPIO35 {fragments gpio_inst:GPIO1_PORTA_I(6:6) properties {} internal_name hps_io_gpio_inst_GPIO35 width 1 instance_name hps_io tristate_output {{intermediate 37} {intermediate 36}} direction bidir role hps_io_gpio_inst_GPIO35} hps_io_gpio_inst_GPIO40 {fragments gpio_inst:GPIO1_PORTA_I(11:11) properties {} internal_name hps_io_gpio_inst_GPIO40 width 1 instance_name hps_io tristate_output {{intermediate 39} {intermediate 38}} direction bidir role hps_io_gpio_inst_GPIO40} hps_io_gpio_inst_GPIO48 {fragments gpio_inst:GPIO1_PORTA_I(19:19) properties {} internal_name hps_io_gpio_inst_GPIO48 width 1 instance_name hps_io tristate_output {{intermediate 41} {intermediate 40}} direction bidir role hps_io_gpio_inst_GPIO48} hps_io_gpio_inst_GPIO53 {fragments gpio_inst:GPIO1_PORTA_I(24:24) properties {} internal_name hps_io_gpio_inst_GPIO53 width 1 instance_name hps_io tristate_output {{intermediate 43} {intermediate 42}} direction bidir role hps_io_gpio_inst_GPIO53} hps_io_gpio_inst_GPIO54 {fragments gpio_inst:GPIO1_PORTA_I(25:25) properties {} internal_name hps_io_gpio_inst_GPIO54 width 1 instance_name hps_io tristate_output {{intermediate 45} {intermediate 44}} direction bidir role hps_io_gpio_inst_GPIO54} hps_io_gpio_inst_GPIO61 {fragments gpio_inst:GPIO2_PORTA_I(3:3) properties {} internal_name hps_io_gpio_inst_GPIO61 width 1 instance_name hps_io tristate_output {{intermediate 47} {intermediate 46}} direction bidir role hps_io_gpio_inst_GPIO61}}}} raw_assign_sim_style {}" />
  <parameter name="MEM_IF_CHIP_BITS" value="-1" />
  <parameter name="ENUM_MEM_IF_CS_PER_RANK" value="MEM_IF_CS_PER_RANK_1" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MEM_IF_CK_WIDTH" value="0" />
  <parameter name="MEM_TCL" value="11" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="0" />
  <parameter name="ENUM_LOCAL_IF_CS_WIDTH" value="ADDR_WIDTH_2" />
  <parameter name="TIMING_TDQSCK" value="255" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="CTL_USR_REFRESH_EN" value="false" />
  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
  <parameter name="ENUM_WR_FIFO_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_WR_FIFO_IN_USE_2" value="FALSE" />
  <parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP" value="0" />
  <parameter name="ENUM_WR_FIFO_IN_USE_1" value="FALSE" />
  <parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_WR_FIFO_IN_USE_0" value="FALSE" />
  <parameter name="ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="AFI_RATE_RATIO" value="0" />
  <parameter name="ENUM_THLD_JAR2_3" value="THRESHOLD_16" />
  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
  <parameter name="ENUM_THLD_JAR2_4" value="THRESHOLD_16" />
  <parameter name="ENUM_THLD_JAR2_5" value="THRESHOLD_16" />
  <parameter name="AV_PORT_0_CONNECT_TO_CV_PORT" value="0" />
  <parameter name="PLL_MEM_CLK_DIV_CACHE" value="0" />
  <parameter name="ENUM_CTL_ECC_RMW_ENABLED" value="CTL_ECC_RMW_DISABLED" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="0" />
  <parameter name="CFG_TCCD_NS" value="2.5" />
  <parameter name="IO_DQS_IN_RESERVE" value="3" />
  <parameter name="AVL_NUM_SYMBOLS" value="2" />
  <parameter name="ENABLE_NIOS_OCI" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="FIX_READ_LATENCY" value="8" />
  <parameter name="CTL_OUTPUT_REGD" value="false" />
  <parameter name="CV_PORT_0_CONNECT_TO_AV_PORT" value="0" />
  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
  <parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
  <parameter name="CTL_CSR_ENABLED" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH" value="0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PHY_CSR_ENABLED" value="false" />
  <parameter name="DQ_DDR" value="0" />
  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_WRITE_CLK_PHASE_DEG" value="0.0" />
  <parameter name="MEM_INIT_FILE" value="" />
  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
  <parameter name="AVL_PORT" value="" />
  <parameter name="TB_RATE" value="" />
  <parameter name="REF_CLK_FREQ_CACHE_VALID" value="false" />
  <parameter name="ALLOCATED_RFIFO_PORT" value="0,None,None,None,None,None" />
  <parameter name="MEM_CK_WIDTH" value="1" />
  <parameter name="MEM_ATCL" value="Disabled" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="AC_ROM_MR0_DLL_RESET" value="" />
  <parameter name="MEM_TDQSCK" value="2" />
  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
  <parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD" value="0" />
  <parameter name="MEM_WTCL" value="8" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP" value="0" />
  <parameter name="CV_ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_MEM_CLK_MULT" value="0" />
  <parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="MEM_IF_CS_PER_DIMM" value="0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="" />
  <parameter name="CTL_ECC_CSR_ENABLED" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP" value="0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
  <parameter name="MEM_AUTO_PD_CYCLES" value="0" />
  <parameter name="CV_ENUM_CPORT3_TYPE" value="DISABLE" />
  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
  <parameter name="PLL_WRITE_CLK_DIV" value="0" />
  <parameter name="CALIB_VFIFO_OFFSET" value="-1" />
  <parameter name="CTL_ECC_MULTIPLES_40_72" value="0" />
  <parameter name="MSB_RFIFO_PORT_2" value="5" />
  <parameter name="MSB_RFIFO_PORT_3" value="5" />
  <parameter name="MSB_RFIFO_PORT_4" value="5" />
  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
  <parameter name="MSB_RFIFO_PORT_5" value="5" />
  <parameter name="CV_ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
  <parameter name="MEM_DRV_STR" value="RZQ/7" />
  <parameter name="MEM_TREFI" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="NUM_SUBGROUP_PER_READ_DQS" value="0" />
  <parameter name="TIMING_BOARD_AC_SKEW" value="0.03" />
  <parameter name="MSB_RFIFO_PORT_0" value="5" />
  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="MEM_TRP_NS" value="13.75" />
  <parameter name="MSB_RFIFO_PORT_1" value="5" />
  <parameter name="QVLD_EXTRA_FLOP_STAGES" value="0" />
  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="CTL_HRB_ENABLED" value="false" />
  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
  <parameter name="PLL_WRITE_CLK_FREQ" value="0.0" />
  <parameter name="EXTRA_SETTINGS" value="" />
  <parameter name="ENUM_MMR_CFG_MEM_BL" value="MP_BL_8" />
  <parameter name="PLL_DR_CLK_FREQ_STR" value="" />
  <parameter name="MEM_IF_CS_WIDTH" value="0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_1" value="USE_NO" />
  <parameter name="STARVE_LIMIT" value="10" />
  <parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_2" value="USE_NO" />
  <parameter name="CV_ENUM_WR_PORT_INFO_3" value="USE_NO" />
  <parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP" value="0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_4" value="USE_NO" />
  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_0" value="USE_NO" />
  <parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="false" />
  <parameter name="SEQUENCER_TYPE_CACHE" value="Unknown" />
  <parameter name="CTL_USR_REFRESH" value="0" />
  <parameter name="AV_PORT_2_CONNECT_TO_CV_PORT" value="2" />
  <parameter name="PLL_MEM_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_5" value="USE_NO" />
  <parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
  <parameter name="MR0_BT" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL" value="0" />
  <parameter name="MR1_AL" value="0" />
  <parameter name="DQS_PHASE_SHIFT" value="9000" />
  <parameter name="MR0_BL" value="2" />
  <parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.09" />
  <parameter name="MEM_TRCD" value="0" />
  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
  <parameter name="MAX_PENDING_RD_CMD" value="32" />
  <parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
  <parameter name="REGISTER_C2P" value="false" />
  <parameter name="MEM_WTCL_INT" value="6" />
  <parameter name="MEM_IF_ROW_ADDR_WIDTH" value="0" />
  <parameter name="DQS_EN_DELAY_MAX" value="-1" />
  <parameter name="ENUM_CPORT1_TYPE" value="DISABLE" />
  <parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
  <parameter name="MR1_BL" value="2" />
  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
  <parameter name="MR1_BT" value="0" />
  <parameter name="REF_CLK_FREQ" value="25.0" />
  <parameter name="AV_PORT_5_CONNECT_TO_CV_PORT" value="5" />
  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
  <parameter name="PLL_NIOS_CLK_DIV" value="0" />
  <parameter name="MR0_DLL" value="1" />
  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
  <parameter name="PINGPONGPHY_EN" value="false" />
  <parameter name="CFG_WRITE_ODT_CHIP" value="0" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_5" value="2" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="" />
  <parameter name="MR2_ASR" value="0" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_3" value="2" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_4" value="2" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_1" value="2" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_2" value="2" />
  <parameter name="MR2_CWL" value="1" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_0" value="2" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV" value="0" />
  <parameter name="HPS_PROTOCOL" value="DDR3" />
  <parameter name="MEM_IF_LRDIMM_RM" value="0" />
  <parameter name="VECT_ATTR_COUNTER_ONE_MATCH" value="0" />
  <parameter name="ENUM_PRIORITY_1_5" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_1" value="WEIGHT_0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ENUM_PRIORITY_1_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="DUPLICATE_AC" value="false" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_5" value="2" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_1" value="2" />
  <parameter name="DUAL_WRITE_CLOCK" value="false" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_2" value="2" />
  <parameter name="AC_ROM_MR1_MIRR" value="" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_3" value="2" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_4" value="2" />
  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
  <parameter name="CFG_POWER_SAVING_EXIT_CYCLES" value="0" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_0" value="2" />
  <parameter name="CV_PORT_2_CONNECT_TO_AV_PORT" value="2" />
  <parameter name="MR1_DS" value="0" />
  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="AUTO_PD_CYCLES" value="0" />
  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
  <parameter name="ENUM_CPORT5_TYPE" value="DISABLE" />
  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD" value="0" />
  <parameter name="AFI_BANKADDR_WIDTH" value="0" />
  <parameter name="CV_ENUM_CPORT0_TYPE" value="DISABLE" />
  <parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_THLD_JAR2_0" value="THRESHOLD_16" />
  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
  <parameter name="CTL_TBP_NUM" value="4" />
  <parameter name="ENUM_THLD_JAR2_1" value="THRESHOLD_16" />
  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
  <parameter name="ENUM_THLD_JAR2_2" value="THRESHOLD_16" />
  <parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
  <parameter name="CTL_ENABLE_BURST_TERMINATE_INT" value="false" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CFG_ECC_DECODER_REG" value="0" />
  <parameter name="CTL_ENABLE_BURST_INTERRUPT_INT" value="false" />
  <parameter name="REF_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="TRACKING_ERROR_TEST" value="false" />
  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="REF_CLK_FREQ_STR" value="" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
  <parameter name="PLL_MEM_CLK_FREQ" value="0.0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
  <parameter name="MR1_RTT" value="1" />
  <parameter name="READ_FIFO_HALF_RATE" value="false" />
  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="" />
  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
  <parameter name="CSR_DATA_WIDTH" value="32" />
  <parameter name="MEM_DLL_EN" value="true" />
  <parameter name="IS_ES_DEVICE" value="false" />
  <parameter name="PRE_V_SERIES_FAMILY" value="false" />
  <parameter name="USE_MM_ADAPTOR" value="true" />
  <parameter name="HHP_HPS_SIMULATION" value="false" />
  <parameter name="CV_ENUM_PRIORITY_6_1" value="WEIGHT_0" />
  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
  <parameter name="CV_ENUM_PRIORITY_6_0" value="WEIGHT_0" />
  <parameter name="IO_OUT2_DELAY_MAX" value="-1" />
  <parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
  <parameter name="PLL_MEM_CLK_MULT_CACHE" value="0" />
  <parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
  <parameter name="HCX_COMPAT_MODE" value="false" />
  <parameter name="MEM_IF_DQSN_EN" value="true" />
  <parameter name="ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="AC_ROM_MR0" value="" />
  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MEM_TRAS" value="0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_ECC_DQ_WIDTH" value="ECC_DQ_WIDTH_0" />
  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP" value="0" />
  <parameter name="MEM_TINIT_US" value="500" />
  <parameter name="CTL_SELF_REFRESH" value="0" />
  <parameter name="ENUM_MEM_IF_TWTR" value="TWTR_4" />
  <parameter name="CALIBRATION_MODE" value="Skip" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
  <parameter name="ENUM_USER_ECC_EN" value="DISABLE" />
  <parameter name="PLL_MEM_CLK_DIV" value="0" />
  <parameter name="OCT_SHARING_MODE" value="None" />
  <parameter name="AC_ROM_MR2" value="" />
  <parameter name="AC_ROM_MR1" value="" />
  <parameter name="PLL_AFI_PHY_CLK_DIV" value="0" />
  <parameter name="AC_ROM_MR3" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH" value="0" />
  <parameter name="USE_HARD_READ_FIFO" value="false" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID" value="0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
  <parameter name="ENUM_CFG_BURST_LENGTH" value="BL_8" />
  <parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
  <parameter name="CV_ENUM_PRIORITY_6_3" value="WEIGHT_0" />
  <parameter name="PHY_VERSION_NUMBER" value="0" />
  <parameter name="CV_ENUM_PRIORITY_6_2" value="WEIGHT_0" />
  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
  <parameter name="CV_ENUM_PRIORITY_6_5" value="WEIGHT_0" />
  <parameter name="TIMING_BOARD_TIH_APPLIED" value="0.0" />
  <parameter name="CV_ENUM_PRIORITY_6_4" value="WEIGHT_0" />
  <parameter name="MEM_SRT" value="Normal" />
  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
  <parameter name="MEM_IF_READ_DQS_WIDTH" value="0" />
  <parameter name="PLL_WRITE_CLK_MULT_CACHE" value="0" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
  <parameter name="EXTRA_VFIFO_SHIFT" value="0" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
  <parameter name="CFG_TYPE" value="0" />
  <parameter name="ENUM_CLR_INTR" value="NO_CLR_INTR" />
  <parameter name="ENUM_CPORT3_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
  <parameter name="MR3_DS" value="2" />
  <parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
  <parameter name="MR2_RLWL" value="1" />
  <parameter name="DELAY_CHAIN_LENGTH" value="8" />
  <parameter name="PLL_WRITE_CLK_DIV_CACHE" value="0" />
  <parameter name="CV_ENUM_PRIORITY_4_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_2" value="WEIGHT_0" />
  <parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID" value="0" />
  <parameter name="ENUM_PRIORITY_5_5" value="WEIGHT_0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_PRIORITY_5_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_2" value="WEIGHT_0" />
  <parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="ENUM_PRIORITY_5_0" value="WEIGHT_0" />
  <parameter name="TIMING_TQHS" value="300" />
  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="0" />
  <parameter name="AV_PORT_1_CONNECT_TO_CV_PORT" value="1" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="CV_PORT_5_CONNECT_TO_AV_PORT" value="5" />
  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="0" />
  <parameter name="MEM_TMRD_CK" value="4" />
  <parameter name="CFG_INTERFACE_WIDTH" value="0" />
  <parameter name="IO_OUT1_DELAY_MAX" value="-1" />
  <parameter name="DEVICE_DEPTH" value="1" />
  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
  <parameter name="CV_ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="ENUM_MASK_CORR_DROPPED_INTR" value="DISABLED" />
  <parameter name="AC_PACKAGE_DESKEW" value="false" />
  <parameter name="ENUM_ATTR_STATIC_CONFIG_VALID" value="DISABLED" />
  <parameter name="CTL_ENABLE_WDATA_PATH_LATENCY" value="false" />
  <parameter name="ENUM_CLOCK_OFF_2" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_1" value="DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
  <parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="ENUM_CLOCK_OFF_0" value="DISABLED" />
  <parameter name="SEQ_BURST_COUNT_WIDTH" value="0" />
  <parameter name="CFG_BURST_LENGTH" value="0" />
  <parameter name="ENUM_CLOCK_OFF_5" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_4" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_3" value="DISABLED" />
  <parameter name="PHY_ONLY" value="false" />
  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="false" />
  <parameter name="TRFC" value="350" />
  <parameter name="IO_STANDARD" value="" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
  <parameter name="CV_ENUM_PRIORITY_4_5" value="WEIGHT_0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="SPEED_GRADE_CACHE" value="" />
  <parameter name="CV_ENUM_PRIORITY_4_4" value="WEIGHT_0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_AFI_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="READ_FIFO_SIZE" value="8" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="TB_MEM_IF_DQ_WIDTH" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="NEGATIVE_WRITE_CK_PHASE" value="false" />
  <parameter name="CFG_MEM_CLK_ENTRY_CYCLES" value="0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
  <parameter name="CV_ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
  <parameter name="ENUM_CFG_INTERFACE_WIDTH" value="DWIDTH_32" />
  <parameter name="ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="MEM_ATCL_INT" value="0" />
  <parameter name="ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
  <parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
  <parameter name="CV_ENUM_CPORT4_TYPE" value="DISABLE" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="TIMING_TDSS" value="0.2" />
  <parameter name="CV_ENUM_PRIORITY_2_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_0" value="WEIGHT_0" />
  <parameter name="CSR_BE_WIDTH" value="4" />
  <parameter name="CV_ENUM_PRIORITY_2_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_2" value="WEIGHT_0" />
  <parameter name="PLL_LOCATION" value="Top_Bottom" />
  <parameter name="CV_ENUM_PRIORITY_2_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_4" value="WEIGHT_0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="" />
  <parameter name="MEM_TRTP_NS" value="7.5" />
  <parameter name="CV_CPORT_TYPE_PORT_2" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_3" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_0" value="0" />
  <parameter name="PLL_SHARING_MODE" value="None" />
  <parameter name="CV_CPORT_TYPE_PORT_1" value="0" />
  <parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_4" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_5" value="0" />
  <parameter name="ENUM_PRIORITY_3_5" value="WEIGHT_0" />
  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="AP_MODE" value="false" />
  <parameter name="ENUM_PRIORITY_3_3" value="WEIGHT_0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="ENUM_PRIORITY_3_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_3_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_3_2" value="WEIGHT_0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="" />
  <parameter name="ENUM_PRIORITY_3_0" value="WEIGHT_0" />
  <parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="false" />
  <parameter name="ENUM_MEM_IF_MEMTYPE" value="DDR3_SDRAM" />
  <parameter name="MEM_PD" value="DLL off" />
  <parameter name="MAX10_RTL_SEQ" value="false" />
  <parameter name="TIMING_TDSH" value="0.2" />
  <parameter name="CTL_AUTOPCH_EN" value="false" />
  <parameter name="ENUM_PDN_EXIT_CYCLES" value="SLOW_EXIT" />
  <parameter name="REF_CLK_FREQ_MAX_CACHE" value="0.0" />
  <parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID" value="0" />
  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
  <parameter name="MEM_DQ_WIDTH" value="32" />
  <parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
  <parameter name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES" value="" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="FLY_BY" value="true" />
  <parameter name="ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="TIMING_TQSH" value="0.4" />
  <parameter name="CV_ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
  <parameter name="LSB_RFIFO_PORT_0" value="5" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ" value="0.0" />
  <parameter name="AFI_CLK_PAIR_COUNT" value="0" />
  <parameter name="HARD_EMIF" value="true" />
  <parameter name="LSB_RFIFO_PORT_5" value="5" />
  <parameter name="LSB_RFIFO_PORT_3" value="5" />
  <parameter name="LSB_RFIFO_PORT_4" value="5" />
  <parameter name="LSB_RFIFO_PORT_1" value="5" />
  <parameter name="CV_ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
  <parameter name="LSB_RFIFO_PORT_2" value="5" />
  <parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
  <parameter name="MEM_CLK_MAX_NS" value="2.5" />
  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
  <parameter name="CALIB_REG_WIDTH" value="8" />
  <parameter name="DWIDTH_RATIO" value="4" />
  <parameter name="INTG_MEM_IF_TREFI" value="3120" />
  <parameter name="CFG_CLR_INTR" value="0" />
  <parameter name="ENABLE_ABSTRACT_RAM" value="false" />
  <parameter name="ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
  <parameter name="ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_ENABLE_NO_DM" value="DISABLED" />
  <parameter name="ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="MEM_TINIT_CK" value="499" />
  <parameter name="ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
  <parameter name="MR1_PASR" value="0" />
  <parameter name="IO_DQS_OUT_RESERVE" value="3" />
  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
  <parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
  <parameter name="MEM_BL" value="OTF" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
  <parameter name="MEM_BT" value="Sequential" />
  <parameter name="ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="CONTROLLER_LATENCY" value="5" />
  <parameter name="MEM_TRTP" value="0" />
  <parameter name="ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="TREFI" value="35100" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="PLL_AFI_CLK_DIV_CACHE" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="0" />
  <parameter name="MEM_DQ_PER_DQS" value="8" />
  <parameter name="CV_ENUM_PRIORITY_0_1" value="WEIGHT_0" />
  <parameter name="ENUM_CTL_REGDIMM_ENABLED" value="REGDIMM_DISABLED" />
  <parameter name="CV_ENUM_PRIORITY_0_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_0_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_0_2" value="WEIGHT_0" />
  <parameter name="ENABLE_BURST_MERGE" value="false" />
  <parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="2" />
  <parameter name="CV_ENUM_PRIORITY_0_5" value="WEIGHT_0" />
  <parameter name="ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="CV_ENUM_PRIORITY_0_4" value="WEIGHT_0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
  <parameter name="ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.08" />
  <parameter name="CV_ENUM_CPORT5_TYPE" value="DISABLE" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="ENUM_ENABLE_BURST_TERMINATE" value="DISABLED" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
  <parameter name="VECT_ATTR_DEBUG_SELECT_BYTE" value="0" />
  <parameter name="CV_PORT_4_CONNECT_TO_AV_PORT" value="4" />
  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
  <parameter name="DEVICE_WIDTH" value="1" />
  <parameter name="SOPC_COMPAT_RESET" value="false" />
  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
  <parameter name="PLL_HR_CLK_FREQ_STR" value="" />
  <parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
  <parameter name="ENUM_ENABLE_PIPELINEGLOBAL" value="DISABLED" />
  <parameter name="COMMAND_PHASE_CACHE" value="0.0" />
  <parameter name="AFI_CONTROL_WIDTH" value="0" />
  <parameter name="PLL_HR_CLK_DIV" value="0" />
  <parameter name="REF_CLK_FREQ_MIN_CACHE" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="USER_DEBUG_LEVEL" value="1" />
  <parameter name="ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="ENUM_SINGLE_READY_3" value="CONCATENATE_RDY" />
  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
  <parameter name="ENUM_SINGLE_READY_1" value="CONCATENATE_RDY" />
  <parameter name="ENUM_SINGLE_READY_2" value="CONCATENATE_RDY" />
  <parameter name="ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="ENUM_GEN_DBE" value="GEN_DBE_DISABLED" />
  <parameter name="ENUM_SINGLE_READY_0" value="CONCATENATE_RDY" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="DATA_RATE_RATIO" value="0" />
  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
  <parameter name="ENUM_ENABLE_DQS_TRACKING" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_3" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_2" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_5" value="DISABLED" />
  <parameter name="ENUM_MEM_IF_TCL" value="TCL_6" />
  <parameter name="ENUM_ENABLE_BONDING_4" value="DISABLED" />
  <parameter name="CV_ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="CV_ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="CV_ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
  <parameter name="LOW_LATENCY" value="false" />
  <parameter name="ENUM_ENABLE_BONDING_1" value="DISABLED" />
  <parameter name="CV_ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="ENUM_ENABLE_BONDING_0" value="DISABLED" />
  <parameter name="CV_ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="CV_ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="0.0" />
  <parameter name="ENUM_MEM_IF_DQ_PER_CHIP" value="MEM_IF_DQ_PER_CHIP_8" />
  <parameter name="MR1_WC" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="" />
  <parameter name="ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_WRITE_CLK_FREQ_STR" value="" />
  <parameter name="RATE" value="Full" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MR1_WL" value="0" />
  <parameter name="POWER_OF_TWO_BUS" value="false" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="MR1_WR" value="1" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="MR3_MPR_RF" value="0" />
  <parameter name="MEM_IF_CONTROL_WIDTH" value="0" />
  <parameter name="DEBUG_MODE" value="false" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="MEM_RTT_WR" value="RZQ/4" />
  <parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="0" />
  <parameter name="CFG_STARVE_LIMIT" value="0" />
  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT" value="0" />
  <parameter name="ENUM_PRIORITY_7_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_4" value="WEIGHT_0" />
  <parameter name="MEM_CLK_MAX_PS" value="2500.0" />
  <parameter name="ENUM_PRIORITY_7_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_0" value="WEIGHT_0" />
  <parameter name="MEM_IF_NUMBER_OF_RANKS" value="0" />
  <parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="0" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
  <parameter name="ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="MEM_BURST_LENGTH" value="8" />
  <parameter name="ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="PLL_AFI_CLK_FREQ_STR" value="" />
  <parameter name="IO_DQDQS_OUT_PHASE_MAX" value="0" />
  <parameter name="MEM_TRRD" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="REFRESH_INTERVAL" value="15000" />
  <parameter name="ENUM_PRIORITY_7_5" value="WEIGHT_0" />
  <parameter name="MEM_INIT_EN" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH" value="0" />
  <parameter name="TIMING_BOARD_TDH_APPLIED" value="0.0" />
  <parameter name="ADDR_RATE_RATIO" value="0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CFG_SELF_RFSH_EXIT_CYCLES" value="0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="CTL_REGDIMM_ENABLED" value="false" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="CV_LSB_WFIFO_PORT_1" value="5" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="CV_LSB_WFIFO_PORT_0" value="5" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_0" value="0" />
  <parameter name="CV_ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="ENUM_GEN_SBE" value="GEN_SBE_DISABLED" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="ENUM_ENABLE_BONDING_WRAPBACK" value="DISABLED" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_2" value="0" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_1" value="0" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
  <parameter name="ENUM_THLD_JAR1_4" value="THRESHOLD_32" />
  <parameter name="MEM_RTT_NOM" value="RZQ/4" />
  <parameter name="ENUM_THLD_JAR1_5" value="THRESHOLD_32" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_4" value="0" />
  <parameter name="PLL_CONFIG_CLK_MULT" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_3" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_5" value="0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.16" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="AFI_WRANK_WIDTH" value="0" />
  <parameter name="LRDIMM" value="false" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MR1_DLL" value="0" />
  <parameter name="CFG_ADDR_ORDER" value="0" />
  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
  <parameter name="ENUM_WR_PORT_INFO_0" value="USE_NO" />
  <parameter name="CTL_ODT_ENABLED" value="false" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="SEQUENCER_TYPE" value="NIOS" />
  <parameter name="ENUM_WR_PORT_INFO_5" value="USE_NO" />
  <parameter name="MEM_IF_CLK_EN_WIDTH" value="0" />
  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="ENUM_WR_PORT_INFO_1" value="USE_NO" />
  <parameter name="ENUM_WR_PORT_INFO_2" value="USE_NO" />
  <parameter name="ENUM_WR_PORT_INFO_3" value="USE_NO" />
  <parameter name="VFIFO_AS_SHIFT_REG" value="false" />
  <parameter name="ENUM_WR_PORT_INFO_4" value="USE_NO" />
  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
  <parameter name="ENUM_THLD_JAR1_0" value="THRESHOLD_32" />
  <parameter name="ENUM_THLD_JAR1_1" value="THRESHOLD_32" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
  <parameter name="ENUM_THLD_JAR1_2" value="THRESHOLD_32" />
  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
  <parameter name="ENUM_THLD_JAR1_3" value="THRESHOLD_32" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="DLL_SHARING_MODE" value="None" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="ENUM_CPORT2_TYPE" value="DISABLE" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_ENABLE_ATPG" value="DISABLED" />
  <parameter name="PLL_DR_CLK_MULT" value="0" />
  <parameter name="USE_USER_RDIMM_VALUE" value="false" />
  <parameter name="MEM_FORMAT" value="DISCRETE" />
  <parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
  <parameter name="CONTROLLER_TYPE" value="nextgen_v110" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="AFI_WLAT_WIDTH" value="0" />
  <parameter name="MEM_IF_WRITE_DQS_WIDTH" value="0" />
  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="RATE_CACHE" value="Unknown" />
  <parameter name="COMMAND_PHASE" value="0.0" />
  <parameter name="CTL_CS_WIDTH" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_MULT" value="0" />
  <parameter name="ENUM_OUTPUT_REGD" value="DISABLED" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MR1_ODS" value="1" />
  <parameter name="MEM_TRFC" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="AV_PORT_4_CONNECT_TO_CV_PORT" value="4" />
  <parameter name="ENUM_SYNC_MODE_1" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="ENUM_SYNC_MODE_0" value="ASYNCHRONOUS" />
  <parameter name="ENUM_SYNC_MODE_3" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_SYNC_MODE_2" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="ENUM_CPORT1_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="ENUM_SYNC_MODE_5" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_CPORT4_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="ENUM_SYNC_MODE_4" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
  <parameter name="MEM_CK_PHASE" value="0.0" />
  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
  <parameter name="ENUM_CFG_TYPE" value="DDR3" />
  <parameter name="CV_ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="-0.01" />
  <parameter name="ADDR_ORDER" value="0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MEM_VERBOSE" value="true" />
  <parameter name="HARD_PHY" value="false" />
  <parameter name="MR2_SRF" value="0" />
  <parameter name="ENUM_CPORT4_TYPE" value="DISABLE" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="false" />
  <parameter name="ENUM_MEM_IF_BANKADDR_WIDTH" value="ADDR_WIDTH_3" />
  <parameter name="ENUM_MASK_SBE_INTR" value="DISABLED" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK" value="0" />
  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
  <parameter name="ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_READ_ODT_CHIP" value="ODT_DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
  <parameter name="VECT_ATTR_COUNTER_ONE_MASK" value="0" />
  <parameter name="MULTICAST_EN" value="false" />
  <parameter name="VCALIB_COUNT_WIDTH" value="0" />
  <parameter name="CV_ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
  <parameter name="OCT_TERM_CONTROL_WIDTH" value="14" />
  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="DLL_USE_DR_CLK" value="false" />
  <parameter name="ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="AC_PARITY" value="false" />
  <parameter name="AC_ROM_MR2_MIRR" value="" />
  <parameter name="MR1_DQS" value="0" />
  <parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES" value="DISABLED" />
  <parameter name="MR2_SRT" value="0" />
  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
  <parameter name="ENUM_MEM_IF_TMRD" value="" />
  <parameter name="CV_LSB_WFIFO_PORT_3" value="5" />
  <parameter name="CV_LSB_WFIFO_PORT_2" value="5" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CV_LSB_WFIFO_PORT_5" value="5" />
  <parameter name="CV_LSB_WFIFO_PORT_4" value="5" />
  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
  <parameter name="MR1_QOFF" value="0" />
  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
  <parameter name="TB_MEM_CLK_FREQ" value="0.0" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="DLL_DELAY_CTRL_WIDTH" value="6" />
  <parameter name="MEM_CLK_FREQ" value="400.0" />
  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
  <parameter name="CV_ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="USE_FAKE_PHY" value="false" />
  <parameter name="ENUM_MEM_IF_TWR" value="TWR_6" />
  <parameter name="SEQ_MODE" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
  <parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
  <parameter name="ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
  <parameter name="MEM_TYPE" value="" />
  <parameter name="REF_CLK_PS" value="0.0" />
  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
  <parameter name="ENUM_MEM_IF_TRAS" value="TRAS_16" />
  <parameter name="ENUM_INC_SYNC" value="FIFO_SET_2" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01" />
  <parameter name="ENUM_MEM_IF_TRCD" value="TRCD_6" />
  <parameter name="MARGIN_VARIATION_TEST" value="false" />
  <parameter name="TIMING_TIS" value="180" />
  <parameter name="ENUM_PRIORITY_0_4" value="WEIGHT_0" />
  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.03" />
  <parameter name="ENUM_PRIORITY_0_5" value="WEIGHT_0" />
  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
  <parameter name="ENUM_PRIORITY_0_2" value="WEIGHT_0" />
  <parameter name="IO_IN_DELAY_MAX" value="-1" />
  <parameter name="ENUM_PRIORITY_0_3" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID" value="0" />
  <parameter name="ENUM_PRIORITY_0_0" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_0_1" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR" value="0" />
  <parameter name="FAST_SIM_CALIBRATION" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
  <parameter name="AUTO_DEVICE" value="5CSEMA5F31C6" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="AVL_ADDR_WIDTH" value="0" />
  <parameter name="CV_ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
  <parameter name="MAX10_CFG" value="false" />
  <parameter name="CFG_REORDER_DATA" value="true" />
  <parameter name="ENUM_ENABLE_FAST_EXIT_PPD" value="DISABLED" />
  <parameter name="DELAY_BUFFER_MODE" value="HIGH" />
  <parameter name="ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="0.0" />
  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
  <parameter name="CONTINUE_AFTER_CAL_FAIL" value="false" />
  <parameter name="AFI_RRANK_WIDTH" value="0" />
  <parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="" />
  <parameter name="MR3_MPR" value="0" />
  <parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
  <parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
  <parameter name="ENUM_CFG_STARVE_LIMIT" value="STARVE_LIMIT_32" />
  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.02" />
  <parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
  <parameter name="MEM_IF_ODT_WIDTH" value="0" />
  <parameter name="TIMING_TDQSCKDL" value="1200" />
  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
  <parameter name="TIMING_TDQSCKDS" value="450" />
  <parameter name="TIMING_TDQSCKDM" value="900" />
  <parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="TIMING_BOARD_TIS" value="0.0" />
  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
  <parameter name="ENUM_MEM_IF_TCCD" value="TCCD_4" />
  <parameter name="CV_ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
  <parameter name="NIOS_HEX_FILE_LOCATION" value="" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="" />
  <parameter name="AVL_BE_WIDTH" value="0" />
  <parameter name="AVL_MAX_SIZE" value="4" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
  <parameter name="TIMING_BOARD_TIH" value="0.0" />
  <parameter name="PLL_WRITE_CLK_MULT" value="0" />
  <parameter name="ENUM_CTL_USR_REFRESH" value="CTL_USR_REFRESH_DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="TIMING_BOARD_TDS" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="CV_ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
  <parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
  <parameter name="CFG_ERRCMD_FIFO_REG" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
  <parameter name="TIMING_BOARD_TDH" value="0.0" />
  <parameter name="PACKAGE_DESKEW" value="false" />
  <parameter name="PLL_NIOS_CLK_PHASE_DEG" value="0.0" />
  <parameter name="TRACKING_WATCH_TEST" value="false" />
  <parameter name="ENUM_DISABLE_MERGING" value="MERGING_ENABLED" />
  <parameter name="CV_ENUM_PRIORITY_7_0" value="WEIGHT_0" />
  <parameter name="ENUM_CTL_ADDR_ORDER" value="CHIP_BANK_ROW_COL" />
  <parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="AFI_DM_WIDTH" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_CONFIG_CLK_DIV" value="0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
  <parameter name="ENUM_CTL_ECC_ENABLED" value="CTL_ECC_DISABLED" />
  <parameter name="BYTE_ENABLE" value="true" />
  <parameter name="USE_SHADOW_REGS" value="false" />
  <parameter name="ENUM_MEM_IF_CS_WIDTH" value="MEM_IF_CS_WIDTH_1" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="MEM_IF_BANKADDR_WIDTH" value="0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="CV_ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
  <parameter name="ENUM_CAL_REQ" value="DISABLED" />
  <parameter name="ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
  <parameter name="MEM_IF_DQ_WIDTH" value="0" />
  <parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
  <parameter name="ADDR_CMD_DDR" value="0" />
  <parameter name="GENERIC_PLL" value="false" />
  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="ENABLE_NON_DES_CAL" value="false" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="MR3_MPR_AA" value="0" />
  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_1" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_0" value="0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_3" value="0" />
  <parameter name="MEM_TFAW_NS" value="30.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_2" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ" value="0.0" />
  <parameter name="AVL_DATA_WIDTH_PORT_5" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_4" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_3" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_2" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_1" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_0" value="0" />
  <parameter name="REF_CLK_NS" value="0.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_5" value="0" />
  <parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_4" value="0" />
  <parameter name="AFI_CLK_EN_WIDTH" value="0" />
  <parameter name="TIMING_TQH" value="0.38" />
  <parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_CLK_CACHE_VALID" value="false" />
  <parameter name="ENUM_MEM_IF_DWIDTH" value="MEM_IF_DWIDTH_32" />
  <parameter name="ENUM_RD_PORT_INFO_2" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="ENUM_RD_PORT_INFO_3" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_RD_PORT_INFO_4" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_MEM_IF_SPEEDBIN" value="DDR3_1066_6_6_6" />
  <parameter name="ENUM_RD_PORT_INFO_5" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="ENUM_CPORT0_TYPE" value="DISABLE" />
  <parameter name="CV_ENUM_PRIORITY_7_2" value="WEIGHT_0" />
  <parameter name="PLL_HR_CLK_MULT" value="0" />
  <parameter name="ENUM_MEM_IF_TRP" value="TRP_6" />
  <parameter name="CV_ENUM_PRIORITY_7_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_7_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_7_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_ENUM_PRIORITY_7_5" value="WEIGHT_0" />
  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="HHP_HPS" value="true" />
  <parameter name="CV_ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
  <parameter name="ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
  <parameter name="AVL_SIZE_WIDTH" value="0" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="" />
  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
  <parameter name="RDBUFFER_ADDR_WIDTH" value="6" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_MEM_IF_TRC" value="TRC_22" />
  <parameter name="ENUM_RD_PORT_INFO_0" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="ENUM_RD_PORT_INFO_1" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
  <parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
  <parameter name="DAT_DATA_WIDTH" value="32" />
  <parameter
     name="CPORT_TYPE_PORT"
     value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
  <parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
  <parameter name="AC_ROM_MR1_CALIB" value="" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="INTG_CYC_TO_RLD_JARS_5" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_4" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_3" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_2" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_1" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_0" value="1" />
  <parameter name="SPEED_GRADE" value="7" />
  <parameter name="CV_ENUM_PRIORITY_5_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_5_2" value="WEIGHT_0" />
  <parameter name="PLL_NIOS_CLK_FREQ" value="0.0" />
  <parameter name="ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
  <parameter name="CV_ENUM_PRIORITY_5_1" value="WEIGHT_0" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="0" />
  <parameter name="MEM_TRCD_NS" value="13.75" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="ENUM_PRIORITY_4_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_5" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_0" value="WEIGHT_0" />
  <parameter name="AFI_ADDR_WIDTH" value="0" />
  <parameter name="ENUM_PRIORITY_4_1" value="WEIGHT_0" />
  <parameter name="USE_HPS_DQS_TRACKING" value="false" />
  <parameter name="MEM_IF_COL_ADDR_WIDTH" value="0" />
  <parameter name="EXPORT_CSR_PORT" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="" />
  <parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
  <parameter name="MSB_WFIFO_PORT_0" value="5" />
  <parameter name="CV_LSB_RFIFO_PORT_5" value="5" />
  <parameter name="MSB_WFIFO_PORT_1" value="5" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="TIMING_TDS" value="30" />
  <parameter name="MSB_WFIFO_PORT_2" value="5" />
  <parameter name="MSB_WFIFO_PORT_3" value="5" />
  <parameter name="MEM_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="MSB_WFIFO_PORT_4" value="5" />
  <parameter name="MSB_WFIFO_PORT_5" value="5" />
  <parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
  <parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
  <parameter name="CFG_TCCD" value="0" />
  <parameter name="ENUM_MEM_IF_AL" value="AL_0" />
  <parameter name="ENUM_TEST_MODE" value="NORMAL_MODE" />
  <parameter name="MEM_CS_WIDTH" value="1" />
  <parameter name="CV_LSB_RFIFO_PORT_0" value="5" />
  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
  <parameter name="ENUM_CPORT0_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="CV_LSB_RFIFO_PORT_2" value="5" />
  <parameter name="CV_LSB_RFIFO_PORT_1" value="5" />
  <parameter name="TIMING_TDH" value="65" />
  <parameter name="AV_PORT_3_CONNECT_TO_CV_PORT" value="3" />
  <parameter name="CV_LSB_RFIFO_PORT_4" value="5" />
  <parameter name="SCC_DATA_WIDTH" value="0" />
  <parameter name="CV_LSB_RFIFO_PORT_3" value="5" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC" value="0" />
  <parameter name="CV_ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ" value="0.0" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="MEM_TREFI_US" value="7.8" />
  <parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
  <parameter name="USE_DQS_TRACKING" value="false" />
  <parameter name="MEM_LRDIMM_ENABLED" value="false" />
  <parameter name="TIMING_BOARD_TIS_APPLIED" value="0.0" />
  <parameter name="ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.01" />
  <parameter name="ENUM_MEM_IF_DQS_WIDTH" value="DQS_WIDTH_4" />
  <parameter name="CTL_ZQCAL_EN" value="false" />
  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
  <parameter name="ENUM_DFX_BYPASS_ENABLE" value="DFX_BYPASS_DISABLED" />
  <parameter name="AC_ROM_MR0_CALIB" value="" />
  <parameter name="MEM_TWR_NS" value="15.0" />
  <parameter name="ENUM_CTRL_WIDTH" value="DATA_WIDTH_64_BIT" />
  <parameter name="MEM_T_WL" value="0" />
  <parameter name="CV_ENUM_PRIORITY_5_4" value="WEIGHT_0" />
  <parameter name="AFI_WRITE_DQS_WIDTH" value="0" />
  <parameter name="CV_ENUM_PRIORITY_5_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_5_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_CPORT2_TYPE" value="DISABLE" />
  <parameter name="AFI_RLAT_WIDTH" value="0" />
  <parameter name="ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
  <parameter name="MEM_TRP" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR" value="0" />
  <parameter name="MEM_CLK_PS" value="0.0" />
  <parameter name="IS_ES_DEVICE_CACHE" value="false" />
  <parameter name="PLL_AFI_CLK_FREQ" value="0.0" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_1" value="EMPTY" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_2" value="EMPTY" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_3" value="EMPTY" />
  <parameter name="MEM_TRRD_NS" value="7.7" />
  <parameter name="CV_PORT_3_CONNECT_TO_AV_PORT" value="3" />
  <parameter name="ENUM_DELAY_BONDING" value="BONDING_LATENCY_0" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_0" value="EMPTY" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="DQS_IN_DELAY_MAX" value="-1" />
  <parameter name="LSB_WFIFO_PORT_4" value="5" />
  <parameter name="LSB_WFIFO_PORT_5" value="5" />
  <parameter name="LSB_WFIFO_PORT_2" value="5" />
  <parameter name="LSB_WFIFO_PORT_3" value="5" />
  <parameter name="MR0_CAS_LATENCY" value="3" />
  <parameter name="LSB_WFIFO_PORT_0" value="5" />
  <parameter name="LSB_WFIFO_PORT_1" value="5" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.05" />
  <parameter name="CFG_PDN_EXIT_CYCLES" value="0" />
  <parameter name="MR0_WR" value="4" />
  <parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="CV_ENUM_PRIORITY_3_0" value="WEIGHT_0" />
  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
  <parameter name="CV_ENUM_PRIORITY_3_2" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_3" value="WEIGHT_0" />
  <parameter name="PLL_MEM_CLK_FREQ_STR" value="" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
  <parameter name="LOCAL_ID_WIDTH" value="8" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="TIMING_TDQSS" value="0.25" />
  <parameter name="TIMING_TDQSQ" value="125" />
  <parameter name="ENUM_PRIORITY_2_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_PRIORITY_2_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_0" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="ENUM_PRIORITY_2_1" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="TIMING_TDQSH" value="0.35" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="USE_2X_FF" value="false" />
  <parameter name="MEM_ASR" value="Manual" />
  <parameter name="ENUM_RD_FIFO_IN_USE_2" value="FALSE" />
  <parameter name="PLL_DR_CLK_FREQ" value="0.0" />
  <parameter name="ENUM_RD_FIFO_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_RD_FIFO_IN_USE_0" value="FALSE" />
  <parameter name="ENUM_RD_FIFO_IN_USE_1" value="FALSE" />
  <parameter name="ADVANCED_CK_PHASES" value="false" />
  <parameter name="ENUM_REORDER_DATA" value="DATA_REORDERING" />
  <parameter name="NEXTGEN" value="true" />
  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
  <parameter name="PRIORITY_PORT_0" value="0" />
  <parameter name="MEM_T_RL" value="0" />
  <parameter name="MEM_TWR" value="0" />
  <parameter name="PRIORITY_PORT_2" value="0" />
  <parameter name="PRIORITY_PORT_1" value="0" />
  <parameter name="USE_DR_CLK" value="false" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="AC_ROM_MR3_MIRR" value="" />
  <parameter name="ENABLE_EMIT_JTAG_MASTER" value="false" />
  <parameter name="CPORT_TYPE_PORT_3" value="0" />
  <parameter name="MEM_IF_DQS_WIDTH" value="0" />
  <parameter name="CPORT_TYPE_PORT_2" value="0" />
  <parameter name="CPORT_TYPE_PORT_1" value="0" />
  <parameter name="TIMING_TIH" value="140" />
  <parameter name="CPORT_TYPE_PORT_0" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD" value="0" />
  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
  <parameter name="USE_AXI_ADAPTOR" value="false" />
  <parameter name="PRIORITY_PORT_4" value="0" />
  <parameter name="PRIORITY_PORT_3" value="0" />
  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
  <parameter name="PRIORITY_PORT_5" value="0" />
  <parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
  <parameter name="ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
  <parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
  <parameter name="ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
  <parameter name="ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
  <parameter name="NUM_OF_PORTS" value="1" />
  <parameter name="CV_ENUM_PRIORITY_3_5" value="WEIGHT_0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="false" />
  <parameter name="ENUM_CPORT3_TYPE" value="DISABLE" />
  <parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
  <parameter
     name="hps_parameter_map"
     value="AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 1.25 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 200000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 32 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 4 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 1000.0 MEM_TRCD 6 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA5F31C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 14 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 25.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 64 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 125 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.02 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 32 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 25.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 25000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 2500.0 periph_pll_vco_hz 1000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 30 PLL_WRITE_CLK_PHASE_PS_CACHE 1875 UART0_PinMuxing {HPS I/O Set 0} sdmmc_clk_hz 200000000 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode RGMII NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz 1600000000 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 2.5 PLL_AFI_CLK_MULT_CACHE 32 PLL_ADDR_CMD_CLK_DIV 2 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 3 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 32 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {45000 ps} PLL_AFI_CLK_DIV 2 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 13.75 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 400.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 2 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.8 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.08 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 25000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 200.0 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 180 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {25.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.03 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 6 TIMING_TIH 140 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 0 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing {HPS I/O Set 0} desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 200000000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_8 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 1875 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 200.0 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 30 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 6 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 65 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {2500 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 20 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 32 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 64 PLL_AFI_PHY_CLK_FREQ 400.0 periph_nand_sdmmc_clk_mhz 200.0 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000110 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No Yes No No No No Yes No No No No No No No Yes No No No No Yes Yes No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 4 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {400.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode I2C IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 12500000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.09 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 200000000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 35.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 2 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {2500 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED true TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode {No Flow Control} S2FCLK_USER0CLK_FREQ_HZ 97368421 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 800.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 4 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 1875 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 8 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 10 dbg_timer_clk_hz 25000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode {Single Slave Select} hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 97.368421 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM RZQ/4 AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 40000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_6 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 13.75 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 8 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.16 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 40.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 2 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 400.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_6 MR2_RTT_WR 1 MEM_TCL 11 GPIO_Pin_Used_DERIVED true JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 104 USE_2X_FF false ENUM_MEM_IF_TRC TRC_20 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 27 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 50000000 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable true desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 2 F2SDRAM_Width {} dbg_clk_hz 12500000 PLL_AFI_CLK_FREQ 400.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.18 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 400.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 66.6666666667 dbg_timer_clk_mhz 25.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {2500 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 9 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 0 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {1875 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 15 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 100.0 PLL_AFI_HALF_CLK_MULT_CACHE 32 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 32 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 400.0 AFI_WRITE_DQS_WIDTH 4 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 200.0 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 25000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.16 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 10 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 200.0 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz 1600.0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.33 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {1875 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {2500 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 15 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {1875 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0010011101000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/7 MEM_IF_DM_WIDTH 4 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.7 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 32 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 32 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 30.0 DELAY_PER_OPA_TAP 312 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing {HPS I/O Set 0} MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {2500 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 12.5 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 6000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 2 ENUM_MEM_IF_TCL TCL_11 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR JEDEC device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing {HPS I/O Set 0} CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_4 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 2 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 97.368421 MR2_CWL 3 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 211 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 39 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 12.5 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 73 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 400.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 15 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 1 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 32000 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 MR0_BT 0 PLL_CONFIG_CLK_FREQ 22.2222222222 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 1 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {400.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 32 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 25.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR RZQ/4 TIMING_TDQSCK 255 REF_CLK_FREQ_CACHE 25.0 AC_ROM_MR0_DLL_RESET 0010101110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {15000 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0010001101001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 12 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {400.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing {HPS I/O Set 0} MEM_TREFI 3120 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 32 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 25.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.09 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {2500 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 4 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 10 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_6 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 50000000 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.165 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {2500 ps} emac1_clk_mhz 250.0 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 500 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 32 TIMING_BOARD_SKEW_WITHIN_DQS 0.01 ENUM_MEM_IF_TRAS TRAS_14 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 1 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.03 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 7 H2F_LW_AXI_CLOCK_FREQ 50000000 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {400.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 2 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {1875 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 12500000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 250000000 eosc2_clk_mhz 25.0 PLL_MEM_CLK_DIV_CACHE 2 periph_base_clk_mhz 200.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_32 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 8 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.24 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing {HPS I/O Set 0} INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 400.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 25.0 desired_cfg_clk_hz 97368421 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 2 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 200000000 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 4 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {5000 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 8 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 11 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 200000000 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 6249 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0001000011000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode I2C quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 3120 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 1875 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {400.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 4 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 260.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY true ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 4 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 1 pin_muxing_check {Cyclone V+5CSEMA5F31C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 100000000 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 2 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 200000 PLL_WRITE_CLK_MULT_CACHE 32 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 400.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 4 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 50.0 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} USB1.D0 USB1.D1 USB1.D2 USB1.D3 USB1.D4 USB1.D5 USB1.D6 USB1.D7 {} USB1.CLK USB1.STP USB1.DIR USB1.NXT EMAC1.TX_CLK EMAC1.TXD0 EMAC1.TXD1 EMAC1.TXD2 EMAC1.TXD3 EMAC1.RXD0 EMAC1.MDIO EMAC1.MDC EMAC1.RX_CTL EMAC1.TX_CTL EMAC1.RX_CLK EMAC1.RXD1 EMAC1.RXD2 EMAC1.RXD3 {} {} {} {} {} {} {} {} SDIO.CMD {} SDIO.D0 SDIO.D1 {} {} {} {} {} SDIO.CLK SDIO.D2 SDIO.D3 {} UART0.RX UART0.TX I2C1.SDA I2C1.SCL {} {} I2C0.SDA I2C0.SCL {} {} {} {} {} {} SPIM1.CLK SPIM1.MOSI SPIM1.MISO SPIM1.SS0} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 8 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 400.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 8 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 32 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0001000011000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000000000110 TB_MEM_CLK_FREQ 400.0 AC_ROM_MR0 0010001110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 18000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 400.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {2500 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 12.5 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 5 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_4 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing {HPS I/O Set 0} CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 25000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {5000 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode SDR ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.4 dbg_base_clk_hz 25000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 400.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 2 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 1250.0 S2FCLK_USER1CLK_Enable true SDIO_Mode {4-bit Data} desired_qspi_clk_mhz 400.0 MEM_TRFC 104 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="CPORT_TYPE_PORT_5" value="0" />
  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
  <parameter name="CPORT_TYPE_PORT_4" value="0" />
  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="CV_MSB_RFIFO_PORT_1" value="5" />
  <parameter name="CV_MSB_RFIFO_PORT_0" value="5" />
  <parameter name="PLL_AFI_CLK_DIV" value="0" />
  <parameter name="ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
  <parameter name="CV_MSB_RFIFO_PORT_5" value="5" />
  <parameter name="MEM_TFAW" value="0" />
  <parameter name="CV_MSB_RFIFO_PORT_4" value="5" />
  <parameter name="CV_MSB_RFIFO_PORT_3" value="5" />
  <parameter name="CV_ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_MSB_RFIFO_PORT_2" value="5" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_inst_ROM.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_AC_ROM.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sdram_io.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/alt_types.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/system.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/tclrpt.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/tclrpt.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_defines.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/emif.pre.xml"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_parameters.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_pin_map.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_report_timing_core.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_report_timing.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_timing.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.sdc"
       type="SDC"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.ppf"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_pll.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sdc"
       type="SDC"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps.pre.xml"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_hps_io/altera_hps_io_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_interface_generator/altera_interface_generator_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
  </childSourceFiles>
  <instantiator instantiator="soc_system_hps_0" as="hps_io" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 29 starting:altera_hps_io "submodules/soc_system_hps_0_hps_io"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="hps_io"><![CDATA["<b>hps_io</b>" reuses <b>altera_interface_generator</b> "<b>submodules/soc_system_hps_0_hps_io_border</b>"]]></message>
   <message level="Info" culprit="hps_io"><![CDATA["<b>hps_0</b>" instantiated <b>altera_hps_io</b> "<b>hps_io</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 2 starting:altera_interface_generator "submodules/soc_system_hps_0_hps_io_border"</message>
   <message level="Info" culprit="border"><![CDATA["<b>hps_io</b>" instantiated <b>altera_interface_generator</b> "<b>border</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_slave_translator:21.1:AV_ADDRESSGROUP=0,AV_ADDRESS_SYMBOLS=0,AV_ADDRESS_W=16,AV_ALWAYSBURSTMAXBURST=0,AV_BITS_PER_SYMBOL=8,AV_BURSTBOUNDARIES=0,AV_BURSTCOUNT_SYMBOLS=0,AV_BURSTCOUNT_W=1,AV_BYTEENABLE_W=4,AV_CONSTANT_BURST_BEHAVIOR=0,AV_DATA_HOLD=0,AV_DATA_HOLD_CYCLES=0,AV_DATA_W=32,AV_INTERLEAVEBURSTS=0,AV_ISBIGENDIAN=0,AV_LINEWRAPBURSTS=0,AV_MAX_PENDING_READ_TRANSACTIONS=1,AV_MAX_PENDING_WRITE_TRANSACTIONS=0,AV_READLATENCY=0,AV_READ_WAIT=1,AV_READ_WAIT_CYCLES=1,AV_REGISTERINCOMINGSIGNALS=0,AV_REGISTEROUTGOINGSIGNALS=0,AV_REQUIRE_UNALIGNED_ADDRESSES=0,AV_SETUP_WAIT=0,AV_SETUP_WAIT_CYCLES=0,AV_SYMBOLS_PER_WORD=4,AV_TIMING_UNITS=1,AV_WRITE_WAIT=0,AV_WRITE_WAIT_CYCLES=0,CHIPSELECT_THROUGH_READLATENCY=0,CLOCK_RATE=50000000,UAV_ADDRESSGROUP=0,UAV_ADDRESS_W=21,UAV_BURSTCOUNT_W=3,UAV_BYTEENABLE_W=4,UAV_CONSTANT_BURST_BEHAVIOR=0,UAV_DATA_W=32,USE_ADDRESS=1,USE_AV_CLKEN=0,USE_BEGINBURSTTRANSFER=0,USE_BEGINTRANSFER=0,USE_BURSTCOUNT=0,USE_BYTEENABLE=0,USE_CHIPSELECT=1,USE_DEBUGACCESS=0,USE_LOCK=0,USE_OUTPUTENABLE=0,USE_READ=0,USE_READDATA=0,USE_READDATAVALID=0,USE_READRESPONSE=0,USE_UAV_CLKEN=0,USE_WAITREQUEST=0,USE_WRITE=1,USE_WRITEBYTEENABLE=0,USE_WRITEDATA=1,USE_WRITERESPONSE=0"
   instancePathKey="soc_system:.:mm_interconnect_0:.:admm_solver_0_avalon_slave_0_translator"
   kind="altera_merlin_slave_translator"
   version="21.1"
   name="altera_merlin_slave_translator">
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_slave_translator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="soc_system_mm_interconnect_0"
     as="admm_solver_0_avalon_slave_0_translator,RAM_s1_translator" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 29 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_translator"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>admm_solver_0_avalon_slave_0_translator</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_axi_master_ni:21.1:ADDR_MAP=&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;1&quot;
   name=&quot;admm_solver_0_avalon_slave_0_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000040000&quot;
   responds=&quot;0&quot;
   user_default=&quot;0&quot; /&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;RAM_s1_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000040000&quot;
   end=&quot;0x00000000000042000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
,ADDR_USER_WIDTH=1,ADDR_WIDTH=21,AXI_BURST_LENGTH_WIDTH=4,AXI_LOCK_WIDTH=2,AXI_VERSION=AXI3,DATA_USER_WIDTH=1,ID=0,ID_WIDTH=12,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),PKT_ADDR_H=56,PKT_ADDR_L=36,PKT_ADDR_SIDEBAND_H=82,PKT_ADDR_SIDEBAND_L=82,PKT_BEGIN_BURST=84,PKT_BURSTWRAP_H=76,PKT_BURSTWRAP_L=70,PKT_BURST_SIZE_H=79,PKT_BURST_SIZE_L=77,PKT_BURST_TYPE_H=81,PKT_BURST_TYPE_L=80,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=69,PKT_BYTE_CNT_L=63,PKT_CACHE_H=106,PKT_CACHE_L=103,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DATA_SIDEBAND_H=83,PKT_DATA_SIDEBAND_L=83,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_ORI_BURST_SIZE_H=111,PKT_ORI_BURST_SIZE_L=109,PKT_PROTECTION_H=102,PKT_PROTECTION_L=100,PKT_QOS_H=85,PKT_QOS_L=85,PKT_RESPONSE_STATUS_H=108,PKT_RESPONSE_STATUS_L=107,PKT_SRC_ID_H=86,PKT_SRC_ID_L=86,PKT_THREAD_ID_H=99,PKT_THREAD_ID_L=88,PKT_TRANS_COMPRESSED_READ=57,PKT_TRANS_EXCLUSIVE=62,PKT_TRANS_LOCK=61,PKT_TRANS_POSTED=58,PKT_TRANS_READ=60,PKT_TRANS_WRITE=59,RDATA_WIDTH=32,READ_ISSUING_CAPABILITY=8,ST_CHANNEL_W=2,ST_DATA_W=112,USE_ADDR_USER=0,WDATA_WIDTH=32,WRITE_ISSUING_CAPABILITY=8"
   instancePathKey="soc_system:.:mm_interconnect_0:.:hps_0_h2f_lw_axi_master_agent"
   kind="altera_merlin_axi_master_ni"
   version="21.1"
   name="altera_merlin_axi_master_ni">
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_axi_master_ni.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_axi_master_ni/altera_merlin_axi_master_ni_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="soc_system_mm_interconnect_0"
     as="hps_0_h2f_lw_axi_master_agent" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 27 starting:altera_merlin_axi_master_ni "submodules/altera_merlin_axi_master_ni"</message>
   <message level="Info" culprit="hps_0_h2f_lw_axi_master_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_axi_master_ni</b> "<b>hps_0_h2f_lw_axi_master_agent</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_slave_agent:21.1:AVS_BURSTCOUNT_SYMBOLS=0,AVS_BURSTCOUNT_W=3,AV_LINEWRAPBURSTS=0,ECC_ENABLE=0,ID=1,MAX_BURSTWRAP=127,MAX_BYTE_CNT=4,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),PKT_ADDR_H=56,PKT_ADDR_L=36,PKT_BEGIN_BURST=84,PKT_BURSTWRAP_H=76,PKT_BURSTWRAP_L=70,PKT_BURST_SIZE_H=79,PKT_BURST_SIZE_L=77,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=69,PKT_BYTE_CNT_L=63,PKT_DATA_H=31,PKT_DATA_L=0,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_ORI_BURST_SIZE_H=111,PKT_ORI_BURST_SIZE_L=109,PKT_PROTECTION_H=102,PKT_PROTECTION_L=100,PKT_RESPONSE_STATUS_H=108,PKT_RESPONSE_STATUS_L=107,PKT_SRC_ID_H=86,PKT_SRC_ID_L=86,PKT_SYMBOL_W=8,PKT_TRANS_COMPRESSED_READ=57,PKT_TRANS_LOCK=61,PKT_TRANS_POSTED=58,PKT_TRANS_READ=60,PKT_TRANS_WRITE=59,PREVENT_FIFO_OVERFLOW=1,ST_CHANNEL_W=2,ST_DATA_W=112,SUPPRESS_0_BYTEEN_CMD=1,USE_READRESPONSE=0,USE_WRITERESPONSE=0"
   instancePathKey="soc_system:.:mm_interconnect_0:.:admm_solver_0_avalon_slave_0_agent"
   kind="altera_merlin_slave_agent"
   version="21.1"
   name="altera_merlin_slave_agent">
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_slave_agent.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="soc_system_mm_interconnect_0"
     as="admm_solver_0_avalon_slave_0_agent,RAM_s1_agent" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 26 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_agent"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>admm_solver_0_avalon_slave_0_agent</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_avalon_sc_fifo:21.1:BITS_PER_SYMBOL=113,CHANNEL_WIDTH=0,EMPTY_LATENCY=1,ENABLE_EXPLICIT_MAXCHANNEL=false,ERROR_WIDTH=0,EXPLICIT_MAXCHANNEL=0,FIFO_DEPTH=2,SYMBOLS_PER_BEAT=1,USE_ALMOST_EMPTY_IF=0,USE_ALMOST_FULL_IF=0,USE_FILL_LEVEL=0,USE_MEMORY_BLOCKS=0,USE_PACKETS=1,USE_STORE_FORWARD=0"
   instancePathKey="soc_system:.:mm_interconnect_0:.:admm_solver_0_avalon_slave_0_agent_rsp_fifo"
   kind="altera_avalon_sc_fifo"
   version="21.1"
   name="altera_avalon_sc_fifo">
  <parameter name="EXPLICIT_MAXCHANNEL" value="0" />
  <parameter name="ENABLE_EXPLICIT_MAXCHANNEL" value="false" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v"
       type="VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="soc_system_mm_interconnect_0"
     as="admm_solver_0_avalon_slave_0_agent_rsp_fifo,admm_solver_0_avalon_slave_0_agent_rdata_fifo,RAM_s1_agent_rsp_fifo,RAM_s1_agent_rdata_fifo" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 25 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_agent_rsp_fifo"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>admm_solver_0_avalon_slave_0_agent_rsp_fifo</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_router:21.1:CHANNEL_ID=01,10,DECODER_TYPE=0,DEFAULT_CHANNEL=1,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=-1,DEFAULT_WR_CHANNEL=-1,DESTINATION_ID=1,0,END_ADDRESS=0x40000,0x42000,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=56,PKT_ADDR_L=36,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_PROTECTION_H=102,PKT_PROTECTION_L=100,PKT_TRANS_READ=60,PKT_TRANS_WRITE=59,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=1:01:0x0:0x40000:write:1:0:0:1,0:10:0x40000:0x42000:both:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x40000,ST_CHANNEL_W=2,ST_DATA_W=112,TYPE_OF_TRANSACTION=write,both"
   instancePathKey="soc_system:.:mm_interconnect_0:.:router"
   kind="altera_merlin_router"
   version="21.1"
   name="soc_system_mm_interconnect_0_router">
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
  <parameter name="PKT_TRANS_READ" value="60" />
  <parameter name="START_ADDRESS" value="0x0,0x40000" />
  <parameter name="DEFAULT_CHANNEL" value="1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter
     name="SLAVES_INFO"
     value="1:01:0x0:0x40000:write:1:0:0:1,0:10:0x40000:0x42000:both:1:0:0:1" />
  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
  <parameter name="PKT_ADDR_H" value="56" />
  <parameter name="PKT_DEST_ID_H" value="87" />
  <parameter name="PKT_ADDR_L" value="36" />
  <parameter name="PKT_DEST_ID_L" value="87" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)" />
  <parameter name="CHANNEL_ID" value="01,10" />
  <parameter name="TYPE_OF_TRANSACTION" value="write,both" />
  <parameter name="SECURED_RANGE_PAIRS" value="0,0" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="ST_DATA_W" value="112" />
  <parameter name="SECURED_RANGE_LIST" value="0,0" />
  <parameter name="DECODER_TYPE" value="0" />
  <parameter name="PKT_PROTECTION_H" value="102" />
  <parameter name="END_ADDRESS" value="0x40000,0x42000" />
  <parameter name="PKT_PROTECTION_L" value="100" />
  <parameter name="PKT_TRANS_WRITE" value="59" />
  <parameter name="DEFAULT_DESTID" value="0" />
  <parameter name="DESTINATION_ID" value="1,0" />
  <parameter name="NON_SECURED_TAG" value="1,1" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="soc_system_mm_interconnect_0" as="router,router_001" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 20 starting:altera_merlin_router "submodules/soc_system_mm_interconnect_0_router"</message>
   <message level="Info" culprit="router"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_router:21.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=-1,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=1,DEFAULT_WR_CHANNEL=0,DESTINATION_ID=0,0,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=56,PKT_ADDR_L=36,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_PROTECTION_H=102,PKT_PROTECTION_L=100,PKT_TRANS_READ=60,PKT_TRANS_WRITE=59,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=2,ST_DATA_W=112,TYPE_OF_TRANSACTION=write,read"
   instancePathKey="soc_system:.:mm_interconnect_0:.:router_002"
   kind="altera_merlin_router"
   version="21.1"
   name="soc_system_mm_interconnect_0_router_002">
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="DEFAULT_WR_CHANNEL" value="0" />
  <parameter name="PKT_TRANS_READ" value="60" />
  <parameter name="START_ADDRESS" value="0x0,0x0" />
  <parameter name="DEFAULT_CHANNEL" value="-1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter
     name="SLAVES_INFO"
     value="0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1" />
  <parameter name="DEFAULT_RD_CHANNEL" value="1" />
  <parameter name="PKT_ADDR_H" value="56" />
  <parameter name="PKT_DEST_ID_H" value="87" />
  <parameter name="PKT_ADDR_L" value="36" />
  <parameter name="PKT_DEST_ID_L" value="87" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)" />
  <parameter name="CHANNEL_ID" value="01,10" />
  <parameter name="TYPE_OF_TRANSACTION" value="write,read" />
  <parameter name="SECURED_RANGE_PAIRS" value="0,0" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="ST_DATA_W" value="112" />
  <parameter name="SECURED_RANGE_LIST" value="0,0" />
  <parameter name="DECODER_TYPE" value="1" />
  <parameter name="PKT_PROTECTION_H" value="102" />
  <parameter name="END_ADDRESS" value="0x0,0x0" />
  <parameter name="PKT_PROTECTION_L" value="100" />
  <parameter name="PKT_TRANS_WRITE" value="59" />
  <parameter name="DEFAULT_DESTID" value="0" />
  <parameter name="DESTINATION_ID" value="0,0" />
  <parameter name="NON_SECURED_TAG" value="1,1" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_002.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="soc_system_mm_interconnect_0" as="router_002" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 18 starting:altera_merlin_router "submodules/soc_system_mm_interconnect_0_router_002"</message>
   <message level="Info" culprit="router_002"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_002</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_router:21.1:CHANNEL_ID=01,10,DECODER_TYPE=1,DEFAULT_CHANNEL=-1,DEFAULT_DESTID=0,DEFAULT_RD_CHANNEL=1,DEFAULT_WR_CHANNEL=0,DESTINATION_ID=0,0,END_ADDRESS=0x0,0x0,MEMORY_ALIASING_DECODE=0,MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0),NON_SECURED_TAG=1,1,PKT_ADDR_H=38,PKT_ADDR_L=18,PKT_DEST_ID_H=69,PKT_DEST_ID_L=69,PKT_PROTECTION_H=84,PKT_PROTECTION_L=82,PKT_TRANS_READ=42,PKT_TRANS_WRITE=41,SECURED_RANGE_LIST=0,0,SECURED_RANGE_PAIRS=0,0,SLAVES_INFO=0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1,SPAN_OFFSET=,START_ADDRESS=0x0,0x0,ST_CHANNEL_W=2,ST_DATA_W=94,TYPE_OF_TRANSACTION=write,read"
   instancePathKey="soc_system:.:mm_interconnect_0:.:router_003"
   kind="altera_merlin_router"
   version="21.1"
   name="soc_system_mm_interconnect_0_router_003">
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="DEFAULT_WR_CHANNEL" value="0" />
  <parameter name="PKT_TRANS_READ" value="42" />
  <parameter name="START_ADDRESS" value="0x0,0x0" />
  <parameter name="DEFAULT_CHANNEL" value="-1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter
     name="SLAVES_INFO"
     value="0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1" />
  <parameter name="DEFAULT_RD_CHANNEL" value="1" />
  <parameter name="PKT_ADDR_H" value="38" />
  <parameter name="PKT_DEST_ID_H" value="69" />
  <parameter name="PKT_ADDR_L" value="18" />
  <parameter name="PKT_DEST_ID_L" value="69" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)" />
  <parameter name="CHANNEL_ID" value="01,10" />
  <parameter name="TYPE_OF_TRANSACTION" value="write,read" />
  <parameter name="SECURED_RANGE_PAIRS" value="0,0" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="ST_DATA_W" value="94" />
  <parameter name="SECURED_RANGE_LIST" value="0,0" />
  <parameter name="DECODER_TYPE" value="1" />
  <parameter name="PKT_PROTECTION_H" value="84" />
  <parameter name="END_ADDRESS" value="0x0,0x0" />
  <parameter name="PKT_PROTECTION_L" value="82" />
  <parameter name="PKT_TRANS_WRITE" value="41" />
  <parameter name="DEFAULT_DESTID" value="0" />
  <parameter name="DESTINATION_ID" value="0,0" />
  <parameter name="NON_SECURED_TAG" value="1,1" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_router_003.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="soc_system_mm_interconnect_0" as="router_003" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 17 starting:altera_merlin_router "submodules/soc_system_mm_interconnect_0_router_003"</message>
   <message level="Info" culprit="router_003"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_router</b> "<b>router_003</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_traffic_limiter:21.1:ENFORCE_ORDER=1,MAX_BURST_LENGTH=16,MAX_OUTSTANDING_RESPONSES=3,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),PIPELINED=0,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=69,PKT_BYTE_CNT_L=63,PKT_DEST_ID_H=87,PKT_DEST_ID_L=87,PKT_SRC_ID_H=86,PKT_SRC_ID_L=86,PKT_THREAD_ID_H=99,PKT_THREAD_ID_L=88,PKT_TRANS_POSTED=58,PKT_TRANS_WRITE=59,PREVENT_HAZARDS=0,REORDER=0,ST_CHANNEL_W=2,ST_DATA_W=112,SUPPORTS_NONPOSTED_WRITES=0,SUPPORTS_POSTED_WRITES=1,VALID_WIDTH=2"
   instancePathKey="soc_system:.:mm_interconnect_0:.:hps_0_h2f_lw_axi_master_wr_limiter"
   kind="altera_merlin_traffic_limiter"
   version="21.1"
   name="altera_merlin_traffic_limiter">
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_traffic_limiter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_reorder_memory.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="soc_system_mm_interconnect_0"
     as="hps_0_h2f_lw_axi_master_wr_limiter,hps_0_h2f_lw_axi_master_rd_limiter" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 16 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"</message>
   <message level="Info" culprit="hps_0_h2f_lw_axi_master_wr_limiter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>hps_0_h2f_lw_axi_master_wr_limiter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_sc_fifo.v</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_burst_adapter:21.1:ADAPTER_VERSION=13.1,BURSTWRAP_CONST_MASK=0,BURSTWRAP_CONST_VALUE=0,BYTEENABLE_SYNTHESIS=1,COMPRESSED_READ_SUPPORT=1,INCOMPLETE_WRAP_SUPPORT=0,IN_NARROW_SIZE=1,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NO_WRAP_SUPPORT=0,OUT_BURSTWRAP_H=76,OUT_BYTE_CNT_H=65,OUT_COMPLETE_WRAP=0,OUT_FIXED=0,OUT_NARROW_SIZE=0,PIPE_INPUTS=0,PKT_ADDR_H=56,PKT_ADDR_L=36,PKT_BEGIN_BURST=84,PKT_BURSTWRAP_H=76,PKT_BURSTWRAP_L=70,PKT_BURST_SIZE_H=79,PKT_BURST_SIZE_L=77,PKT_BURST_TYPE_H=81,PKT_BURST_TYPE_L=80,PKT_BYTEEN_H=35,PKT_BYTEEN_L=32,PKT_BYTE_CNT_H=69,PKT_BYTE_CNT_L=63,PKT_TRANS_COMPRESSED_READ=57,PKT_TRANS_READ=60,PKT_TRANS_WRITE=59,ST_CHANNEL_W=2,ST_DATA_W=112"
   instancePathKey="soc_system:.:mm_interconnect_0:.:admm_solver_0_avalon_slave_0_burst_adapter"
   kind="altera_merlin_burst_adapter"
   version="21.1"
   name="altera_merlin_burst_adapter">
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)" />
  <parameter name="PKT_TRANS_COMPRESSED_READ" value="57" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_adapter_new.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_incr_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_wrap_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_default_burst_converter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_stage.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="soc_system_mm_interconnect_0"
     as="admm_solver_0_avalon_slave_0_burst_adapter,RAM_s1_burst_adapter" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 14 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"</message>
   <message level="Info" culprit="admm_solver_0_avalon_slave_0_burst_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_burst_adapter</b> "<b>admm_solver_0_avalon_slave_0_burst_adapter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_avalon_st_pipeline_base.v</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_demultiplexer:21.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone V,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=2,ST_DATA_W=112,VALID_WIDTH=2"
   instancePathKey="soc_system:.:mm_interconnect_0:.:cmd_demux"
   kind="altera_merlin_demultiplexer"
   version="21.1"
   name="soc_system_mm_interconnect_0_cmd_demux">
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
  <parameter name="VALID_WIDTH" value="2" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="ST_DATA_W" value="112" />
  <parameter name="NUM_OUTPUTS" value="2" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_demux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="soc_system_mm_interconnect_0"
     as="cmd_demux,cmd_demux_001" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 12 starting:altera_merlin_demultiplexer "submodules/soc_system_mm_interconnect_0_cmd_demux"</message>
   <message level="Info" culprit="cmd_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_demux</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_multiplexer:21.1:ARBITRATION_SCHEME=round-robin,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=1,PKT_TRANS_LOCK=61,ST_CHANNEL_W=2,ST_DATA_W=112,USE_EXTERNAL_ARB=0"
   instancePathKey="soc_system:.:mm_interconnect_0:.:cmd_mux"
   kind="altera_merlin_multiplexer"
   version="21.1"
   name="soc_system_mm_interconnect_0_cmd_mux">
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="ARBITRATION_SHARES" value="1,1" />
  <parameter name="NUM_INPUTS" value="2" />
  <parameter name="PIPELINE_ARB" value="1" />
  <parameter name="ARBITRATION_SCHEME" value="round-robin" />
  <parameter name="ST_DATA_W" value="112" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="PKT_TRANS_LOCK" value="61" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_cmd_mux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="soc_system_mm_interconnect_0" as="cmd_mux,cmd_mux_001" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 10 starting:altera_merlin_multiplexer "submodules/soc_system_mm_interconnect_0_cmd_mux"</message>
   <message level="Info" culprit="cmd_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_mux</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_demultiplexer:21.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone V,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_OUTPUTS=2,ST_CHANNEL_W=2,ST_DATA_W=112,VALID_WIDTH=1"
   instancePathKey="soc_system:.:mm_interconnect_0:.:rsp_demux"
   kind="altera_merlin_demultiplexer"
   version="21.1"
   name="soc_system_mm_interconnect_0_rsp_demux">
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
  <parameter name="VALID_WIDTH" value="1" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="ST_DATA_W" value="112" />
  <parameter name="NUM_OUTPUTS" value="2" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_demux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="soc_system_mm_interconnect_0"
     as="rsp_demux,rsp_demux_001" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 8 starting:altera_merlin_demultiplexer "submodules/soc_system_mm_interconnect_0_rsp_demux"</message>
   <message level="Info" culprit="rsp_demux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_demux</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_multiplexer:21.1:ARBITRATION_SCHEME=no-arb,ARBITRATION_SHARES=1,1,MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),NUM_INPUTS=2,PIPELINE_ARB=0,PKT_TRANS_LOCK=61,ST_CHANNEL_W=2,ST_DATA_W=112,USE_EXTERNAL_ARB=0"
   instancePathKey="soc_system:.:mm_interconnect_0:.:rsp_mux"
   kind="altera_merlin_multiplexer"
   version="21.1"
   name="soc_system_mm_interconnect_0_rsp_mux">
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="ARBITRATION_SHARES" value="1,1" />
  <parameter name="NUM_INPUTS" value="2" />
  <parameter name="PIPELINE_ARB" value="0" />
  <parameter name="ARBITRATION_SCHEME" value="no-arb" />
  <parameter name="ST_DATA_W" value="112" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="PKT_TRANS_LOCK" value="61" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_rsp_mux.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="soc_system_mm_interconnect_0" as="rsp_mux,rsp_mux_001" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 6 starting:altera_merlin_multiplexer "submodules/soc_system_mm_interconnect_0_rsp_mux"</message>
   <message level="Info" culprit="rsp_mux"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_mux</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_merlin_width_adapter:21.1:COMMAND_SIZE_W=3,CONSTANT_BURST_SIZE=0,ENABLE_ADDRESS_ALIGNMENT=1,IN_MERLIN_PACKET_FORMAT=ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0),IN_PKT_ADDR_H=38,IN_PKT_ADDR_L=18,IN_PKT_BURSTWRAP_H=58,IN_PKT_BURSTWRAP_L=52,IN_PKT_BURST_SIZE_H=61,IN_PKT_BURST_SIZE_L=59,IN_PKT_BURST_TYPE_H=63,IN_PKT_BURST_TYPE_L=62,IN_PKT_BYTEEN_H=17,IN_PKT_BYTEEN_L=16,IN_PKT_BYTE_CNT_H=51,IN_PKT_BYTE_CNT_L=45,IN_PKT_DATA_H=15,IN_PKT_DATA_L=0,IN_PKT_ORI_BURST_SIZE_H=93,IN_PKT_ORI_BURST_SIZE_L=91,IN_PKT_RESPONSE_STATUS_H=90,IN_PKT_RESPONSE_STATUS_L=89,IN_PKT_TRANS_COMPRESSED_READ=39,IN_PKT_TRANS_EXCLUSIVE=44,IN_PKT_TRANS_WRITE=41,IN_ST_DATA_W=94,OPTIMIZE_FOR_RSP=0,OUT_MERLIN_PACKET_FORMAT=ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0),OUT_PKT_ADDR_H=56,OUT_PKT_ADDR_L=36,OUT_PKT_BURST_SIZE_H=79,OUT_PKT_BURST_SIZE_L=77,OUT_PKT_BURST_TYPE_H=81,OUT_PKT_BURST_TYPE_L=80,OUT_PKT_BYTEEN_H=35,OUT_PKT_BYTEEN_L=32,OUT_PKT_BYTE_CNT_H=69,OUT_PKT_BYTE_CNT_L=63,OUT_PKT_DATA_H=31,OUT_PKT_DATA_L=0,OUT_PKT_ORI_BURST_SIZE_H=111,OUT_PKT_ORI_BURST_SIZE_L=109,OUT_PKT_RESPONSE_STATUS_H=108,OUT_PKT_RESPONSE_STATUS_L=107,OUT_PKT_TRANS_COMPRESSED_READ=57,OUT_PKT_TRANS_EXCLUSIVE=62,OUT_ST_DATA_W=112,PACKING=1,RESPONSE_PATH=1,ST_CHANNEL_W=2"
   instancePathKey="soc_system:.:mm_interconnect_0:.:RAM_s1_rsp_width_adapter"
   kind="altera_merlin_width_adapter"
   version="21.1"
   name="altera_merlin_width_adapter">
  <parameter name="OUT_PKT_ORI_BURST_SIZE_H" value="111" />
  <parameter name="OUT_PKT_ORI_BURST_SIZE_L" value="109" />
  <parameter name="IN_PKT_ORI_BURST_SIZE_H" value="93" />
  <parameter
     name="OUT_MERLIN_PACKET_FORMAT"
     value="ori_burst_size(111:109) response_status(108:107) cache(106:103) protection(102:100) thread_id(99:88) dest_id(87) src_id(86) qos(85) begin_burst(84) data_sideband(83) addr_sideband(82) burst_type(81:80) burst_size(79:77) burstwrap(76:70) byte_cnt(69:63) trans_exclusive(62) trans_lock(61) trans_read(60) trans_write(59) trans_posted(58) trans_compressed_read(57) addr(56:36) byteen(35:32) data(31:0)" />
  <parameter
     name="IN_MERLIN_PACKET_FORMAT"
     value="ori_burst_size(93:91) response_status(90:89) cache(88:85) protection(84:82) thread_id(81:70) dest_id(69) src_id(68) qos(67) begin_burst(66) data_sideband(65) addr_sideband(64) burst_type(63:62) burst_size(61:59) burstwrap(58:52) byte_cnt(51:45) trans_exclusive(44) trans_lock(43) trans_read(42) trans_write(41) trans_posted(40) trans_compressed_read(39) addr(38:18) byteen(17:16) data(15:0)" />
  <parameter name="IN_PKT_ORI_BURST_SIZE_L" value="91" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_width_adapter.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="soc_system_mm_interconnect_0"
     as="RAM_s1_rsp_width_adapter,RAM_s1_cmd_width_adapter" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 4 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"</message>
   <message level="Info" culprit="RAM_s1_rsp_width_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_width_adapter</b> "<b>RAM_s1_rsp_width_adapter</b>"]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_address_alignment.sv</b>]]></message>
   <message level="Info"><![CDATA[Reusing file <b>/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv</b>]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_avalon_st_adapter:21.1:AUTO_DEVICE=5CSEMA5F31C6,AUTO_DEVICE_FAMILY=Cyclone V,AUTO_DEVICE_SPEEDGRADE=,inBitsPerSymbol=34,inChannelWidth=0,inDataWidth=34,inEmptyWidth=1,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inUseEmptyPort=0,inUsePackets=0,inUseReady=1,inUseValid=1,outChannelWidth=0,outDataWidth=34,outEmptyWidth=1,outErrorDescriptor=,outErrorWidth=1,outMaxChannel=0,outReadyLatency=0,outUseEmptyPort=0,outUseReady=1,outUseValid=1(altera_clock_bridge:21.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:21.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(error_adapter:21.1:inBitsPerSymbol=34,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1)(clock:21.1:)(clock:21.1:)(reset:21.1:)"
   instancePathKey="soc_system:.:mm_interconnect_0:.:avalon_st_adapter"
   kind="altera_avalon_st_adapter"
   version="21.1"
   name="soc_system_mm_interconnect_0_avalon_st_adapter">
  <parameter name="inUseValid" value="1" />
  <parameter name="inBitsPerSymbol" value="34" />
  <parameter name="outUseEmptyPort" value="0" />
  <parameter name="inChannelWidth" value="0" />
  <parameter name="outErrorWidth" value="1" />
  <parameter name="outUseValid" value="1" />
  <parameter name="outMaxChannel" value="0" />
  <parameter name="inErrorDescriptor" value="" />
  <parameter name="inUsePackets" value="0" />
  <parameter name="inErrorWidth" value="0" />
  <parameter name="inEmptyWidth" value="1" />
  <parameter name="inUseReady" value="1" />
  <parameter name="outReadyLatency" value="0" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="outDataWidth" value="34" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
  <parameter name="inUseEmptyPort" value="0" />
  <parameter name="outChannelWidth" value="0" />
  <parameter name="inMaxChannel" value="0" />
  <parameter name="outUseReady" value="1" />
  <parameter name="inReadyLatency" value="0" />
  <parameter name="AUTO_DEVICE" value="5CSEMA5F31C6" />
  <parameter name="inDataWidth" value="34" />
  <parameter name="outErrorDescriptor" value="" />
  <parameter name="outEmptyWidth" value="1" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
  </childSourceFiles>
  <instantiator instantiator="soc_system_mm_interconnect_0" as="avalon_st_adapter" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 2 starting:altera_avalon_st_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="avalon_st_adapter"><![CDATA["<b>avalon_st_adapter</b>" reuses <b>error_adapter</b> "<b>submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0</b>"]]></message>
   <message level="Info" culprit="avalon_st_adapter"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 1 starting:error_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0"</message>
   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_avalon_st_adapter:21.1:AUTO_DEVICE=5CSEMA5F31C6,AUTO_DEVICE_FAMILY=Cyclone V,AUTO_DEVICE_SPEEDGRADE=,inBitsPerSymbol=18,inChannelWidth=0,inDataWidth=18,inEmptyWidth=1,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inUseEmptyPort=0,inUsePackets=0,inUseReady=1,inUseValid=1,outChannelWidth=0,outDataWidth=18,outEmptyWidth=1,outErrorDescriptor=,outErrorWidth=1,outMaxChannel=0,outReadyLatency=0,outUseEmptyPort=0,outUseReady=1,outUseValid=1(altera_clock_bridge:21.1:DERIVED_CLOCK_RATE=0,EXPLICIT_CLOCK_RATE=0,NUM_CLOCK_OUTPUTS=1)(altera_reset_bridge:21.1:ACTIVE_LOW_RESET=0,AUTO_CLK_CLOCK_RATE=0,NUM_RESET_OUTPUTS=1,SYNCHRONOUS_EDGES=deassert,USE_RESET_REQUEST=0)(error_adapter:21.1:inBitsPerSymbol=18,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1)(clock:21.1:)(clock:21.1:)(reset:21.1:)"
   instancePathKey="soc_system:.:mm_interconnect_0:.:avalon_st_adapter_001"
   kind="altera_avalon_st_adapter"
   version="21.1"
   name="soc_system_mm_interconnect_0_avalon_st_adapter_001">
  <parameter name="inUseValid" value="1" />
  <parameter name="inBitsPerSymbol" value="18" />
  <parameter name="outUseEmptyPort" value="0" />
  <parameter name="inChannelWidth" value="0" />
  <parameter name="outErrorWidth" value="1" />
  <parameter name="outUseValid" value="1" />
  <parameter name="outMaxChannel" value="0" />
  <parameter name="inErrorDescriptor" value="" />
  <parameter name="inUsePackets" value="0" />
  <parameter name="inErrorWidth" value="0" />
  <parameter name="inEmptyWidth" value="1" />
  <parameter name="inUseReady" value="1" />
  <parameter name="outReadyLatency" value="0" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="outDataWidth" value="18" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
  <parameter name="inUseEmptyPort" value="0" />
  <parameter name="outChannelWidth" value="0" />
  <parameter name="inMaxChannel" value="0" />
  <parameter name="outUseReady" value="1" />
  <parameter name="inReadyLatency" value="0" />
  <parameter name="AUTO_DEVICE" value="5CSEMA5F31C6" />
  <parameter name="inDataWidth" value="18" />
  <parameter name="outErrorDescriptor" value="" />
  <parameter name="outEmptyWidth" value="1" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
  </childSourceFiles>
  <instantiator
     instantiator="soc_system_mm_interconnect_0"
     as="avalon_st_adapter_001" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 2 starting:altera_avalon_st_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>3</b> modules, <b>3</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="avalon_st_adapter_001"><![CDATA["<b>avalon_st_adapter_001</b>" reuses <b>error_adapter</b> "<b>submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0</b>"]]></message>
   <message level="Info" culprit="avalon_st_adapter_001"><![CDATA["<b>mm_interconnect_0</b>" instantiated <b>altera_avalon_st_adapter</b> "<b>avalon_st_adapter_001</b>"]]></message>
   <message level="Debug" culprit="soc_system">queue size: 0 starting:error_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0"</message>
   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_001</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altera_interface_generator:21.1:ABSTRACT_REAL_COMPARE_TEST=false,ABS_RAM_MEM_INIT_FILENAME=meminit,ACV_PHY_CLK_ADD_FR_PHASE=0.0,ACV_PHY_CLK_ADD_FR_PHASE_CACHE=0.0,AC_PACKAGE_DESKEW=false,AC_PARITY=false,AC_ROM_MR0=,AC_ROM_MR0_CALIB=,AC_ROM_MR0_DLL_RESET=,AC_ROM_MR0_DLL_RESET_MIRR=,AC_ROM_MR0_MIRR=,AC_ROM_MR1=,AC_ROM_MR1_CALIB=,AC_ROM_MR1_MIRR=,AC_ROM_MR1_OCD_ENABLE=,AC_ROM_MR2=,AC_ROM_MR2_MIRR=,AC_ROM_MR3=,AC_ROM_MR3_MIRR=,AC_ROM_USER_ADD_0=0_0000_0000_0000,AC_ROM_USER_ADD_1=0_0000_0000_1000,ADDR_CMD_DDR=0,ADDR_ORDER=0,ADDR_RATE_RATIO=0,ADD_EFFICIENCY_MONITOR=false,ADD_EXTERNAL_SEQ_DEBUG_NIOS=false,ADVANCED_CK_PHASES=false,ADVERTIZE_SEQUENCER_SW_BUILD_FILES=false,AFI_ADDR_WIDTH=0,AFI_BANKADDR_WIDTH=0,AFI_CLK_EN_WIDTH=0,AFI_CLK_PAIR_COUNT=0,AFI_CONTROL_WIDTH=0,AFI_CS_WIDTH=0,AFI_DEBUG_INFO_WIDTH=32,AFI_DM_WIDTH=0,AFI_DQ_WIDTH=0,AFI_ODT_WIDTH=0,AFI_RATE_RATIO=0,AFI_RLAT_WIDTH=0,AFI_RRANK_WIDTH=0,AFI_WLAT_WIDTH=0,AFI_WRANK_WIDTH=0,AFI_WRITE_DQS_WIDTH=0,ALLOCATED_RFIFO_PORT=0,None,None,None,None,None,ALLOCATED_WFIFO_PORT=0,None,None,None,None,None,ALTMEMPHY_COMPATIBLE_MODE=false,AP_MODE=false,AP_MODE_EN=0,AUTO_PD_CYCLES=0,AUTO_POWERDN_EN=false,AVL_ADDR_WIDTH=0,AVL_ADDR_WIDTH_PORT_0=0,AVL_ADDR_WIDTH_PORT_1=0,AVL_ADDR_WIDTH_PORT_2=0,AVL_ADDR_WIDTH_PORT_3=0,AVL_ADDR_WIDTH_PORT_4=0,AVL_ADDR_WIDTH_PORT_5=0,AVL_BE_WIDTH=0,AVL_DATA_WIDTH=0,AVL_DATA_WIDTH_PORT=32,32,32,32,32,32,AVL_DATA_WIDTH_PORT_0=0,AVL_DATA_WIDTH_PORT_1=0,AVL_DATA_WIDTH_PORT_2=0,AVL_DATA_WIDTH_PORT_3=0,AVL_DATA_WIDTH_PORT_4=0,AVL_DATA_WIDTH_PORT_5=0,AVL_MAX_SIZE=4,AVL_NUM_SYMBOLS=2,AVL_NUM_SYMBOLS_PORT_0=2,AVL_NUM_SYMBOLS_PORT_1=2,AVL_NUM_SYMBOLS_PORT_2=2,AVL_NUM_SYMBOLS_PORT_3=2,AVL_NUM_SYMBOLS_PORT_4=2,AVL_NUM_SYMBOLS_PORT_5=2,AVL_PORT=,AVL_SIZE_WIDTH=0,AVL_SYMBOL_WIDTH=8,AV_PORT_0_CONNECT_TO_CV_PORT=0,AV_PORT_1_CONNECT_TO_CV_PORT=1,AV_PORT_2_CONNECT_TO_CV_PORT=2,AV_PORT_3_CONNECT_TO_CV_PORT=3,AV_PORT_4_CONNECT_TO_CV_PORT=4,AV_PORT_5_CONNECT_TO_CV_PORT=5,BYTE_ENABLE=true,C2P_WRITE_CLOCK_ADD_PHASE=0.0,C2P_WRITE_CLOCK_ADD_PHASE_CACHE=0.0,CALIBRATION_MODE=Skip,CALIB_LFIFO_OFFSET=-1,CALIB_REG_WIDTH=8,CALIB_VFIFO_OFFSET=-1,CFG_ADDR_ORDER=0,CFG_BURST_LENGTH=0,CFG_CLR_INTR=0,CFG_DATA_REORDERING_TYPE=INTER_BANK,CFG_ECC_DECODER_REG=0,CFG_ENABLE_NO_DM=0,CFG_ERRCMD_FIFO_REG=0,CFG_INTERFACE_WIDTH=0,CFG_MEM_CLK_ENTRY_CYCLES=0,CFG_PDN_EXIT_CYCLES=0,CFG_PORT_WIDTH_READ_ODT_CHIP=0,CFG_PORT_WIDTH_WRITE_ODT_CHIP=0,CFG_POWER_SAVING_EXIT_CYCLES=0,CFG_READ_ODT_CHIP=0,CFG_REORDER_DATA=true,CFG_SELF_RFSH_EXIT_CYCLES=0,CFG_STARVE_LIMIT=0,CFG_TCCD=0,CFG_TCCD_NS=2.5,CFG_TYPE=0,CFG_WRITE_ODT_CHIP=0,COMMAND_PHASE=0.0,COMMAND_PHASE_CACHE=0.0,CONTINUE_AFTER_CAL_FAIL=false,CONTROLLER_LATENCY=5,CONTROLLER_TYPE=nextgen_v110,CORE_DEBUG_CONNECTION=EXPORT,CORE_PERIPHERY_DUAL_CLOCK=false,CPORT_TYPE_PORT=Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,CPORT_TYPE_PORT_0=0,CPORT_TYPE_PORT_1=0,CPORT_TYPE_PORT_2=0,CPORT_TYPE_PORT_3=0,CPORT_TYPE_PORT_4=0,CPORT_TYPE_PORT_5=0,CSR_ADDR_WIDTH=8,CSR_BE_WIDTH=4,CSR_DATA_WIDTH=32,CTL_AUTOPCH_EN=false,CTL_CMD_QUEUE_DEPTH=8,CTL_CSR_CONNECTION=INTERNAL_JTAG,CTL_CSR_ENABLED=false,CTL_CSR_READ_ONLY=1,CTL_CS_WIDTH=0,CTL_DEEP_POWERDN_EN=false,CTL_DYNAMIC_BANK_ALLOCATION=false,CTL_DYNAMIC_BANK_NUM=4,CTL_ECC_AUTO_CORRECTION_ENABLED=false,CTL_ECC_CSR_ENABLED=false,CTL_ECC_ENABLED=false,CTL_ECC_MULTIPLES_16_24_40_72=0,CTL_ECC_MULTIPLES_40_72=0,CTL_ENABLE_BURST_INTERRUPT=false,CTL_ENABLE_BURST_INTERRUPT_INT=false,CTL_ENABLE_BURST_TERMINATE=false,CTL_ENABLE_BURST_TERMINATE_INT=false,CTL_ENABLE_WDATA_PATH_LATENCY=false,CTL_HRB_ENABLED=false,CTL_LOOK_AHEAD_DEPTH=4,CTL_ODT_ENABLED=false,CTL_OUTPUT_REGD=false,CTL_RD_TO_PCH_EXTRA_CLK=0,CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK=0,CTL_RD_TO_RD_EXTRA_CLK=0,CTL_REGDIMM_ENABLED=false,CTL_SELF_REFRESH=0,CTL_SELF_REFRESH_EN=false,CTL_TBP_NUM=4,CTL_USR_REFRESH=0,CTL_USR_REFRESH_EN=false,CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK=0,CTL_WR_TO_WR_EXTRA_CLK=0,CTL_ZQCAL_EN=false,CUT_NEW_FAMILY_TIMING=true,CV_AVL_ADDR_WIDTH_PORT_0=0,CV_AVL_ADDR_WIDTH_PORT_1=0,CV_AVL_ADDR_WIDTH_PORT_2=0,CV_AVL_ADDR_WIDTH_PORT_3=0,CV_AVL_ADDR_WIDTH_PORT_4=0,CV_AVL_ADDR_WIDTH_PORT_5=0,CV_AVL_DATA_WIDTH_PORT_0=0,CV_AVL_DATA_WIDTH_PORT_1=0,CV_AVL_DATA_WIDTH_PORT_2=0,CV_AVL_DATA_WIDTH_PORT_3=0,CV_AVL_DATA_WIDTH_PORT_4=0,CV_AVL_DATA_WIDTH_PORT_5=0,CV_AVL_NUM_SYMBOLS_PORT_0=2,CV_AVL_NUM_SYMBOLS_PORT_1=2,CV_AVL_NUM_SYMBOLS_PORT_2=2,CV_AVL_NUM_SYMBOLS_PORT_3=2,CV_AVL_NUM_SYMBOLS_PORT_4=2,CV_AVL_NUM_SYMBOLS_PORT_5=2,CV_CPORT_TYPE_PORT_0=0,CV_CPORT_TYPE_PORT_1=0,CV_CPORT_TYPE_PORT_2=0,CV_CPORT_TYPE_PORT_3=0,CV_CPORT_TYPE_PORT_4=0,CV_CPORT_TYPE_PORT_5=0,CV_ENUM_AUTO_PCH_ENABLE_0=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_1=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_2=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_3=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_4=DISABLED,CV_ENUM_AUTO_PCH_ENABLE_5=DISABLED,CV_ENUM_CMD_PORT_IN_USE_0=FALSE,CV_ENUM_CMD_PORT_IN_USE_1=FALSE,CV_ENUM_CMD_PORT_IN_USE_2=FALSE,CV_ENUM_CMD_PORT_IN_USE_3=FALSE,CV_ENUM_CMD_PORT_IN_USE_4=FALSE,CV_ENUM_CMD_PORT_IN_USE_5=FALSE,CV_ENUM_CPORT0_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT0_TYPE=DISABLE,CV_ENUM_CPORT0_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT1_TYPE=DISABLE,CV_ENUM_CPORT1_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT2_TYPE=DISABLE,CV_ENUM_CPORT2_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT3_TYPE=DISABLE,CV_ENUM_CPORT3_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT4_TYPE=DISABLE,CV_ENUM_CPORT4_WFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_RFIFO_MAP=FIFO_0,CV_ENUM_CPORT5_TYPE=DISABLE,CV_ENUM_CPORT5_WFIFO_MAP=FIFO_0,CV_ENUM_ENABLE_BONDING_0=DISABLED,CV_ENUM_ENABLE_BONDING_1=DISABLED,CV_ENUM_ENABLE_BONDING_2=DISABLED,CV_ENUM_ENABLE_BONDING_3=DISABLED,CV_ENUM_ENABLE_BONDING_4=DISABLED,CV_ENUM_ENABLE_BONDING_5=DISABLED,CV_ENUM_PORT0_WIDTH=PORT_64_BIT,CV_ENUM_PORT1_WIDTH=PORT_64_BIT,CV_ENUM_PORT2_WIDTH=PORT_64_BIT,CV_ENUM_PORT3_WIDTH=PORT_64_BIT,CV_ENUM_PORT4_WIDTH=PORT_64_BIT,CV_ENUM_PORT5_WIDTH=PORT_64_BIT,CV_ENUM_PRIORITY_0_0=WEIGHT_0,CV_ENUM_PRIORITY_0_1=WEIGHT_0,CV_ENUM_PRIORITY_0_2=WEIGHT_0,CV_ENUM_PRIORITY_0_3=WEIGHT_0,CV_ENUM_PRIORITY_0_4=WEIGHT_0,CV_ENUM_PRIORITY_0_5=WEIGHT_0,CV_ENUM_PRIORITY_1_0=WEIGHT_0,CV_ENUM_PRIORITY_1_1=WEIGHT_0,CV_ENUM_PRIORITY_1_2=WEIGHT_0,CV_ENUM_PRIORITY_1_3=WEIGHT_0,CV_ENUM_PRIORITY_1_4=WEIGHT_0,CV_ENUM_PRIORITY_1_5=WEIGHT_0,CV_ENUM_PRIORITY_2_0=WEIGHT_0,CV_ENUM_PRIORITY_2_1=WEIGHT_0,CV_ENUM_PRIORITY_2_2=WEIGHT_0,CV_ENUM_PRIORITY_2_3=WEIGHT_0,CV_ENUM_PRIORITY_2_4=WEIGHT_0,CV_ENUM_PRIORITY_2_5=WEIGHT_0,CV_ENUM_PRIORITY_3_0=WEIGHT_0,CV_ENUM_PRIORITY_3_1=WEIGHT_0,CV_ENUM_PRIORITY_3_2=WEIGHT_0,CV_ENUM_PRIORITY_3_3=WEIGHT_0,CV_ENUM_PRIORITY_3_4=WEIGHT_0,CV_ENUM_PRIORITY_3_5=WEIGHT_0,CV_ENUM_PRIORITY_4_0=WEIGHT_0,CV_ENUM_PRIORITY_4_1=WEIGHT_0,CV_ENUM_PRIORITY_4_2=WEIGHT_0,CV_ENUM_PRIORITY_4_3=WEIGHT_0,CV_ENUM_PRIORITY_4_4=WEIGHT_0,CV_ENUM_PRIORITY_4_5=WEIGHT_0,CV_ENUM_PRIORITY_5_0=WEIGHT_0,CV_ENUM_PRIORITY_5_1=WEIGHT_0,CV_ENUM_PRIORITY_5_2=WEIGHT_0,CV_ENUM_PRIORITY_5_3=WEIGHT_0,CV_ENUM_PRIORITY_5_4=WEIGHT_0,CV_ENUM_PRIORITY_5_5=WEIGHT_0,CV_ENUM_PRIORITY_6_0=WEIGHT_0,CV_ENUM_PRIORITY_6_1=WEIGHT_0,CV_ENUM_PRIORITY_6_2=WEIGHT_0,CV_ENUM_PRIORITY_6_3=WEIGHT_0,CV_ENUM_PRIORITY_6_4=WEIGHT_0,CV_ENUM_PRIORITY_6_5=WEIGHT_0,CV_ENUM_PRIORITY_7_0=WEIGHT_0,CV_ENUM_PRIORITY_7_1=WEIGHT_0,CV_ENUM_PRIORITY_7_2=WEIGHT_0,CV_ENUM_PRIORITY_7_3=WEIGHT_0,CV_ENUM_PRIORITY_7_4=WEIGHT_0,CV_ENUM_PRIORITY_7_5=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_RD_DWIDTH_0=DWIDTH_0,CV_ENUM_RD_DWIDTH_1=DWIDTH_0,CV_ENUM_RD_DWIDTH_2=DWIDTH_0,CV_ENUM_RD_DWIDTH_3=DWIDTH_0,CV_ENUM_RD_DWIDTH_4=DWIDTH_0,CV_ENUM_RD_DWIDTH_5=DWIDTH_0,CV_ENUM_RD_PORT_INFO_0=USE_NO,CV_ENUM_RD_PORT_INFO_1=USE_NO,CV_ENUM_RD_PORT_INFO_2=USE_NO,CV_ENUM_RD_PORT_INFO_3=USE_NO,CV_ENUM_RD_PORT_INFO_4=USE_NO,CV_ENUM_RD_PORT_INFO_5=USE_NO,CV_ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_STATIC_WEIGHT_0=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_1=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_2=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_3=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_4=WEIGHT_0,CV_ENUM_STATIC_WEIGHT_5=WEIGHT_0,CV_ENUM_USER_PRIORITY_0=PRIORITY_0,CV_ENUM_USER_PRIORITY_1=PRIORITY_0,CV_ENUM_USER_PRIORITY_2=PRIORITY_0,CV_ENUM_USER_PRIORITY_3=PRIORITY_0,CV_ENUM_USER_PRIORITY_4=PRIORITY_0,CV_ENUM_USER_PRIORITY_5=PRIORITY_0,CV_ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,CV_ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,CV_ENUM_WR_DWIDTH_0=DWIDTH_0,CV_ENUM_WR_DWIDTH_1=DWIDTH_0,CV_ENUM_WR_DWIDTH_2=DWIDTH_0,CV_ENUM_WR_DWIDTH_3=DWIDTH_0,CV_ENUM_WR_DWIDTH_4=DWIDTH_0,CV_ENUM_WR_DWIDTH_5=DWIDTH_0,CV_ENUM_WR_PORT_INFO_0=USE_NO,CV_ENUM_WR_PORT_INFO_1=USE_NO,CV_ENUM_WR_PORT_INFO_2=USE_NO,CV_ENUM_WR_PORT_INFO_3=USE_NO,CV_ENUM_WR_PORT_INFO_4=USE_NO,CV_ENUM_WR_PORT_INFO_5=USE_NO,CV_INTG_RCFG_SUM_WT_PRIORITY_0=0,CV_INTG_RCFG_SUM_WT_PRIORITY_1=0,CV_INTG_RCFG_SUM_WT_PRIORITY_2=0,CV_INTG_RCFG_SUM_WT_PRIORITY_3=0,CV_INTG_RCFG_SUM_WT_PRIORITY_4=0,CV_INTG_RCFG_SUM_WT_PRIORITY_5=0,CV_INTG_RCFG_SUM_WT_PRIORITY_6=0,CV_INTG_RCFG_SUM_WT_PRIORITY_7=0,CV_INTG_SUM_WT_PRIORITY_0=0,CV_INTG_SUM_WT_PRIORITY_1=0,CV_INTG_SUM_WT_PRIORITY_2=0,CV_INTG_SUM_WT_PRIORITY_3=0,CV_INTG_SUM_WT_PRIORITY_4=0,CV_INTG_SUM_WT_PRIORITY_5=0,CV_INTG_SUM_WT_PRIORITY_6=0,CV_INTG_SUM_WT_PRIORITY_7=0,CV_LSB_RFIFO_PORT_0=5,CV_LSB_RFIFO_PORT_1=5,CV_LSB_RFIFO_PORT_2=5,CV_LSB_RFIFO_PORT_3=5,CV_LSB_RFIFO_PORT_4=5,CV_LSB_RFIFO_PORT_5=5,CV_LSB_WFIFO_PORT_0=5,CV_LSB_WFIFO_PORT_1=5,CV_LSB_WFIFO_PORT_2=5,CV_LSB_WFIFO_PORT_3=5,CV_LSB_WFIFO_PORT_4=5,CV_LSB_WFIFO_PORT_5=5,CV_MSB_RFIFO_PORT_0=5,CV_MSB_RFIFO_PORT_1=5,CV_MSB_RFIFO_PORT_2=5,CV_MSB_RFIFO_PORT_3=5,CV_MSB_RFIFO_PORT_4=5,CV_MSB_RFIFO_PORT_5=5,CV_MSB_WFIFO_PORT_0=5,CV_MSB_WFIFO_PORT_1=5,CV_MSB_WFIFO_PORT_2=5,CV_MSB_WFIFO_PORT_3=5,CV_MSB_WFIFO_PORT_4=5,CV_MSB_WFIFO_PORT_5=5,CV_PORT_0_CONNECT_TO_AV_PORT=0,CV_PORT_1_CONNECT_TO_AV_PORT=1,CV_PORT_2_CONNECT_TO_AV_PORT=2,CV_PORT_3_CONNECT_TO_AV_PORT=3,CV_PORT_4_CONNECT_TO_AV_PORT=4,CV_PORT_5_CONNECT_TO_AV_PORT=5,DATA_RATE_RATIO=0,DAT_DATA_WIDTH=32,DEBUG_MODE=false,DELAYED_CLOCK_PHASE_SETTING=2,DELAY_BUFFER_MODE=HIGH,DELAY_CHAIN_LENGTH=8,DELAY_PER_DCHAIN_TAP=-1,DELAY_PER_DQS_EN_DCHAIN_TAP=-1,DELAY_PER_OPA_TAP=-1,DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG=false,DEVICE_DEPTH=1,DEVICE_FAMILY=,DEVICE_FAMILY_PARAM=,DEVICE_WIDTH=1,DISABLE_CHILD_MESSAGING=false,DISCRETE_FLY_BY=true,DLL_DELAY_CTRL_WIDTH=6,DLL_MASTER=false,DLL_OFFSET_CTRL_WIDTH=6,DLL_SHARING_MODE=None,DLL_USE_DR_CLK=false,DQS_DELAY_CHAIN_PHASE_SETTING=2,DQS_DQSN_MODE=DIFFERENTIAL,DQS_EN_DELAY_MAX=-1,DQS_IN_DELAY_MAX=-1,DQS_PHASE_SHIFT=9000,DQ_DDR=0,DQ_INPUT_REG_USE_CLKN=false,DUAL_WRITE_CLOCK=false,DUPLICATE_AC=false,DUPLICATE_PLL_FOR_PHY_CLK=false,DWIDTH_RATIO=4,EARLY_ADDR_CMD_CLK_TRANSFER=false,ED_EXPORT_SEQ_DEBUG=false,ENABLE_ABSTRACT_RAM=false,ENABLE_ABS_RAM_INTERNAL=false,ENABLE_ABS_RAM_MEM_INIT=false,ENABLE_BONDING=false,ENABLE_BURST_MERGE=false,ENABLE_CSR_SOFT_RESET_REQ=false,ENABLE_CTRL_AVALON_INTERFACE=true,ENABLE_DELAY_CHAIN_WRITE=false,ENABLE_EMIT_BFM_MASTER=false,ENABLE_EMIT_JTAG_MASTER=false,ENABLE_EXPORT_SEQ_DEBUG_BRIDGE=false,ENABLE_EXTRA_REPORTING=false,ENABLE_ISS_PROBES=false,ENABLE_LARGE_RW_MGR_DI_BUFFER=false,ENABLE_LDC_MEM_CK_ADJUSTMENT=false,ENABLE_MAX_SIZE_SEQ_MEM=false,ENABLE_NIOS_JTAG_UART=false,ENABLE_NIOS_OCI=false,ENABLE_NIOS_PRINTF_OUTPUT=false,ENABLE_NON_DESTRUCTIVE_CALIB=false,ENABLE_NON_DES_CAL=false,ENABLE_NON_DES_CAL_TEST=false,ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT=false,ENABLE_USER_ECC=false,ENUM_ATTR_COUNTER_ONE_RESET=DISABLED,ENUM_ATTR_COUNTER_ZERO_RESET=DISABLED,ENUM_ATTR_STATIC_CONFIG_VALID=DISABLED,ENUM_AUTO_PCH_ENABLE_0=DISABLED,ENUM_AUTO_PCH_ENABLE_1=DISABLED,ENUM_AUTO_PCH_ENABLE_2=DISABLED,ENUM_AUTO_PCH_ENABLE_3=DISABLED,ENUM_AUTO_PCH_ENABLE_4=DISABLED,ENUM_AUTO_PCH_ENABLE_5=DISABLED,ENUM_CAL_REQ=DISABLED,ENUM_CFG_BURST_LENGTH=BL_8,ENUM_CFG_INTERFACE_WIDTH=DWIDTH_32,ENUM_CFG_SELF_RFSH_EXIT_CYCLES=,ENUM_CFG_STARVE_LIMIT=STARVE_LIMIT_32,ENUM_CFG_TYPE=DDR3,ENUM_CLOCK_OFF_0=DISABLED,ENUM_CLOCK_OFF_1=DISABLED,ENUM_CLOCK_OFF_2=DISABLED,ENUM_CLOCK_OFF_3=DISABLED,ENUM_CLOCK_OFF_4=DISABLED,ENUM_CLOCK_OFF_5=DISABLED,ENUM_CLR_INTR=NO_CLR_INTR,ENUM_CMD_PORT_IN_USE_0=FALSE,ENUM_CMD_PORT_IN_USE_1=FALSE,ENUM_CMD_PORT_IN_USE_2=FALSE,ENUM_CMD_PORT_IN_USE_3=FALSE,ENUM_CMD_PORT_IN_USE_4=FALSE,ENUM_CMD_PORT_IN_USE_5=FALSE,ENUM_CPORT0_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT0_RFIFO_MAP=FIFO_0,ENUM_CPORT0_TYPE=DISABLE,ENUM_CPORT0_WFIFO_MAP=FIFO_0,ENUM_CPORT1_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT1_RFIFO_MAP=FIFO_0,ENUM_CPORT1_TYPE=DISABLE,ENUM_CPORT1_WFIFO_MAP=FIFO_0,ENUM_CPORT2_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT2_RFIFO_MAP=FIFO_0,ENUM_CPORT2_TYPE=DISABLE,ENUM_CPORT2_WFIFO_MAP=FIFO_0,ENUM_CPORT3_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT3_RFIFO_MAP=FIFO_0,ENUM_CPORT3_TYPE=DISABLE,ENUM_CPORT3_WFIFO_MAP=FIFO_0,ENUM_CPORT4_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT4_RFIFO_MAP=FIFO_0,ENUM_CPORT4_TYPE=DISABLE,ENUM_CPORT4_WFIFO_MAP=FIFO_0,ENUM_CPORT5_RDY_ALMOST_FULL=NOT_FULL,ENUM_CPORT5_RFIFO_MAP=FIFO_0,ENUM_CPORT5_TYPE=DISABLE,ENUM_CPORT5_WFIFO_MAP=FIFO_0,ENUM_CTL_ADDR_ORDER=CHIP_BANK_ROW_COL,ENUM_CTL_ECC_ENABLED=CTL_ECC_DISABLED,ENUM_CTL_ECC_RMW_ENABLED=CTL_ECC_RMW_DISABLED,ENUM_CTL_REGDIMM_ENABLED=REGDIMM_DISABLED,ENUM_CTL_USR_REFRESH=CTL_USR_REFRESH_DISABLED,ENUM_CTRL_WIDTH=DATA_WIDTH_64_BIT,ENUM_DELAY_BONDING=BONDING_LATENCY_0,ENUM_DFX_BYPASS_ENABLE=DFX_BYPASS_DISABLED,ENUM_DISABLE_MERGING=MERGING_ENABLED,ENUM_ECC_DQ_WIDTH=ECC_DQ_WIDTH_0,ENUM_ENABLE_ATPG=DISABLED,ENUM_ENABLE_BONDING_0=DISABLED,ENUM_ENABLE_BONDING_1=DISABLED,ENUM_ENABLE_BONDING_2=DISABLED,ENUM_ENABLE_BONDING_3=DISABLED,ENUM_ENABLE_BONDING_4=DISABLED,ENUM_ENABLE_BONDING_5=DISABLED,ENUM_ENABLE_BONDING_WRAPBACK=DISABLED,ENUM_ENABLE_BURST_INTERRUPT=DISABLED,ENUM_ENABLE_BURST_TERMINATE=DISABLED,ENUM_ENABLE_DQS_TRACKING=DISABLED,ENUM_ENABLE_ECC_CODE_OVERWRITES=DISABLED,ENUM_ENABLE_FAST_EXIT_PPD=DISABLED,ENUM_ENABLE_INTR=DISABLED,ENUM_ENABLE_NO_DM=DISABLED,ENUM_ENABLE_PIPELINEGLOBAL=DISABLED,ENUM_GANGED_ARF=DISABLED,ENUM_GEN_DBE=GEN_DBE_DISABLED,ENUM_GEN_SBE=GEN_SBE_DISABLED,ENUM_INC_SYNC=FIFO_SET_2,ENUM_LOCAL_IF_CS_WIDTH=ADDR_WIDTH_2,ENUM_MASK_CORR_DROPPED_INTR=DISABLED,ENUM_MASK_DBE_INTR=DISABLED,ENUM_MASK_SBE_INTR=DISABLED,ENUM_MEM_IF_AL=AL_0,ENUM_MEM_IF_BANKADDR_WIDTH=ADDR_WIDTH_3,ENUM_MEM_IF_BURSTLENGTH=MEM_IF_BURSTLENGTH_8,ENUM_MEM_IF_COLADDR_WIDTH=ADDR_WIDTH_12,ENUM_MEM_IF_CS_PER_RANK=MEM_IF_CS_PER_RANK_1,ENUM_MEM_IF_CS_WIDTH=MEM_IF_CS_WIDTH_1,ENUM_MEM_IF_DQS_WIDTH=DQS_WIDTH_4,ENUM_MEM_IF_DQ_PER_CHIP=MEM_IF_DQ_PER_CHIP_8,ENUM_MEM_IF_DWIDTH=MEM_IF_DWIDTH_32,ENUM_MEM_IF_MEMTYPE=DDR3_SDRAM,ENUM_MEM_IF_ROWADDR_WIDTH=ADDR_WIDTH_16,ENUM_MEM_IF_SPEEDBIN=DDR3_1066_6_6_6,ENUM_MEM_IF_TCCD=TCCD_4,ENUM_MEM_IF_TCL=TCL_6,ENUM_MEM_IF_TCWL=TCWL_5,ENUM_MEM_IF_TFAW=TFAW_16,ENUM_MEM_IF_TMRD=,ENUM_MEM_IF_TRAS=TRAS_16,ENUM_MEM_IF_TRC=TRC_22,ENUM_MEM_IF_TRCD=TRCD_6,ENUM_MEM_IF_TRP=TRP_6,ENUM_MEM_IF_TRRD=TRRD_4,ENUM_MEM_IF_TRTP=TRTP_4,ENUM_MEM_IF_TWR=TWR_6,ENUM_MEM_IF_TWTR=TWTR_4,ENUM_MMR_CFG_MEM_BL=MP_BL_8,ENUM_OUTPUT_REGD=DISABLED,ENUM_PDN_EXIT_CYCLES=SLOW_EXIT,ENUM_PORT0_WIDTH=PORT_64_BIT,ENUM_PORT1_WIDTH=PORT_64_BIT,ENUM_PORT2_WIDTH=PORT_64_BIT,ENUM_PORT3_WIDTH=PORT_64_BIT,ENUM_PORT4_WIDTH=PORT_64_BIT,ENUM_PORT5_WIDTH=PORT_64_BIT,ENUM_PRIORITY_0_0=WEIGHT_0,ENUM_PRIORITY_0_1=WEIGHT_0,ENUM_PRIORITY_0_2=WEIGHT_0,ENUM_PRIORITY_0_3=WEIGHT_0,ENUM_PRIORITY_0_4=WEIGHT_0,ENUM_PRIORITY_0_5=WEIGHT_0,ENUM_PRIORITY_1_0=WEIGHT_0,ENUM_PRIORITY_1_1=WEIGHT_0,ENUM_PRIORITY_1_2=WEIGHT_0,ENUM_PRIORITY_1_3=WEIGHT_0,ENUM_PRIORITY_1_4=WEIGHT_0,ENUM_PRIORITY_1_5=WEIGHT_0,ENUM_PRIORITY_2_0=WEIGHT_0,ENUM_PRIORITY_2_1=WEIGHT_0,ENUM_PRIORITY_2_2=WEIGHT_0,ENUM_PRIORITY_2_3=WEIGHT_0,ENUM_PRIORITY_2_4=WEIGHT_0,ENUM_PRIORITY_2_5=WEIGHT_0,ENUM_PRIORITY_3_0=WEIGHT_0,ENUM_PRIORITY_3_1=WEIGHT_0,ENUM_PRIORITY_3_2=WEIGHT_0,ENUM_PRIORITY_3_3=WEIGHT_0,ENUM_PRIORITY_3_4=WEIGHT_0,ENUM_PRIORITY_3_5=WEIGHT_0,ENUM_PRIORITY_4_0=WEIGHT_0,ENUM_PRIORITY_4_1=WEIGHT_0,ENUM_PRIORITY_4_2=WEIGHT_0,ENUM_PRIORITY_4_3=WEIGHT_0,ENUM_PRIORITY_4_4=WEIGHT_0,ENUM_PRIORITY_4_5=WEIGHT_0,ENUM_PRIORITY_5_0=WEIGHT_0,ENUM_PRIORITY_5_1=WEIGHT_0,ENUM_PRIORITY_5_2=WEIGHT_0,ENUM_PRIORITY_5_3=WEIGHT_0,ENUM_PRIORITY_5_4=WEIGHT_0,ENUM_PRIORITY_5_5=WEIGHT_0,ENUM_PRIORITY_6_0=WEIGHT_0,ENUM_PRIORITY_6_1=WEIGHT_0,ENUM_PRIORITY_6_2=WEIGHT_0,ENUM_PRIORITY_6_3=WEIGHT_0,ENUM_PRIORITY_6_4=WEIGHT_0,ENUM_PRIORITY_6_5=WEIGHT_0,ENUM_PRIORITY_7_0=WEIGHT_0,ENUM_PRIORITY_7_1=WEIGHT_0,ENUM_PRIORITY_7_2=WEIGHT_0,ENUM_PRIORITY_7_3=WEIGHT_0,ENUM_PRIORITY_7_4=WEIGHT_0,ENUM_PRIORITY_7_5=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_0=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_1=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_2=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_3=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_4=WEIGHT_0,ENUM_RCFG_STATIC_WEIGHT_5=WEIGHT_0,ENUM_RCFG_USER_PRIORITY_0=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_1=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_2=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_3=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_4=PRIORITY_0,ENUM_RCFG_USER_PRIORITY_5=PRIORITY_0,ENUM_RD_DWIDTH_0=DWIDTH_0,ENUM_RD_DWIDTH_1=DWIDTH_0,ENUM_RD_DWIDTH_2=DWIDTH_0,ENUM_RD_DWIDTH_3=DWIDTH_0,ENUM_RD_DWIDTH_4=DWIDTH_0,ENUM_RD_DWIDTH_5=DWIDTH_0,ENUM_RD_FIFO_IN_USE_0=FALSE,ENUM_RD_FIFO_IN_USE_1=FALSE,ENUM_RD_FIFO_IN_USE_2=FALSE,ENUM_RD_FIFO_IN_USE_3=FALSE,ENUM_RD_PORT_INFO_0=USE_NO,ENUM_RD_PORT_INFO_1=USE_NO,ENUM_RD_PORT_INFO_2=USE_NO,ENUM_RD_PORT_INFO_3=USE_NO,ENUM_RD_PORT_INFO_4=USE_NO,ENUM_RD_PORT_INFO_5=USE_NO,ENUM_READ_ODT_CHIP=ODT_DISABLED,ENUM_REORDER_DATA=DATA_REORDERING,ENUM_RFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_RFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_SINGLE_READY_0=CONCATENATE_RDY,ENUM_SINGLE_READY_1=CONCATENATE_RDY,ENUM_SINGLE_READY_2=CONCATENATE_RDY,ENUM_SINGLE_READY_3=CONCATENATE_RDY,ENUM_STATIC_WEIGHT_0=WEIGHT_0,ENUM_STATIC_WEIGHT_1=WEIGHT_0,ENUM_STATIC_WEIGHT_2=WEIGHT_0,ENUM_STATIC_WEIGHT_3=WEIGHT_0,ENUM_STATIC_WEIGHT_4=WEIGHT_0,ENUM_STATIC_WEIGHT_5=WEIGHT_0,ENUM_SYNC_MODE_0=ASYNCHRONOUS,ENUM_SYNC_MODE_1=ASYNCHRONOUS,ENUM_SYNC_MODE_2=ASYNCHRONOUS,ENUM_SYNC_MODE_3=ASYNCHRONOUS,ENUM_SYNC_MODE_4=ASYNCHRONOUS,ENUM_SYNC_MODE_5=ASYNCHRONOUS,ENUM_TEST_MODE=NORMAL_MODE,ENUM_THLD_JAR1_0=THRESHOLD_32,ENUM_THLD_JAR1_1=THRESHOLD_32,ENUM_THLD_JAR1_2=THRESHOLD_32,ENUM_THLD_JAR1_3=THRESHOLD_32,ENUM_THLD_JAR1_4=THRESHOLD_32,ENUM_THLD_JAR1_5=THRESHOLD_32,ENUM_THLD_JAR2_0=THRESHOLD_16,ENUM_THLD_JAR2_1=THRESHOLD_16,ENUM_THLD_JAR2_2=THRESHOLD_16,ENUM_THLD_JAR2_3=THRESHOLD_16,ENUM_THLD_JAR2_4=THRESHOLD_16,ENUM_THLD_JAR2_5=THRESHOLD_16,ENUM_USER_ECC_EN=DISABLE,ENUM_USER_PRIORITY_0=PRIORITY_0,ENUM_USER_PRIORITY_1=PRIORITY_0,ENUM_USER_PRIORITY_2=PRIORITY_0,ENUM_USER_PRIORITY_3=PRIORITY_0,ENUM_USER_PRIORITY_4=PRIORITY_0,ENUM_USER_PRIORITY_5=PRIORITY_0,ENUM_USE_ALMOST_EMPTY_0=EMPTY,ENUM_USE_ALMOST_EMPTY_1=EMPTY,ENUM_USE_ALMOST_EMPTY_2=EMPTY,ENUM_USE_ALMOST_EMPTY_3=EMPTY,ENUM_WFIFO0_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO0_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO1_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO1_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO2_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO2_RDY_ALMOST_FULL=NOT_FULL,ENUM_WFIFO3_CPORT_MAP=CMD_PORT_0,ENUM_WFIFO3_RDY_ALMOST_FULL=NOT_FULL,ENUM_WRITE_ODT_CHIP=ODT_DISABLED,ENUM_WR_DWIDTH_0=DWIDTH_0,ENUM_WR_DWIDTH_1=DWIDTH_0,ENUM_WR_DWIDTH_2=DWIDTH_0,ENUM_WR_DWIDTH_3=DWIDTH_0,ENUM_WR_DWIDTH_4=DWIDTH_0,ENUM_WR_DWIDTH_5=DWIDTH_0,ENUM_WR_FIFO_IN_USE_0=FALSE,ENUM_WR_FIFO_IN_USE_1=FALSE,ENUM_WR_FIFO_IN_USE_2=FALSE,ENUM_WR_FIFO_IN_USE_3=FALSE,ENUM_WR_PORT_INFO_0=USE_NO,ENUM_WR_PORT_INFO_1=USE_NO,ENUM_WR_PORT_INFO_2=USE_NO,ENUM_WR_PORT_INFO_3=USE_NO,ENUM_WR_PORT_INFO_4=USE_NO,ENUM_WR_PORT_INFO_5=USE_NO,EXPORT_AFI_HALF_CLK=false,EXPORT_CSR_PORT=false,EXTRA_SETTINGS=,EXTRA_VFIFO_SHIFT=0,FAST_SIM_CALIBRATION=false,FIX_READ_LATENCY=8,FLY_BY=true,FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,FORCED_NUM_WRITE_FR_CYCLE_SHIFTS=0,FORCE_DQS_TRACKING=AUTO,FORCE_MAX_LATENCY_COUNT_WIDTH=0,FORCE_SEQUENCER_TCL_DEBUG_MODE=false,FORCE_SHADOW_REGS=AUTO,FORCE_SYNTHESIS_LANGUAGE=,GENERIC_PLL=false,HARD_EMIF=true,HARD_PHY=false,HCX_COMPAT_MODE=false,HCX_COMPAT_MODE_CACHE=false,HHP_HPS=true,HHP_HPS_SIMULATION=false,HHP_HPS_VERIFICATION=false,HPS_PROTOCOL=DDR3,HR_DDIO_OUT_HAS_THREE_REGS=false,INCLUDE_BOARD_DELAY_MODEL=false,INCLUDE_MULTIRANK_BOARD_DELAY_MODEL=false,INTG_CYC_TO_RLD_JARS_0=1,INTG_CYC_TO_RLD_JARS_1=1,INTG_CYC_TO_RLD_JARS_2=1,INTG_CYC_TO_RLD_JARS_3=1,INTG_CYC_TO_RLD_JARS_4=1,INTG_CYC_TO_RLD_JARS_5=1,INTG_EXTRA_CTL_CLK_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK=0,INTG_EXTRA_CTL_CLK_ACT_TO_PCH=0,INTG_EXTRA_CTL_CLK_ACT_TO_RDWR=0,INTG_EXTRA_CTL_CLK_ARF_PERIOD=0,INTG_EXTRA_CTL_CLK_ARF_TO_VALID=0,INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT=0,INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID=0,INTG_EXTRA_CTL_CLK_PCH_TO_VALID=0,INTG_EXTRA_CTL_CLK_PDN_PERIOD=0,INTG_EXTRA_CTL_CLK_PDN_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_RD_TO_PCH=0,INTG_EXTRA_CTL_CLK_RD_TO_RD=0,INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_RD_TO_WR=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_BC=0,INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_SRF_TO_VALID=0,INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL=0,INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID=0,INTG_EXTRA_CTL_CLK_WR_TO_PCH=0,INTG_EXTRA_CTL_CLK_WR_TO_RD=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_BC=0,INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP=0,INTG_EXTRA_CTL_CLK_WR_TO_WR=0,INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP=0,INTG_MEM_AUTO_PD_CYCLES=0,INTG_MEM_CLK_ENTRY_CYCLES=10,INTG_MEM_IF_TREFI=3120,INTG_MEM_IF_TRFC=34,INTG_POWER_SAVING_EXIT_CYCLES=5,INTG_RCFG_SUM_WT_PRIORITY_0=0,INTG_RCFG_SUM_WT_PRIORITY_1=0,INTG_RCFG_SUM_WT_PRIORITY_2=0,INTG_RCFG_SUM_WT_PRIORITY_3=0,INTG_RCFG_SUM_WT_PRIORITY_4=0,INTG_RCFG_SUM_WT_PRIORITY_5=0,INTG_RCFG_SUM_WT_PRIORITY_6=0,INTG_RCFG_SUM_WT_PRIORITY_7=0,INTG_SUM_WT_PRIORITY_0=0,INTG_SUM_WT_PRIORITY_1=0,INTG_SUM_WT_PRIORITY_2=0,INTG_SUM_WT_PRIORITY_3=0,INTG_SUM_WT_PRIORITY_4=0,INTG_SUM_WT_PRIORITY_5=0,INTG_SUM_WT_PRIORITY_6=0,INTG_SUM_WT_PRIORITY_7=0,IO_DM_OUT_RESERVE=0,IO_DQDQS_OUT_PHASE_MAX=0,IO_DQS_EN_DELAY_OFFSET=0,IO_DQS_EN_PHASE_MAX=0,IO_DQS_IN_RESERVE=3,IO_DQS_OUT_RESERVE=3,IO_DQ_OUT_RESERVE=0,IO_IN_DELAY_MAX=-1,IO_OUT1_DELAY_MAX=-1,IO_OUT2_DELAY_MAX=-1,IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS=false,IO_STANDARD=,IS_ES_DEVICE=false,IS_ES_DEVICE_CACHE=false,LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT=true,LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE=0,LOCAL_CS_WIDTH=0,LOCAL_ID_WIDTH=8,LOW_LATENCY=false,LRDIMM=false,LRDIMM_EXTENDED_CONFIG=0x000000000000000000,LRDIMM_INT=0,LSB_RFIFO_PORT_0=5,LSB_RFIFO_PORT_1=5,LSB_RFIFO_PORT_2=5,LSB_RFIFO_PORT_3=5,LSB_RFIFO_PORT_4=5,LSB_RFIFO_PORT_5=5,LSB_WFIFO_PORT_0=5,LSB_WFIFO_PORT_1=5,LSB_WFIFO_PORT_2=5,LSB_WFIFO_PORT_3=5,LSB_WFIFO_PORT_4=5,LSB_WFIFO_PORT_5=5,MAKE_INTERNAL_NIOS_VISIBLE=false,MARGIN_VARIATION_TEST=false,MAX10_CFG=false,MAX10_RTL_SEQ=false,MAX_LATENCY_COUNT_WIDTH=6,MAX_PENDING_RD_CMD=32,MAX_PENDING_WR_CMD=16,MAX_WRITE_LATENCY_COUNT_WIDTH=4,MEM_ADD_LAT=0,MEM_ASR=Manual,MEM_ATCL=Disabled,MEM_ATCL_INT=0,MEM_AUTO_LEVELING_MODE=true,MEM_AUTO_PD_CYCLES=0,MEM_BANKADDR_WIDTH=3,MEM_BL=OTF,MEM_BT=Sequential,MEM_BURST_LENGTH=8,MEM_CK_LDC_ADJUSTMENT_THRESHOLD=0,MEM_CK_PHASE=0.0,MEM_CK_PHASE_CACHE=0.0,MEM_CK_WIDTH=1,MEM_CLK_EN_WIDTH=1,MEM_CLK_FREQ=400.0,MEM_CLK_FREQ_CACHE=0.0,MEM_CLK_FREQ_MAX=800.0,MEM_CLK_MAX_NS=2.5,MEM_CLK_MAX_PS=2500.0,MEM_CLK_NS=0.0,MEM_CLK_PS=0.0,MEM_CLK_TO_DQS_CAPTURE_DELAY=0,MEM_COL_ADDR_WIDTH=10,MEM_CS_WIDTH=1,MEM_DEVICE=MISSING_MODEL,MEM_DLL_EN=true,MEM_DQS_TO_CLK_CAPTURE_DELAY=0,MEM_DQ_PER_DQS=8,MEM_DQ_WIDTH=32,MEM_DRV_STR=RZQ/7,MEM_FORMAT=DISCRETE,MEM_GUARANTEED_WRITE_INIT=false,MEM_IF_ADDR_WIDTH=0,MEM_IF_ADDR_WIDTH_MIN=10,MEM_IF_BANKADDR_WIDTH=0,MEM_IF_BOARD_BASE_DELAY=10,MEM_IF_CHIP_BITS=-1,MEM_IF_CK_WIDTH=0,MEM_IF_CLK_EN_WIDTH=0,MEM_IF_CLK_PAIR_COUNT=1,MEM_IF_COL_ADDR_WIDTH=0,MEM_IF_CONTROL_WIDTH=0,MEM_IF_CS_PER_DIMM=0,MEM_IF_CS_PER_RANK=0,MEM_IF_CS_WIDTH=0,MEM_IF_DM_PINS_EN=true,MEM_IF_DM_WIDTH=0,MEM_IF_DQSN_EN=true,MEM_IF_DQS_WIDTH=0,MEM_IF_DQ_WIDTH=0,MEM_IF_LRDIMM_RM=0,MEM_IF_NUMBER_OF_RANKS=0,MEM_IF_ODT_WIDTH=0,MEM_IF_RD_TO_WR_TURNAROUND_OCT=0,MEM_IF_READ_DQS_WIDTH=0,MEM_IF_ROW_ADDR_WIDTH=0,MEM_IF_SIM_VALID_WINDOW=0,MEM_IF_WRITE_DQS_WIDTH=0,MEM_IF_WR_TO_RD_TURNAROUND_OCT=3,MEM_INIT_EN=false,MEM_INIT_FILE=,MEM_LEVELING=true,MEM_LRDIMM_ENABLED=false,MEM_MIRROR_ADDRESSING=0,MEM_MIRROR_ADDRESSING_DEC=0,MEM_NUMBER_OF_DIMMS=1,MEM_NUMBER_OF_RANKS_PER_DEVICE=1,MEM_NUMBER_OF_RANKS_PER_DIMM=1,MEM_PD=DLL off,MEM_RANK_MULTIPLICATION_FACTOR=1,MEM_REGDIMM_ENABLED=false,MEM_ROW_ADDR_WIDTH=15,MEM_RTT_NOM=RZQ/4,MEM_RTT_WR=RZQ/4,MEM_SRT=Normal,MEM_TCL=11,MEM_TDQSCK=2,MEM_TFAW=0,MEM_TFAW_NS=30.0,MEM_TINIT_CK=499,MEM_TINIT_US=500,MEM_TMRD_CK=4,MEM_TRAS=0,MEM_TRAS_NS=35.0,MEM_TRC=0,MEM_TRCD=0,MEM_TRCD_NS=13.75,MEM_TREFI=0,MEM_TREFI_US=7.8,MEM_TRFC=0,MEM_TRFC_NS=260.0,MEM_TRP=0,MEM_TRP_NS=13.75,MEM_TRRD=0,MEM_TRRD_NS=7.7,MEM_TRTP=0,MEM_TRTP_NS=7.5,MEM_TWR=0,MEM_TWR_NS=15.0,MEM_TWTR=4,MEM_TYPE=,MEM_T_RL=0,MEM_T_WL=0,MEM_USER_LEVELING_MODE=Leveling,MEM_VENDOR=JEDEC,MEM_VERBOSE=true,MEM_VOLTAGE=1.5V DDR3,MEM_WTCL=8,MEM_WTCL_INT=6,MR0_BL=2,MR0_BT=0,MR0_CAS_LATENCY=3,MR0_DLL=1,MR0_PD=0,MR0_WR=4,MR1_AL=0,MR1_BL=2,MR1_BT=0,MR1_DLL=0,MR1_DQS=0,MR1_DS=0,MR1_ODS=1,MR1_PASR=0,MR1_QOFF=0,MR1_RDQS=0,MR1_RTT=1,MR1_TDQS=0,MR1_WC=0,MR1_WL=0,MR1_WR=1,MR2_ASR=0,MR2_CWL=1,MR2_RLWL=1,MR2_RTT_WR=1,MR2_SRF=0,MR2_SRT=0,MR3_DS=2,MR3_MPR=0,MR3_MPR_AA=0,MR3_MPR_RF=0,MRS_MIRROR_PING_PONG_ATSO=false,MSB_RFIFO_PORT_0=5,MSB_RFIFO_PORT_1=5,MSB_RFIFO_PORT_2=5,MSB_RFIFO_PORT_3=5,MSB_RFIFO_PORT_4=5,MSB_RFIFO_PORT_5=5,MSB_WFIFO_PORT_0=5,MSB_WFIFO_PORT_1=5,MSB_WFIFO_PORT_2=5,MSB_WFIFO_PORT_3=5,MSB_WFIFO_PORT_4=5,MSB_WFIFO_PORT_5=5,MULTICAST_EN=false,NEGATIVE_WRITE_CK_PHASE=false,NEXTGEN=true,NIOS_HEX_FILE_LOCATION=,NIOS_ROM_ADDRESS_WIDTH=13,NIOS_ROM_DATA_WIDTH=32,NON_LDC_ADDR_CMD_MEM_CK_INVERT=false,NUM_AC_FR_CYCLE_SHIFTS=0,NUM_DLL_SHARING_INTERFACES=1,NUM_EXTRA_REPORT_PATH=10,NUM_OCT_SHARING_INTERFACES=1,NUM_OF_PORTS=1,NUM_PLL_SHARING_INTERFACES=1,NUM_SUBGROUP_PER_READ_DQS=0,NUM_WRITE_FR_CYCLE_SHIFTS=0,NUM_WRITE_PATH_FLOP_STAGES=0,OCT_SHARING_MODE=None,OCT_TERM_CONTROL_WIDTH=14,P2C_READ_CLOCK_ADD_PHASE=0.0,P2C_READ_CLOCK_ADD_PHASE_CACHE=0.0,PACKAGE_DESKEW=false,PARSE_FRIENDLY_DEVICE_FAMILY=,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE=Unknown,PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID=false,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM=,PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID=false,PERFORM_READ_AFTER_WRITE_CALIBRATION=false,PHY_CLKBUF=false,PHY_CSR_CONNECTION=INTERNAL_JTAG,PHY_CSR_ENABLED=false,PHY_ONLY=false,PHY_VERSION_NUMBER=0,PINGPONGPHY_EN=false,PLL_ADDR_CMD_CLK_DIV=0,PLL_ADDR_CMD_CLK_DIV_CACHE=0,PLL_ADDR_CMD_CLK_DIV_PARAM=0,PLL_ADDR_CMD_CLK_FREQ=0.0,PLL_ADDR_CMD_CLK_FREQ_CACHE=0.0,PLL_ADDR_CMD_CLK_FREQ_PARAM=0.0,PLL_ADDR_CMD_CLK_FREQ_SIM_STR=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_FREQ_STR=,PLL_ADDR_CMD_CLK_MULT=0,PLL_ADDR_CMD_CLK_MULT_CACHE=0,PLL_ADDR_CMD_CLK_MULT_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_DEG=0.0,PLL_ADDR_CMD_CLK_PHASE_DEG_SIM=0.0,PLL_ADDR_CMD_CLK_PHASE_PS=0,PLL_ADDR_CMD_CLK_PHASE_PS_CACHE=0,PLL_ADDR_CMD_CLK_PHASE_PS_PARAM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM=0,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_ADDR_CMD_CLK_PHASE_PS_STR=,PLL_AFI_CLK_DIV=0,PLL_AFI_CLK_DIV_CACHE=0,PLL_AFI_CLK_DIV_PARAM=0,PLL_AFI_CLK_FREQ=0.0,PLL_AFI_CLK_FREQ_CACHE=0.0,PLL_AFI_CLK_FREQ_PARAM=0.0,PLL_AFI_CLK_FREQ_SIM_STR=,PLL_AFI_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_CLK_FREQ_STR=,PLL_AFI_CLK_MULT=0,PLL_AFI_CLK_MULT_CACHE=0,PLL_AFI_CLK_MULT_PARAM=0,PLL_AFI_CLK_PHASE_DEG=0.0,PLL_AFI_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_CLK_PHASE_PS=0,PLL_AFI_CLK_PHASE_PS_CACHE=0,PLL_AFI_CLK_PHASE_PS_PARAM=0,PLL_AFI_CLK_PHASE_PS_SIM=0,PLL_AFI_CLK_PHASE_PS_SIM_STR=,PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_CLK_PHASE_PS_STR=,PLL_AFI_HALF_CLK_DIV=0,PLL_AFI_HALF_CLK_DIV_CACHE=0,PLL_AFI_HALF_CLK_DIV_PARAM=0,PLL_AFI_HALF_CLK_FREQ=0.0,PLL_AFI_HALF_CLK_FREQ_CACHE=0.0,PLL_AFI_HALF_CLK_FREQ_PARAM=0.0,PLL_AFI_HALF_CLK_FREQ_SIM_STR=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_FREQ_STR=,PLL_AFI_HALF_CLK_MULT=0,PLL_AFI_HALF_CLK_MULT_CACHE=0,PLL_AFI_HALF_CLK_MULT_PARAM=0,PLL_AFI_HALF_CLK_PHASE_DEG=0.0,PLL_AFI_HALF_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_HALF_CLK_PHASE_PS=0,PLL_AFI_HALF_CLK_PHASE_PS_CACHE=0,PLL_AFI_HALF_CLK_PHASE_PS_PARAM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM=0,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_HALF_CLK_PHASE_PS_STR=,PLL_AFI_PHY_CLK_DIV=0,PLL_AFI_PHY_CLK_DIV_CACHE=0,PLL_AFI_PHY_CLK_DIV_PARAM=0,PLL_AFI_PHY_CLK_FREQ=0.0,PLL_AFI_PHY_CLK_FREQ_CACHE=0.0,PLL_AFI_PHY_CLK_FREQ_PARAM=0.0,PLL_AFI_PHY_CLK_FREQ_SIM_STR=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_FREQ_STR=,PLL_AFI_PHY_CLK_MULT=0,PLL_AFI_PHY_CLK_MULT_CACHE=0,PLL_AFI_PHY_CLK_MULT_PARAM=0,PLL_AFI_PHY_CLK_PHASE_DEG=0.0,PLL_AFI_PHY_CLK_PHASE_DEG_SIM=0.0,PLL_AFI_PHY_CLK_PHASE_PS=0,PLL_AFI_PHY_CLK_PHASE_PS_CACHE=0,PLL_AFI_PHY_CLK_PHASE_PS_PARAM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM=0,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_AFI_PHY_CLK_PHASE_PS_STR=,PLL_C2P_WRITE_CLK_DIV=0,PLL_C2P_WRITE_CLK_DIV_CACHE=0,PLL_C2P_WRITE_CLK_DIV_PARAM=0,PLL_C2P_WRITE_CLK_FREQ=0.0,PLL_C2P_WRITE_CLK_FREQ_CACHE=0.0,PLL_C2P_WRITE_CLK_FREQ_PARAM=0.0,PLL_C2P_WRITE_CLK_FREQ_SIM_STR=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_FREQ_STR=,PLL_C2P_WRITE_CLK_MULT=0,PLL_C2P_WRITE_CLK_MULT_CACHE=0,PLL_C2P_WRITE_CLK_MULT_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_DEG=0.0,PLL_C2P_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_C2P_WRITE_CLK_PHASE_PS=0,PLL_C2P_WRITE_CLK_PHASE_PS_CACHE=0,PLL_C2P_WRITE_CLK_PHASE_PS_PARAM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM=0,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_C2P_WRITE_CLK_PHASE_PS_STR=,PLL_CLK_CACHE_VALID=false,PLL_CLK_PARAM_VALID=false,PLL_CONFIG_CLK_DIV=0,PLL_CONFIG_CLK_DIV_CACHE=0,PLL_CONFIG_CLK_DIV_PARAM=0,PLL_CONFIG_CLK_FREQ=0.0,PLL_CONFIG_CLK_FREQ_CACHE=0.0,PLL_CONFIG_CLK_FREQ_PARAM=0.0,PLL_CONFIG_CLK_FREQ_SIM_STR=,PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE=,PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM=,PLL_CONFIG_CLK_FREQ_STR=,PLL_CONFIG_CLK_MULT=0,PLL_CONFIG_CLK_MULT_CACHE=0,PLL_CONFIG_CLK_MULT_PARAM=0,PLL_CONFIG_CLK_PHASE_DEG=0.0,PLL_CONFIG_CLK_PHASE_DEG_SIM=0.0,PLL_CONFIG_CLK_PHASE_PS=0,PLL_CONFIG_CLK_PHASE_PS_CACHE=0,PLL_CONFIG_CLK_PHASE_PS_PARAM=0,PLL_CONFIG_CLK_PHASE_PS_SIM=0,PLL_CONFIG_CLK_PHASE_PS_SIM_STR=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_CONFIG_CLK_PHASE_PS_STR=,PLL_DR_CLK_DIV=0,PLL_DR_CLK_DIV_CACHE=0,PLL_DR_CLK_DIV_PARAM=0,PLL_DR_CLK_FREQ=0.0,PLL_DR_CLK_FREQ_CACHE=0.0,PLL_DR_CLK_FREQ_PARAM=0.0,PLL_DR_CLK_FREQ_SIM_STR=,PLL_DR_CLK_FREQ_SIM_STR_CACHE=,PLL_DR_CLK_FREQ_SIM_STR_PARAM=,PLL_DR_CLK_FREQ_STR=,PLL_DR_CLK_MULT=0,PLL_DR_CLK_MULT_CACHE=0,PLL_DR_CLK_MULT_PARAM=0,PLL_DR_CLK_PHASE_DEG=0.0,PLL_DR_CLK_PHASE_DEG_SIM=0.0,PLL_DR_CLK_PHASE_PS=0,PLL_DR_CLK_PHASE_PS_CACHE=0,PLL_DR_CLK_PHASE_PS_PARAM=0,PLL_DR_CLK_PHASE_PS_SIM=0,PLL_DR_CLK_PHASE_PS_SIM_STR=,PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_DR_CLK_PHASE_PS_STR=,PLL_HR_CLK_DIV=0,PLL_HR_CLK_DIV_CACHE=0,PLL_HR_CLK_DIV_PARAM=0,PLL_HR_CLK_FREQ=0.0,PLL_HR_CLK_FREQ_CACHE=0.0,PLL_HR_CLK_FREQ_PARAM=0.0,PLL_HR_CLK_FREQ_SIM_STR=,PLL_HR_CLK_FREQ_SIM_STR_CACHE=,PLL_HR_CLK_FREQ_SIM_STR_PARAM=,PLL_HR_CLK_FREQ_STR=,PLL_HR_CLK_MULT=0,PLL_HR_CLK_MULT_CACHE=0,PLL_HR_CLK_MULT_PARAM=0,PLL_HR_CLK_PHASE_DEG=0.0,PLL_HR_CLK_PHASE_DEG_SIM=0.0,PLL_HR_CLK_PHASE_PS=0,PLL_HR_CLK_PHASE_PS_CACHE=0,PLL_HR_CLK_PHASE_PS_PARAM=0,PLL_HR_CLK_PHASE_PS_SIM=0,PLL_HR_CLK_PHASE_PS_SIM_STR=,PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_HR_CLK_PHASE_PS_STR=,PLL_LOCATION=Top_Bottom,PLL_MASTER=false,PLL_MEM_CLK_DIV=0,PLL_MEM_CLK_DIV_CACHE=0,PLL_MEM_CLK_DIV_PARAM=0,PLL_MEM_CLK_FREQ=0.0,PLL_MEM_CLK_FREQ_CACHE=0.0,PLL_MEM_CLK_FREQ_PARAM=0.0,PLL_MEM_CLK_FREQ_SIM_STR=,PLL_MEM_CLK_FREQ_SIM_STR_CACHE=,PLL_MEM_CLK_FREQ_SIM_STR_PARAM=,PLL_MEM_CLK_FREQ_STR=,PLL_MEM_CLK_MULT=0,PLL_MEM_CLK_MULT_CACHE=0,PLL_MEM_CLK_MULT_PARAM=0,PLL_MEM_CLK_PHASE_DEG=0.0,PLL_MEM_CLK_PHASE_DEG_SIM=0.0,PLL_MEM_CLK_PHASE_PS=0,PLL_MEM_CLK_PHASE_PS_CACHE=0,PLL_MEM_CLK_PHASE_PS_PARAM=0,PLL_MEM_CLK_PHASE_PS_SIM=0,PLL_MEM_CLK_PHASE_PS_SIM_STR=,PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_MEM_CLK_PHASE_PS_STR=,PLL_NIOS_CLK_DIV=0,PLL_NIOS_CLK_DIV_CACHE=0,PLL_NIOS_CLK_DIV_PARAM=0,PLL_NIOS_CLK_FREQ=0.0,PLL_NIOS_CLK_FREQ_CACHE=0.0,PLL_NIOS_CLK_FREQ_PARAM=0.0,PLL_NIOS_CLK_FREQ_SIM_STR=,PLL_NIOS_CLK_FREQ_SIM_STR_CACHE=,PLL_NIOS_CLK_FREQ_SIM_STR_PARAM=,PLL_NIOS_CLK_FREQ_STR=,PLL_NIOS_CLK_MULT=0,PLL_NIOS_CLK_MULT_CACHE=0,PLL_NIOS_CLK_MULT_PARAM=0,PLL_NIOS_CLK_PHASE_DEG=0.0,PLL_NIOS_CLK_PHASE_DEG_SIM=0.0,PLL_NIOS_CLK_PHASE_PS=0,PLL_NIOS_CLK_PHASE_PS_CACHE=0,PLL_NIOS_CLK_PHASE_PS_PARAM=0,PLL_NIOS_CLK_PHASE_PS_SIM=0,PLL_NIOS_CLK_PHASE_PS_SIM_STR=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_NIOS_CLK_PHASE_PS_STR=,PLL_P2C_READ_CLK_DIV=0,PLL_P2C_READ_CLK_DIV_CACHE=0,PLL_P2C_READ_CLK_DIV_PARAM=0,PLL_P2C_READ_CLK_FREQ=0.0,PLL_P2C_READ_CLK_FREQ_CACHE=0.0,PLL_P2C_READ_CLK_FREQ_PARAM=0.0,PLL_P2C_READ_CLK_FREQ_SIM_STR=,PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE=,PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM=,PLL_P2C_READ_CLK_FREQ_STR=,PLL_P2C_READ_CLK_MULT=0,PLL_P2C_READ_CLK_MULT_CACHE=0,PLL_P2C_READ_CLK_MULT_PARAM=0,PLL_P2C_READ_CLK_PHASE_DEG=0.0,PLL_P2C_READ_CLK_PHASE_DEG_SIM=0.0,PLL_P2C_READ_CLK_PHASE_PS=0,PLL_P2C_READ_CLK_PHASE_PS_CACHE=0,PLL_P2C_READ_CLK_PHASE_PS_PARAM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM=0,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_P2C_READ_CLK_PHASE_PS_STR=,PLL_PHASE_COUNTER_WIDTH=0,PLL_SHARING_MODE=None,PLL_WRITE_CLK_DIV=0,PLL_WRITE_CLK_DIV_CACHE=0,PLL_WRITE_CLK_DIV_PARAM=0,PLL_WRITE_CLK_FREQ=0.0,PLL_WRITE_CLK_FREQ_CACHE=0.0,PLL_WRITE_CLK_FREQ_PARAM=0.0,PLL_WRITE_CLK_FREQ_SIM_STR=,PLL_WRITE_CLK_FREQ_SIM_STR_CACHE=,PLL_WRITE_CLK_FREQ_SIM_STR_PARAM=,PLL_WRITE_CLK_FREQ_STR=,PLL_WRITE_CLK_MULT=0,PLL_WRITE_CLK_MULT_CACHE=0,PLL_WRITE_CLK_MULT_PARAM=0,PLL_WRITE_CLK_PHASE_DEG=0.0,PLL_WRITE_CLK_PHASE_DEG_SIM=0.0,PLL_WRITE_CLK_PHASE_PS=0,PLL_WRITE_CLK_PHASE_PS_CACHE=0,PLL_WRITE_CLK_PHASE_PS_PARAM=0,PLL_WRITE_CLK_PHASE_PS_SIM=0,PLL_WRITE_CLK_PHASE_PS_SIM_STR=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE=,PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM=,PLL_WRITE_CLK_PHASE_PS_STR=,POWER_OF_TWO_BUS=false,PRE_V_SERIES_FAMILY=false,PRIORITY_PORT=1,1,1,1,1,1,PRIORITY_PORT_0=0,PRIORITY_PORT_1=0,PRIORITY_PORT_2=0,PRIORITY_PORT_3=0,PRIORITY_PORT_4=0,PRIORITY_PORT_5=0,QVLD_EXTRA_FLOP_STAGES=0,QVLD_WR_ADDRESS_OFFSET=0,RATE=Full,RATE_CACHE=Unknown,RDBUFFER_ADDR_WIDTH=6,RDIMM=false,RDIMM_CONFIG=0000000000000000,RDIMM_INT=0,READ_DQ_DQS_CLOCK_SOURCE=INVERTED_DQS_BUS,READ_FIFO_HALF_RATE=false,READ_FIFO_SIZE=8,READ_VALID_FIFO_SIZE=16,REFRESH_BURST_VALIDATION=false,REFRESH_INTERVAL=15000,REF_CLK_FREQ=25.0,REF_CLK_FREQ_CACHE=0.0,REF_CLK_FREQ_CACHE_VALID=false,REF_CLK_FREQ_MAX_CACHE=0.0,REF_CLK_FREQ_MAX_PARAM=0.0,REF_CLK_FREQ_MIN_CACHE=0.0,REF_CLK_FREQ_MIN_PARAM=0.0,REF_CLK_FREQ_PARAM_VALID=false,REF_CLK_FREQ_STR=,REF_CLK_NS=0.0,REF_CLK_PS=0.0,REGISTER_C2P=false,SCC_DATA_WIDTH=0,SEQUENCER_TYPE=NIOS,SEQUENCER_TYPE_CACHE=Unknown,SEQ_BURST_COUNT_WIDTH=0,SEQ_MODE=0,SKIP_MEM_INIT=true,SOPC_COMPAT_RESET=false,SPEED_GRADE=7,SPEED_GRADE_CACHE=,STARVE_LIMIT=10,SYS_INFO_DEVICE_FAMILY=Cyclone V,TB_MEM_CLK_FREQ=0.0,TB_MEM_IF_DQ_WIDTH=0,TB_MEM_IF_READ_DQS_WIDTH=0,TB_PLL_DLL_MASTER=true,TB_RATE=,TG_TEMP_PORT_0=0,TG_TEMP_PORT_1=0,TG_TEMP_PORT_2=0,TG_TEMP_PORT_3=0,TG_TEMP_PORT_4=0,TG_TEMP_PORT_5=0,TIMING_BOARD_AC_EYE_REDUCTION_H=0.0,TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU=0.0,TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED=0.0,TIMING_BOARD_AC_SKEW=0.03,TIMING_BOARD_AC_SLEW_RATE=1.0,TIMING_BOARD_AC_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_AC_TO_CK_SKEW=0.0,TIMING_BOARD_CK_CKN_SLEW_RATE=2.0,TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME=0.0,TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED=0.0,TIMING_BOARD_DERATE_METHOD=AUTO,TIMING_BOARD_DQS_DQSN_SLEW_RATE=2.0,TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED=2.0,TIMING_BOARD_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_DQ_SLEW_RATE=1.0,TIMING_BOARD_DQ_SLEW_RATE_APPLIED=1.0,TIMING_BOARD_DQ_TO_DQS_SKEW=0.0,TIMING_BOARD_ISI_METHOD=AUTO,TIMING_BOARD_MAX_CK_DELAY=0.03,TIMING_BOARD_MAX_DQS_DELAY=0.02,TIMING_BOARD_READ_DQ_EYE_REDUCTION=0.0,TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED=0.0,TIMING_BOARD_SKEW_BETWEEN_DIMMS=0.05,TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED=0.05,TIMING_BOARD_SKEW_BETWEEN_DQS=0.08,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX=0.16,TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED=0.01,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN=0.09,TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED=-0.01,TIMING_BOARD_SKEW_WITHIN_DQS=0.01,TIMING_BOARD_TDH=0.0,TIMING_BOARD_TDH_APPLIED=0.0,TIMING_BOARD_TDS=0.0,TIMING_BOARD_TDS_APPLIED=0.0,TIMING_BOARD_TIH=0.0,TIMING_BOARD_TIH_APPLIED=0.0,TIMING_BOARD_TIS=0.0,TIMING_BOARD_TIS_APPLIED=0.0,TIMING_TDH=65,TIMING_TDQSCK=255,TIMING_TDQSCKDL=1200,TIMING_TDQSCKDM=900,TIMING_TDQSCKDS=450,TIMING_TDQSH=0.35,TIMING_TDQSQ=125,TIMING_TDQSS=0.25,TIMING_TDS=30,TIMING_TDSH=0.2,TIMING_TDSS=0.2,TIMING_TIH=140,TIMING_TIS=180,TIMING_TQH=0.38,TIMING_TQHS=300,TIMING_TQSH=0.4,TRACKING_ERROR_TEST=false,TRACKING_WATCH_TEST=false,TREFI=35100,TRFC=350,TRK_PARALLEL_SCC_LOAD=false,USER_DEBUG_LEVEL=1,USE_2X_FF=false,USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE=false,USE_AXI_ADAPTOR=false,USE_DQS_TRACKING=false,USE_DR_CLK=false,USE_FAKE_PHY=false,USE_FAKE_PHY_INTERNAL=false,USE_HARD_READ_FIFO=false,USE_HPS_DQS_TRACKING=false,USE_LDC_AS_LOW_SKEW_CLOCK=false,USE_LDC_FOR_ADDR_CMD=false,USE_MEM_CLK_FREQ=false,USE_MEM_CLK_FREQ_CACHE=false,USE_MM_ADAPTOR=true,USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY=false,USE_SEQUENCER_BFM=false,USE_SHADOW_REGS=false,USE_USER_RDIMM_VALUE=false,VCALIB_COUNT_WIDTH=0,VECT_ATTR_COUNTER_ONE_MASK=0,VECT_ATTR_COUNTER_ONE_MATCH=0,VECT_ATTR_COUNTER_ZERO_MASK=0,VECT_ATTR_COUNTER_ZERO_MATCH=0,VECT_ATTR_DEBUG_SELECT_BYTE=0,VFIFO_AS_SHIFT_REG=false,WEIGHT_PORT=0,0,0,0,0,0,WEIGHT_PORT_0=0,WEIGHT_PORT_1=0,WEIGHT_PORT_2=0,WEIGHT_PORT_3=0,WEIGHT_PORT_4=0,WEIGHT_PORT_5=0,WRBUFFER_ADDR_WIDTH=6,device=5CSEMA5F31C6,hps_parameter_map=AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 1.25 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 200000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 32 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 4 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 1000.0 MEM_TRCD 6 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA5F31C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 14 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 25.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 64 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 125 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.02 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 32 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 25.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 25000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 2500.0 periph_pll_vco_hz 1000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 30 PLL_WRITE_CLK_PHASE_PS_CACHE 1875 UART0_PinMuxing {HPS I/O Set 0} sdmmc_clk_hz 200000000 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode RGMII NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz 1600000000 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 2.5 PLL_AFI_CLK_MULT_CACHE 32 PLL_ADDR_CMD_CLK_DIV 2 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 3 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 32 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {45000 ps} PLL_AFI_CLK_DIV 2 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 13.75 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 400.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 2 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.8 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.08 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 25000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 200.0 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 180 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {25.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.03 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 6 TIMING_TIH 140 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 0 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing {HPS I/O Set 0} desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 200000000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_8 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 1875 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 200.0 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 30 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 6 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 65 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {2500 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 20 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 32 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 64 PLL_AFI_PHY_CLK_FREQ 400.0 periph_nand_sdmmc_clk_mhz 200.0 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000110 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No Yes No No No No Yes No No No No No No No Yes No No No No Yes Yes No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 4 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {400.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode I2C IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 12500000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.09 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 200000000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 35.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 2 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {2500 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED true TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode {No Flow Control} S2FCLK_USER0CLK_FREQ_HZ 97368421 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 800.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 4 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 1875 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 8 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 10 dbg_timer_clk_hz 25000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode {Single Slave Select} hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 97.368421 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM RZQ/4 AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 40000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_6 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 13.75 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 8 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.16 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 40.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 2 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 400.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_6 MR2_RTT_WR 1 MEM_TCL 11 GPIO_Pin_Used_DERIVED true JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 104 USE_2X_FF false ENUM_MEM_IF_TRC TRC_20 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 27 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 50000000 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable true desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 2 F2SDRAM_Width {} dbg_clk_hz 12500000 PLL_AFI_CLK_FREQ 400.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.18 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 400.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 66.6666666667 dbg_timer_clk_mhz 25.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {2500 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 9 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 0 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {1875 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 15 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 100.0 PLL_AFI_HALF_CLK_MULT_CACHE 32 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 32 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 400.0 AFI_WRITE_DQS_WIDTH 4 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 200.0 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 25000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.16 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 10 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 200.0 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz 1600.0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.33 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {1875 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {2500 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 15 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {1875 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0010011101000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/7 MEM_IF_DM_WIDTH 4 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.7 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 32 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 32 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 30.0 DELAY_PER_OPA_TAP 312 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing {HPS I/O Set 0} MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {2500 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 12.5 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 6000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 2 ENUM_MEM_IF_TCL TCL_11 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR JEDEC device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing {HPS I/O Set 0} CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_4 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 2 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 97.368421 MR2_CWL 3 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 211 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 39 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 12.5 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 73 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 400.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 15 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 1 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 32000 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 MR0_BT 0 PLL_CONFIG_CLK_FREQ 22.2222222222 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 1 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {400.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 32 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 25.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR RZQ/4 TIMING_TDQSCK 255 REF_CLK_FREQ_CACHE 25.0 AC_ROM_MR0_DLL_RESET 0010101110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {15000 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0010001101001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 12 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {400.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing {HPS I/O Set 0} MEM_TREFI 3120 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 32 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 25.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.09 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {2500 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 4 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 10 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_6 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 50000000 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.165 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {2500 ps} emac1_clk_mhz 250.0 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 500 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 32 TIMING_BOARD_SKEW_WITHIN_DQS 0.01 ENUM_MEM_IF_TRAS TRAS_14 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 1 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.03 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 7 H2F_LW_AXI_CLOCK_FREQ 50000000 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {400.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 2 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {1875 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 12500000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 250000000 eosc2_clk_mhz 25.0 PLL_MEM_CLK_DIV_CACHE 2 periph_base_clk_mhz 200.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_32 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 8 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.24 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing {HPS I/O Set 0} INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 400.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 25.0 desired_cfg_clk_hz 97368421 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 2 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 200000000 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 4 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {5000 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 8 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 11 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 200000000 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 6249 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0001000011000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode I2C quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 3120 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 1875 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {400.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 4 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 260.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY true ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 4 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 1 pin_muxing_check {Cyclone V+5CSEMA5F31C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 100000000 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 2 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 200000 PLL_WRITE_CLK_MULT_CACHE 32 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 400.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 4 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 50.0 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} USB1.D0 USB1.D1 USB1.D2 USB1.D3 USB1.D4 USB1.D5 USB1.D6 USB1.D7 {} USB1.CLK USB1.STP USB1.DIR USB1.NXT EMAC1.TX_CLK EMAC1.TXD0 EMAC1.TXD1 EMAC1.TXD2 EMAC1.TXD3 EMAC1.RXD0 EMAC1.MDIO EMAC1.MDC EMAC1.RX_CTL EMAC1.TX_CTL EMAC1.RX_CLK EMAC1.RXD1 EMAC1.RXD2 EMAC1.RXD3 {} {} {} {} {} {} {} {} SDIO.CMD {} SDIO.D0 SDIO.D1 {} {} {} {} {} SDIO.CLK SDIO.D2 SDIO.D3 {} UART0.RX UART0.TX I2C1.SDA I2C1.SCL {} {} I2C0.SDA I2C0.SCL {} {} {} {} {} {} SPIM1.CLK SPIM1.MOSI SPIM1.MISO SPIM1.SS0} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 8 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 400.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 8 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 32 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0001000011000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000000000110 TB_MEM_CLK_FREQ 400.0 AC_ROM_MR0 0010001110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 18000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 400.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {2500 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 12.5 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 5 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_4 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing {HPS I/O Set 0} CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 25000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {5000 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode SDR ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.4 dbg_base_clk_hz 25000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 400.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 2 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 1250.0 S2FCLK_USER1CLK_Enable true SDIO_Mode {4-bit Data} desired_qspi_clk_mhz 400.0 MEM_TRFC 104 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2,ignoreSimulation=true,interfaceDefinition=instances {sdio_inst {entity_name cyclonev_hps_peripheral_sdmmc location HPSPERIPHERALSDMMC_X87_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} emac1_inst {entity_name cyclonev_hps_peripheral_emac location HPSPERIPHERALEMAC_X77_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c1_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y65_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} spim1_inst {entity_name cyclonev_hps_peripheral_spi_master location HPSPERIPHERALSPIMASTER_X87_Y53_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} uart0_inst {entity_name cyclonev_hps_peripheral_uart location HPSPERIPHERALUART_X87_Y45_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} @orderednames {emac1_inst sdio_inst usb1_inst spim1_inst uart0_inst i2c0_inst i2c1_inst gpio_inst hps_sdram_inst} usb1_inst {entity_name cyclonev_hps_peripheral_usb location HPSPERIPHERALUSB_X55_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} gpio_inst {entity_name cyclonev_hps_peripheral_gpio location HPSPERIPHERALGPIO_X87_Y74_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps_sdram_inst {entity_name hps_sdram location {} signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c0_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y67_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD0]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD1]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD2]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD3]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD0] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_MDIO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDIO]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDC]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CTL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CTL]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CLK] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD1] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD2] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD3] -to *} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1]} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D1]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D4] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D4]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D5] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D5]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D6] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D6]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D7] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D7]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_CLK] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_STP]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_DIR] -to *} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_NXT] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_MOSI]} {set_false_path -from [get_ports hps_io_hps_io_spim1_inst_MISO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_SS0]} {set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO09] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO09]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO35] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO35]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO40] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO40]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO48] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO48]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO53] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO53]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO54] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO54]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO61] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO61]}} properties {SUPPRESS_SDRAM_SYNTH 0 GENERATE_ISW 1} bfm_types {} intermediate_wire_count 48 interfaces {@orderednames {memory hps_io} memory {properties {} type conduit direction end signals {@orderednames {mem_a mem_ba mem_ck mem_ck_n mem_cke mem_cs_n mem_ras_n mem_cas_n mem_we_n mem_reset_n mem_dq mem_dqs mem_dqs_n mem_odt mem_dm oct_rzqin} mem_a {fragments {} properties {} internal_name mem_a width 15 instance_name hps_sdram_inst direction Output role mem_a} mem_ba {fragments {} properties {} internal_name mem_ba width 3 instance_name hps_sdram_inst direction Output role mem_ba} mem_ck {fragments {} properties {} internal_name mem_ck width 1 instance_name hps_sdram_inst direction Output role mem_ck} mem_ck_n {fragments {} properties {} internal_name mem_ck_n width 1 instance_name hps_sdram_inst direction Output role mem_ck_n} mem_cke {fragments {} properties {} internal_name mem_cke width 1 instance_name hps_sdram_inst direction Output role mem_cke} mem_cs_n {fragments {} properties {} internal_name mem_cs_n width 1 instance_name hps_sdram_inst direction Output role mem_cs_n} mem_ras_n {fragments {} properties {} internal_name mem_ras_n width 1 instance_name hps_sdram_inst direction Output role mem_ras_n} mem_cas_n {fragments {} properties {} internal_name mem_cas_n width 1 instance_name hps_sdram_inst direction Output role mem_cas_n} mem_we_n {fragments {} properties {} internal_name mem_we_n width 1 instance_name hps_sdram_inst direction Output role mem_we_n} mem_reset_n {fragments {} properties {} internal_name mem_reset_n width 1 instance_name hps_sdram_inst direction Output role mem_reset_n} mem_dq {fragments {} properties {} internal_name mem_dq width 32 instance_name hps_sdram_inst direction Bidir role mem_dq} mem_dqs {fragments {} properties {} internal_name mem_dqs width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs} mem_dqs_n {fragments {} properties {} internal_name mem_dqs_n width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs_n} mem_odt {fragments {} properties {} internal_name mem_odt width 1 instance_name hps_sdram_inst direction Output role mem_odt} mem_dm {fragments {} properties {} internal_name mem_dm width 4 instance_name hps_sdram_inst direction Output role mem_dm} oct_rzqin {fragments {} properties {} internal_name oct_rzqin width 1 instance_name hps_sdram_inst direction Input role oct_rzqin}}} hps_io {properties {} type conduit direction input signals {@orderednames {hps_io_emac1_inst_TX_CLK hps_io_emac1_inst_TXD0 hps_io_emac1_inst_TXD1 hps_io_emac1_inst_TXD2 hps_io_emac1_inst_TXD3 hps_io_emac1_inst_RXD0 hps_io_emac1_inst_MDIO hps_io_emac1_inst_MDC hps_io_emac1_inst_RX_CTL hps_io_emac1_inst_TX_CTL hps_io_emac1_inst_RX_CLK hps_io_emac1_inst_RXD1 hps_io_emac1_inst_RXD2 hps_io_emac1_inst_RXD3 hps_io_sdio_inst_CMD hps_io_sdio_inst_D0 hps_io_sdio_inst_D1 hps_io_sdio_inst_CLK hps_io_sdio_inst_D2 hps_io_sdio_inst_D3 hps_io_usb1_inst_D0 hps_io_usb1_inst_D1 hps_io_usb1_inst_D2 hps_io_usb1_inst_D3 hps_io_usb1_inst_D4 hps_io_usb1_inst_D5 hps_io_usb1_inst_D6 hps_io_usb1_inst_D7 hps_io_usb1_inst_CLK hps_io_usb1_inst_STP hps_io_usb1_inst_DIR hps_io_usb1_inst_NXT hps_io_spim1_inst_CLK hps_io_spim1_inst_MOSI hps_io_spim1_inst_MISO hps_io_spim1_inst_SS0 hps_io_uart0_inst_RX hps_io_uart0_inst_TX hps_io_i2c0_inst_SDA hps_io_i2c0_inst_SCL hps_io_i2c1_inst_SDA hps_io_i2c1_inst_SCL hps_io_gpio_inst_GPIO09 hps_io_gpio_inst_GPIO35 hps_io_gpio_inst_GPIO40 hps_io_gpio_inst_GPIO48 hps_io_gpio_inst_GPIO53 hps_io_gpio_inst_GPIO54 hps_io_gpio_inst_GPIO61} hps_io_emac1_inst_TX_CLK {fragments emac1_inst:EMAC_CLK_TX(0:0) properties {} internal_name hps_io_emac1_inst_TX_CLK width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CLK} hps_io_emac1_inst_TXD0 {fragments emac1_inst:EMAC_PHY_TXD(0:0) properties {} internal_name hps_io_emac1_inst_TXD0 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD0} hps_io_emac1_inst_TXD1 {fragments emac1_inst:EMAC_PHY_TXD(1:1) properties {} internal_name hps_io_emac1_inst_TXD1 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD1} hps_io_emac1_inst_TXD2 {fragments emac1_inst:EMAC_PHY_TXD(2:2) properties {} internal_name hps_io_emac1_inst_TXD2 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD2} hps_io_emac1_inst_TXD3 {fragments emac1_inst:EMAC_PHY_TXD(3:3) properties {} internal_name hps_io_emac1_inst_TXD3 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD3} hps_io_emac1_inst_RXD0 {fragments emac1_inst:EMAC_PHY_RXD(0:0) properties {} internal_name hps_io_emac1_inst_RXD0 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD0} hps_io_emac1_inst_MDIO {fragments emac1_inst:EMAC_GMII_MDO_I(0:0) properties {} internal_name hps_io_emac1_inst_MDIO width 1 instance_name hps_io tristate_output {{intermediate 1} {intermediate 0}} direction bidir role hps_io_emac1_inst_MDIO} hps_io_emac1_inst_MDC {fragments emac1_inst:EMAC_GMII_MDC(0:0) properties {} internal_name hps_io_emac1_inst_MDC width 1 instance_name hps_io direction output role hps_io_emac1_inst_MDC} hps_io_emac1_inst_RX_CTL {fragments emac1_inst:EMAC_PHY_RXDV(0:0) properties {} internal_name hps_io_emac1_inst_RX_CTL width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CTL} hps_io_emac1_inst_TX_CTL {fragments emac1_inst:EMAC_PHY_TX_OE(0:0) properties {} internal_name hps_io_emac1_inst_TX_CTL width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CTL} hps_io_emac1_inst_RX_CLK {fragments emac1_inst:EMAC_CLK_RX(0:0) properties {} internal_name hps_io_emac1_inst_RX_CLK width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CLK} hps_io_emac1_inst_RXD1 {fragments emac1_inst:EMAC_PHY_RXD(1:1) properties {} internal_name hps_io_emac1_inst_RXD1 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD1} hps_io_emac1_inst_RXD2 {fragments emac1_inst:EMAC_PHY_RXD(2:2) properties {} internal_name hps_io_emac1_inst_RXD2 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD2} hps_io_emac1_inst_RXD3 {fragments emac1_inst:EMAC_PHY_RXD(3:3) properties {} internal_name hps_io_emac1_inst_RXD3 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD3} hps_io_sdio_inst_CMD {fragments sdio_inst:SDMMC_CMD_I(0:0) properties {} internal_name hps_io_sdio_inst_CMD width 1 instance_name hps_io tristate_output {{intermediate 3} {intermediate 2}} direction bidir role hps_io_sdio_inst_CMD} hps_io_sdio_inst_D0 {fragments sdio_inst:SDMMC_DATA_I(0:0) properties {} internal_name hps_io_sdio_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 5} {intermediate 4}} direction bidir role hps_io_sdio_inst_D0} hps_io_sdio_inst_D1 {fragments sdio_inst:SDMMC_DATA_I(1:1) properties {} internal_name hps_io_sdio_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 7} {intermediate 6}} direction bidir role hps_io_sdio_inst_D1} hps_io_sdio_inst_CLK {fragments sdio_inst:SDMMC_CCLK(0:0) properties {} internal_name hps_io_sdio_inst_CLK width 1 instance_name hps_io direction output role hps_io_sdio_inst_CLK} hps_io_sdio_inst_D2 {fragments sdio_inst:SDMMC_DATA_I(2:2) properties {} internal_name hps_io_sdio_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 9} {intermediate 8}} direction bidir role hps_io_sdio_inst_D2} hps_io_sdio_inst_D3 {fragments sdio_inst:SDMMC_DATA_I(3:3) properties {} internal_name hps_io_sdio_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 11} {intermediate 10}} direction bidir role hps_io_sdio_inst_D3} hps_io_usb1_inst_D0 {fragments usb1_inst:USB_ULPI_DATA_I(0:0) properties {} internal_name hps_io_usb1_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 13} {intermediate 12}} direction bidir role hps_io_usb1_inst_D0} hps_io_usb1_inst_D1 {fragments usb1_inst:USB_ULPI_DATA_I(1:1) properties {} internal_name hps_io_usb1_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 15} {intermediate 14}} direction bidir role hps_io_usb1_inst_D1} hps_io_usb1_inst_D2 {fragments usb1_inst:USB_ULPI_DATA_I(2:2) properties {} internal_name hps_io_usb1_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 17} {intermediate 16}} direction bidir role hps_io_usb1_inst_D2} hps_io_usb1_inst_D3 {fragments usb1_inst:USB_ULPI_DATA_I(3:3) properties {} internal_name hps_io_usb1_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 19} {intermediate 18}} direction bidir role hps_io_usb1_inst_D3} hps_io_usb1_inst_D4 {fragments usb1_inst:USB_ULPI_DATA_I(4:4) properties {} internal_name hps_io_usb1_inst_D4 width 1 instance_name hps_io tristate_output {{intermediate 21} {intermediate 20}} direction bidir role hps_io_usb1_inst_D4} hps_io_usb1_inst_D5 {fragments usb1_inst:USB_ULPI_DATA_I(5:5) properties {} internal_name hps_io_usb1_inst_D5 width 1 instance_name hps_io tristate_output {{intermediate 23} {intermediate 22}} direction bidir role hps_io_usb1_inst_D5} hps_io_usb1_inst_D6 {fragments usb1_inst:USB_ULPI_DATA_I(6:6) properties {} internal_name hps_io_usb1_inst_D6 width 1 instance_name hps_io tristate_output {{intermediate 25} {intermediate 24}} direction bidir role hps_io_usb1_inst_D6} hps_io_usb1_inst_D7 {fragments usb1_inst:USB_ULPI_DATA_I(7:7) properties {} internal_name hps_io_usb1_inst_D7 width 1 instance_name hps_io tristate_output {{intermediate 27} {intermediate 26}} direction bidir role hps_io_usb1_inst_D7} hps_io_usb1_inst_CLK {fragments usb1_inst:USB_ULPI_CLK(0:0) properties {} internal_name hps_io_usb1_inst_CLK width 1 instance_name hps_io direction input role hps_io_usb1_inst_CLK} hps_io_usb1_inst_STP {fragments usb1_inst:USB_ULPI_STP(0:0) properties {} internal_name hps_io_usb1_inst_STP width 1 instance_name hps_io direction output role hps_io_usb1_inst_STP} hps_io_usb1_inst_DIR {fragments usb1_inst:USB_ULPI_DIR(0:0) properties {} internal_name hps_io_usb1_inst_DIR width 1 instance_name hps_io direction input role hps_io_usb1_inst_DIR} hps_io_usb1_inst_NXT {fragments usb1_inst:USB_ULPI_NXT(0:0) properties {} internal_name hps_io_usb1_inst_NXT width 1 instance_name hps_io direction input role hps_io_usb1_inst_NXT} hps_io_spim1_inst_CLK {fragments spim1_inst:SPI_MASTER_SCLK(0:0) properties {} internal_name hps_io_spim1_inst_CLK width 1 instance_name hps_io direction output role hps_io_spim1_inst_CLK} hps_io_spim1_inst_MOSI {fragments {} properties {} internal_name hps_io_spim1_inst_MOSI width 1 instance_name hps_io tristate_output {{intermediate 29} {intermediate 28}} direction output role hps_io_spim1_inst_MOSI} hps_io_spim1_inst_MISO {fragments spim1_inst:SPI_MASTER_RXD(0:0) properties {} internal_name hps_io_spim1_inst_MISO width 1 instance_name hps_io direction input role hps_io_spim1_inst_MISO} hps_io_spim1_inst_SS0 {fragments spim1_inst:SPI_MASTER_SS_0_N(0:0) properties {} internal_name hps_io_spim1_inst_SS0 width 1 instance_name hps_io direction output role hps_io_spim1_inst_SS0} hps_io_uart0_inst_RX {fragments uart0_inst:UART_RXD(0:0) properties {} internal_name hps_io_uart0_inst_RX width 1 instance_name hps_io direction input role hps_io_uart0_inst_RX} hps_io_uart0_inst_TX {fragments uart0_inst:UART_TXD(0:0) properties {} internal_name hps_io_uart0_inst_TX width 1 instance_name hps_io direction output role hps_io_uart0_inst_TX} hps_io_i2c0_inst_SDA {fragments i2c0_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c0_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 30} {}} direction bidir role hps_io_i2c0_inst_SDA} hps_io_i2c0_inst_SCL {fragments i2c0_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c0_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 31} {}} direction bidir role hps_io_i2c0_inst_SCL} hps_io_i2c1_inst_SDA {fragments i2c1_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c1_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 32} {}} direction bidir role hps_io_i2c1_inst_SDA} hps_io_i2c1_inst_SCL {fragments i2c1_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c1_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 33} {}} direction bidir role hps_io_i2c1_inst_SCL} hps_io_gpio_inst_GPIO09 {fragments gpio_inst:GPIO0_PORTA_I(9:9) properties {} internal_name hps_io_gpio_inst_GPIO09 width 1 instance_name hps_io tristate_output {{intermediate 35} {intermediate 34}} direction bidir role hps_io_gpio_inst_GPIO09} hps_io_gpio_inst_GPIO35 {fragments gpio_inst:GPIO1_PORTA_I(6:6) properties {} internal_name hps_io_gpio_inst_GPIO35 width 1 instance_name hps_io tristate_output {{intermediate 37} {intermediate 36}} direction bidir role hps_io_gpio_inst_GPIO35} hps_io_gpio_inst_GPIO40 {fragments gpio_inst:GPIO1_PORTA_I(11:11) properties {} internal_name hps_io_gpio_inst_GPIO40 width 1 instance_name hps_io tristate_output {{intermediate 39} {intermediate 38}} direction bidir role hps_io_gpio_inst_GPIO40} hps_io_gpio_inst_GPIO48 {fragments gpio_inst:GPIO1_PORTA_I(19:19) properties {} internal_name hps_io_gpio_inst_GPIO48 width 1 instance_name hps_io tristate_output {{intermediate 41} {intermediate 40}} direction bidir role hps_io_gpio_inst_GPIO48} hps_io_gpio_inst_GPIO53 {fragments gpio_inst:GPIO1_PORTA_I(24:24) properties {} internal_name hps_io_gpio_inst_GPIO53 width 1 instance_name hps_io tristate_output {{intermediate 43} {intermediate 42}} direction bidir role hps_io_gpio_inst_GPIO53} hps_io_gpio_inst_GPIO54 {fragments gpio_inst:GPIO1_PORTA_I(25:25) properties {} internal_name hps_io_gpio_inst_GPIO54 width 1 instance_name hps_io tristate_output {{intermediate 45} {intermediate 44}} direction bidir role hps_io_gpio_inst_GPIO54} hps_io_gpio_inst_GPIO61 {fragments gpio_inst:GPIO2_PORTA_I(3:3) properties {} internal_name hps_io_gpio_inst_GPIO61 width 1 instance_name hps_io tristate_output {{intermediate 47} {intermediate 46}} direction bidir role hps_io_gpio_inst_GPIO61}}}} wires_to_fragments {{intermediate 9} {output sdio_inst:SDMMC_DATA_OE(2:2)} {intermediate 8} {output sdio_inst:SDMMC_DATA_O(2:2)} {intermediate 7} {output sdio_inst:SDMMC_DATA_OE(1:1)} {intermediate 6} {output sdio_inst:SDMMC_DATA_O(1:1)} {intermediate 5} {output sdio_inst:SDMMC_DATA_OE(0:0)} {intermediate 4} {output sdio_inst:SDMMC_DATA_O(0:0)} {intermediate 3} {output sdio_inst:SDMMC_CMD_OE(0:0)} {intermediate 2} {output sdio_inst:SDMMC_CMD_O(0:0)} {intermediate 1} {output emac1_inst:EMAC_GMII_MDO_OE(0:0)} {intermediate 0} {output emac1_inst:EMAC_GMII_MDO_O(0:0)} {intermediate 19} {output usb1_inst:USB_ULPI_DATA_OE(3:3)} {intermediate 18} {output usb1_inst:USB_ULPI_DATA_O(3:3)} {intermediate 17} {output usb1_inst:USB_ULPI_DATA_OE(2:2)} {intermediate 16} {output usb1_inst:USB_ULPI_DATA_O(2:2)} {intermediate 47} {output gpio_inst:GPIO2_PORTA_OE(3:3)} {intermediate 15} {output usb1_inst:USB_ULPI_DATA_OE(1:1)} {intermediate 46} {output gpio_inst:GPIO2_PORTA_O(3:3)} {intermediate 14} {output usb1_inst:USB_ULPI_DATA_O(1:1)} {intermediate 45} {output gpio_inst:GPIO1_PORTA_OE(25:25)} {intermediate 13} {output usb1_inst:USB_ULPI_DATA_OE(0:0)} {intermediate 44} {output gpio_inst:GPIO1_PORTA_O(25:25)} {intermediate 12} {output usb1_inst:USB_ULPI_DATA_O(0:0)} {intermediate 43} {output gpio_inst:GPIO1_PORTA_OE(24:24)} {intermediate 11} {output sdio_inst:SDMMC_DATA_OE(3:3)} {intermediate 42} {output gpio_inst:GPIO1_PORTA_O(24:24)} {intermediate 10} {output sdio_inst:SDMMC_DATA_O(3:3)} {intermediate 41} {output gpio_inst:GPIO1_PORTA_OE(19:19)} {intermediate 40} {output gpio_inst:GPIO1_PORTA_O(19:19)} {intermediate 39} {output gpio_inst:GPIO1_PORTA_OE(11:11)} {intermediate 38} {output gpio_inst:GPIO1_PORTA_O(11:11)} {intermediate 37} {output gpio_inst:GPIO1_PORTA_OE(6:6)} {intermediate 36} {output gpio_inst:GPIO1_PORTA_O(6:6)} {intermediate 35} {output gpio_inst:GPIO0_PORTA_OE(9:9)} {intermediate 34} {output gpio_inst:GPIO0_PORTA_O(9:9)} {intermediate 33} {output i2c1_inst:I2C_CLK_OE(0:0)} {intermediate 32} {output i2c1_inst:I2C_DATA_OE(0:0)} {intermediate 31} {output i2c0_inst:I2C_CLK_OE(0:0)} {intermediate 30} {output i2c0_inst:I2C_DATA_OE(0:0)} {intermediate 29} {output spim1_inst:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 28} {output spim1_inst:SPI_MASTER_TXD(0:0)} {intermediate 27} {output usb1_inst:USB_ULPI_DATA_OE(7:7)} {intermediate 26} {output usb1_inst:USB_ULPI_DATA_O(7:7)} {intermediate 25} {output usb1_inst:USB_ULPI_DATA_OE(6:6)} {intermediate 24} {output usb1_inst:USB_ULPI_DATA_O(6:6)} {intermediate 23} {output usb1_inst:USB_ULPI_DATA_OE(5:5)} {intermediate 22} {output usb1_inst:USB_ULPI_DATA_O(5:5)} {intermediate 21} {output usb1_inst:USB_ULPI_DATA_OE(4:4)} {intermediate 20} {output usb1_inst:USB_ULPI_DATA_O(4:4)}} raw_assign_sim_style {},qipEntries={set_instance_assignment -name hps_partition on -entity %entityName% -library %libraryName%}"
   instancePathKey="soc_system:.:hps_0:.:hps_io:.:border"
   kind="altera_interface_generator"
   version="21.1"
   name="soc_system_hps_0_hps_io_border">
  <parameter name="IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS" value="false" />
  <parameter name="VECT_ATTR_COUNTER_ZERO_MATCH" value="0" />
  <parameter name="ENUM_GANGED_ARF" value="DISABLED" />
  <parameter name="LRDIMM_INT" value="0" />
  <parameter name="ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
  <parameter name="MAX_LATENCY_COUNT_WIDTH" value="6" />
  <parameter name="MEM_IF_ADDR_WIDTH_MIN" value="10" />
  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
  <parameter name="MEM_DQS_TO_CLK_CAPTURE_DELAY" value="0" />
  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
  <parameter name="MEM_LEVELING" value="true" />
  <parameter name="CV_ENUM_PRIORITY_1_0" value="WEIGHT_0" />
  <parameter name="ENUM_MEM_IF_TRRD" value="TRRD_4" />
  <parameter name="CV_ENUM_PRIORITY_1_2" value="WEIGHT_0" />
  <parameter name="ENUM_ATTR_COUNTER_ZERO_RESET" value="DISABLED" />
  <parameter name="CV_ENUM_PRIORITY_1_1" value="WEIGHT_0" />
  <parameter name="PLL_AFI_HALF_CLK_DIV" value="0" />
  <parameter name="MEM_ADD_LAT" value="0" />
  <parameter name="CV_ENUM_PRIORITY_1_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_1_3" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR" value="0" />
  <parameter name="CV_ENUM_PRIORITY_1_5" value="WEIGHT_0" />
  <parameter name="ignoreSimulation" value="true" />
  <parameter name="INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT" value="0" />
  <parameter name="CTL_RD_TO_RD_EXTRA_CLK" value="0" />
  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
  <parameter name="ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
  <parameter name="INTG_MEM_IF_TRFC" value="34" />
  <parameter name="MEM_REGDIMM_ENABLED" value="false" />
  <parameter name="PLL_HR_CLK_FREQ" value="0.0" />
  <parameter name="AFI_DQ_WIDTH" value="0" />
  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
  <parameter name="AP_MODE_EN" value="0" />
  <parameter name="ENUM_CPORT5_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CALIB_LFIFO_OFFSET" value="-1" />
  <parameter name="INTG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="ENUM_CPORT2_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="VECT_ATTR_COUNTER_ZERO_MASK" value="0" />
  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ALLOCATED_WFIFO_PORT" value="0,None,None,None,None,None" />
  <parameter name="MEM_TRAS_NS" value="35.0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
  <parameter name="IO_DQ_OUT_RESERVE" value="0" />
  <parameter name="IO_DM_OUT_RESERVE" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="CV_ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
  <parameter name="INTG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="INTG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="DELAY_PER_OPA_TAP" value="-1" />
  <parameter name="INTG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="ENABLE_BONDING" value="false" />
  <parameter name="HHP_HPS_VERIFICATION" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_BC" value="0" />
  <parameter name="CV_ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP" value="0" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="CV_ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_ENABLE_INTR" value="DISABLED" />
  <parameter name="INTG_MEM_AUTO_PD_CYCLES" value="0" />
  <parameter name="AVL_DATA_WIDTH" value="0" />
  <parameter name="PLL_AFI_CLK_MULT_CACHE" value="0" />
  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
  <parameter name="MR1_RDQS" value="0" />
  <parameter name="ENUM_MEM_IF_ROWADDR_WIDTH" value="ADDR_WIDTH_16" />
  <parameter name="PLL_DR_CLK_DIV_CACHE" value="0" />
  <parameter name="MR0_PD" value="0" />
  <parameter name="MEM_VENDOR" value="JEDEC" />
  <parameter name="MEM_IF_CS_PER_RANK" value="0" />
  <parameter name="CV_PORT_1_CONNECT_TO_AV_PORT" value="1" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_DR_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="TRK_PARALLEL_SCC_LOAD" value="false" />
  <parameter name="CV_ENUM_CPORT1_TYPE" value="DISABLE" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_STR" value="" />
  <parameter name="ENABLE_LDC_MEM_CK_ADJUSTMENT" value="false" />
  <parameter name="USE_MEM_CLK_FREQ" value="false" />
  <parameter name="CV_MSB_WFIFO_PORT_5" value="5" />
  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
  <parameter name="CFG_READ_ODT_CHIP" value="0" />
  <parameter name="CV_MSB_WFIFO_PORT_4" value="5" />
  <parameter name="CV_MSB_WFIFO_PORT_3" value="5" />
  <parameter name="IO_DQS_EN_PHASE_MAX" value="0" />
  <parameter name="RDIMM" value="false" />
  <parameter name="ENUM_MEM_IF_COLADDR_WIDTH" value="ADDR_WIDTH_12" />
  <parameter name="PLL_CONFIG_CLK_FREQ" value="0.0" />
  <parameter name="ENABLE_USER_ECC" value="false" />
  <parameter name="PLL_PHASE_COUNTER_WIDTH" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ARF_PERIOD" value="0" />
  <parameter name="MEM_TRC" value="0" />
  <parameter name="AVL_ADDR_WIDTH_PORT_2" value="0" />
  <parameter name="ENUM_PRIORITY_6_4" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID" value="0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_3" value="USE_NO" />
  <parameter name="AVL_ADDR_WIDTH_PORT_1" value="0" />
  <parameter name="ENUM_PRIORITY_6_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_2" value="USE_NO" />
  <parameter name="AVL_ADDR_WIDTH_PORT_0" value="0" />
  <parameter name="ENUM_PRIORITY_6_2" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_5" value="USE_NO" />
  <parameter name="ENUM_PRIORITY_6_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_4" value="USE_NO" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_PRIORITY_6_0" value="WEIGHT_0" />
  <parameter name="MEM_CK_LDC_ADJUSTMENT_THRESHOLD" value="0" />
  <parameter name="AFI_CS_WIDTH" value="0" />
  <parameter name="AVL_ADDR_WIDTH_PORT_5" value="0" />
  <parameter name="ENUM_PRIORITY_6_1" value="WEIGHT_0" />
  <parameter name="AVL_ADDR_WIDTH_PORT_4" value="0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_1" value="USE_NO" />
  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
  <parameter name="AVL_ADDR_WIDTH_PORT_3" value="0" />
  <parameter name="CV_ENUM_RD_PORT_INFO_0" value="USE_NO" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="CV_MSB_WFIFO_PORT_2" value="5" />
  <parameter name="CV_MSB_WFIFO_PORT_1" value="5" />
  <parameter name="PLL_NIOS_CLK_MULT" value="0" />
  <parameter name="ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_MSB_WFIFO_PORT_0" value="5" />
  <parameter name="TG_TEMP_PORT_5" value="0" />
  <parameter name="PLL_P2C_READ_CLK_DIV" value="0" />
  <parameter name="TG_TEMP_PORT_3" value="0" />
  <parameter name="TG_TEMP_PORT_4" value="0" />
  <parameter name="TG_TEMP_PORT_1" value="0" />
  <parameter name="TG_TEMP_PORT_2" value="0" />
  <parameter name="MEM_CLK_NS" value="0.0" />
  <parameter name="TG_TEMP_PORT_0" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
  <parameter name="ENUM_MEM_IF_BURSTLENGTH" value="MEM_IF_BURSTLENGTH_8" />
  <parameter name="PLL_AFI_CLK_MULT" value="0" />
  <parameter name="SKIP_MEM_INIT" value="true" />
  <parameter name="CFG_ENABLE_NO_DM" value="0" />
  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
  <parameter name="MR1_TDQS" value="0" />
  <parameter name="INTG_MEM_CLK_ENTRY_CYCLES" value="10" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
  <parameter name="CTL_ECC_MULTIPLES_16_24_40_72" value="0" />
  <parameter name="CV_ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="ENUM_MEM_IF_TCWL" value="TCWL_5" />
  <parameter name="DEVICE_FAMILY" value="" />
  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
  <parameter name="DEVICE_FAMILY_PARAM" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID" value="0" />
  <parameter name="ENUM_MEM_IF_TRTP" value="TRTP_4" />
  <parameter name="PLL_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="INTG_POWER_SAVING_EXIT_CYCLES" value="5" />
  <parameter name="DELAY_PER_DQS_EN_DCHAIN_TAP" value="-1" />
  <parameter name="MEM_IF_ADDR_WIDTH" value="0" />
  <parameter name="PLL_DR_CLK_DIV" value="0" />
  <parameter name="USE_SEQUENCER_BFM" value="false" />
  <parameter name="DELAY_PER_DCHAIN_TAP" value="-1" />
  <parameter name="CSR_ADDR_WIDTH" value="8" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_VALID" value="0" />
  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
  <parameter name="CV_ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="CV_ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="RDIMM_INT" value="0" />
  <parameter name="CV_ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="CTL_CSR_READ_ONLY" value="1" />
  <parameter name="ENUM_MASK_DBE_INTR" value="DISABLED" />
  <parameter name="CV_ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="CV_ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="PLL_AFI_PHY_CLK_MULT_CACHE" value="0" />
  <parameter name="CV_ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="READ_VALID_FIFO_SIZE" value="16" />
  <parameter name="DLL_MASTER" value="false" />
  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="AC_ROM_MR0_MIRR" value="" />
  <parameter name="MEM_TWTR" value="4" />
  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
  <parameter name="ENUM_ENABLE_BURST_INTERRUPT" value="DISABLED" />
  <parameter name="CV_ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="WEIGHT_PORT_2" value="0" />
  <parameter name="WEIGHT_PORT_1" value="0" />
  <parameter name="WEIGHT_PORT_0" value="0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE" value="Unknown" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="WEIGHT_PORT_5" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR" value="" />
  <parameter name="WEIGHT_PORT_4" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT" value="0" />
  <parameter name="WEIGHT_PORT_3" value="0" />
  <parameter name="ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_2" value="DISABLED" />
  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
  <parameter name="CV_ENUM_ENABLE_BONDING_3" value="DISABLED" />
  <parameter name="MEM_TRFC_NS" value="260.0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_4" value="DISABLED" />
  <parameter name="CV_ENUM_ENABLE_BONDING_5" value="DISABLED" />
  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="ENABLE_ISS_PROBES" value="false" />
  <parameter name="MR2_RTT_WR" value="1" />
  <parameter name="ENUM_MEM_IF_TFAW" value="TFAW_16" />
  <parameter name="TIMING_BOARD_TDS_APPLIED" value="0.0" />
  <parameter name="AFI_ODT_WIDTH" value="0" />
  <parameter name="PLL_MASTER" value="false" />
  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_0" value="DISABLED" />
  <parameter name="PLL_P2C_READ_CLK_FREQ" value="0.0" />
  <parameter name="CV_ENUM_ENABLE_BONDING_1" value="DISABLED" />
  <parameter name="ENUM_WFIFO0_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="DISCRETE_FLY_BY" value="true" />
  <parameter name="QVLD_WR_ADDRESS_OFFSET" value="0" />
  <parameter name="TB_MEM_IF_READ_DQS_WIDTH" value="0" />
  <parameter name="AVL_SYMBOL_WIDTH" value="8" />
  <parameter name="TB_PLL_DLL_MASTER" value="true" />
  <parameter name="MEM_IF_DM_WIDTH" value="0" />
  <parameter name="LOCAL_CS_WIDTH" value="0" />
  <parameter name="CTL_ECC_ENABLED" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="AUTO_POWERDN_EN" value="false" />
  <parameter name="ENUM_WFIFO3_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_HR_CLK_DIV_CACHE" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS" value="0" />
  <parameter name="PHY_CLKBUF" value="false" />
  <parameter name="ENABLE_ABS_RAM_INTERNAL" value="false" />
  <parameter name="MAX_PENDING_WR_CMD" value="16" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_ATTR_COUNTER_ONE_RESET" value="DISABLED" />
  <parameter name="ENUM_WRITE_ODT_CHIP" value="ODT_DISABLED" />
  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
  <parameter name="MEM_IF_CHIP_BITS" value="-1" />
  <parameter name="ENUM_MEM_IF_CS_PER_RANK" value="MEM_IF_CS_PER_RANK_1" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MEM_IF_CK_WIDTH" value="0" />
  <parameter name="MEM_TCL" value="11" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT_CACHE" value="0" />
  <parameter name="ENUM_LOCAL_IF_CS_WIDTH" value="ADDR_WIDTH_2" />
  <parameter name="TIMING_TDQSCK" value="255" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="CTL_USR_REFRESH_EN" value="false" />
  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
  <parameter name="ENUM_WR_FIFO_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_WR_FIFO_IN_USE_2" value="FALSE" />
  <parameter name="CFG_PORT_WIDTH_READ_ODT_CHIP" value="0" />
  <parameter name="ENUM_WR_FIFO_IN_USE_1" value="FALSE" />
  <parameter name="PLL_WRITE_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_WR_FIFO_IN_USE_0" value="FALSE" />
  <parameter name="ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="AFI_RATE_RATIO" value="0" />
  <parameter name="ENUM_THLD_JAR2_3" value="THRESHOLD_16" />
  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
  <parameter name="ENUM_THLD_JAR2_4" value="THRESHOLD_16" />
  <parameter name="ENUM_THLD_JAR2_5" value="THRESHOLD_16" />
  <parameter name="AV_PORT_0_CONNECT_TO_CV_PORT" value="0" />
  <parameter name="PLL_MEM_CLK_DIV_CACHE" value="0" />
  <parameter name="ENUM_CTL_ECC_RMW_ENABLED" value="CTL_ECC_RMW_DISABLED" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV_CACHE" value="0" />
  <parameter name="CFG_TCCD_NS" value="2.5" />
  <parameter name="IO_DQS_IN_RESERVE" value="3" />
  <parameter name="AVL_NUM_SYMBOLS" value="2" />
  <parameter name="ENABLE_NIOS_OCI" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="FIX_READ_LATENCY" value="8" />
  <parameter name="CTL_OUTPUT_REGD" value="false" />
  <parameter name="CV_PORT_0_CONNECT_TO_AV_PORT" value="0" />
  <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" />
  <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" />
  <parameter name="PLL_CONFIG_CLK_PHASE_DEG" value="0.0" />
  <parameter name="CTL_CSR_ENABLED" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_PCH" value="0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PHY_CSR_ENABLED" value="false" />
  <parameter name="DQ_DDR" value="0" />
  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_WRITE_CLK_PHASE_DEG" value="0.0" />
  <parameter name="MEM_INIT_FILE" value="" />
  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
  <parameter name="AVL_PORT" value="" />
  <parameter name="TB_RATE" value="" />
  <parameter name="REF_CLK_FREQ_CACHE_VALID" value="false" />
  <parameter name="ALLOCATED_RFIFO_PORT" value="0,None,None,None,None,None" />
  <parameter name="MEM_CK_WIDTH" value="1" />
  <parameter name="MEM_ATCL" value="Disabled" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="AC_ROM_MR0_DLL_RESET" value="" />
  <parameter name="MEM_TDQSCK" value="2" />
  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
  <parameter name="PLL_HR_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD" value="0" />
  <parameter name="MEM_WTCL" value="8" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP" value="0" />
  <parameter name="CV_ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_MEM_CLK_MULT" value="0" />
  <parameter name="USE_MEM_CLK_FREQ_CACHE" value="false" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="MEM_IF_CS_PER_DIMM" value="0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY" value="" />
  <parameter name="CTL_ECC_CSR_ENABLED" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP" value="0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED" value="0.0" />
  <parameter name="MEM_AUTO_PD_CYCLES" value="0" />
  <parameter name="CV_ENUM_CPORT3_TYPE" value="DISABLE" />
  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
  <parameter name="PLL_WRITE_CLK_DIV" value="0" />
  <parameter name="CALIB_VFIFO_OFFSET" value="-1" />
  <parameter name="CTL_ECC_MULTIPLES_40_72" value="0" />
  <parameter name="MSB_RFIFO_PORT_2" value="5" />
  <parameter name="MSB_RFIFO_PORT_3" value="5" />
  <parameter name="MSB_RFIFO_PORT_4" value="5" />
  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
  <parameter name="MSB_RFIFO_PORT_5" value="5" />
  <parameter name="CV_ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
  <parameter name="MEM_DRV_STR" value="RZQ/7" />
  <parameter name="MEM_TREFI" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="NUM_SUBGROUP_PER_READ_DQS" value="0" />
  <parameter name="TIMING_BOARD_AC_SKEW" value="0.03" />
  <parameter name="MSB_RFIFO_PORT_0" value="5" />
  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="MEM_TRP_NS" value="13.75" />
  <parameter name="MSB_RFIFO_PORT_1" value="5" />
  <parameter name="QVLD_EXTRA_FLOP_STAGES" value="0" />
  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="CTL_HRB_ENABLED" value="false" />
  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
  <parameter name="PLL_WRITE_CLK_FREQ" value="0.0" />
  <parameter name="EXTRA_SETTINGS" value="" />
  <parameter name="ENUM_MMR_CFG_MEM_BL" value="MP_BL_8" />
  <parameter name="PLL_DR_CLK_FREQ_STR" value="" />
  <parameter name="MEM_IF_CS_WIDTH" value="0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_1" value="USE_NO" />
  <parameter name="STARVE_LIMIT" value="10" />
  <parameter name="PLL_NIOS_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_2" value="USE_NO" />
  <parameter name="CV_ENUM_WR_PORT_INFO_3" value="USE_NO" />
  <parameter name="CFG_PORT_WIDTH_WRITE_ODT_CHIP" value="0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_4" value="USE_NO" />
  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_0" value="USE_NO" />
  <parameter name="DUPLICATE_PLL_FOR_PHY_CLK" value="false" />
  <parameter name="SEQUENCER_TYPE_CACHE" value="Unknown" />
  <parameter name="CTL_USR_REFRESH" value="0" />
  <parameter name="AV_PORT_2_CONNECT_TO_CV_PORT" value="2" />
  <parameter name="PLL_MEM_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="CV_ENUM_WR_PORT_INFO_5" value="USE_NO" />
  <parameter name="CORE_PERIPHERY_DUAL_CLOCK" value="false" />
  <parameter name="MR0_BT" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_DEG" value="0.0" />
  <parameter name="INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL" value="0" />
  <parameter name="MR1_AL" value="0" />
  <parameter name="DQS_PHASE_SHIFT" value="9000" />
  <parameter name="MR0_BL" value="2" />
  <parameter name="DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG" value="false" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.09" />
  <parameter name="MEM_TRCD" value="0" />
  <parameter name="MEM_IF_WR_TO_RD_TURNAROUND_OCT" value="3" />
  <parameter name="MAX_PENDING_RD_CMD" value="32" />
  <parameter name="PLL_NIOS_CLK_MULT_CACHE" value="0" />
  <parameter name="REGISTER_C2P" value="false" />
  <parameter name="MEM_WTCL_INT" value="6" />
  <parameter name="MEM_IF_ROW_ADDR_WIDTH" value="0" />
  <parameter name="DQS_EN_DELAY_MAX" value="-1" />
  <parameter name="ENUM_CPORT1_TYPE" value="DISABLE" />
  <parameter name="ENABLE_NIOS_PRINTF_OUTPUT" value="false" />
  <parameter name="MR1_BL" value="2" />
  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
  <parameter name="MR1_BT" value="0" />
  <parameter name="REF_CLK_FREQ" value="25.0" />
  <parameter name="AV_PORT_5_CONNECT_TO_CV_PORT" value="5" />
  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE" value="0" />
  <parameter name="PLL_NIOS_CLK_DIV" value="0" />
  <parameter name="MR0_DLL" value="1" />
  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
  <parameter name="PINGPONGPHY_EN" value="false" />
  <parameter name="CFG_WRITE_ODT_CHIP" value="0" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_5" value="2" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR" value="" />
  <parameter name="MR2_ASR" value="0" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_3" value="2" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_4" value="2" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_1" value="2" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_2" value="2" />
  <parameter name="MR2_CWL" value="1" />
  <parameter name="CV_AVL_NUM_SYMBOLS_PORT_0" value="2" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV" value="0" />
  <parameter name="HPS_PROTOCOL" value="DDR3" />
  <parameter name="MEM_IF_LRDIMM_RM" value="0" />
  <parameter name="VECT_ATTR_COUNTER_ONE_MATCH" value="0" />
  <parameter name="ENUM_PRIORITY_1_5" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_1" value="WEIGHT_0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ENUM_PRIORITY_1_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_1_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_RFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="DUPLICATE_AC" value="false" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_5" value="2" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_1" value="2" />
  <parameter name="DUAL_WRITE_CLOCK" value="false" />
  <parameter
     name="interfaceDefinition"
     value="instances {sdio_inst {entity_name cyclonev_hps_peripheral_sdmmc location HPSPERIPHERALSDMMC_X87_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} emac1_inst {entity_name cyclonev_hps_peripheral_emac location HPSPERIPHERALEMAC_X77_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c1_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y65_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} spim1_inst {entity_name cyclonev_hps_peripheral_spi_master location HPSPERIPHERALSPIMASTER_X87_Y53_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} uart0_inst {entity_name cyclonev_hps_peripheral_uart location HPSPERIPHERALUART_X87_Y45_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} @orderednames {emac1_inst sdio_inst usb1_inst spim1_inst uart0_inst i2c0_inst i2c1_inst gpio_inst hps_sdram_inst} usb1_inst {entity_name cyclonev_hps_peripheral_usb location HPSPERIPHERALUSB_X55_Y39_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} gpio_inst {entity_name cyclonev_hps_peripheral_gpio location HPSPERIPHERALGPIO_X87_Y74_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} hps_sdram_inst {entity_name hps_sdram location {} signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}} i2c0_inst {entity_name cyclonev_hps_peripheral_i2c location HPSPERIPHERALI2C_X87_Y67_N111 signal_widths {} signal_terminations {} parameters {} signal_default_terminations {}}} raw_assigns {} wire_sim_style {} interface_sim_style {} constraints {{set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD0]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD1]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD2]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TXD3]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD0] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_MDIO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDIO]} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_MDC]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CTL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CTL]} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RX_CLK] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD1] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD2] -to *} {set_false_path -from [get_ports hps_io_hps_io_emac1_inst_RXD3] -to *} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_CMD] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CMD]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D1]} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_CLK]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_sdio_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_sdio_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D0] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D0]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D1] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D1]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D2] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D2]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D3] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D3]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D4] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D4]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D5] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D5]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D6] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D6]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_D7] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_D7]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_CLK] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_usb1_inst_STP]} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_DIR] -to *} {set_false_path -from [get_ports hps_io_hps_io_usb1_inst_NXT] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_CLK]} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_MOSI]} {set_false_path -from [get_ports hps_io_hps_io_spim1_inst_MISO] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_spim1_inst_SS0]} {set_false_path -from [get_ports hps_io_hps_io_uart0_inst_RX] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_uart0_inst_TX]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c0_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c0_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SDA] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SDA]} {set_false_path -from [get_ports hps_io_hps_io_i2c1_inst_SCL] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_i2c1_inst_SCL]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO09] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO09]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO35] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO35]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO40] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO40]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO48] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO48]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO53] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO53]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO54] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO54]} {set_false_path -from [get_ports hps_io_hps_io_gpio_inst_GPIO61] -to *} {set_false_path -from * -to [get_ports hps_io_hps_io_gpio_inst_GPIO61]}} properties {SUPPRESS_SDRAM_SYNTH 0 GENERATE_ISW 1} bfm_types {} intermediate_wire_count 48 interfaces {@orderednames {memory hps_io} memory {properties {} type conduit direction end signals {@orderednames {mem_a mem_ba mem_ck mem_ck_n mem_cke mem_cs_n mem_ras_n mem_cas_n mem_we_n mem_reset_n mem_dq mem_dqs mem_dqs_n mem_odt mem_dm oct_rzqin} mem_a {fragments {} properties {} internal_name mem_a width 15 instance_name hps_sdram_inst direction Output role mem_a} mem_ba {fragments {} properties {} internal_name mem_ba width 3 instance_name hps_sdram_inst direction Output role mem_ba} mem_ck {fragments {} properties {} internal_name mem_ck width 1 instance_name hps_sdram_inst direction Output role mem_ck} mem_ck_n {fragments {} properties {} internal_name mem_ck_n width 1 instance_name hps_sdram_inst direction Output role mem_ck_n} mem_cke {fragments {} properties {} internal_name mem_cke width 1 instance_name hps_sdram_inst direction Output role mem_cke} mem_cs_n {fragments {} properties {} internal_name mem_cs_n width 1 instance_name hps_sdram_inst direction Output role mem_cs_n} mem_ras_n {fragments {} properties {} internal_name mem_ras_n width 1 instance_name hps_sdram_inst direction Output role mem_ras_n} mem_cas_n {fragments {} properties {} internal_name mem_cas_n width 1 instance_name hps_sdram_inst direction Output role mem_cas_n} mem_we_n {fragments {} properties {} internal_name mem_we_n width 1 instance_name hps_sdram_inst direction Output role mem_we_n} mem_reset_n {fragments {} properties {} internal_name mem_reset_n width 1 instance_name hps_sdram_inst direction Output role mem_reset_n} mem_dq {fragments {} properties {} internal_name mem_dq width 32 instance_name hps_sdram_inst direction Bidir role mem_dq} mem_dqs {fragments {} properties {} internal_name mem_dqs width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs} mem_dqs_n {fragments {} properties {} internal_name mem_dqs_n width 4 instance_name hps_sdram_inst direction Bidir role mem_dqs_n} mem_odt {fragments {} properties {} internal_name mem_odt width 1 instance_name hps_sdram_inst direction Output role mem_odt} mem_dm {fragments {} properties {} internal_name mem_dm width 4 instance_name hps_sdram_inst direction Output role mem_dm} oct_rzqin {fragments {} properties {} internal_name oct_rzqin width 1 instance_name hps_sdram_inst direction Input role oct_rzqin}}} hps_io {properties {} type conduit direction input signals {@orderednames {hps_io_emac1_inst_TX_CLK hps_io_emac1_inst_TXD0 hps_io_emac1_inst_TXD1 hps_io_emac1_inst_TXD2 hps_io_emac1_inst_TXD3 hps_io_emac1_inst_RXD0 hps_io_emac1_inst_MDIO hps_io_emac1_inst_MDC hps_io_emac1_inst_RX_CTL hps_io_emac1_inst_TX_CTL hps_io_emac1_inst_RX_CLK hps_io_emac1_inst_RXD1 hps_io_emac1_inst_RXD2 hps_io_emac1_inst_RXD3 hps_io_sdio_inst_CMD hps_io_sdio_inst_D0 hps_io_sdio_inst_D1 hps_io_sdio_inst_CLK hps_io_sdio_inst_D2 hps_io_sdio_inst_D3 hps_io_usb1_inst_D0 hps_io_usb1_inst_D1 hps_io_usb1_inst_D2 hps_io_usb1_inst_D3 hps_io_usb1_inst_D4 hps_io_usb1_inst_D5 hps_io_usb1_inst_D6 hps_io_usb1_inst_D7 hps_io_usb1_inst_CLK hps_io_usb1_inst_STP hps_io_usb1_inst_DIR hps_io_usb1_inst_NXT hps_io_spim1_inst_CLK hps_io_spim1_inst_MOSI hps_io_spim1_inst_MISO hps_io_spim1_inst_SS0 hps_io_uart0_inst_RX hps_io_uart0_inst_TX hps_io_i2c0_inst_SDA hps_io_i2c0_inst_SCL hps_io_i2c1_inst_SDA hps_io_i2c1_inst_SCL hps_io_gpio_inst_GPIO09 hps_io_gpio_inst_GPIO35 hps_io_gpio_inst_GPIO40 hps_io_gpio_inst_GPIO48 hps_io_gpio_inst_GPIO53 hps_io_gpio_inst_GPIO54 hps_io_gpio_inst_GPIO61} hps_io_emac1_inst_TX_CLK {fragments emac1_inst:EMAC_CLK_TX(0:0) properties {} internal_name hps_io_emac1_inst_TX_CLK width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CLK} hps_io_emac1_inst_TXD0 {fragments emac1_inst:EMAC_PHY_TXD(0:0) properties {} internal_name hps_io_emac1_inst_TXD0 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD0} hps_io_emac1_inst_TXD1 {fragments emac1_inst:EMAC_PHY_TXD(1:1) properties {} internal_name hps_io_emac1_inst_TXD1 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD1} hps_io_emac1_inst_TXD2 {fragments emac1_inst:EMAC_PHY_TXD(2:2) properties {} internal_name hps_io_emac1_inst_TXD2 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD2} hps_io_emac1_inst_TXD3 {fragments emac1_inst:EMAC_PHY_TXD(3:3) properties {} internal_name hps_io_emac1_inst_TXD3 width 1 instance_name hps_io direction output role hps_io_emac1_inst_TXD3} hps_io_emac1_inst_RXD0 {fragments emac1_inst:EMAC_PHY_RXD(0:0) properties {} internal_name hps_io_emac1_inst_RXD0 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD0} hps_io_emac1_inst_MDIO {fragments emac1_inst:EMAC_GMII_MDO_I(0:0) properties {} internal_name hps_io_emac1_inst_MDIO width 1 instance_name hps_io tristate_output {{intermediate 1} {intermediate 0}} direction bidir role hps_io_emac1_inst_MDIO} hps_io_emac1_inst_MDC {fragments emac1_inst:EMAC_GMII_MDC(0:0) properties {} internal_name hps_io_emac1_inst_MDC width 1 instance_name hps_io direction output role hps_io_emac1_inst_MDC} hps_io_emac1_inst_RX_CTL {fragments emac1_inst:EMAC_PHY_RXDV(0:0) properties {} internal_name hps_io_emac1_inst_RX_CTL width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CTL} hps_io_emac1_inst_TX_CTL {fragments emac1_inst:EMAC_PHY_TX_OE(0:0) properties {} internal_name hps_io_emac1_inst_TX_CTL width 1 instance_name hps_io direction output role hps_io_emac1_inst_TX_CTL} hps_io_emac1_inst_RX_CLK {fragments emac1_inst:EMAC_CLK_RX(0:0) properties {} internal_name hps_io_emac1_inst_RX_CLK width 1 instance_name hps_io direction input role hps_io_emac1_inst_RX_CLK} hps_io_emac1_inst_RXD1 {fragments emac1_inst:EMAC_PHY_RXD(1:1) properties {} internal_name hps_io_emac1_inst_RXD1 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD1} hps_io_emac1_inst_RXD2 {fragments emac1_inst:EMAC_PHY_RXD(2:2) properties {} internal_name hps_io_emac1_inst_RXD2 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD2} hps_io_emac1_inst_RXD3 {fragments emac1_inst:EMAC_PHY_RXD(3:3) properties {} internal_name hps_io_emac1_inst_RXD3 width 1 instance_name hps_io direction input role hps_io_emac1_inst_RXD3} hps_io_sdio_inst_CMD {fragments sdio_inst:SDMMC_CMD_I(0:0) properties {} internal_name hps_io_sdio_inst_CMD width 1 instance_name hps_io tristate_output {{intermediate 3} {intermediate 2}} direction bidir role hps_io_sdio_inst_CMD} hps_io_sdio_inst_D0 {fragments sdio_inst:SDMMC_DATA_I(0:0) properties {} internal_name hps_io_sdio_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 5} {intermediate 4}} direction bidir role hps_io_sdio_inst_D0} hps_io_sdio_inst_D1 {fragments sdio_inst:SDMMC_DATA_I(1:1) properties {} internal_name hps_io_sdio_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 7} {intermediate 6}} direction bidir role hps_io_sdio_inst_D1} hps_io_sdio_inst_CLK {fragments sdio_inst:SDMMC_CCLK(0:0) properties {} internal_name hps_io_sdio_inst_CLK width 1 instance_name hps_io direction output role hps_io_sdio_inst_CLK} hps_io_sdio_inst_D2 {fragments sdio_inst:SDMMC_DATA_I(2:2) properties {} internal_name hps_io_sdio_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 9} {intermediate 8}} direction bidir role hps_io_sdio_inst_D2} hps_io_sdio_inst_D3 {fragments sdio_inst:SDMMC_DATA_I(3:3) properties {} internal_name hps_io_sdio_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 11} {intermediate 10}} direction bidir role hps_io_sdio_inst_D3} hps_io_usb1_inst_D0 {fragments usb1_inst:USB_ULPI_DATA_I(0:0) properties {} internal_name hps_io_usb1_inst_D0 width 1 instance_name hps_io tristate_output {{intermediate 13} {intermediate 12}} direction bidir role hps_io_usb1_inst_D0} hps_io_usb1_inst_D1 {fragments usb1_inst:USB_ULPI_DATA_I(1:1) properties {} internal_name hps_io_usb1_inst_D1 width 1 instance_name hps_io tristate_output {{intermediate 15} {intermediate 14}} direction bidir role hps_io_usb1_inst_D1} hps_io_usb1_inst_D2 {fragments usb1_inst:USB_ULPI_DATA_I(2:2) properties {} internal_name hps_io_usb1_inst_D2 width 1 instance_name hps_io tristate_output {{intermediate 17} {intermediate 16}} direction bidir role hps_io_usb1_inst_D2} hps_io_usb1_inst_D3 {fragments usb1_inst:USB_ULPI_DATA_I(3:3) properties {} internal_name hps_io_usb1_inst_D3 width 1 instance_name hps_io tristate_output {{intermediate 19} {intermediate 18}} direction bidir role hps_io_usb1_inst_D3} hps_io_usb1_inst_D4 {fragments usb1_inst:USB_ULPI_DATA_I(4:4) properties {} internal_name hps_io_usb1_inst_D4 width 1 instance_name hps_io tristate_output {{intermediate 21} {intermediate 20}} direction bidir role hps_io_usb1_inst_D4} hps_io_usb1_inst_D5 {fragments usb1_inst:USB_ULPI_DATA_I(5:5) properties {} internal_name hps_io_usb1_inst_D5 width 1 instance_name hps_io tristate_output {{intermediate 23} {intermediate 22}} direction bidir role hps_io_usb1_inst_D5} hps_io_usb1_inst_D6 {fragments usb1_inst:USB_ULPI_DATA_I(6:6) properties {} internal_name hps_io_usb1_inst_D6 width 1 instance_name hps_io tristate_output {{intermediate 25} {intermediate 24}} direction bidir role hps_io_usb1_inst_D6} hps_io_usb1_inst_D7 {fragments usb1_inst:USB_ULPI_DATA_I(7:7) properties {} internal_name hps_io_usb1_inst_D7 width 1 instance_name hps_io tristate_output {{intermediate 27} {intermediate 26}} direction bidir role hps_io_usb1_inst_D7} hps_io_usb1_inst_CLK {fragments usb1_inst:USB_ULPI_CLK(0:0) properties {} internal_name hps_io_usb1_inst_CLK width 1 instance_name hps_io direction input role hps_io_usb1_inst_CLK} hps_io_usb1_inst_STP {fragments usb1_inst:USB_ULPI_STP(0:0) properties {} internal_name hps_io_usb1_inst_STP width 1 instance_name hps_io direction output role hps_io_usb1_inst_STP} hps_io_usb1_inst_DIR {fragments usb1_inst:USB_ULPI_DIR(0:0) properties {} internal_name hps_io_usb1_inst_DIR width 1 instance_name hps_io direction input role hps_io_usb1_inst_DIR} hps_io_usb1_inst_NXT {fragments usb1_inst:USB_ULPI_NXT(0:0) properties {} internal_name hps_io_usb1_inst_NXT width 1 instance_name hps_io direction input role hps_io_usb1_inst_NXT} hps_io_spim1_inst_CLK {fragments spim1_inst:SPI_MASTER_SCLK(0:0) properties {} internal_name hps_io_spim1_inst_CLK width 1 instance_name hps_io direction output role hps_io_spim1_inst_CLK} hps_io_spim1_inst_MOSI {fragments {} properties {} internal_name hps_io_spim1_inst_MOSI width 1 instance_name hps_io tristate_output {{intermediate 29} {intermediate 28}} direction output role hps_io_spim1_inst_MOSI} hps_io_spim1_inst_MISO {fragments spim1_inst:SPI_MASTER_RXD(0:0) properties {} internal_name hps_io_spim1_inst_MISO width 1 instance_name hps_io direction input role hps_io_spim1_inst_MISO} hps_io_spim1_inst_SS0 {fragments spim1_inst:SPI_MASTER_SS_0_N(0:0) properties {} internal_name hps_io_spim1_inst_SS0 width 1 instance_name hps_io direction output role hps_io_spim1_inst_SS0} hps_io_uart0_inst_RX {fragments uart0_inst:UART_RXD(0:0) properties {} internal_name hps_io_uart0_inst_RX width 1 instance_name hps_io direction input role hps_io_uart0_inst_RX} hps_io_uart0_inst_TX {fragments uart0_inst:UART_TXD(0:0) properties {} internal_name hps_io_uart0_inst_TX width 1 instance_name hps_io direction output role hps_io_uart0_inst_TX} hps_io_i2c0_inst_SDA {fragments i2c0_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c0_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 30} {}} direction bidir role hps_io_i2c0_inst_SDA} hps_io_i2c0_inst_SCL {fragments i2c0_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c0_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 31} {}} direction bidir role hps_io_i2c0_inst_SCL} hps_io_i2c1_inst_SDA {fragments i2c1_inst:I2C_DATA(0:0) properties {} internal_name hps_io_i2c1_inst_SDA width 1 instance_name hps_io tristate_output {{intermediate 32} {}} direction bidir role hps_io_i2c1_inst_SDA} hps_io_i2c1_inst_SCL {fragments i2c1_inst:I2C_CLK(0:0) properties {} internal_name hps_io_i2c1_inst_SCL width 1 instance_name hps_io tristate_output {{intermediate 33} {}} direction bidir role hps_io_i2c1_inst_SCL} hps_io_gpio_inst_GPIO09 {fragments gpio_inst:GPIO0_PORTA_I(9:9) properties {} internal_name hps_io_gpio_inst_GPIO09 width 1 instance_name hps_io tristate_output {{intermediate 35} {intermediate 34}} direction bidir role hps_io_gpio_inst_GPIO09} hps_io_gpio_inst_GPIO35 {fragments gpio_inst:GPIO1_PORTA_I(6:6) properties {} internal_name hps_io_gpio_inst_GPIO35 width 1 instance_name hps_io tristate_output {{intermediate 37} {intermediate 36}} direction bidir role hps_io_gpio_inst_GPIO35} hps_io_gpio_inst_GPIO40 {fragments gpio_inst:GPIO1_PORTA_I(11:11) properties {} internal_name hps_io_gpio_inst_GPIO40 width 1 instance_name hps_io tristate_output {{intermediate 39} {intermediate 38}} direction bidir role hps_io_gpio_inst_GPIO40} hps_io_gpio_inst_GPIO48 {fragments gpio_inst:GPIO1_PORTA_I(19:19) properties {} internal_name hps_io_gpio_inst_GPIO48 width 1 instance_name hps_io tristate_output {{intermediate 41} {intermediate 40}} direction bidir role hps_io_gpio_inst_GPIO48} hps_io_gpio_inst_GPIO53 {fragments gpio_inst:GPIO1_PORTA_I(24:24) properties {} internal_name hps_io_gpio_inst_GPIO53 width 1 instance_name hps_io tristate_output {{intermediate 43} {intermediate 42}} direction bidir role hps_io_gpio_inst_GPIO53} hps_io_gpio_inst_GPIO54 {fragments gpio_inst:GPIO1_PORTA_I(25:25) properties {} internal_name hps_io_gpio_inst_GPIO54 width 1 instance_name hps_io tristate_output {{intermediate 45} {intermediate 44}} direction bidir role hps_io_gpio_inst_GPIO54} hps_io_gpio_inst_GPIO61 {fragments gpio_inst:GPIO2_PORTA_I(3:3) properties {} internal_name hps_io_gpio_inst_GPIO61 width 1 instance_name hps_io tristate_output {{intermediate 47} {intermediate 46}} direction bidir role hps_io_gpio_inst_GPIO61}}}} wires_to_fragments {{intermediate 9} {output sdio_inst:SDMMC_DATA_OE(2:2)} {intermediate 8} {output sdio_inst:SDMMC_DATA_O(2:2)} {intermediate 7} {output sdio_inst:SDMMC_DATA_OE(1:1)} {intermediate 6} {output sdio_inst:SDMMC_DATA_O(1:1)} {intermediate 5} {output sdio_inst:SDMMC_DATA_OE(0:0)} {intermediate 4} {output sdio_inst:SDMMC_DATA_O(0:0)} {intermediate 3} {output sdio_inst:SDMMC_CMD_OE(0:0)} {intermediate 2} {output sdio_inst:SDMMC_CMD_O(0:0)} {intermediate 1} {output emac1_inst:EMAC_GMII_MDO_OE(0:0)} {intermediate 0} {output emac1_inst:EMAC_GMII_MDO_O(0:0)} {intermediate 19} {output usb1_inst:USB_ULPI_DATA_OE(3:3)} {intermediate 18} {output usb1_inst:USB_ULPI_DATA_O(3:3)} {intermediate 17} {output usb1_inst:USB_ULPI_DATA_OE(2:2)} {intermediate 16} {output usb1_inst:USB_ULPI_DATA_O(2:2)} {intermediate 47} {output gpio_inst:GPIO2_PORTA_OE(3:3)} {intermediate 15} {output usb1_inst:USB_ULPI_DATA_OE(1:1)} {intermediate 46} {output gpio_inst:GPIO2_PORTA_O(3:3)} {intermediate 14} {output usb1_inst:USB_ULPI_DATA_O(1:1)} {intermediate 45} {output gpio_inst:GPIO1_PORTA_OE(25:25)} {intermediate 13} {output usb1_inst:USB_ULPI_DATA_OE(0:0)} {intermediate 44} {output gpio_inst:GPIO1_PORTA_O(25:25)} {intermediate 12} {output usb1_inst:USB_ULPI_DATA_O(0:0)} {intermediate 43} {output gpio_inst:GPIO1_PORTA_OE(24:24)} {intermediate 11} {output sdio_inst:SDMMC_DATA_OE(3:3)} {intermediate 42} {output gpio_inst:GPIO1_PORTA_O(24:24)} {intermediate 10} {output sdio_inst:SDMMC_DATA_O(3:3)} {intermediate 41} {output gpio_inst:GPIO1_PORTA_OE(19:19)} {intermediate 40} {output gpio_inst:GPIO1_PORTA_O(19:19)} {intermediate 39} {output gpio_inst:GPIO1_PORTA_OE(11:11)} {intermediate 38} {output gpio_inst:GPIO1_PORTA_O(11:11)} {intermediate 37} {output gpio_inst:GPIO1_PORTA_OE(6:6)} {intermediate 36} {output gpio_inst:GPIO1_PORTA_O(6:6)} {intermediate 35} {output gpio_inst:GPIO0_PORTA_OE(9:9)} {intermediate 34} {output gpio_inst:GPIO0_PORTA_O(9:9)} {intermediate 33} {output i2c1_inst:I2C_CLK_OE(0:0)} {intermediate 32} {output i2c1_inst:I2C_DATA_OE(0:0)} {intermediate 31} {output i2c0_inst:I2C_CLK_OE(0:0)} {intermediate 30} {output i2c0_inst:I2C_DATA_OE(0:0)} {intermediate 29} {output spim1_inst:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 28} {output spim1_inst:SPI_MASTER_TXD(0:0)} {intermediate 27} {output usb1_inst:USB_ULPI_DATA_OE(7:7)} {intermediate 26} {output usb1_inst:USB_ULPI_DATA_O(7:7)} {intermediate 25} {output usb1_inst:USB_ULPI_DATA_OE(6:6)} {intermediate 24} {output usb1_inst:USB_ULPI_DATA_O(6:6)} {intermediate 23} {output usb1_inst:USB_ULPI_DATA_OE(5:5)} {intermediate 22} {output usb1_inst:USB_ULPI_DATA_O(5:5)} {intermediate 21} {output usb1_inst:USB_ULPI_DATA_OE(4:4)} {intermediate 20} {output usb1_inst:USB_ULPI_DATA_O(4:4)}} raw_assign_sim_style {}" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_2" value="2" />
  <parameter name="AC_ROM_MR1_MIRR" value="" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_3" value="2" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_4" value="2" />
  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED" value="0.0" />
  <parameter name="CFG_POWER_SAVING_EXIT_CYCLES" value="0" />
  <parameter name="AVL_NUM_SYMBOLS_PORT_0" value="2" />
  <parameter name="CV_PORT_2_CONNECT_TO_AV_PORT" value="2" />
  <parameter name="MR1_DS" value="0" />
  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="AUTO_PD_CYCLES" value="0" />
  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
  <parameter name="ENUM_CPORT5_TYPE" value="DISABLE" />
  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_PDN_PERIOD" value="0" />
  <parameter name="AFI_BANKADDR_WIDTH" value="0" />
  <parameter name="CV_ENUM_CPORT0_TYPE" value="DISABLE" />
  <parameter name="PLL_HR_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_THLD_JAR2_0" value="THRESHOLD_16" />
  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
  <parameter name="CTL_TBP_NUM" value="4" />
  <parameter name="ENUM_THLD_JAR2_1" value="THRESHOLD_16" />
  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
  <parameter name="ENUM_THLD_JAR2_2" value="THRESHOLD_16" />
  <parameter name="TIMING_BOARD_AC_SLEW_RATE_APPLIED" value="1.0" />
  <parameter name="CTL_ENABLE_BURST_TERMINATE_INT" value="false" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CFG_ECC_DECODER_REG" value="0" />
  <parameter name="CTL_ENABLE_BURST_INTERRUPT_INT" value="false" />
  <parameter name="REF_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="TRACKING_ERROR_TEST" value="false" />
  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="REF_CLK_FREQ_STR" value="" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_STR" value="" />
  <parameter name="PLL_MEM_CLK_FREQ" value="0.0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
  <parameter name="MR1_RTT" value="1" />
  <parameter name="READ_FIFO_HALF_RATE" value="false" />
  <parameter name="AC_ROM_MR0_DLL_RESET_MIRR" value="" />
  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE_CACHE" value="0.0" />
  <parameter name="CSR_DATA_WIDTH" value="32" />
  <parameter name="MEM_DLL_EN" value="true" />
  <parameter name="IS_ES_DEVICE" value="false" />
  <parameter name="PRE_V_SERIES_FAMILY" value="false" />
  <parameter name="USE_MM_ADAPTOR" value="true" />
  <parameter name="HHP_HPS_SIMULATION" value="false" />
  <parameter name="CV_ENUM_PRIORITY_6_1" value="WEIGHT_0" />
  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
  <parameter name="CV_ENUM_PRIORITY_6_0" value="WEIGHT_0" />
  <parameter name="IO_OUT2_DELAY_MAX" value="-1" />
  <parameter name="DELAYED_CLOCK_PHASE_SETTING" value="2" />
  <parameter name="PLL_MEM_CLK_MULT_CACHE" value="0" />
  <parameter name="USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE" value="false" />
  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
  <parameter name="HCX_COMPAT_MODE" value="false" />
  <parameter name="MEM_IF_DQSN_EN" value="true" />
  <parameter name="ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="AC_ROM_MR0" value="" />
  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MEM_TRAS" value="0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_ECC_DQ_WIDTH" value="ECC_DQ_WIDTH_0" />
  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP" value="0" />
  <parameter name="MEM_TINIT_US" value="500" />
  <parameter name="CTL_SELF_REFRESH" value="0" />
  <parameter name="ENUM_MEM_IF_TWTR" value="TWTR_4" />
  <parameter name="CALIBRATION_MODE" value="Skip" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
  <parameter name="ENUM_USER_ECC_EN" value="DISABLE" />
  <parameter name="PLL_MEM_CLK_DIV" value="0" />
  <parameter name="OCT_SHARING_MODE" value="None" />
  <parameter name="AC_ROM_MR2" value="" />
  <parameter name="AC_ROM_MR1" value="" />
  <parameter name="PLL_AFI_PHY_CLK_DIV" value="0" />
  <parameter name="AC_ROM_MR3" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_PCH" value="0" />
  <parameter name="USE_HARD_READ_FIFO" value="false" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_STR" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_PCH_TO_VALID" value="0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_STR" value="" />
  <parameter name="ENUM_CFG_BURST_LENGTH" value="BL_8" />
  <parameter name="MEM_IF_CLK_PAIR_COUNT" value="1" />
  <parameter name="CV_ENUM_PRIORITY_6_3" value="WEIGHT_0" />
  <parameter name="PHY_VERSION_NUMBER" value="0" />
  <parameter name="CV_ENUM_PRIORITY_6_2" value="WEIGHT_0" />
  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
  <parameter name="CV_ENUM_PRIORITY_6_5" value="WEIGHT_0" />
  <parameter name="TIMING_BOARD_TIH_APPLIED" value="0.0" />
  <parameter name="CV_ENUM_PRIORITY_6_4" value="WEIGHT_0" />
  <parameter name="MEM_SRT" value="Normal" />
  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
  <parameter name="MEM_IF_READ_DQS_WIDTH" value="0" />
  <parameter name="PLL_WRITE_CLK_MULT_CACHE" value="0" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
  <parameter name="EXTRA_VFIFO_SHIFT" value="0" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
  <parameter name="CV_ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
  <parameter name="CFG_TYPE" value="0" />
  <parameter name="ENUM_CLR_INTR" value="NO_CLR_INTR" />
  <parameter name="ENUM_CPORT3_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS" value="0" />
  <parameter name="MR3_DS" value="2" />
  <parameter name="PLL_AFI_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
  <parameter name="MR2_RLWL" value="1" />
  <parameter name="DELAY_CHAIN_LENGTH" value="8" />
  <parameter name="PLL_WRITE_CLK_DIV_CACHE" value="0" />
  <parameter name="CV_ENUM_PRIORITY_4_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_4_2" value="WEIGHT_0" />
  <parameter name="PLL_AFI_PHY_CLK_MULT" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID" value="0" />
  <parameter name="ENUM_PRIORITY_5_5" value="WEIGHT_0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_PRIORITY_5_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_5_2" value="WEIGHT_0" />
  <parameter name="PLL_DR_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="ENUM_PRIORITY_5_0" value="WEIGHT_0" />
  <parameter name="TIMING_TQHS" value="300" />
  <parameter name="CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK" value="0" />
  <parameter name="AV_PORT_1_CONNECT_TO_CV_PORT" value="1" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="CV_PORT_5_CONNECT_TO_AV_PORT" value="5" />
  <parameter name="CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK" value="0" />
  <parameter name="MEM_TMRD_CK" value="4" />
  <parameter name="CFG_INTERFACE_WIDTH" value="0" />
  <parameter name="IO_OUT1_DELAY_MAX" value="-1" />
  <parameter name="DEVICE_DEPTH" value="1" />
  <parameter name="HR_DDIO_OUT_HAS_THREE_REGS" value="false" />
  <parameter name="CV_ENUM_RFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="ENUM_MASK_CORR_DROPPED_INTR" value="DISABLED" />
  <parameter name="AC_PACKAGE_DESKEW" value="false" />
  <parameter name="ENUM_ATTR_STATIC_CONFIG_VALID" value="DISABLED" />
  <parameter name="CTL_ENABLE_WDATA_PATH_LATENCY" value="false" />
  <parameter name="ENUM_CLOCK_OFF_2" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_1" value="DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_STR" value="" />
  <parameter name="PLL_HR_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="ENUM_CLOCK_OFF_0" value="DISABLED" />
  <parameter name="SEQ_BURST_COUNT_WIDTH" value="0" />
  <parameter name="CFG_BURST_LENGTH" value="0" />
  <parameter name="ENUM_CLOCK_OFF_5" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_4" value="DISABLED" />
  <parameter name="ENUM_CLOCK_OFF_3" value="DISABLED" />
  <parameter name="PHY_ONLY" value="false" />
  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="PERFORM_READ_AFTER_WRITE_CALIBRATION" value="false" />
  <parameter name="TRFC" value="350" />
  <parameter name="IO_STANDARD" value="" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
  <parameter name="CV_ENUM_PRIORITY_4_5" value="WEIGHT_0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="SPEED_GRADE_CACHE" value="" />
  <parameter name="CV_ENUM_PRIORITY_4_4" value="WEIGHT_0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_AFI_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="READ_FIFO_SIZE" value="8" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="TB_MEM_IF_DQ_WIDTH" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ" value="0.0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="NEGATIVE_WRITE_CK_PHASE" value="false" />
  <parameter name="CFG_MEM_CLK_ENTRY_CYCLES" value="0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
  <parameter name="CV_ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
  <parameter name="ENUM_CFG_INTERFACE_WIDTH" value="DWIDTH_32" />
  <parameter name="ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="MEM_ATCL_INT" value="0" />
  <parameter name="ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
  <parameter name="PLL_CONFIG_CLK_FREQ_STR" value="" />
  <parameter name="CV_ENUM_CPORT4_TYPE" value="DISABLE" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="TIMING_TDSS" value="0.2" />
  <parameter name="CV_ENUM_PRIORITY_2_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_0" value="WEIGHT_0" />
  <parameter name="CSR_BE_WIDTH" value="4" />
  <parameter name="CV_ENUM_PRIORITY_2_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_2" value="WEIGHT_0" />
  <parameter name="PLL_LOCATION" value="Top_Bottom" />
  <parameter name="CV_ENUM_PRIORITY_2_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_2_4" value="WEIGHT_0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_STR" value="" />
  <parameter name="MEM_TRTP_NS" value="7.5" />
  <parameter name="CV_CPORT_TYPE_PORT_2" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_3" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_0" value="0" />
  <parameter name="PLL_SHARING_MODE" value="None" />
  <parameter name="CV_CPORT_TYPE_PORT_1" value="0" />
  <parameter name="PLL_DR_CLK_MULT_CACHE" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_4" value="0" />
  <parameter name="CV_CPORT_TYPE_PORT_5" value="0" />
  <parameter name="ENUM_PRIORITY_3_5" value="WEIGHT_0" />
  <parameter name="MEM_CLK_TO_DQS_CAPTURE_DELAY" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="AP_MODE" value="false" />
  <parameter name="ENUM_PRIORITY_3_3" value="WEIGHT_0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="ENUM_PRIORITY_3_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_3_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_3_2" value="WEIGHT_0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_STR" value="" />
  <parameter name="ENUM_PRIORITY_3_0" value="WEIGHT_0" />
  <parameter name="ENABLE_CSR_SOFT_RESET_REQ" value="false" />
  <parameter name="ENUM_MEM_IF_MEMTYPE" value="DDR3_SDRAM" />
  <parameter name="MEM_PD" value="DLL off" />
  <parameter name="MAX10_RTL_SEQ" value="false" />
  <parameter name="TIMING_TDSH" value="0.2" />
  <parameter name="CTL_AUTOPCH_EN" value="false" />
  <parameter name="ENUM_PDN_EXIT_CYCLES" value="SLOW_EXIT" />
  <parameter name="REF_CLK_FREQ_MAX_CACHE" value="0.0" />
  <parameter name="INTG_EXTRA_CTL_CLK_PDN_TO_VALID" value="0" />
  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
  <parameter name="MEM_DQ_WIDTH" value="32" />
  <parameter name="MAKE_INTERNAL_NIOS_VISIBLE" value="false" />
  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
  <parameter name="ENUM_CFG_SELF_RFSH_EXIT_CYCLES" value="" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="PLL_P2C_READ_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="FLY_BY" value="true" />
  <parameter name="ENUM_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="TIMING_TQSH" value="0.4" />
  <parameter name="CV_ENUM_CPORT4_WFIFO_MAP" value="FIFO_0" />
  <parameter name="LSB_RFIFO_PORT_0" value="5" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ" value="0.0" />
  <parameter name="AFI_CLK_PAIR_COUNT" value="0" />
  <parameter name="HARD_EMIF" value="true" />
  <parameter name="LSB_RFIFO_PORT_5" value="5" />
  <parameter name="LSB_RFIFO_PORT_3" value="5" />
  <parameter name="LSB_RFIFO_PORT_4" value="5" />
  <parameter name="LSB_RFIFO_PORT_1" value="5" />
  <parameter name="CV_ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
  <parameter name="LSB_RFIFO_PORT_2" value="5" />
  <parameter name="ENABLE_LARGE_RW_MGR_DI_BUFFER" value="false" />
  <parameter name="MEM_CLK_MAX_NS" value="2.5" />
  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
  <parameter name="CALIB_REG_WIDTH" value="8" />
  <parameter name="DWIDTH_RATIO" value="4" />
  <parameter name="INTG_MEM_IF_TREFI" value="3120" />
  <parameter name="CFG_CLR_INTR" value="0" />
  <parameter name="ENABLE_ABSTRACT_RAM" value="false" />
  <parameter name="ENUM_CPORT3_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_HR_CLK_PHASE_PS" value="0" />
  <parameter name="ENUM_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_ENABLE_NO_DM" value="DISABLED" />
  <parameter name="ENUM_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="MEM_TINIT_CK" value="499" />
  <parameter name="ENUM_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="AC_ROM_MR1_OCD_ENABLE" value="" />
  <parameter name="MR1_PASR" value="0" />
  <parameter name="IO_DQS_OUT_RESERVE" value="3" />
  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
  <parameter name="PLL_NIOS_CLK_FREQ_STR" value="" />
  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
  <parameter name="MEM_BL" value="OTF" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="PLL_AFI_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="USE_FAKE_PHY_INTERNAL" value="false" />
  <parameter name="MEM_BT" value="Sequential" />
  <parameter name="ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="CONTROLLER_LATENCY" value="5" />
  <parameter name="MEM_TRTP" value="0" />
  <parameter name="ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="TREFI" value="35100" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="CV_INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="PLL_AFI_CLK_DIV_CACHE" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_DIV_CACHE" value="0" />
  <parameter name="MEM_DQ_PER_DQS" value="8" />
  <parameter name="CV_ENUM_PRIORITY_0_1" value="WEIGHT_0" />
  <parameter name="ENUM_CTL_REGDIMM_ENABLED" value="REGDIMM_DISABLED" />
  <parameter name="CV_ENUM_PRIORITY_0_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_0_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_0_2" value="WEIGHT_0" />
  <parameter name="ENABLE_BURST_MERGE" value="false" />
  <parameter name="DQS_DELAY_CHAIN_PHASE_SETTING" value="2" />
  <parameter name="CV_ENUM_PRIORITY_0_5" value="WEIGHT_0" />
  <parameter name="ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="CV_ENUM_PRIORITY_0_4" value="WEIGHT_0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_DEG" value="0.0" />
  <parameter name="ENUM_CPORT2_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="CV_ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.08" />
  <parameter name="CV_ENUM_CPORT5_TYPE" value="DISABLE" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="ENUM_ENABLE_BURST_TERMINATE" value="DISABLED" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
  <parameter name="VECT_ATTR_DEBUG_SELECT_BYTE" value="0" />
  <parameter name="CV_PORT_4_CONNECT_TO_AV_PORT" value="4" />
  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
  <parameter name="DEVICE_WIDTH" value="1" />
  <parameter name="SOPC_COMPAT_RESET" value="false" />
  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
  <parameter name="PLL_HR_CLK_FREQ_STR" value="" />
  <parameter name="ENABLE_MAX_SIZE_SEQ_MEM" value="false" />
  <parameter name="ENUM_ENABLE_PIPELINEGLOBAL" value="DISABLED" />
  <parameter name="COMMAND_PHASE_CACHE" value="0.0" />
  <parameter name="AFI_CONTROL_WIDTH" value="0" />
  <parameter name="PLL_HR_CLK_DIV" value="0" />
  <parameter name="REF_CLK_FREQ_MIN_CACHE" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT_CACHE" value="0" />
  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="IO_DQS_EN_DELAY_OFFSET" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="CV_INTG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="USER_DEBUG_LEVEL" value="1" />
  <parameter name="ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="ENUM_SINGLE_READY_3" value="CONCATENATE_RDY" />
  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
  <parameter name="ENUM_SINGLE_READY_1" value="CONCATENATE_RDY" />
  <parameter name="ENUM_SINGLE_READY_2" value="CONCATENATE_RDY" />
  <parameter name="ENUM_WFIFO2_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="ENUM_GEN_DBE" value="GEN_DBE_DISABLED" />
  <parameter name="ENUM_SINGLE_READY_0" value="CONCATENATE_RDY" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="DATA_RATE_RATIO" value="0" />
  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
  <parameter name="ENUM_ENABLE_DQS_TRACKING" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_3" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_2" value="DISABLED" />
  <parameter name="ENUM_ENABLE_BONDING_5" value="DISABLED" />
  <parameter name="ENUM_MEM_IF_TCL" value="TCL_6" />
  <parameter name="ENUM_ENABLE_BONDING_4" value="DISABLED" />
  <parameter name="CV_ENUM_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="CV_ENUM_CPORT1_RFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_ENUM_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="CV_ENUM_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
  <parameter name="LOW_LATENCY" value="false" />
  <parameter name="ENUM_ENABLE_BONDING_1" value="DISABLED" />
  <parameter name="CV_ENUM_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="ENUM_ENABLE_BONDING_0" value="DISABLED" />
  <parameter name="CV_ENUM_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="CV_ENUM_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG" value="0.0" />
  <parameter name="ENUM_MEM_IF_DQ_PER_CHIP" value="MEM_IF_DQ_PER_CHIP_8" />
  <parameter name="MR1_WC" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_STR" value="" />
  <parameter name="ENUM_RFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="PLL_WRITE_CLK_FREQ_STR" value="" />
  <parameter name="RATE" value="Full" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MR1_WL" value="0" />
  <parameter name="POWER_OF_TWO_BUS" value="false" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_0" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="MR1_WR" value="1" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="MR3_MPR_RF" value="0" />
  <parameter name="MEM_IF_CONTROL_WIDTH" value="0" />
  <parameter name="DEBUG_MODE" value="false" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="MEM_RTT_WR" value="RZQ/4" />
  <parameter name="NUM_WRITE_PATH_FLOP_STAGES" value="0" />
  <parameter name="CFG_STARVE_LIMIT" value="0" />
  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT" value="0" />
  <parameter name="ENUM_PRIORITY_7_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_4" value="WEIGHT_0" />
  <parameter name="MEM_CLK_MAX_PS" value="2500.0" />
  <parameter name="ENUM_PRIORITY_7_1" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_7_0" value="WEIGHT_0" />
  <parameter name="MEM_IF_NUMBER_OF_RANKS" value="0" />
  <parameter name="HCX_COMPAT_MODE_CACHE" value="false" />
  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MEM_IF_RD_TO_WR_TURNAROUND_OCT" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
  <parameter name="ENUM_WR_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="MEM_BURST_LENGTH" value="8" />
  <parameter name="ENUM_WR_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_WR_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_WR_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="PLL_AFI_CLK_FREQ_STR" value="" />
  <parameter name="IO_DQDQS_OUT_PHASE_MAX" value="0" />
  <parameter name="MEM_TRRD" value="0" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_WR_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="ENUM_WR_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="REFRESH_INTERVAL" value="15000" />
  <parameter name="ENUM_PRIORITY_7_5" value="WEIGHT_0" />
  <parameter name="MEM_INIT_EN" value="false" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_PCH" value="0" />
  <parameter name="TIMING_BOARD_TDH_APPLIED" value="0.0" />
  <parameter name="ADDR_RATE_RATIO" value="0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CFG_SELF_RFSH_EXIT_CYCLES" value="0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_0" value="0" />
  <parameter name="CTL_REGDIMM_ENABLED" value="false" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_1" value="0" />
  <parameter name="CV_LSB_WFIFO_PORT_1" value="5" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_2" value="0" />
  <parameter name="CV_LSB_WFIFO_PORT_0" value="5" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_3" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_0" value="0" />
  <parameter name="CV_ENUM_WFIFO1_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="ENUM_GEN_SBE" value="GEN_SBE_DISABLED" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_4" value="0" />
  <parameter name="ENUM_ENABLE_BONDING_WRAPBACK" value="DISABLED" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_5" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_2" value="0" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_6" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_1" value="0" />
  <parameter name="INTG_RCFG_SUM_WT_PRIORITY_7" value="0" />
  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
  <parameter name="ENUM_THLD_JAR1_4" value="THRESHOLD_32" />
  <parameter name="MEM_RTT_NOM" value="RZQ/4" />
  <parameter name="ENUM_THLD_JAR1_5" value="THRESHOLD_32" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_4" value="0" />
  <parameter name="PLL_CONFIG_CLK_MULT" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_3" value="0" />
  <parameter name="CV_AVL_ADDR_WIDTH_PORT_5" value="0" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.16" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="AFI_WRANK_WIDTH" value="0" />
  <parameter name="LRDIMM" value="false" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MR1_DLL" value="0" />
  <parameter name="CFG_ADDR_ORDER" value="0" />
  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
  <parameter name="ENUM_WR_PORT_INFO_0" value="USE_NO" />
  <parameter name="CTL_ODT_ENABLED" value="false" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="SEQUENCER_TYPE" value="NIOS" />
  <parameter name="ENUM_WR_PORT_INFO_5" value="USE_NO" />
  <parameter name="MEM_IF_CLK_EN_WIDTH" value="0" />
  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" />
  <parameter name="ENUM_WR_PORT_INFO_1" value="USE_NO" />
  <parameter name="ENUM_WR_PORT_INFO_2" value="USE_NO" />
  <parameter name="ENUM_WR_PORT_INFO_3" value="USE_NO" />
  <parameter name="VFIFO_AS_SHIFT_REG" value="false" />
  <parameter name="ENUM_WR_PORT_INFO_4" value="USE_NO" />
  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
  <parameter name="ENUM_THLD_JAR1_0" value="THRESHOLD_32" />
  <parameter name="ENUM_THLD_JAR1_1" value="THRESHOLD_32" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS" value="0" />
  <parameter name="ENUM_THLD_JAR1_2" value="THRESHOLD_32" />
  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
  <parameter name="ENUM_THLD_JAR1_3" value="THRESHOLD_32" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="DLL_SHARING_MODE" value="None" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="ENUM_CPORT2_TYPE" value="DISABLE" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS" value="0" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_ENABLE_ATPG" value="DISABLED" />
  <parameter name="PLL_DR_CLK_MULT" value="0" />
  <parameter name="USE_USER_RDIMM_VALUE" value="false" />
  <parameter name="MEM_FORMAT" value="DISCRETE" />
  <parameter name="TIMING_BOARD_DQ_SLEW_RATE_APPLIED" value="1.0" />
  <parameter name="CONTROLLER_TYPE" value="nextgen_v110" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="AFI_WLAT_WIDTH" value="0" />
  <parameter name="MEM_IF_WRITE_DQS_WIDTH" value="0" />
  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="RATE_CACHE" value="Unknown" />
  <parameter name="COMMAND_PHASE" value="0.0" />
  <parameter name="CTL_CS_WIDTH" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_MULT" value="0" />
  <parameter name="ENUM_OUTPUT_REGD" value="DISABLED" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="MR1_ODS" value="1" />
  <parameter name="MEM_TRFC" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="AV_PORT_4_CONNECT_TO_CV_PORT" value="4" />
  <parameter name="ENUM_SYNC_MODE_1" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_5" value="WEIGHT_0" />
  <parameter name="ENUM_SYNC_MODE_0" value="ASYNCHRONOUS" />
  <parameter name="ENUM_SYNC_MODE_3" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_3" value="WEIGHT_0" />
  <parameter name="ENUM_SYNC_MODE_2" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_4" value="WEIGHT_0" />
  <parameter name="ENUM_CPORT1_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="ENUM_SYNC_MODE_5" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_1" value="WEIGHT_0" />
  <parameter name="ENUM_CPORT4_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="ENUM_SYNC_MODE_4" value="ASYNCHRONOUS" />
  <parameter name="CV_ENUM_RCFG_STATIC_WEIGHT_2" value="WEIGHT_0" />
  <parameter name="PLL_AFI_CLK_PHASE_DEG" value="0.0" />
  <parameter name="MEM_CK_PHASE" value="0.0" />
  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
  <parameter name="ENUM_CFG_TYPE" value="DDR3" />
  <parameter name="CV_ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED" value="-0.01" />
  <parameter name="ADDR_ORDER" value="0" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="PLL_CONFIG_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="MEM_VERBOSE" value="true" />
  <parameter name="HARD_PHY" value="false" />
  <parameter name="MR2_SRF" value="0" />
  <parameter name="ENUM_CPORT4_TYPE" value="DISABLE" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="EARLY_ADDR_CMD_CLK_TRANSFER" value="false" />
  <parameter name="ENUM_MEM_IF_BANKADDR_WIDTH" value="ADDR_WIDTH_3" />
  <parameter name="ENUM_MASK_SBE_INTR" value="DISABLED" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK" value="0" />
  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
  <parameter name="ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_READ_ODT_CHIP" value="ODT_DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_5" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_4" value="DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV_CACHE" value="0" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_3" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_2" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_1" value="DISABLED" />
  <parameter name="ENUM_AUTO_PCH_ENABLE_0" value="DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV" value="0" />
  <parameter name="VECT_ATTR_COUNTER_ONE_MASK" value="0" />
  <parameter name="MULTICAST_EN" value="false" />
  <parameter name="VCALIB_COUNT_WIDTH" value="0" />
  <parameter name="CV_ENUM_PORT4_WIDTH" value="PORT_64_BIT" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS" value="0" />
  <parameter name="OCT_TERM_CONTROL_WIDTH" value="14" />
  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="DLL_USE_DR_CLK" value="false" />
  <parameter name="ENUM_RFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="AC_PARITY" value="false" />
  <parameter name="AC_ROM_MR2_MIRR" value="" />
  <parameter name="MR1_DQS" value="0" />
  <parameter name="ENUM_ENABLE_ECC_CODE_OVERWRITES" value="DISABLED" />
  <parameter name="MR2_SRT" value="0" />
  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
  <parameter name="ENUM_MEM_IF_TMRD" value="" />
  <parameter name="CV_LSB_WFIFO_PORT_3" value="5" />
  <parameter name="CV_LSB_WFIFO_PORT_2" value="5" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="CV_LSB_WFIFO_PORT_5" value="5" />
  <parameter name="CV_LSB_WFIFO_PORT_4" value="5" />
  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
  <parameter name="MR1_QOFF" value="0" />
  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
  <parameter name="TB_MEM_CLK_FREQ" value="0.0" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="DLL_DELAY_CTRL_WIDTH" value="6" />
  <parameter name="MEM_CLK_FREQ" value="400.0" />
  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
  <parameter name="CV_ENUM_WFIFO0_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="USE_FAKE_PHY" value="false" />
  <parameter name="ENUM_MEM_IF_TWR" value="TWR_6" />
  <parameter name="SEQ_MODE" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="USE_LDC_AS_LOW_SKEW_CLOCK" value="false" />
  <parameter name="NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
  <parameter name="ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
  <parameter name="MEM_TYPE" value="" />
  <parameter name="REF_CLK_PS" value="0.0" />
  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
  <parameter name="ENUM_MEM_IF_TRAS" value="TRAS_16" />
  <parameter name="ENUM_INC_SYNC" value="FIFO_SET_2" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.01" />
  <parameter name="ENUM_MEM_IF_TRCD" value="TRCD_6" />
  <parameter name="MARGIN_VARIATION_TEST" value="false" />
  <parameter name="TIMING_TIS" value="180" />
  <parameter name="ENUM_PRIORITY_0_4" value="WEIGHT_0" />
  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.03" />
  <parameter name="ENUM_PRIORITY_0_5" value="WEIGHT_0" />
  <parameter name="CTL_RD_TO_PCH_EXTRA_CLK" value="0" />
  <parameter name="ENUM_PRIORITY_0_2" value="WEIGHT_0" />
  <parameter name="IO_IN_DELAY_MAX" value="-1" />
  <parameter name="ENUM_PRIORITY_0_3" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ARF_TO_VALID" value="0" />
  <parameter name="ENUM_PRIORITY_0_0" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_0_1" value="WEIGHT_0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_WR" value="0" />
  <parameter name="FAST_SIM_CALIBRATION" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_HR_CLK_PHASE_DEG" value="0.0" />
  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_STR" value="" />
  <parameter name="PLL_DR_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="AVL_ADDR_WIDTH" value="0" />
  <parameter name="CV_ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
  <parameter name="MAX10_CFG" value="false" />
  <parameter name="CFG_REORDER_DATA" value="true" />
  <parameter name="device" value="5CSEMA5F31C6" />
  <parameter name="ENUM_ENABLE_FAST_EXIT_PPD" value="DISABLED" />
  <parameter name="DELAY_BUFFER_MODE" value="HIGH" />
  <parameter name="ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_CPORT4_RFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_PORT3_WIDTH" value="PORT_64_BIT" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_DEG" value="0.0" />
  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
  <parameter name="CONTINUE_AFTER_CAL_FAIL" value="false" />
  <parameter name="AFI_RRANK_WIDTH" value="0" />
  <parameter name="ENUM_WFIFO1_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR" value="" />
  <parameter name="MR3_MPR" value="0" />
  <parameter name="P2C_READ_CLOCK_ADD_PHASE_CACHE" value="0.0" />
  <parameter name="PLL_AFI_HALF_CLK_MULT_CACHE" value="0" />
  <parameter name="PLL_P2C_READ_CLK_MULT" value="0" />
  <parameter name="ENUM_CFG_STARVE_LIMIT" value="STARVE_LIMIT_32" />
  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.02" />
  <parameter name="PLL_HR_CLK_MULT_CACHE" value="0" />
  <parameter name="MEM_IF_ODT_WIDTH" value="0" />
  <parameter name="TIMING_TDQSCKDL" value="1200" />
  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED" value="0.0" />
  <parameter name="TIMING_TDQSCKDS" value="450" />
  <parameter name="TIMING_TDQSCKDM" value="900" />
  <parameter name="PLL_DR_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="TIMING_BOARD_TIS" value="0.0" />
  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
  <parameter name="ENUM_MEM_IF_TCCD" value="TCCD_4" />
  <parameter name="CV_ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
  <parameter name="NIOS_HEX_FILE_LOCATION" value="" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_STR" value="" />
  <parameter name="AVL_BE_WIDTH" value="0" />
  <parameter name="AVL_MAX_SIZE" value="4" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_STR" value="" />
  <parameter name="TIMING_BOARD_TIH" value="0.0" />
  <parameter name="PLL_WRITE_CLK_MULT" value="0" />
  <parameter name="ENUM_CTL_USR_REFRESH" value="CTL_USR_REFRESH_DISABLED" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="TIMING_BOARD_TDS" value="0.0" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="CV_ENUM_CPORT2_RFIFO_MAP" value="FIFO_0" />
  <parameter name="NIOS_ROM_ADDRESS_WIDTH" value="13" />
  <parameter name="CFG_ERRCMD_FIFO_REG" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_DEG" value="0.0" />
  <parameter name="TIMING_BOARD_TDH" value="0.0" />
  <parameter name="PACKAGE_DESKEW" value="false" />
  <parameter name="PLL_NIOS_CLK_PHASE_DEG" value="0.0" />
  <parameter name="TRACKING_WATCH_TEST" value="false" />
  <parameter name="ENUM_DISABLE_MERGING" value="MERGING_ENABLED" />
  <parameter name="CV_ENUM_PRIORITY_7_0" value="WEIGHT_0" />
  <parameter name="ENUM_CTL_ADDR_ORDER" value="CHIP_BANK_ROW_COL" />
  <parameter name="NUM_AC_FR_CYCLE_SHIFTS" value="0" />
  <parameter name="AFI_DM_WIDTH" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR" value="" />
  <parameter name="PLL_CONFIG_CLK_DIV" value="0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED" value="0.0" />
  <parameter name="ENUM_CTL_ECC_ENABLED" value="CTL_ECC_DISABLED" />
  <parameter name="BYTE_ENABLE" value="true" />
  <parameter name="USE_SHADOW_REGS" value="false" />
  <parameter name="ENUM_MEM_IF_CS_WIDTH" value="MEM_IF_CS_WIDTH_1" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="MEM_IF_BANKADDR_WIDTH" value="0" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="CV_ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
  <parameter name="ENUM_CAL_REQ" value="DISABLED" />
  <parameter name="ENUM_PORT0_WIDTH" value="PORT_64_BIT" />
  <parameter name="MEM_IF_DQ_WIDTH" value="0" />
  <parameter name="PLL_DR_CLK_PHASE_PS" value="0" />
  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
  <parameter name="ADDR_CMD_DDR" value="0" />
  <parameter name="GENERIC_PLL" value="false" />
  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="ENABLE_NON_DES_CAL" value="false" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="MR3_MPR_AA" value="0" />
  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_1" value="0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_DEG" value="0.0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_0" value="0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_3" value="0" />
  <parameter name="MEM_TFAW_NS" value="30.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_2" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ" value="0.0" />
  <parameter name="AVL_DATA_WIDTH_PORT_5" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_4" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_3" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_2" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_1" value="0" />
  <parameter name="AVL_DATA_WIDTH_PORT_0" value="0" />
  <parameter name="REF_CLK_NS" value="0.0" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_5" value="0" />
  <parameter name="PLL_CONFIG_CLK_DIV_CACHE" value="0" />
  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
  <parameter name="CV_AVL_DATA_WIDTH_PORT_4" value="0" />
  <parameter name="AFI_CLK_EN_WIDTH" value="0" />
  <parameter name="TIMING_TQH" value="0.38" />
  <parameter name="USE_LDC_FOR_ADDR_CMD" value="false" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_CLK_CACHE_VALID" value="false" />
  <parameter name="ENUM_MEM_IF_DWIDTH" value="MEM_IF_DWIDTH_32" />
  <parameter name="ENUM_RD_PORT_INFO_2" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_3" value="DWIDTH_0" />
  <parameter name="ENUM_RD_PORT_INFO_3" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_2" value="DWIDTH_0" />
  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="ENUM_RD_PORT_INFO_4" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_5" value="DWIDTH_0" />
  <parameter name="ENUM_MEM_IF_SPEEDBIN" value="DDR3_1066_6_6_6" />
  <parameter name="ENUM_RD_PORT_INFO_5" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_4" value="DWIDTH_0" />
  <parameter name="ENUM_CPORT0_TYPE" value="DISABLE" />
  <parameter name="CV_ENUM_PRIORITY_7_2" value="WEIGHT_0" />
  <parameter name="PLL_HR_CLK_MULT" value="0" />
  <parameter name="ENUM_MEM_IF_TRP" value="TRP_6" />
  <parameter name="CV_ENUM_PRIORITY_7_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_7_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_7_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_ENUM_PRIORITY_7_5" value="WEIGHT_0" />
  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="HHP_HPS" value="true" />
  <parameter name="CV_ENUM_WFIFO3_CPORT_MAP" value="CMD_PORT_0" />
  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
  <parameter name="ENUM_CPORT3_WFIFO_MAP" value="FIFO_0" />
  <parameter name="AVL_SIZE_WIDTH" value="0" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR" value="" />
  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
  <parameter name="RDBUFFER_ADDR_WIDTH" value="6" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_MEM_IF_TRC" value="TRC_22" />
  <parameter name="ENUM_RD_PORT_INFO_0" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_1" value="DWIDTH_0" />
  <parameter name="ENUM_RD_PORT_INFO_1" value="USE_NO" />
  <parameter name="CV_ENUM_RD_DWIDTH_0" value="DWIDTH_0" />
  <parameter name="CV_ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
  <parameter name="ENABLE_NIOS_JTAG_UART" value="false" />
  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
  <parameter name="DAT_DATA_WIDTH" value="32" />
  <parameter
     name="CPORT_TYPE_PORT"
     value="Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional" />
  <parameter name="DLL_OFFSET_CTRL_WIDTH" value="6" />
  <parameter name="AC_ROM_MR1_CALIB" value="" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="INTG_CYC_TO_RLD_JARS_5" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_4" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_3" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_2" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_1" value="1" />
  <parameter name="INTG_CYC_TO_RLD_JARS_0" value="1" />
  <parameter name="SPEED_GRADE" value="7" />
  <parameter name="CV_ENUM_PRIORITY_5_0" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_5_2" value="WEIGHT_0" />
  <parameter name="PLL_NIOS_CLK_FREQ" value="0.0" />
  <parameter name="ENUM_PORT1_WIDTH" value="PORT_64_BIT" />
  <parameter name="CV_ENUM_PRIORITY_5_1" value="WEIGHT_0" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS" value="0" />
  <parameter name="MEM_TRCD_NS" value="13.75" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="ENUM_PRIORITY_4_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_5" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_4_0" value="WEIGHT_0" />
  <parameter name="AFI_ADDR_WIDTH" value="0" />
  <parameter name="ENUM_PRIORITY_4_1" value="WEIGHT_0" />
  <parameter name="USE_HPS_DQS_TRACKING" value="false" />
  <parameter name="MEM_IF_COL_ADDR_WIDTH" value="0" />
  <parameter name="EXPORT_CSR_PORT" value="false" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_STR" value="" />
  <parameter name="MEM_CK_PHASE_CACHE" value="0.0" />
  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
  <parameter name="MSB_WFIFO_PORT_0" value="5" />
  <parameter name="CV_LSB_RFIFO_PORT_5" value="5" />
  <parameter name="MSB_WFIFO_PORT_1" value="5" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="TIMING_TDS" value="30" />
  <parameter name="MSB_WFIFO_PORT_2" value="5" />
  <parameter
     name="qipEntries"
     value="{set_instance_assignment -name hps_partition on -entity %entityName% -library %libraryName%}" />
  <parameter name="MSB_WFIFO_PORT_3" value="5" />
  <parameter name="MEM_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="MSB_WFIFO_PORT_4" value="5" />
  <parameter name="MSB_WFIFO_PORT_5" value="5" />
  <parameter name="PLL_DR_CLK_PHASE_DEG" value="0.0" />
  <parameter name="PLL_NIOS_CLK_DIV_CACHE" value="0" />
  <parameter name="CFG_TCCD" value="0" />
  <parameter name="ENUM_MEM_IF_AL" value="AL_0" />
  <parameter name="ENUM_TEST_MODE" value="NORMAL_MODE" />
  <parameter name="MEM_CS_WIDTH" value="1" />
  <parameter name="CV_LSB_RFIFO_PORT_0" value="5" />
  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE_CACHE" value="0.0" />
  <parameter name="ENUM_CPORT0_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="CV_LSB_RFIFO_PORT_2" value="5" />
  <parameter name="CV_LSB_RFIFO_PORT_1" value="5" />
  <parameter name="TIMING_TDH" value="65" />
  <parameter name="AV_PORT_3_CONNECT_TO_CV_PORT" value="3" />
  <parameter name="CV_LSB_RFIFO_PORT_4" value="5" />
  <parameter name="SCC_DATA_WIDTH" value="0" />
  <parameter name="CV_LSB_RFIFO_PORT_3" value="5" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD_BC" value="0" />
  <parameter name="CV_ENUM_CPORT0_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ" value="0.0" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="MEM_TREFI_US" value="7.8" />
  <parameter name="PLL_DR_CLK_PHASE_PS_STR" value="" />
  <parameter name="USE_DQS_TRACKING" value="false" />
  <parameter name="MEM_LRDIMM_ENABLED" value="false" />
  <parameter name="TIMING_BOARD_TIS_APPLIED" value="0.0" />
  <parameter name="ENUM_CPORT5_WFIFO_MAP" value="FIFO_0" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED" value="0.01" />
  <parameter name="ENUM_MEM_IF_DQS_WIDTH" value="DQS_WIDTH_4" />
  <parameter name="CTL_ZQCAL_EN" value="false" />
  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x000000000000000000" />
  <parameter name="ENUM_DFX_BYPASS_ENABLE" value="DFX_BYPASS_DISABLED" />
  <parameter name="AC_ROM_MR0_CALIB" value="" />
  <parameter name="MEM_TWR_NS" value="15.0" />
  <parameter name="ENUM_CTRL_WIDTH" value="DATA_WIDTH_64_BIT" />
  <parameter name="MEM_T_WL" value="0" />
  <parameter name="CV_ENUM_PRIORITY_5_4" value="WEIGHT_0" />
  <parameter name="AFI_WRITE_DQS_WIDTH" value="0" />
  <parameter name="CV_ENUM_PRIORITY_5_3" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_5_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_CPORT2_TYPE" value="DISABLE" />
  <parameter name="AFI_RLAT_WIDTH" value="0" />
  <parameter name="ENUM_PORT2_WIDTH" value="PORT_64_BIT" />
  <parameter name="MEM_TRP" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_ACT_TO_RDWR" value="0" />
  <parameter name="MEM_CLK_PS" value="0.0" />
  <parameter name="IS_ES_DEVICE_CACHE" value="false" />
  <parameter name="PLL_AFI_CLK_FREQ" value="0.0" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_1" value="EMPTY" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_2" value="EMPTY" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_3" value="EMPTY" />
  <parameter name="MEM_TRRD_NS" value="7.7" />
  <parameter name="CV_PORT_3_CONNECT_TO_AV_PORT" value="3" />
  <parameter name="ENUM_DELAY_BONDING" value="BONDING_LATENCY_0" />
  <parameter name="ENUM_USE_ALMOST_EMPTY_0" value="EMPTY" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_DEG_SIM" value="0.0" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="DQS_IN_DELAY_MAX" value="-1" />
  <parameter name="LSB_WFIFO_PORT_4" value="5" />
  <parameter name="LSB_WFIFO_PORT_5" value="5" />
  <parameter name="LSB_WFIFO_PORT_2" value="5" />
  <parameter name="LSB_WFIFO_PORT_3" value="5" />
  <parameter name="MR0_CAS_LATENCY" value="3" />
  <parameter name="LSB_WFIFO_PORT_0" value="5" />
  <parameter name="LSB_WFIFO_PORT_1" value="5" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED" value="0.05" />
  <parameter name="CFG_PDN_EXIT_CYCLES" value="0" />
  <parameter name="MR0_WR" value="4" />
  <parameter name="ENUM_WFIFO2_RDY_ALMOST_FULL" value="NOT_FULL" />
  <parameter name="CV_ENUM_PRIORITY_3_0" value="WEIGHT_0" />
  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED" value="2.0" />
  <parameter name="CV_ENUM_PRIORITY_3_2" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_1" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_4" value="WEIGHT_0" />
  <parameter name="CV_ENUM_PRIORITY_3_3" value="WEIGHT_0" />
  <parameter name="PLL_MEM_CLK_FREQ_STR" value="" />
  <parameter name="PLL_AFI_PHY_CLK_FREQ_CACHE" value="0.0" />
  <parameter name="PLL_AFI_PHY_CLK_DIV_CACHE" value="0" />
  <parameter name="LOCAL_ID_WIDTH" value="8" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_CACHE" value="" />
  <parameter name="TIMING_TDQSS" value="0.25" />
  <parameter name="TIMING_TDQSQ" value="125" />
  <parameter name="ENUM_PRIORITY_2_4" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_5" value="WEIGHT_0" />
  <parameter name="CV_ENUM_CPORT1_WFIFO_MAP" value="FIFO_0" />
  <parameter name="ENUM_PRIORITY_2_2" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_3" value="WEIGHT_0" />
  <parameter name="ENUM_PRIORITY_2_0" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_3" value="PRIORITY_0" />
  <parameter name="ENUM_PRIORITY_2_1" value="WEIGHT_0" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_2" value="PRIORITY_0" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_5" value="PRIORITY_0" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_4" value="PRIORITY_0" />
  <parameter name="PLL_P2C_READ_CLK_DIV_CACHE" value="0" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_1" value="PRIORITY_0" />
  <parameter name="TIMING_TDQSH" value="0.35" />
  <parameter name="ENUM_RCFG_USER_PRIORITY_0" value="PRIORITY_0" />
  <parameter name="USE_2X_FF" value="false" />
  <parameter name="MEM_ASR" value="Manual" />
  <parameter name="ENUM_RD_FIFO_IN_USE_2" value="FALSE" />
  <parameter name="PLL_DR_CLK_FREQ" value="0.0" />
  <parameter name="ENUM_RD_FIFO_IN_USE_3" value="FALSE" />
  <parameter name="ENUM_RD_FIFO_IN_USE_0" value="FALSE" />
  <parameter name="ENUM_RD_FIFO_IN_USE_1" value="FALSE" />
  <parameter name="ADVANCED_CK_PHASES" value="false" />
  <parameter name="ENUM_REORDER_DATA" value="DATA_REORDERING" />
  <parameter name="NEXTGEN" value="true" />
  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
  <parameter name="USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY" value="false" />
  <parameter name="PRIORITY_PORT_0" value="0" />
  <parameter name="MEM_T_RL" value="0" />
  <parameter name="MEM_TWR" value="0" />
  <parameter name="PRIORITY_PORT_2" value="0" />
  <parameter name="PRIORITY_PORT_1" value="0" />
  <parameter name="USE_DR_CLK" value="false" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" />
  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_CACHE" value="0" />
  <parameter name="AC_ROM_MR3_MIRR" value="" />
  <parameter name="ENABLE_EMIT_JTAG_MASTER" value="false" />
  <parameter name="CPORT_TYPE_PORT_3" value="0" />
  <parameter name="MEM_IF_DQS_WIDTH" value="0" />
  <parameter name="CPORT_TYPE_PORT_2" value="0" />
  <parameter name="CPORT_TYPE_PORT_1" value="0" />
  <parameter name="TIMING_TIH" value="140" />
  <parameter name="CPORT_TYPE_PORT_0" value="0" />
  <parameter name="INTG_EXTRA_CTL_CLK_WR_TO_RD" value="0" />
  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
  <parameter name="USE_AXI_ADAPTOR" value="false" />
  <parameter name="PRIORITY_PORT_4" value="0" />
  <parameter name="PRIORITY_PORT_3" value="0" />
  <parameter name="LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT" value="true" />
  <parameter name="PRIORITY_PORT_5" value="0" />
  <parameter name="MEM_MIRROR_ADDRESSING_DEC" value="0" />
  <parameter name="ENUM_CMD_PORT_IN_USE_5" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_4" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_3" value="FALSE" />
  <parameter name="CTL_WR_TO_WR_EXTRA_CLK" value="0" />
  <parameter name="ENUM_CMD_PORT_IN_USE_2" value="FALSE" />
  <parameter name="ENUM_CPORT5_RFIFO_MAP" value="FIFO_0" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR" value="" />
  <parameter name="ENUM_CMD_PORT_IN_USE_1" value="FALSE" />
  <parameter name="ENUM_CMD_PORT_IN_USE_0" value="FALSE" />
  <parameter name="NUM_OF_PORTS" value="1" />
  <parameter name="CV_ENUM_PRIORITY_3_5" value="WEIGHT_0" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID" value="false" />
  <parameter name="ENUM_CPORT3_TYPE" value="DISABLE" />
  <parameter name="MAX_WRITE_LATENCY_COUNT_WIDTH" value="4" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
  <parameter
     name="hps_parameter_map"
     value="AC_PACKAGE_DESKEW false MAX_PENDING_WR_CMD 16 MEM_BANKADDR_WIDTH 3 FORCE_SHADOW_REGS AUTO F2H_SDRAM2_CLOCK_FREQ 100 JAVA_TRACE_DATA {TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} main_pll_c3_auto 511 PLL_CLK_PARAM_VALID false AUTO_POWERDN_EN false VECT_ATTR_COUNTER_ZERO_MATCH 0 ENABLE_BURST_MERGE false VECT_ATTR_COUNTER_ONE_MASK 0 MEM_IF_CK_WIDTH 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 CV_PORT_2_CONNECT_TO_AV_PORT 2 CTL_CSR_ENABLED false MEM_IF_LRDIMM_RM 0 qspi_clk_source 1 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_CLK_MAX_NS 1.25 QSPI_Mode N/A CSR_BE_WIDTH 1 CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 periph_base_clk_hz 200000000 AVL_SYMBOL_WIDTH 8 S2FINTERRUPT_WATCHDOG_Enable false MEM_NUMBER_OF_RANKS_PER_DEVICE 1 ENUM_CPORT0_TYPE DISABLE MEM_IF_DQ_WIDTH 32 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_DR_CLK_MULT 0 F2SDRAM_Name_DERIVED {} PLL_CONFIG_CLK_DIV_PARAM 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 CTL_ZQCAL_EN false MEM_IF_WRITE_DQS_WIDTH 4 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 CFG_DATA_REORDERING_TYPE INTER_BANK CTL_ENABLE_BURST_INTERRUPT false periph_pll_vco_mhz 1000.0 MEM_TRCD 6 CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 SCC_DATA_WIDTH 1 ENUM_MEM_IF_AL AL_0 MR1_DQS 0 MEM_USER_LEVELING_MODE Leveling device_name 5CSEMA5F31C6 HHP_HPS true ENUM_CFG_BURST_LENGTH BL_8 periph_qspi_clk_hz 1953125 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CFG_STARVE_LIMIT 10 AV_PORT_1_CONNECT_TO_CV_PORT 1 TIMING_TDQSCKDS 450 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 TIMING_TDSS 0.2 MEM_TRAS 14 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 ENUM_GANGED_ARF DISABLED ENUM_ENABLE_BURST_INTERRUPT DISABLED S2FINTERRUPT_I2CEMAC_Enable false dbg_base_clk_mhz 25.0 TIMING_TDSH 0.2 S2FINTERRUPT_UART_Enable false PLL_P2C_READ_CLK_PHASE_DEG 0.0 DUAL_WRITE_CLOCK false CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DEVICE_WIDTH 1 AFI_DQ_WIDTH 64 READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS HARD_EMIF true MEM_DEVICE MISSING_MODEL CV_ENUM_PORT4_WIDTH PORT_32_BIT FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 desired_can0_clk_hz 100000000 DB_port_pins {i2c_emac0_out_data {0 ic_data_oe} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} i2c_emac0_sda {0 ic_data_in_a} can0_rxd {0 can_rxd} nand_adq_in {6 adq_in6 5 adq_in5 4 adq_in4 3 adq_in3 2 adq_in2 1 adq_in1 0 adq_in0 7 adq_in7} i2c1_out_clk {0 ic_clk_oe} emac0_gmii_mdi_i {0 mdi} i2c_emac0_scl {0 ic_clk_in_a} sdmmc_vs_o {0 vs_o} nand_wpbar_out {0 wp_outn} emac1_gmii_mdo_o_e {0 mdo_en} emac0_gmii_mdc_o {0 mdc} i2c_emac1_out_data {0 ic_data_oe} uart0_dtr {0 dtr_n} i2c0_sda {0 ic_data_in_a} spis1_txd {0 txd} usb0_ulpi_nxt {0 ulpi_nxt} qspi_mi3 {0 mi3} qspi_mi2 {0 mi2} spis1_rxd {0 rxd} qspi_mi1 {0 mi1} qspi_mi0 {0 mi0} nand_rebar_out {0 re_outn} i2c0_scl {0 ic_clk_in_a} sdmmc_cdn_i {0 cd_i_n} qspi_n_mo_en {3 n_mo_en3 2 n_mo_en2 1 n_mo_en1 0 n_mo_en0} uart0_out1_n {0 out1_n} emac1_phy_txclk_o {0 tx_clk_o} uart0_dsr {0 dsr_n} sdmmc_cmd_o {0 ccmd_o} spim1_ss_2_n {0 ss_cs2} sdmmc_cmd_i {0 ccmd_i} spis0_ss_in_n {0 ss_in_n} usb0_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} spim1_ss_0_n {0 ss_cs0} usb1_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_nxt {0 ulpi_nxt} uart0_ri {0 ri_n} emac1_phy_rxer_i {0 rxer} uart1_dcd {0 dcd_n} nand_cebar_out {3 ce_outn3 2 ce_outn2 1 ce_outn1 0 ce_outn0} emac0_clk_rx_i {0 rx_clk} usb1_ulpi_data_out_en {6 ulpi_data_out_en6 5 ulpi_data_out_en5 4 ulpi_data_out_en4 3 ulpi_data_out_en3 2 ulpi_data_out_en2 1 ulpi_data_out_en1 0 ulpi_data_out_en0 7 ulpi_data_out_en7} nand_adq_out {6 adq_out6 5 adq_out5 4 adq_out4 3 adq_out3 2 adq_out2 1 adq_out1 0 adq_out0 7 adq_out7} emac0_ptp_aux_ts_trig_i {0 ts_trig} spim0_ssi_oe_n {0 ssi_oe_n} usb0_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} emac0_ptp_pps_o {0 ptp_pps} emac0_phy_txer_o {0 txer} emac0_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} uart1_cts {0 cts_n} emac1_clk_rx_i {0 rx_clk} qspi_mo2_wpn {0 mo2_wpn} emac0_phy_txen_o {0 txen} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_gmii_mdo_o {0 mdo} uart1_txd {0 sout} spim0_ss_3_n {0 ss_cs3} spim1_ssi_oe_n {0 ssi_oe_n} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spis0_txd {0 txd} qspi_sclk_out {0 sck_out} uart1_rxd {0 sin} emac1_ptp_pps_o {0 ptp_pps} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_1_n {0 ss_cs1} emac1_phy_rxd_i {6 rxd6 5 rxd5 4 rxd4 3 rxd3 2 rxd2 1 rxd1 0 rxd0 7 rxd7} spis0_rxd {0 rxd} uart1_ri {0 ri_n} usb0_ulpi_dir {0 ulpi_dir} emac1_gmii_mdi_i {0 mdi} uart1_out1_n {0 out1_n} sdmmc_rstn_o {0 rst_out_n} qspi_n_ss_out {3 n_ss_out3 2 n_ss_out2 1 n_ss_out1 0 n_ss_out0} nand_rdy_busy_in {3 rdy_bsy_in3 2 rdy_bsy_in2 1 rdy_bsy_in1 0 rdy_bsy_in0} emac1_gmii_mdc_o {0 mdc} uart0_dcd {0 dcd_n} usb1_ulpi_dir {0 ulpi_dir} emac0_phy_col_i {0 col} sdmmc_data_o {6 cdata_out6 5 cdata_out5 4 cdata_out4 3 cdata_out3 2 cdata_out2 1 cdata_out1 0 cdata_out0 7 cdata_out7} spis1_ss_in_n {0 ss_in_n} sdmmc_data_i {6 cdata_in6 5 cdata_in5 4 cdata_in4 3 cdata_in3 2 cdata_in2 1 cdata_in1 0 cdata_in0 7 cdata_in7} nand_adq_oe {0 adq_oe0} emac0_phy_rxdv_i {0 rxdv} usb1_ulpi_datain {6 ulpi_datain6 5 ulpi_datain5 4 ulpi_datain4 3 ulpi_datain3 2 ulpi_datain2 1 ulpi_datain1 0 ulpi_datain0 7 ulpi_datain7} uart0_cts {0 cts_n} emac0_phy_crs_i {0 crs} emac1_phy_col_i {0 col} i2c_emac0_out_clk {0 ic_clk_oe} spim0_sclk_out {0 sclk_out} i2c0_out_data {0 ic_data_oe} qspi_mo1 {0 mo1} qspi_mo0 {0 mo0} spim0_ss_in_n {0 ss_in_n} spim1_txd {0 txd} uart0_out2_n {0 out2_n} spis0_sclk_in {0 sclk_in} uart0_txd {0 sout} nand_cle_out {0 cle_out} emac0_gmii_mdo_o_e {0 mdo_en} spim1_rxd {0 rxd} emac0_clk_tx_i {0 tx_clk_i} spim1_ss_3_n {0 ss_cs3} i2c0_out_clk {0 ic_clk_oe} uart0_rxd {0 sin} uart1_rts {0 rts_n} spim1_ss_1_n {0 ss_cs1} emac1_phy_crs_i {0 crs} qspi_mo3_hold {0 mo3_hold} can1_txd {0 can_txd} emac1_phy_txer_o {0 txer} usb0_ulpi_clk {0 ulpi_clk} i2c_emac1_sda {0 ic_data_in_a} can1_rxd {0 can_rxd} nand_ale_out {0 ale_out} spim1_sclk_out {0 sclk_out} i2c1_out_data {0 ic_data_oe} emac0_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} emac1_phy_txen_o {0 txen} spis0_ssi_oe_n {0 ssi_oe_n} nand_webar_out {0 we_outn} emac1_clk_tx_i {0 tx_clk_i} i2c_emac1_scl {0 ic_clk_in_a} emac1_ptp_aux_ts_trig_i {0 ts_trig} usb0_ulpi_dataout {6 ulpi_dataout6 5 ulpi_dataout5 4 ulpi_dataout4 3 ulpi_dataout3 2 ulpi_dataout2 1 ulpi_dataout1 0 ulpi_dataout0 7 ulpi_dataout7} usb1_ulpi_clk {0 ulpi_clk} emac0_phy_rxer_i {0 rxer} uart1_dtr {0 dtr_n} i2c1_sda {0 ic_data_in_a} sdmmc_wp_i {0 wp_i} emac1_phy_txd_o {6 txd6 5 txd5 4 txd4 3 txd3 2 txd2 1 txd1 0 txd0 7 txd7} sdmmc_cclk_out {0 cclk_out} spis1_ssi_oe_n {0 ssi_oe_n} sdmmc_card_intn_i {0 card_int_n} i2c1_scl {0 ic_clk_in_a} emac0_phy_txclk_o {0 tx_clk_o} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim0_ss_2_n {0 ss_cs2} uart1_dsr {0 dsr_n} spim1_ss_in_n {0 ss_in_n} usb0_ulpi_stp {0 ulpi_stp} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} spim0_ss_0_n {0 ss_cs0} spim0_txd {0 txd} uart1_out2_n {0 out2_n} spim0_rxd {0 rxd} i2c_emac1_out_clk {0 ic_clk_oe} sdmmc_cmd_en {0 ccmd_en} emac1_phy_rxdv_i {0 rxdv} uart0_rts {0 rts_n} emac0_gmii_mdo_o {0 mdo} sdmmc_data_en {6 cdata_out_en6 5 cdata_out_en5 4 cdata_out_en4 3 cdata_out_en3 2 cdata_out_en2 1 cdata_out_en1 0 cdata_out_en0 7 cdata_out_en7} can0_txd {0 can_txd}} PLL_CONFIG_CLK_DIV_CACHE 0 PLL_DR_CLK_PHASE_DEG_SIM 0.0 CONTINUE_AFTER_CAL_FAIL false TIMING_TDQSS 0.25 PACKAGE_DESKEW false TIMING_TDQSQ 125 S2FINTERRUPT_QSPI_Enable false INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 MEM_MIRROR_ADDRESSING_DEC 0 CTL_OUTPUT_REGD false BSEL 1 TIMING_BOARD_MAX_DQS_DELAY 0.02 TIMING_TDQSH 0.35 OCT_TERM_CONTROL_WIDTH 16 main_pll_n 0 main_pll_m 63 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 CV_ENUM_PORT3_WIDTH PORT_32_BIT ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 ENUM_WR_DWIDTH_1 DWIDTH_0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM {} ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_HR_CLK_FREQ 0.0 F2SCLK_PERIPHCLK_Enable false MR1_PASR 0 PLL_ADDR_CMD_CLK_MULT 32 CSEL_EN false MRS_MIRROR_PING_PONG_ATSO false eosc1_clk_mhz 25.0 LOCAL_ID_WIDTH 8 READ_FIFO_HALF_RATE false PLL_LOCATION Top_Bottom MEM_NUMBER_OF_DIMMS 1 AP_MODE_EN 0 desired_emac1_clk_mhz 250.0 PLL_WRITE_CLK_PHASE_PS_PARAM 0 CV_ENUM_PORT2_WIDTH PORT_32_BIT dbg_trace_clk_hz 25000000 ENABLE_CTRL_AVALON_INTERFACE true H2F_TPIU_CLOCK_IN_FREQ 100 BSEL_EN false PHY_ONLY false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 CAN1_Mode N/A IO_IN_DELAY_MAX 31 MR1_DLL 0 Customer_Pin_Name_DERIVED {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} desired_can0_clk_mhz 100.0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 TIMING_TQHS 300 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 PLL_P2C_READ_CLK_FREQ 0.0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false AFI_RLAT_WIDTH 6 ENABLE_BONDING false MEM_DLL_EN true PLL_AFI_CLK_MULT_PARAM 0 F2SCLK_SDRAMCLK_FREQ 0 CTL_CMD_QUEUE_DEPTH 8 READ_FIFO_SIZE 8 AVL_MAX_SIZE 4 PLL_MEM_CLK_FREQ_SIM_STR_PARAM {} qspi_clk_hz 3613281 desired_l4_mp_clk_hz 100000000 NIOS_HEX_FILE_LOCATION ../ PLL_ADDR_CMD_CLK_MULT_PARAM 0 TIMING_TQH 0.38 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 mpu_periph_clk_mhz 231.25 ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_CLK_PS 2500.0 periph_pll_vco_hz 1000000000 CTL_ECC_CSR_ENABLED false REF_CLK_FREQ_CACHE_VALID true AFI_ADDR_WIDTH 30 PLL_WRITE_CLK_PHASE_PS_CACHE 1875 UART0_PinMuxing {HPS I/O Set 0} sdmmc_clk_hz 200000000 F2SCLK_COLDRST_Enable false PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 periph_pll_c5 9 MEM_IF_CLK_EN_WIDTH 1 periph_pll_c4 4 periph_pll_c3 19 periph_pll_c2 1 periph_pll_c1 3 QSPI_PinMuxing Unused periph_pll_c0 3 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 TIMING_BOARD_DQ_SLEW_RATE 1.0 ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 mpu_l2_ram_clk_hz 462500000 ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_0 EMPTY MULTICAST_EN false READ_VALID_FIFO_SIZE 16 CV_ENUM_CPORT2_TYPE DISABLE INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 EMAC1_Mode RGMII NIOS_ROM_ADDRESS_WIDTH 13 main_pll_c0_internal 1 main_pll_vco_hz 1600000000 S2FINTERRUPT_CAN_Enable false MEM_CLK_NS 2.5 PLL_AFI_CLK_MULT_CACHE 32 PLL_ADDR_CMD_CLK_DIV 2 NIOS_ROM_DATA_WIDTH 32 ENUM_MEM_IF_TMRD TMRD_4 ENUM_PRIORITY_1_5 WEIGHT_0 periph_pll_c1_auto 3 PLL_MEM_CLK_FREQ_SIM_STR_CACHE {2500 ps} ENUM_PRIORITY_1_4 WEIGHT_0 PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 MR1_QOFF 0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 PLL_ADDR_CMD_CLK_MULT_CACHE 32 IO_DQ_OUT_RESERVE 0 CFG_BURST_LENGTH 8 MEM_TWR_NS 15.0 TRACKING_WATCH_TEST false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 PLL_ADDR_CMD_CLK_FREQ_CACHE 400.0 JAVA_USB1_DATA {USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} SPIS1_Mode N/A USE_FAKE_PHY false INTG_MEM_CLK_ENTRY_CYCLES 10 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 PLL_C2P_WRITE_CLK_DIV 0 AFI_ODT_WIDTH 1 BONDING_OUT_ENABLED false IO_DQDQS_OUT_PHASE_MAX 0 CV_PORT_5_CONNECT_TO_AV_PORT 5 INCLUDE_BOARD_DELAY_MODEL false cfg_clk_hz 97368421 PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR {45000 ps} PLL_AFI_CLK_DIV 2 F2SDRAM_WR_PORT_USED 0x0 ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 PLL_AFI_PHY_CLK_DIV_PARAM 0 ENUM_PORT3_WIDTH PORT_32_BIT ENABLE_USER_ECC false CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 MEM_TRP_NS 13.75 JAVA_I2C3_DATA {I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}}} ADVANCED_CK_PHASES false ENUM_CFG_TYPE DDR3 JAVA_GUI_PIN_LIST {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} PRE_V_SERIES_FAMILY false INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 AFI_WLAT_WIDTH 6 PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 TPIUFPGA_Enable false PLL_MEM_CLK_FREQ 400.0 l3_mp_clk_div 1 F2SCLK_WARMRST_Enable false ENUM_PORT2_WIDTH PORT_32_BIT PLL_WRITE_CLK_DIV 2 LOANIO_Enable {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 JAVA_SDIO_DATA {SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV 0 NUM_EXTRA_REPORT_PATH 10 PLL_HR_CLK_MULT 0 CV_PORT_3_CONNECT_TO_AV_PORT 3 MEM_TREFI_US 7.8 PLL_DR_CLK_FREQ_SIM_STR {0 ps} main_pll_c5 15 main_pll_c4 3 PLL_HR_CLK_DIV_PARAM 0 main_pll_c3 3 TIMING_BOARD_SKEW_BETWEEN_DQS 0.08 periph_pll_n_auto 0 ENUM_PORT1_WIDTH PORT_32_BIT MEM_ASR Manual AVL_SIZE_WIDTH 3 l4_mp_clk_source 1 CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces false PLL_AFI_PHY_CLK_DIV_CACHE 0 CTI_Enable false dbg_at_clk_hz 25000000 CONTROLLER_LATENCY 5 S2FINTERRUPT_GPIO_Enable false INTG_EXTRA_CTL_CLK_RD_TO_RD 0 spi_m_clk_mhz 200.0 EARLY_ADDR_CMD_CLK_TRANSFER true FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 JAVA_QSPI_DATA {QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}}} CTL_CSR_CONNECTION INTERNAL_JTAG PERFORM_READ_AFTER_WRITE_CALIBRATION true main_nand_sdmmc_clk_mhz 3.613281 PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 1875 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 main_pll_c5_auto 18 TIMING_TIS 180 ENUM_GEN_DBE GEN_DBE_DISABLED REF_CLK_FREQ_STR {25.0 MHz} TIMING_BOARD_MAX_CK_DELAY 0.03 PLL_P2C_READ_CLK_MULT 0 MEM_TWR 6 TIMING_TIH 140 main_pll_n_auto 0 TIMING_BOARD_TIS 0.0 PLL_NIOS_CLK_PHASE_PS_STR {} AV_PORT_2_CONNECT_TO_CV_PORT 2 PLL_HR_CLK_PHASE_PS_STR {} TIMING_BOARD_TIH 0.0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 PLL_HR_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 ALLOCATED_RFIFO_PORT {None None None None None None} ENUM_CPORT2_TYPE DISABLE ENUM_ENABLE_INTR DISABLED main_pll_c1_internal 4 VECT_ATTR_COUNTER_ONE_MATCH 0 CTL_WR_TO_WR_EXTRA_CLK 0 usb_mp_clk_div_auto 0 MEM_CK_PHASE 0.0 VECT_ATTR_COUNTER_ZERO_MASK 0 IO_STANDARD SSTL-15 SPIM1_PinMuxing {HPS I/O Set 0} desired_qspi_clk_hz 400000000 desired_usb_mp_clk_mhz 200.0 desired_nand_clk_hz 12500000 BYTE_ENABLE true usb_mp_clk_hz 200000000 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 AVL_DATA_WIDTH_PORT_5 1 AVL_DATA_WIDTH_PORT_4 1 ENUM_MEM_IF_TCWL TCWL_8 AVL_DATA_WIDTH_PORT_3 1 PLL_MEM_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS 0 AVL_DATA_WIDTH_PORT_2 1 AVL_DATA_WIDTH_PORT_1 1 AVL_DATA_WIDTH_PORT_0 1 MAX_WRITE_LATENCY_COUNT_WIDTH 4 TEST_Enable false IS_ES_DEVICE_CACHE false MEM_INIT_EN false PLL_WRITE_CLK_FREQ_SIM_STR_PARAM {} ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 MEM_IF_CLK_PAIR_COUNT 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 HCX_COMPAT_MODE false PLL_AFI_CLK_PHASE_PS_PARAM 0 ENABLE_ISS_PROBES false PLL_WRITE_CLK_PHASE_PS 1875 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 sdmmc_clk_mhz 200.0 AFI_RATE_RATIO 1 MEM_IF_CHIP_BITS 1 CV_ENUM_PRIORITY_7_5 WEIGHT_0 MEM_AUTO_PD_CYCLES 0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 PLL_NIOS_CLK_PHASE_DEG 10.0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 TPIUFPGA_alt false l4_sp_clk_source 1 F2H_SDRAM3_CLOCK_FREQ 100 F2SDRAM_RST_PORT_USED 0x0 AC_ROM_USER_ADD_1 0_0000_0000_1000 AC_ROM_USER_ADD_0 0_0000_0000_0000 cfg_clk_mhz 97.368421 PLL_AFI_PHY_CLK_PHASE_PS_STR {} TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 DLL_SHARING_MODE None MEM_IF_DM_PINS_EN true FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 AVL_DATA_WIDTH_PORT {32 32 32 32 32 32} TIMING_TDS 30 INTG_CYC_TO_RLD_JARS_5 1 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL INTG_CYC_TO_RLD_JARS_4 1 DEBUG_MODE false F2SDRAM_Type {} INTG_CYC_TO_RLD_JARS_3 1 F2SCLK_SDRAMCLK_Enable false MEM_TRP 6 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_0 1 TIMING_TDH 65 PLL_AFI_CLK_PHASE_DEG 0.0 REF_CLK_FREQ_MIN_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE {2500 ps} TIMING_BOARD_TDS 0.0 MEM_IF_CONTROL_WIDTH 1 MEM_TRC 20 sdmmc_clk_source 2 DELAY_BUFFER_MODE HIGH PLL_MEM_CLK_MULT 32 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 DWIDTH_RATIO 2 MR2_ASR 0 JAVA_UART1_DATA {UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}}} IO_DQS_EN_PHASE_MAX 7 PLL_P2C_READ_CLK_PHASE_PS 0 USE_DQS_TRACKING true COMMAND_PHASE_CACHE 0.0 PLL_AFI_CLK_PHASE_PS_CACHE 0 use_default_mpu_clk true TIMING_BOARD_TDH 0.0 PLL_NIOS_CLK_PHASE_PS_SIM_STR {} USE_SHADOW_REGS false MAX_PENDING_RD_CMD 32 PLL_CONFIG_CLK_FREQ_STR {} mpu_base_clk_hz 925000000 AVL_DATA_WIDTH 64 PLL_AFI_PHY_CLK_FREQ 400.0 periph_nand_sdmmc_clk_mhz 200.0 desired_spi_m_clk_mhz 200.0 LRDIMM_INT 0 JAVA_CAN1_DATA {CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}}} EXTRA_SETTINGS {} PLL_HR_CLK_MULT_PARAM 0 ALLOCATED_WFIFO_PORT {None None None None None None} AC_ROM_MR1_MIRR 0000000000110 main_clk_hz 370000000 GPIO_Enable {No No No No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No Yes No No No No Yes No No No No No No No Yes No No No No Yes Yes No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} PLL_ADDR_CMD_CLK_DIV_PARAM 0 CV_ENUM_ENABLE_BONDING_5 DISABLED ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_ENABLE_BONDING_4 DISABLED ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_ENABLE_BONDING_3 DISABLED ENUM_CMD_PORT_IN_USE_3 FALSE MEM_IF_READ_DQS_WIDTH 4 CV_ENUM_ENABLE_BONDING_2 DISABLED ENUM_CMD_PORT_IN_USE_2 FALSE PLL_NIOS_CLK_FREQ_PARAM 0.0 CV_ENUM_ENABLE_BONDING_1 DISABLED ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_ENABLE_BONDING_0 DISABLED ENUM_CMD_PORT_IN_USE_0 FALSE ENUM_PRIORITY_7_5 WEIGHT_0 PLL_WRITE_CLK_FREQ_STR {400.0 MHz} ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK 100 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 I2C2_PinMuxing Unused ENUM_TEST_MODE NORMAL_MODE DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false I2C0_Mode I2C IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM {} can0_clk_hz 12500000 VECT_ATTR_DEBUG_SELECT_BYTE 0 emac0_clk_hz 1953125 REF_CLK_FREQ_MIN_CACHE 10.0 TIMING_BOARD_AC_TO_CK_SKEW 0.0 CTL_LOOK_AHEAD_DEPTH 4 main_pll_c2_internal 4 MPU_EVENTS_Enable false ENUM_AUTO_PCH_ENABLE_5 DISABLED INTG_RCFG_SUM_WT_PRIORITY_7 0 ENUM_AUTO_PCH_ENABLE_4 DISABLED INTG_RCFG_SUM_WT_PRIORITY_6 0 ENUM_AUTO_PCH_ENABLE_3 DISABLED INTG_RCFG_SUM_WT_PRIORITY_5 0 ENUM_AUTO_PCH_ENABLE_2 DISABLED INTG_RCFG_SUM_WT_PRIORITY_4 0 ENUM_AUTO_PCH_ENABLE_1 DISABLED INTG_RCFG_SUM_WT_PRIORITY_3 0 ENUM_AUTO_PCH_ENABLE_0 DISABLED INTG_RCFG_SUM_WT_PRIORITY_2 0 ENUM_ENABLE_DQS_TRACKING ENABLED INTG_RCFG_SUM_WT_PRIORITY_1 0 desired_usb_mp_clk_hz 200000000 INTG_RCFG_SUM_WT_PRIORITY_0 0 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.09 PLL_CONFIG_CLK_PHASE_PS_PARAM 0 LOW_LATENCY false CV_LSB_RFIFO_PORT_5 5 F2SCLK_DBGRST_Enable false CV_LSB_RFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_3 5 usb_mp_clk_div 0 CV_LSB_RFIFO_PORT_2 5 spi_m_clk_hz 200000000 PLL_HR_CLK_MULT_CACHE 0 CV_LSB_RFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_0 5 PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 ENUM_MASK_SBE_INTR DISABLED PLL_P2C_READ_CLK_FREQ_STR {} MEM_TRAS_NS 35.0 mpu_l2_ram_clk_mhz 462.5 cfg_h2f_user0_clk_mhz 97.368421 USB0_PinMuxing Unused DELAY_PER_DCHAIN_TAP 25 PLL_ADDR_CMD_CLK_DIV_CACHE 2 l3_sp_clk_div 1 ENUM_CPORT1_RFIFO_MAP FIFO_0 PLL_NIOS_CLK_FREQ_CACHE 0.0 MEM_CS_WIDTH 1 EXPORT_AFI_HALF_CLK false desired_sdmmc_clk_mhz 200.0 configure_advanced_parameters false MAX10_RTL_SEQ false PLL_MEM_CLK_FREQ_SIM_STR {2500 ps} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN 100 CTL_ODT_ENABLED true TIMING_BOARD_ISI_METHOD AUTO CV_ENUM_CPORT4_TYPE DISABLE PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CPORT4_WFIFO_MAP FIFO_0 UART0_Mode {No Flow Control} S2FCLK_USER0CLK_FREQ_HZ 97368421 S2FCLK_USER2CLK_Enable false CV_LSB_WFIFO_PORT_5 5 CV_LSB_WFIFO_PORT_4 5 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM {} MEM_CLK_FREQ_MAX 800.0 CV_LSB_WFIFO_PORT_3 5 periph_pll_c3_auto 4 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 CV_LSB_WFIFO_PORT_2 5 CV_LSB_WFIFO_PORT_1 5 CV_LSB_WFIFO_PORT_0 5 ENABLE_EMIT_JTAG_MASTER true CTL_DYNAMIC_BANK_ALLOCATION false CTL_AUTOPCH_EN false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false MEM_TWTR 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 PLL_CONFIG_CLK_PHASE_PS_CACHE 0 F2SDRAM_RD_PORT_USED 0x0 PLL_NIOS_CLK_PHASE_PS_SIM 0 S2FCLK_PENDINGRST_Enable false PLL_HR_CLK_PHASE_PS_SIM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_ADDR_CMD_CLK_PHASE_PS 1875 PLL_P2C_READ_CLK_PHASE_PS_STR {} USE_MM_ADAPTOR true AV_PORT_5_CONNECT_TO_CV_PORT 5 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 CTL_USR_REFRESH 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 CTL_SELF_REFRESH_EN false CFG_WRITE_ODT_CHIP 1 CTL_ENABLE_BURST_INTERRUPT_INT false MEM_WTCL 8 WEIGHT_PORT_5 0 WEIGHT_PORT_4 0 WEIGHT_PORT_3 0 WEIGHT_PORT_2 0 dbctrl_stayosc1 true WEIGHT_PORT_1 0 WEIGHT_PORT_0 0 CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 MEM_IF_COL_ADDR_WIDTH 10 dbg_timer_clk_hz 25000000 TRK_PARALLEL_SCC_LOAD false periph_pll_vco_auto_hz 1000000000 show_debug_info_as_warning_msg false IO_OUT1_DELAY_MAX 31 MEM_IF_SIM_VALID_WINDOW 0 MEM_INIT_FILE {} PLL_AFI_PHY_CLK_MULT_CACHE 0 SPIM1_Mode {Single Slave Select} hps_device_family {Cyclone V} F2H_SDRAM0_CLOCK_FREQ 100 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_FREQ_CACHE 0.0 l3_mp_clk_hz 185000000 PHY_CSR_CONNECTION INTERNAL_JTAG TB_RATE FULL S2FCLK_USER2CLK_FREQ 100.0 MR3_MPR_RF 0 PLL_P2C_READ_CLK_MULT_PARAM 0 desired_sdmmc_clk_hz 200000000 desired_cfg_clk_mhz 97.368421 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 MEM_RTT_NOM RZQ/4 AV_PORT_3_CONNECT_TO_CV_PORT 3 PLL_AFI_PHY_CLK_MULT 0 CONTROLLER_TYPE nextgen_v110 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 DQ_DDR 1 CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 dbg_clk_div 1 CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 S2FINTERRUPT_OSCTIMER_Enable false CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 PLL_HR_CLK_PHASE_PS_SIM_STR {} PLL_AFI_HALF_CLK_DIV_PARAM 0 REF_CLK_PS 40000.0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_MEM_IF_TWR TWR_6 can1_clk_div_auto 4 TIMING_BOARD_DERATE_METHOD AUTO CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 MEM_TRCD_NS 13.75 RATE Full SEQUENCER_TYPE NIOS ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 AVL_BE_WIDTH 8 LSB_RFIFO_PORT_5 5 LOCAL_CS_WIDTH 0 LSB_RFIFO_PORT_4 5 LSB_RFIFO_PORT_3 5 LSB_RFIFO_PORT_2 5 LSB_RFIFO_PORT_1 5 LSB_RFIFO_PORT_0 5 MEM_IF_NUMBER_OF_RANKS 1 MEM_CLK_EN_WIDTH 1 ENUM_CAL_REQ DISABLED l3_mp_clk_mhz 185.0 CV_ENUM_PORT5_WIDTH PORT_32_BIT emac0_clk_mhz 1.953125 CFG_ECC_DECODER_REG 0 ENUM_ATTR_COUNTER_ZERO_RESET DISABLED TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.16 PLL_P2C_READ_CLK_MULT_CACHE 0 quartus_ini_hps_ip_enable_test_interface false PLL_P2C_READ_CLK_FREQ_CACHE 0.0 INTG_MEM_AUTO_PD_CYCLES 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 REF_CLK_NS 40.0 TRACE_Mode N/A ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT MR1_TDQS 0 ENUM_CPORT4_TYPE DISABLE l4_mp_clk_div 1 OCT_SHARING_MODE None PLL_AFI_HALF_CLK_DIV_CACHE 2 LRDIMM_EXTENDED_CONFIG 0x000000000000000000 USE_MEM_CLK_FREQ false PLL_DR_CLK_PHASE_PS 0 desired_gpio_db_clk_hz 32000 CFG_POWER_SAVING_EXIT_CYCLES 5 S2FINTERRUPT_NAND_Enable false FORCE_DQS_TRACKING AUTO ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED EXTRA_VFIFO_SHIFT 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true NUM_WRITE_PATH_FLOP_STAGES 1 CSEL 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_CONFIG_CLK_PHASE_PS_STR {} MEM_ATCL_INT 0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_MASK_CORR_DROPPED_INTR DISABLED CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_DATA_WIDTH_PORT_4 1 PLL_AFI_HALF_CLK_FREQ 400.0 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_DATA_WIDTH_PORT_2 1 SKIP_MEM_INIT true CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_DATA_WIDTH_PORT_0 1 F2SINTERRUPT_Enable false USE_USER_RDIMM_VALUE false ENUM_MEM_IF_TRP TRP_6 MR2_RTT_WR 1 MEM_TCL 11 GPIO_Pin_Used_DERIVED true JAVA_CONFLICT_PIN {No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No} INTG_MEM_IF_TRFC 104 USE_2X_FF false ENUM_MEM_IF_TRC TRC_20 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 CTL_DEEP_POWERDN_EN false MEM_GUARANTEED_WRITE_INIT false MEM_IF_ADDR_WIDTH_MIN 13 default_mpu_clk_mhz 925.0 AVL_ADDR_WIDTH 27 DAT_DATA_WIDTH 32 UART1_PinMuxing Unused ENABLE_LARGE_RW_MGR_DI_BUFFER false PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} PLL_DR_CLK_FREQ_STR {} PLL_AFI_CLK_FREQ_PARAM 0.0 nand_clk_hz 50000000 can0_clk_div 1 DQS_IN_DELAY_MAX 31 JAVA_SPIM0_DATA {SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}}} USB0_Mode N/A PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM {} CFG_READ_ODT_CHIP 0 h2f_user0_clk_hz 97368421 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false PLL_CONFIG_CLK_MULT_PARAM 0 AVL_ADDR_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_4 1 JAVA_I2C0_DATA {I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}}} INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 AVL_ADDR_WIDTH_PORT_3 1 AC_ROM_MR3_MIRR 0000000000000 ENUM_MEM_IF_TCCD TCCD_4 AVL_ADDR_WIDTH_PORT_2 1 CV_ENUM_PRIORITY_0_5 WEIGHT_0 AVL_ADDR_WIDTH_PORT_1 1 CV_ENUM_PRIORITY_0_4 WEIGHT_0 AVL_ADDR_WIDTH_PORT_0 1 PLL_CONFIG_CLK_FREQ_PARAM 0.0 CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_0_0 WEIGHT_0 RDIMM false LWH2F_Enable true desired_emac0_clk_mhz 250.0 USE_LDC_AS_LOW_SKEW_CLOCK false PLL_P2C_READ_CLK_PHASE_PS_SIM 0 ENUM_PORT5_WIDTH PORT_32_BIT I2C2_Mode N/A MR0_WR 2 F2SDRAM_Width {} dbg_clk_hz 12500000 PLL_AFI_CLK_FREQ 400.0 ENUM_WR_PORT_INFO_5 USE_NO FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 TIMING_BOARD_TDS_APPLIED 0.18 ENUM_WR_PORT_INFO_4 USE_NO CTL_REGDIMM_ENABLED false ENABLE_ABSTRACT_RAM false FORCE_SYNTHESIS_LANGUAGE {} ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_0 USE_NO ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL F2H_SDRAM4_CLOCK_FREQ 100 ADVERTIZE_SEQUENCER_SW_BUILD_FILES false PLL_AFI_CLK_FREQ_CACHE 400.0 ENUM_PORT4_WIDTH PORT_32_BIT PLL_NIOS_CLK_FREQ 66.6666666667 dbg_timer_clk_mhz 25.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE {2500 ps} FORCE_MAX_LATENCY_COUNT_WIDTH 0 SPIS0_PinMuxing Unused PLL_AFI_HALF_CLK_MULT_PARAM 0 S2FINTERRUPT_USB_Enable false PLL_CONFIG_CLK_MULT_CACHE 0 TRACE_PinMuxing Unused l4_sp_clk_hz 100000000 PLL_DR_CLK_PHASE_DEG 0.0 AC_PARITY false desired_nand_clk_mhz 12.5 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_CACHE 0.0 ENUM_ATTR_STATIC_CONFIG_VALID DISABLED customize_device_pll_info false ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 MEM_TDQSCK 1 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_PRIORITY_0_0 WEIGHT_0 ENABLE_NIOS_PRINTF_OUTPUT false ABSTRACT_REAL_COMPARE_TEST false RATE_CACHE Full PLL_MASTER true USE_HPS_DQS_TRACKING false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 PLL_DR_CLK_MULT_PARAM 0 BOOTFROMFPGA_Enable false periph_pll_c5_auto 9 PLL_P2C_READ_CLK_DIV 0 PLL_DR_CLK_FREQ_PARAM 0.0 CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 spi_m_clk_div_auto 0 dbg_at_clk_div 0 ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED PLL_WRITE_CLK_PHASE_PS_SIM_STR {1875 ps} USE_MEM_CLK_FREQ_CACHE false MEM_IF_ROW_ADDR_WIDTH 15 ENUM_CLR_INTR NO_CLR_INTR INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM {} h2f_user1_clk_mhz 100.0 PLL_AFI_HALF_CLK_MULT_CACHE 32 MEM_RANK_MULTIPLICATION_FACTOR 1 PLL_AFI_HALF_CLK_MULT 32 AV_PORT_4_CONNECT_TO_CV_PORT 4 desired_mpu_clk_hz 800000000 PLL_AFI_HALF_CLK_FREQ_CACHE 400.0 AFI_WRITE_DQS_WIDTH 4 ENUM_OUTPUT_REGD DISABLED usb_mp_clk_mhz 200.0 PLL_MEM_CLK_PHASE_DEG_SIM 0.0 desired_emac0_clk_hz 250000000 eosc2_clk_hz 25000000 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.16 desired_can1_clk_mhz 100.0 l3_sp_clk_mhz 92.5 CV_ENUM_PRIORITY_3_5 WEIGHT_0 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_COL_ADDR_WIDTH 10 CV_ENUM_PRIORITY_3_4 WEIGHT_0 NEXTGEN true nand_x_clk_mhz 200.0 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 main_pll_vco_mhz 1600.0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 F2SCLK_SDRAMCLK_FREQ_MHZ 0.0 TIMING_BOARD_TIS_APPLIED 0.33 EMAC0_PTP false CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 PLL_DR_CLK_MULT_CACHE 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR {1875 ps} PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_FREQ_SIM_STR {2500 ps} F2SCLK_PERIPHCLK_FREQ_MHZ 0.0 PLL_DR_CLK_FREQ_CACHE 0.0 IO_DQS_OUT_RESERVE 4 TREFI 35100 l4_sp_clk_div 1 PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 MEM_IF_ADDR_WIDTH 15 ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 ENUM_MEM_IF_TFAW TFAW_12 PLL_ADDR_CMD_CLK_PHASE_PS_STR {1875 ps} PLL_AFI_PHY_CLK_DIV 1000000 AC_ROM_MR0_DLL_RESET_MIRR 0010011101000 H2F_AXI_CLOCK_FREQ 50000000 MEM_CK_WIDTH 1 ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_GEN_SBE GEN_SBE_DISABLED MEM_DRV_STR RZQ/7 MEM_IF_DM_WIDTH 4 DEVICE_FAMILY {Cyclone V} PLL_HR_CLK_FREQ_SIM_STR_CACHE {} DQS_DQSN_MODE DIFFERENTIAL NAND_PinMuxing Unused EMAC0_PinMuxing Unused S2FCLK_USER1CLK_FREQ_HZ 100000000 VCALIB_COUNT_WIDTH 2 MEM_TRRD_NS 7.7 MR0_PD 0 JAVA_EMAC1_DATA {EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} MR3_MPR_AA 0 PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV INTG_POWER_SAVING_EXIT_CYCLES 5 SYS_INFO_DEVICE_FAMILY {Cyclone V} CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 MEM_DQ_WIDTH 32 PRIORITY_PORT {1 1 1 1 1 1} ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CTL_DYNAMIC_BANK_NUM 4 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 MEM_ADD_LAT 0 AFI_BANKADDR_WIDTH 6 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 JAVA_SPIS1_DATA {SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}}} ENUM_PRIORITY_3_0 WEIGHT_0 PLL_AFI_CLK_MULT 32 PLL_AFI_HALF_CLK_PHASE_PS_STR {0 ps} dbg_trace_clk_div 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 PLL_MEM_CLK_PHASE_PS_CACHE 0 MR3_DS 2 PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 MEM_TFAW_NS 30.0 DELAY_PER_OPA_TAP 312 ADDR_RATE_RATIO 2 PLL_C2P_WRITE_CLK_FREQ_SIM_STR {0 ps} SDIO_PinMuxing {HPS I/O Set 0} MEM_IF_CS_PER_RANK 1 PINGPONGPHY_EN false S2FINTERRUPT_SPISLAVE_Enable false CAN0_Mode N/A PARSE_FRIENDLY_DEVICE_FAMILY_PARAM {} INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 PLL_NIOS_CLK_MULT 0 PLL_WRITE_CLK_FREQ_SIM_STR {2500 ps} WRBUFFER_ADDR_WIDTH 6 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM {} TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM {} dbg_clk_mhz 12.5 ENUM_ENABLE_BONDING_WRAPBACK DISABLED MEM_LRDIMM_ENABLED false RDBUFFER_ADDR_WIDTH 8 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 DEVICE_FAMILY_PARAM {} TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 AFI_WRANK_WIDTH 0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 PLL_NIOS_CLK_DIV 6000000 CV_ENUM_PRIORITY_6_2 WEIGHT_0 SEQ_MODE 0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4 DISCRETE_FLY_BY true WEIGHT_PORT {0 0 0 0 0 0} PLL_MEM_CLK_DIV 2 ENUM_MEM_IF_TCL TCL_11 MEM_IF_BOARD_BASE_DELAY 10 ENUM_MEM_IF_TRTP TRTP_3 CALIB_REG_WIDTH 8 PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV CV_ENUM_CPORT1_TYPE DISABLE EMAC0_Mode N/A PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE {} PLL_HR_CLK_FREQ_PARAM 0.0 MEM_SRT Normal PRIORITY_PORT_5 1 PRIORITY_PORT_4 1 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE {} PRIORITY_PORT_3 1 PRIORITY_PORT_2 1 PRIORITY_PORT_1 1 PRIORITY_PORT_0 1 periph_pll_c0_auto 511 l4_mp_clk_mhz 100.0 desired_can1_clk_hz 100000000 MEM_VENDOR JEDEC device_pll_info_auto {{320000000 1850000000} {320000000 1000000000} {925000000 400000000 400000000}} FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false CFG_MEM_CLK_ENTRY_CYCLES 10 JAVA_USB0_DATA {USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}}} SPIS0_Mode N/A ALTMEMPHY_COMPATIBLE_MODE false MEM_FORMAT DISCRETE USB1_PinMuxing {HPS I/O Set 0} CORE_DEBUG_CONNECTION EXPORT ENUM_CPORT2_RFIFO_MAP FIFO_0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM {} PLL_C2P_WRITE_CLK_DIV_CACHE 0 DQS_DELAY_CHAIN_PHASE_SETTING 0 CTL_USR_REFRESH_EN false ENUM_RD_PORT_INFO_5 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_MEM_IF_TRRD TRRD_4 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_0 USE_NO ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 AVL_NUM_SYMBOLS_PORT_5 1 S2F_Width 2 AVL_NUM_SYMBOLS_PORT_4 1 AVL_NUM_SYMBOLS_PORT_3 1 AVL_NUM_SYMBOLS_PORT_2 1 show_advanced_parameters false AVL_NUM_SYMBOLS_PORT_1 1 ENABLE_NON_DES_CAL false AVL_NUM_SYMBOLS_PORT_0 1 ENUM_CPORT5_WFIFO_MAP FIFO_0 JAVA_I2C2_DATA {I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}}} RDIMM_CONFIG 0000000000000000 PLL_HR_CLK_FREQ_CACHE 0.0 TB_PLL_DLL_MASTER true MEM_PD {DLL off} main_pll_c2_internal_auto 4 S2FCLK_USER0CLK_FREQ 97.368421 MR2_CWL 3 PLL_P2C_READ_CLK_DIV_PARAM 0 S2FCLK_USER2CLK 5 USE_LDC_FOR_ADDR_CMD false ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL NUM_WRITE_FR_CYCLE_SHIFTS 0 AP_MODE false ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CAN0_PinMuxing Unused CV_AVL_ADDR_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_2 1 PHY_VERSION_NUMBER 211 ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_AVL_ADDR_WIDTH_PORT_1 1 ENUM_STATIC_WEIGHT_4 WEIGHT_0 FAST_SIM_CALIBRATION false CV_AVL_ADDR_WIDTH_PORT_0 1 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 MEM_VERBOSE true ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CTL_SELF_REFRESH 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 periph_pll_m_auto 39 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE {} CV_AVL_NUM_SYMBOLS_PORT_3 1 ENABLE_CSR_SOFT_RESET_REQ true CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_AVL_NUM_SYMBOLS_PORT_1 1 DQS_EN_DELAY_MAX 31 CV_AVL_NUM_SYMBOLS_PORT_0 1 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM {} CUT_NEW_FAMILY_TIMING true CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 can0_clk_mhz 12.5 IO_OUT2_DELAY_MAX 0 NUM_OCT_SHARING_INTERFACES 1 PLL_DR_CLK_PHASE_PS_SIM_STR {} periph_pll_source 0 HPS_PROTOCOL DDR3 PLL_HR_CLK_PHASE_PS_PARAM 0 main_pll_c1_internal_auto 4 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 1875 MEM_MIRROR_ADDRESSING 0 main_pll_c4_auto 511 CTL_ECC_MULTIPLES_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 PLL_CLK_CACHE_VALID true ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 PLL_P2C_READ_CLK_DIV_CACHE 0 main_pll_m_auto 73 ENUM_MMR_CFG_MEM_BL MP_BL_8 LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 REFRESH_INTERVAL 15000 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 PLL_WRITE_CLK_FREQ 400.0 ENUM_CPORT1_TYPE DISABLE ENUM_READ_ODT_CHIP ODT_DISABLED CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 SEQ_BURST_COUNT_WIDTH 2 MEM_VOLTAGE {1.5V DDR3} MR2_SRT 0 PLL_MEM_CLK_MULT_PARAM 0 MEM_ROW_ADDR_WIDTH 15 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 desired_l4_mp_clk_mhz 100.0 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 nand_clk_source 2 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 l4_mp_clk_div_auto 1 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_DWIDTH_0 DWIDTH_0 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE {} main_pll_c0_internal_auto 1 MR2_SRF 0 ENUM_DISABLE_MERGING MERGING_ENABLED USER_DEBUG_LEVEL 1 PLL_HR_CLK_PHASE_PS_CACHE 0 ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED PLL_AFI_PHY_CLK_PHASE_DEG 0.0 gpio_db_clk_hz 32000 F2H_SDRAM5_CLOCK_FREQ 100 ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 MR0_BT 0 PLL_CONFIG_CLK_FREQ 22.2222222222 ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL MR1_RTT 1 periph_qspi_clk_mhz 1.953125 MR0_BL 1 HARD_PHY true DEBUGAPB_Enable false INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 PLL_ADDR_CMD_CLK_FREQ_STR {400.0 MHz} MEM_TRTP_NS 7.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK 100 PLL_MEM_CLK_PHASE_PS_SIM_STR {0 ps} PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM {} desired_l4_sp_clk_hz 100000000 PLL_MEM_CLK_MULT_CACHE 32 STARVE_LIMIT 10 PLL_C2P_WRITE_CLK_PHASE_PS 0 CFG_ERRCMD_FIFO_REG 0 ED_EXPORT_SEQ_DEBUG false dbg_at_clk_mhz 25.0 AVL_PORT {{Port 0}} PLL_HR_CLK_PHASE_DEG 0.0 S2FINTERRUPT_SPIMASTER_Enable false ENABLE_ABS_RAM_MEM_INIT false DUPLICATE_PLL_FOR_PHY_CLK true MEM_RTT_WR RZQ/4 TIMING_TDQSCK 255 REF_CLK_FREQ_CACHE 25.0 AC_ROM_MR0_DLL_RESET 0010101110000 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_DELAY_BONDING BONDING_LATENCY_0 STM_Enable false PLL_AFI_CLK_PHASE_PS 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 MAX10_CFG false LSB_WFIFO_PORT_5 5 LSB_WFIFO_PORT_4 5 LSB_WFIFO_PORT_3 5 LSB_WFIFO_PORT_2 5 LSB_WFIFO_PORT_1 5 LSB_WFIFO_PORT_0 5 JAVA_UART0_DATA {UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}}} PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR {} PLL_AFI_PHY_CLK_PHASE_PS 0 NUM_DLL_SHARING_INTERFACES 1 JAVA_CAN0_DATA {CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}}} PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR {15000 ps} ENUM_THLD_JAR2_5 THRESHOLD_16 USE_SEQUENCER_BFM false ENUM_THLD_JAR2_4 THRESHOLD_16 PLL_HR_CLK_FREQ_SIM_STR {0 ps} ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 ENABLE_EXTRA_REPORTING false ENUM_THLD_JAR2_0 THRESHOLD_16 AC_ROM_MR0_MIRR 0010001101001 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 ENABLE_NON_DESTRUCTIVE_CALIB false PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE {} ENUM_MEM_IF_MEMTYPE DDR3_SDRAM quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces false MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 l4_sp_clk_mhz 100.0 ENABLE_MAX_SIZE_SEQ_MEM false quartus_ini_hps_ip_suppress_sdram_synth false device_pll_info_manual {{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}} ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL H2F_DEBUG_APB_CLOCK_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 DLL_OFFSET_CTRL_WIDTH 6 CFG_REORDER_DATA true GPIO_Name_DERIVED {GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55 GPIO56 GPIO57 GPIO58 GPIO59 GPIO60 GPIO61 GPIO62 GPIO63 GPIO64 GPIO65 GPIO66} PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false CALIB_LFIFO_OFFSET 12 TIMING_BOARD_AC_SLEW_RATE 1.0 DLL_DELAY_CTRL_WIDTH 7 PLL_DR_CLK_PHASE_PS_STR {} TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_0 DWIDTH_0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 SOPC_COMPAT_RESET false PLL_AFI_CLK_FREQ_STR {400.0 MHz} CSR_DATA_WIDTH 8 PLL_AFI_CLK_FREQ_SIM_STR_PARAM {} I2C0_PinMuxing {HPS I/O Set 0} MEM_TREFI 3120 VFIFO_AS_SHIFT_REG true S2FCLK_USER2CLK_FREQ_HZ 100000000 PLL_WRITE_CLK_MULT 32 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 dbg_trace_clk_mhz 25.0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.09 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 PLL_AFI_PHY_CLK_FREQ_STR {} CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED PLL_AFI_PHY_CLK_FREQ_SIM_STR {2500 ps} PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_NIOS_CLK_PHASE_PS 0 IO_DQS_IN_RESERVE 4 CV_ENUM_CPORT3_TYPE DISABLE MEM_TMRD_CK 4 PLL_AFI_CLK_PHASE_PS_STR {0 ps} PLL_DR_CLK_PHASE_PS_PARAM 0 DQS_PHASE_SHIFT 0 periph_pll_c2_auto 511 MEM_BT Sequential HLGPI_Enable false NEGATIVE_WRITE_CK_PHASE true ENABLE_ABS_RAM_INTERNAL false main_clk_mhz 370.0 MEM_BL OTF PLL_CONFIG_CLK_MULT 0 CALIB_VFIFO_OFFSET 10 TG_TEMP_PORT_5 0 TG_TEMP_PORT_4 0 ENUM_MEM_IF_TRCD TRCD_6 DMA_Enable {No No No No No No No No} TG_TEMP_PORT_3 0 TG_TEMP_PORT_2 0 SPIS1_PinMuxing Unused TG_TEMP_PORT_1 0 F2H_AXI_CLOCK_FREQ 50000000 TG_TEMP_PORT_0 0 MEM_TYPE DDR3 PLL_NIOS_CLK_PHASE_PS_PARAM 0 TIMING_BOARD_TDH_APPLIED 0.165 NON_LDC_ADDR_CMD_MEM_CK_INVERT false MR1_WR 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 MR1_WL 0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 PLL_AFI_CLK_FREQ_SIM_STR_CACHE {2500 ps} emac1_clk_mhz 250.0 ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS MR1_WC 0 ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS MEM_TINIT_US 500 ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_0 ASYNCHRONOUS PLL_MEM_CLK_DIV_PARAM 0 MEM_ATCL Disabled PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 ENUM_CPORT2_WFIFO_MAP FIFO_0 S2FCLK_USER0CLK_Enable false DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CFG_INTERFACE_WIDTH 32 TIMING_BOARD_SKEW_WITHIN_DQS 0.01 ENUM_MEM_IF_TRAS TRAS_14 PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR {0 ps} USE_HARD_READ_FIFO false MR1_ODS 1 SPEED_GRADE 7 ENABLE_NIOS_JTAG_UART false SPIM0_Mode N/A AFI_CONTROL_WIDTH 2 TIMING_BOARD_AC_SKEW 0.03 PLL_DR_CLK_PHASE_PS_CACHE 0 MR0_CAS_LATENCY 7 H2F_LW_AXI_CLOCK_FREQ 50000000 PLL_C2P_WRITE_CLK_PHASE_PS_STR {} ADD_EXTERNAL_SEQ_DEBUG_NIOS false ENABLE_NON_DES_CAL_TEST false INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_STR {400.0 MHz} PLL_NIOS_CLK_FREQ_STR {} F2S_Width 2 PHY_CLKBUF false desired_l4_sp_clk_mhz 100.0 PLL_WRITE_CLK_PHASE_PS_STR {1875 ps} PLL_NIOS_CLK_PHASE_PS_CACHE 0 ENUM_SINGLE_READY_3 CONCATENATE_RDY USE_FAKE_PHY_INTERNAL false ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 REGISTER_C2P false can1_clk_hz 12500000 CV_PORT_0_CONNECT_TO_AV_PORT 0 emac1_clk_hz 250000000 eosc2_clk_mhz 25.0 PLL_MEM_CLK_DIV_CACHE 2 periph_base_clk_mhz 200.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM {} EMAC1_PTP false quartus_ini_hps_ip_fast_f2sdram_sim_model false PLL_AFI_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 MR1_RDQS 0 MEM_AUTO_LEVELING_MODE true CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 mpu_base_clk_mhz 925.0 ENUM_CFG_INTERFACE_WIDTH DWIDTH_32 CFG_TCCD_NS 2.5 TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 NUM_SUBGROUP_PER_READ_DQS 1 TRFC 350 CALIBRATION_MODE Skip C2P_WRITE_CLOCK_ADD_PHASE 0.0 MEM_T_WL 8 PLL_NIOS_CLK_DIV_CACHE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 TIMING_BOARD_TIH_APPLIED 0.24 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM {} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN 100 EMAC1_PinMuxing {HPS I/O Set 0} INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 can1_clk_div 1 MEM_CLK_FREQ_CACHE 400.0 ENUM_CPORT3_TYPE DISABLE TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM {} MR2_RLWL 1 REF_CLK_FREQ 25.0 desired_cfg_clk_hz 97368421 desired_spi_m_clk_hz 200000000 main_qspi_clk_hz 3613281 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_ENABLE_BONDING_5 DISABLED TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 PLL_P2C_READ_CLK_FREQ_SIM_STR {0 ps} ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_1 DISABLED PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} ENUM_ENABLE_BONDING_0 DISABLED PLL_AFI_CLK_DIV_CACHE 2 PLL_C2P_WRITE_CLK_MULT_CACHE 0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CFG_SELF_RFSH_EXIT_CYCLES 512 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM {} DB_periph_ifaces {USB0 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb0 usb0_clk_in} usb0 {@no_export 0 properties {} type conduit direction Input} usb0_clk_in {@no_export 0 properties {} type clock direction Input}}} UART1 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart1 uart1 {@no_export 0 properties {} type conduit direction Input}}} UART0 {atom_name hps_interface_peripheral_uart interfaces {@orderednames uart0 uart0 {@no_export 0 properties {} type conduit direction Input}}} SDIO {atom_name hps_interface_peripheral_sdmmc interfaces {sdio_cclk {@no_export 0 properties {} type clock direction Output} sdio {@no_export 0 properties {} type conduit direction Input} @orderednames {sdio sdio_reset sdio_cclk} sdio_reset {@no_export 0 properties {synchronousEdges none} type reset direction Output}}} I2C3 {atom_name hps_interface_peripheral_i2c interfaces {i2c3_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c3_scl_in i2c3_clk i2c3} i2c3 {@no_export 0 properties {} type conduit direction Input} i2c3_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C2 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c2_scl_in i2c2_clk i2c2} i2c2 {@no_export 0 properties {} type conduit direction Input} i2c2_clk {@no_export 0 properties {} type clock direction Output} i2c2_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C1 {atom_name hps_interface_peripheral_i2c interfaces {i2c1_clk {@no_export 0 properties {} type clock direction Output} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1 {@no_export 0 properties {} type conduit direction Input} i2c1_scl_in {@no_export 0 properties {} type clock direction Input}}} I2C0 {atom_name hps_interface_peripheral_i2c interfaces {@orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0_clk {@no_export 0 properties {} type clock direction Output} i2c0 {@no_export 0 properties {} type conduit direction Input} i2c0_scl_in {@no_export 0 properties {} type clock direction Input}}} @orderednames {EMAC0 EMAC1 NAND QSPI SDIO USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 UART0 UART1 I2C0 I2C1 I2C2 I2C3 CAN0 CAN1} CAN1 {atom_name hps_interface_peripheral_can interfaces {can1 {@no_export 0 properties {} type conduit direction Input} @orderednames can1}} CAN0 {atom_name hps_interface_peripheral_can interfaces {can0 {@no_export 0 properties {} type conduit direction Input} @orderednames can0}} QSPI {atom_name hps_interface_peripheral_qspi interfaces {qspi {@no_export 0 properties {} type conduit direction Input} @orderednames {qspi_sclk_out qspi} qspi_sclk_out {@no_export 0 properties {} type clock direction Output}}} SPIM1 {atom_name hps_interface_peripheral_spi_master interfaces {spim1_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim1 spim1_sclk_out} spim1 {@no_export 0 properties {} type conduit direction Input}}} NAND {atom_name hps_interface_peripheral_nand interfaces {@orderednames nand nand {@no_export 0 properties {} type conduit direction Input}}} SPIM0 {atom_name hps_interface_peripheral_spi_master interfaces {spim0_sclk_out {@no_export 0 properties {} type clock direction Output} @orderednames {spim0 spim0_sclk_out} spim0 {@no_export 0 properties {} type conduit direction Input}}} SPIS1 {atom_name hps_interface_peripheral_spi_slave interfaces {spis1_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis1 spis1_sclk_in} spis1 {@no_export 0 properties {} type conduit direction Input}}} SPIS0 {atom_name hps_interface_peripheral_spi_slave interfaces {spis0_sclk_in {@no_export 0 properties {} type clock direction Input} @orderednames {spis0 spis0_sclk_in} spis0 {@no_export 0 properties {} type conduit direction Input}}} EMAC1 {atom_name hps_interface_peripheral_emac interfaces {emac1_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_rx_clk_in {@no_export 0 properties {} type clock direction Input} emac1_tx_reset {@no_export 0 properties {associatedClock emac1_tx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_rx_reset {@no_export 0 properties {associatedClock emac1_rx_clk_in associatedResetSinks none} type reset direction Output} emac1_md_clk {@no_export 0 properties {} type clock direction Output} emac1_gtx_clk {@no_export 0 properties {} type clock direction Output} emac1 {@no_export 0 properties {} type conduit direction Input}}} EMAC0 {atom_name hps_interface_peripheral_emac interfaces {emac0_rx_reset {@no_export 0 properties {associatedClock emac0_rx_clk_in associatedResetSinks none} type reset direction Output} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_tx_reset {@no_export 0 properties {associatedClock emac0_tx_clk_in associatedResetSinks none} type reset direction Output} emac0_md_clk {@no_export 0 properties {} type clock direction Output} emac0_gtx_clk {@no_export 0 properties {} type clock direction Output} emac0 {@no_export 0 properties {} type conduit direction Input} emac0_tx_clk_in {@no_export 0 properties {} type clock direction Input} emac0_rx_clk_in {@no_export 0 properties {} type clock direction Input}}} USB1 {atom_name hps_interface_peripheral_usb interfaces {@orderednames {usb1 usb1_clk_in} usb1 {@no_export 0 properties {} type conduit direction Input} usb1_clk_in {@no_export 0 properties {} type clock direction Input}}}} CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 ADDR_ORDER 0 periph_nand_sdmmc_clk_hz 200000000 CTL_HRB_ENABLED false TB_MEM_IF_READ_DQS_WIDTH 4 ENABLE_LDC_MEM_CK_ADJUSTMENT false MR3_MPR 0 IO_DQS_EN_DELAY_OFFSET 0 h2f_user0_clk_mhz 97.368421 ENUM_ENABLE_FAST_EXIT_PPD DISABLED CFG_PDN_EXIT_CYCLES 10 DELAY_CHAIN_LENGTH 8 COMMAND_PHASE 0.0 ENUM_USER_ECC_EN DISABLE CTL_ENABLE_WDATA_PATH_LATENCY false USE_AXI_ADAPTOR false PLL_AFI_CLK_PHASE_PS_SIM_STR {0 ps} MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE {5000 ps} MAKE_INTERNAL_NIOS_VISIBLE false PLL_DR_CLK_PHASE_PS_SIM 0 HCX_COMPAT_MODE_CACHE false CV_ENUM_PORT1_WIDTH PORT_32_BIT qspi_clk_mhz 3.613281 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE {} CV_ENUM_WR_PORT_INFO_5 USE_NO CV_ENUM_WR_PORT_INFO_4 USE_NO CV_ENUM_WR_PORT_INFO_3 USE_NO ENUM_ENABLE_PIPELINEGLOBAL DISABLED CV_ENUM_WR_PORT_INFO_2 USE_NO CV_ENUM_WR_PORT_INFO_1 USE_NO CV_ENUM_WR_PORT_INFO_0 USE_NO GENERIC_PLL true CTL_ECC_MULTIPLES_16_24_40_72 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 AUTO_PD_CYCLES 0 PLL_MEM_CLK_PHASE_PS_STR {0 ps} MEM_TFAW 12 S2FINTERRUPT_DMA_Enable false LRDIMM false AFI_DM_WIDTH 8 CTL_ENABLE_BURST_TERMINATE_INT false PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE {0 ps} CV_ENUM_PORT0_WIDTH PORT_32_BIT PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_DEG 0.0 F2H_SDRAM1_CLOCK_FREQ 100 ENUM_PRIORITY_2_5 WEIGHT_0 MEM_T_RL 11 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 MEM_IF_CS_WIDTH 1 PLL_AFI_CLK_PHASE_PS_SIM 0 nand_x_clk_hz 200000000 MR0_DLL 1 CORE_PERIPHERY_DUAL_CLOCK false DB_bfm_types {} periph_pll_vco_auto_mhz 1000.0 NAND_Mode N/A PLL_MEM_CLK_PHASE_PS 0 REF_CLK_FREQ_PARAM_VALID false DUPLICATE_AC false CPORT_TYPE_PORT {Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional} gpio_db_clk_div_auto 6249 H2F_CTI_CLOCK_FREQ 100 CFG_ENABLE_NO_DM 0 MEM_DQ_PER_DQS 8 AC_ROM_MR2_MIRR 0001000011000 MEM_IF_CS_PER_DIMM 1 PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 AFI_RRANK_WIDTH 0 mpu_clk_hz 925000000 ENUM_MASK_DBE_INTR DISABLED F2SDRAM_CMD_PORT_USED 0x0 I2C3_PinMuxing Unused ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL PLL_PHASE_COUNTER_WIDTH 4 ADDR_CMD_DDR 1 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL default_mpu_clk_hz 925000000 quartus_ini_hps_ip_enable_bsel_csel false I2C1_Mode I2C quartus_ini_hps_ip_f2sdram_bonding_out false PLL_C2P_WRITE_CLK_MULT 0 CTL_ENABLE_BURST_TERMINATE false ADD_EFFICIENCY_MONITOR false ENUM_CPORT3_RFIFO_MAP FIFO_0 ABS_RAM_MEM_INIT_FILENAME meminit CFG_CLR_INTR 0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM {} S2FINTERRUPT_EMAC_Enable false AFI_CS_WIDTH 1 CSR_ADDR_WIDTH 10 INTG_MEM_IF_TREFI 3120 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 MAX_LATENCY_COUNT_WIDTH 5 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 MEM_IF_ODT_WIDTH 1 ENUM_REORDER_DATA DATA_REORDERING MARGIN_VARIATION_TEST false DEVICE_DEPTH 1 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 main_pll_vco_auto_hz 1850000000 NUM_PLL_SHARING_INTERFACES 1 AFI_CLK_PAIR_COUNT 1 PLL_WRITE_CLK_PHASE_PS_SIM 1875 PLL_SHARING_MODE None ENABLE_DELAY_CHAIN_WRITE false l3_sp_clk_hz 92500000 ENUM_ENABLE_BURST_TERMINATE DISABLED CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 MEM_IF_BANKADDR_WIDTH 3 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 PLL_MEM_CLK_FREQ_STR {400.0 MHz} CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CTL_ECC_ENABLED false CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 mpu_clk_mhz 925.0 IO_DM_OUT_RESERVE 0 ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 MEM_TRTP 3 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 CAN1_PinMuxing Unused ENABLE_EMIT_BFM_MASTER false INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 CV_ENUM_CPORT5_TYPE DISABLE ENUM_CPORT0_WFIFO_MAP FIFO_0 UART1_Mode N/A PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 periph_pll_c4_auto 4 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE {} MEM_TRFC_NS 260.0 AC_ROM_MR1_CALIB {} CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 TRACKING_ERROR_TEST false POWER_OF_TWO_BUS false ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface false ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 FLY_BY true ENUM_PRIORITY_5_1 WEIGHT_0 main_nand_sdmmc_clk_hz 3613281 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 PLL_WRITE_CLK_MULT_PARAM 0 AFI_CLK_EN_WIDTH 1 PLL_DR_CLK_DIV 0 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 PLL_WRITE_CLK_FREQ_PARAM 0.0 can0_clk_div_auto 4 ENUM_PORT0_WIDTH PORT_32_BIT CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 IS_ES_DEVICE false AC_ROM_MR0_CALIB {} DLL_USE_DR_CLK false ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 DB_iface_ports {can0 {can0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {can0_rxd can0_txd} can0_txd {atom_signal_name txd direction Output role txd}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} emac1 {emac1_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i} emac1_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac1_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} emac1_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} @orderednames {emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i} emac1_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac1_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac1_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac1_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac1_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac1_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac1_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac1_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac1_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i}} emac0 {emac0_phy_rxd_i {atom_signal_name phy_rxd_i direction Input role phy_rxd_i} emac0_phy_crs_i {atom_signal_name phy_crs_i direction Input role phy_crs_i} emac0_phy_rxer_i {atom_signal_name phy_rxer_i direction Input role phy_rxer_i} @orderednames {emac0_phy_txd_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i} emac0_ptp_pps_o {atom_signal_name ptp_pps_o direction Output role ptp_pps_o} emac0_phy_rxdv_i {atom_signal_name phy_rxdv_i direction Input role phy_rxdv_i} emac0_phy_col_i {atom_signal_name phy_col_i direction Input role phy_col_i} emac0_gmii_mdo_o_e {atom_signal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e} emac0_gmii_mdi_i {atom_signal_name gmii_mdi_i direction Input role gmii_mdi_i} emac0_phy_txer_o {atom_signal_name phy_txer_o direction Output role phy_txer_o} emac0_gmii_mdo_o {atom_signal_name gmii_mdo_o direction Output role gmii_mdo_o} emac0_phy_txd_o {atom_signal_name phy_txd_o direction Output role phy_txd_o} emac0_phy_txen_o {atom_signal_name phy_txen_o direction Output role phy_txen_o} emac0_ptp_aux_ts_trig_i {atom_signal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i}} sdio_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {atom_signal_name cclk_out direction Output role clk}} i2c1_clk {@orderednames i2c1_out_clk i2c1_out_clk {atom_signal_name out_clk direction Output role clk}} sdio {sdmmc_cmd_o {atom_signal_name cmd_o direction Output role cmd_o} @orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_en sdmmc_data_i sdmmc_data_o sdmmc_data_en} sdmmc_cmd_i {atom_signal_name cmd_i direction Input role cmd_i} sdmmc_data_o {atom_signal_name data_o direction Output role data_o} sdmmc_card_intn_i {atom_signal_name card_intn_i direction Input role card_intn_i} sdmmc_vs_o {atom_signal_name vs_o direction Output role vs_o} sdmmc_data_en {atom_signal_name data_en direction Output role data_en} sdmmc_data_i {atom_signal_name data_i direction Input role data_i} sdmmc_cmd_en {atom_signal_name cmd_en direction Output role cmd_en} sdmmc_pwr_ena_o {atom_signal_name pwr_ena_o direction Output role pwr_ena_o} sdmmc_wp_i {atom_signal_name wp_i direction Input role wp_i} sdmmc_cdn_i {atom_signal_name cdn_i direction Input role cdn_i}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk}} emac0_tx_reset {@orderednames emac0_rst_clk_tx_n_o emac0_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n}} usb1 {usb1_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb1_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} usb1_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_datain usb1_ulpi_stp usb1_ulpi_dataout usb1_ulpi_data_out_en} usb1_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb1_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain} usb1_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en}} usb0 {usb0_ulpi_stp {atom_signal_name stp direction Output role ulpi_stp} usb0_ulpi_nxt {atom_signal_name nxt direction Input role ulpi_nxt} usb0_ulpi_dataout {atom_signal_name dataout direction Output role ulpi_dataout} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_datain usb0_ulpi_stp usb0_ulpi_dataout usb0_ulpi_data_out_en} usb0_ulpi_dir {atom_signal_name dir direction Input role ulpi_dir} usb0_ulpi_data_out_en {atom_signal_name data_out_en direction Output role ulpi_data_out_en} usb0_ulpi_datain {atom_signal_name datain direction Input role ulpi_datain}} uart1 {uart1_ri {atom_signal_name ri direction Input role ri} uart1_rxd {atom_signal_name rxd direction Input role rxd} uart1_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart1_cts uart1_dsr uart1_dcd uart1_ri uart1_dtr uart1_rts uart1_out1_n uart1_out2_n uart1_rxd uart1_txd} uart1_out1_n {atom_signal_name out1_n direction Output role out1_n} uart1_dcd {atom_signal_name dcd direction Input role dcd} uart1_txd {atom_signal_name txd direction Output role txd} uart1_cts {atom_signal_name cts direction Input role cts} uart1_out2_n {atom_signal_name out2_n direction Output role out2_n} uart1_dtr {atom_signal_name dtr direction Output role dtr} uart1_rts {atom_signal_name rts direction Output role rts}} emac1_rx_reset {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {atom_signal_name rst_clk_rx_n_o direction Output role reset_n}} uart0 {uart0_rxd {atom_signal_name rxd direction Input role rxd} uart0_dsr {atom_signal_name dsr direction Input role dsr} @orderednames {uart0_cts uart0_dsr uart0_dcd uart0_ri uart0_dtr uart0_rts uart0_out1_n uart0_out2_n uart0_rxd uart0_txd} uart0_ri {atom_signal_name ri direction Input role ri} uart0_dcd {atom_signal_name dcd direction Input role dcd} uart0_out1_n {atom_signal_name out1_n direction Output role out1_n} uart0_txd {atom_signal_name txd direction Output role txd} uart0_cts {atom_signal_name cts direction Input role cts} uart0_out2_n {atom_signal_name out2_n direction Output role out2_n} uart0_dtr {atom_signal_name dtr direction Output role dtr} uart0_rts {atom_signal_name rts direction Output role rts}} spim1 {spim1_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} spim1_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} @orderednames {spim1_txd spim1_rxd spim1_ss_in_n spim1_ssi_oe_n spim1_ss_0_n spim1_ss_1_n spim1_ss_2_n spim1_ss_3_n} spim1_rxd {atom_signal_name rxd direction Input role rxd} spim1_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim1_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n} spim1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim1_txd {atom_signal_name txd direction Output role txd}} spim0 {spim0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spim0_txd {atom_signal_name txd direction Output role txd} spim0_ss_2_n {atom_signal_name ss_2_n direction Output role ss_2_n} @orderednames {spim0_txd spim0_rxd spim0_ss_in_n spim0_ssi_oe_n spim0_ss_0_n spim0_ss_1_n spim0_ss_2_n spim0_ss_3_n} spim0_ss_3_n {atom_signal_name ss_3_n direction Output role ss_3_n} spim0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spim0_rxd {atom_signal_name rxd direction Input role rxd} spim0_ss_0_n {atom_signal_name ss_0_n direction Output role ss_0_n} spim0_ss_1_n {atom_signal_name ss_1_n direction Output role ss_1_n}} spis1 {spis1_txd {atom_signal_name txd direction Output role txd} @orderednames {spis1_txd spis1_rxd spis1_ss_in_n spis1_ssi_oe_n} spis1_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis1_rxd {atom_signal_name rxd direction Input role rxd} spis1_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n}} spis0 {spis0_ss_in_n {atom_signal_name ss_in_n direction Input role ss_in_n} spis0_rxd {atom_signal_name rxd direction Input role rxd} @orderednames {spis0_txd spis0_rxd spis0_ss_in_n spis0_ssi_oe_n} spis0_ssi_oe_n {atom_signal_name ssi_oe_n direction Output role ssi_oe_n} spis0_txd {atom_signal_name txd direction Output role txd}} spis1_sclk_in {spis1_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis1_sclk_in} emac1_tx_reset {emac1_rst_clk_tx_n_o {atom_signal_name rst_clk_tx_n_o direction Output role reset_n} @orderednames emac1_rst_clk_tx_n_o} emac0_md_clk {emac0_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk} @orderednames emac0_gmii_mdc_o} emac0_tx_clk_in {emac0_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk} @orderednames emac0_clk_tx_i} qspi {qspi_n_mo_en {atom_signal_name n_mo_en direction Output role n_mo_en} @orderednames {qspi_mi0 qspi_mi1 qspi_mi2 qspi_mi3 qspi_mo0 qspi_mo1 qspi_mo2_wpn qspi_mo3_hold qspi_n_mo_en qspi_n_ss_out} qspi_mi3 {atom_signal_name mi3 direction Input role mi3} qspi_mo1 {atom_signal_name mo1 direction Output role mo1} qspi_n_ss_out {atom_signal_name n_ss_out direction Output role n_ss_out} qspi_mi2 {atom_signal_name mi2 direction Input role mi2} qspi_mo2_wpn {atom_signal_name mo2_wpn direction Output role mo2_wpn} qspi_mo0 {atom_signal_name mo0 direction Output role mo0} qspi_mi1 {atom_signal_name mi1 direction Input role mi1} qspi_mi0 {atom_signal_name mi0 direction Input role mi0} qspi_mo3_hold {atom_signal_name mo3_hold direction Output role mo3_hold}} spim0_sclk_out {spim0_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim0_sclk_out} i2c3 {@orderednames {i2c_emac1_out_data i2c_emac1_sda} i2c_emac1_sda {atom_signal_name sda direction Input role sda} i2c_emac1_out_data {atom_signal_name out_data direction Output role out_data}} i2c0_clk {@orderednames i2c0_out_clk i2c0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_md_clk {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {atom_signal_name gmii_mdc_o direction Output role clk}} i2c2 {@orderednames {i2c_emac0_out_data i2c_emac0_sda} i2c_emac0_out_data {atom_signal_name out_data direction Output role out_data} i2c_emac0_sda {atom_signal_name sda direction Input role sda}} i2c1 {i2c1_out_data {atom_signal_name out_data direction Output role out_data} @orderednames {i2c1_out_data i2c1_sda} i2c1_sda {atom_signal_name sda direction Input role sda}} i2c0 {i2c0_sda {atom_signal_name sda direction Input role sda} @orderednames {i2c0_out_data i2c0_sda} i2c0_out_data {atom_signal_name out_data direction Output role out_data}} emac0_rx_clk_in {@orderednames emac0_clk_rx_i emac0_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} i2c0_scl_in {i2c0_scl {atom_signal_name scl direction Input role clk} @orderednames i2c0_scl} i2c3_clk {@orderednames i2c_emac1_out_clk i2c_emac1_out_clk {atom_signal_name out_clk direction Output role clk}} i2c1_scl_in {@orderednames i2c1_scl i2c1_scl {atom_signal_name scl direction Input role clk}} spim1_sclk_out {spim1_sclk_out {atom_signal_name sclk_out direction Output role clk} @orderednames spim1_sclk_out} i2c2_scl_in {@orderednames i2c_emac0_scl i2c_emac0_scl {atom_signal_name scl direction Input role clk}} usb0_clk_in {@orderednames usb0_ulpi_clk usb0_ulpi_clk {atom_signal_name clk direction Input role clk}} sdio_reset {@orderednames sdmmc_rstn_o sdmmc_rstn_o {atom_signal_name rstn_o direction Output role reset}} emac0_gtx_clk {emac0_phy_txclk_o {atom_signal_name phy_txclk_o direction Output role clk} @orderednames emac0_phy_txclk_o} qspi_sclk_out {@orderednames qspi_sclk_out qspi_sclk_out {atom_signal_name sclk_out direction Output role clk}} i2c3_scl_in {i2c_emac1_scl {atom_signal_name scl direction Input role clk} @orderednames i2c_emac1_scl} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {atom_signal_name clk_tx_i direction Input role clk}} usb1_clk_in {@orderednames usb1_ulpi_clk usb1_ulpi_clk {atom_signal_name clk direction Input role clk}} spis0_sclk_in {spis0_sclk_in {atom_signal_name sclk_in direction Input role clk} @orderednames spis0_sclk_in} i2c2_clk {@orderednames i2c_emac0_out_clk i2c_emac0_out_clk {atom_signal_name out_clk direction Output role clk}} emac1_rx_clk_in {@orderednames emac1_clk_rx_i emac1_clk_rx_i {atom_signal_name clk_rx_i direction Input role clk}} nand {nand_rdy_busy_in {atom_signal_name rdy_busy direction Input role rdy_busy_in} nand_rebar_out {atom_signal_name rebar direction Output role rebar_out} nand_adq_in {atom_signal_name adq_in direction Input role adq_in} @orderednames {nand_adq_in nand_adq_oe nand_adq_out nand_ale_out nand_cebar_out nand_cle_out nand_rebar_out nand_rdy_busy_in nand_webar_out nand_wpbar_out} nand_webar_out {atom_signal_name webar direction Output role webar_out} nand_adq_out {atom_signal_name adq_out direction Output role adq_out} nand_wpbar_out {atom_signal_name wpbar direction Output role wpbar_out} nand_adq_oe {atom_signal_name adq_oe direction Output role adq_oe} nand_cebar_out {atom_signal_name cebar direction Output role cebar_out} nand_ale_out {atom_signal_name ale direction Output role ale_out} nand_cle_out {atom_signal_name cle direction Output role cle_out}} can1 {@orderednames {can1_rxd can1_txd} can1_rxd {atom_signal_name rxd direction Input role rxd} can1_txd {atom_signal_name txd direction Output role txd}}} REFRESH_BURST_VALIDATION false MEM_TRRD 4 ENUM_RD_FIFO_IN_USE_3 FALSE CV_PORT_1_CONNECT_TO_AV_PORT 1 ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_0 FALSE l4_sp_clk_div_auto 1 pin_muxing_check {Cyclone V+5CSEMA5F31C6} INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false DISABLE_CHILD_MESSAGING false show_warning_as_error_msg false mpu_periph_clk_hz 231250000 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} h2f_user1_clk_hz 100000000 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 SEQUENCER_TYPE_CACHE NIOS l4_mp_clk_hz 100000000 CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 PLL_AFI_HALF_CLK_DIV 2 CV_MSB_RFIFO_PORT_5 5 ENABLE_NIOS_OCI false CV_MSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_0 5 S2FINTERRUPT_I2CPERIPHERAL_Enable false main_qspi_clk_mhz 3.613281 DLL_MASTER true S2FINTERRUPT_FPGAMANAGER_Enable false QVLD_WR_ADDRESS_OFFSET 5 MEM_TINIT_CK 200000 PLL_WRITE_CLK_MULT_CACHE 32 MR1_DS 0 PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_WRITE_CLK_FREQ_CACHE 400.0 INTG_SUM_WT_PRIORITY_7 0 USE_DR_CLK false INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_SUM_WT_PRIORITY_6 0 HR_DDIO_OUT_HAS_THREE_REGS false INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_0 0 PLL_MEM_CLK_FREQ_PARAM 0.0 JAVA_EMAC0_DATA {EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}}} AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_MSB_WFIFO_PORT_5 5 MEM_IF_DQS_WIDTH 4 CV_MSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_2 5 FIX_READ_LATENCY 8 CV_MSB_WFIFO_PORT_1 5 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 FORCE_SEQUENCER_TCL_DEBUG_MODE false CV_MSB_WFIFO_PORT_0 5 CTL_RD_TO_PCH_EXTRA_CLK 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR {} SPIM0_PinMuxing Unused PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {1875 ps} ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_0 FALSE JAVA_SPIS0_DATA {SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}}} F2SDRAM_Width_Last_Size 0 CFG_TYPE 2 AC_ROM_MR1_OCD_ENABLE {} gpio_db_clk_div 6249 DQ_INPUT_REG_USE_CLKN false MR1_BT 0 CV_INTG_SUM_WT_PRIORITY_7 0 MR1_BL 2 S2FCLK_COLDRST_Enable false CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_5 0 GP_Enable false CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_0 0 nand_clk_mhz 50.0 ENUM_CPORT5_TYPE DISABLE GPIO_Conflict_DERIVED {{} USB1.D0 USB1.D1 USB1.D2 USB1.D3 USB1.D4 USB1.D5 USB1.D6 USB1.D7 {} USB1.CLK USB1.STP USB1.DIR USB1.NXT EMAC1.TX_CLK EMAC1.TXD0 EMAC1.TXD1 EMAC1.TXD2 EMAC1.TXD3 EMAC1.RXD0 EMAC1.MDIO EMAC1.MDC EMAC1.RX_CTL EMAC1.TX_CTL EMAC1.RX_CLK EMAC1.RXD1 EMAC1.RXD2 EMAC1.RXD3 {} {} {} {} {} {} {} {} SDIO.CMD {} SDIO.D0 SDIO.D1 {} {} {} {} {} SDIO.CLK SDIO.D2 SDIO.D3 {} UART0.RX UART0.TX I2C1.SDA I2C1.SCL {} {} I2C0.SDA I2C0.SCL {} {} {} {} {} {} SPIM1.CLK SPIM1.MOSI SPIM1.MISO SPIM1.SS0} INTG_EXTRA_CTL_CLK_WR_TO_RD 3 S2FINTERRUPT_SDMMC_Enable false MEM_CK_PHASE_CACHE 0.0 MEM_WTCL_INT 8 MR1_AL 0 cfg_h2f_user0_clk_hz 97368421 PLL_MEM_CLK_FREQ_CACHE 400.0 CFG_ADDR_ORDER 0 AFI_DEBUG_INFO_WIDTH 32 AVL_NUM_SYMBOLS 8 NUM_AC_FR_CYCLE_SHIFTS 0 TB_MEM_IF_DQ_WIDTH 32 CV_ENUM_RD_PORT_INFO_5 USE_NO CFG_TCCD 1 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_RD_PORT_INFO_2 USE_NO HHP_HPS_VERIFICATION false CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_RD_PORT_INFO_0 USE_NO AC_ROM_MR3 0000000000000 AC_ROM_MR2 0001000011000 S2FCLK_USER1CLK_FREQ 100.0 AC_ROM_MR1 0000000000110 TB_MEM_CLK_FREQ 400.0 AC_ROM_MR0 0010001110001 TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 LOANIO_Name_DERIVED {LOANIO00 LOANIO01 LOANIO02 LOANIO03 LOANIO04 LOANIO05 LOANIO06 LOANIO07 LOANIO08 LOANIO09 LOANIO10 LOANIO11 LOANIO12 LOANIO13 LOANIO14 LOANIO15 LOANIO16 LOANIO17 LOANIO18 LOANIO19 LOANIO20 LOANIO21 LOANIO22 LOANIO23 LOANIO24 LOANIO25 LOANIO26 LOANIO27 LOANIO28 LOANIO29 LOANIO30 LOANIO31 LOANIO32 LOANIO33 LOANIO34 LOANIO35 LOANIO36 LOANIO37 LOANIO38 LOANIO39 LOANIO40 LOANIO41 LOANIO42 LOANIO43 LOANIO44 LOANIO45 LOANIO46 LOANIO47 LOANIO48 LOANIO49 LOANIO50 LOANIO51 LOANIO52 LOANIO53 LOANIO54 LOANIO55 LOANIO56 LOANIO57 LOANIO58 LOANIO59 LOANIO60 LOANIO61 LOANIO62 LOANIO63 LOANIO64 LOANIO65 LOANIO66} P2C_READ_CLOCK_ADD_PHASE 0.0 PLL_CONFIG_CLK_DIV 18000000 test_iface_definition {DFX_OUT_FPGA_PR_REQUEST 1 output DFX_OUT_FPGA_DCLK 1 output DFX_OUT_FPGA_S2F_DATA 32 output DFX_SCAN_DOUT 1 output DFX_OUT_FPGA_SDRAM_OBSERVE 5 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_OSC1_CLK 1 output DFX_OUT_FPGA_T2_DATAOUT 1 output DFX_IN_FPGA_T2_CLK 1 input DFX_IN_FPGA_T2_DATAIN 1 input DFX_IN_FPGA_T2_SCAN_EN_N 1 input DFX_SCAN_CLK 1 input DFX_SCAN_DIN 1 input DFX_SCAN_EN 1 input DFX_SCAN_LOAD 1 input CFG_DFX_BYPASS_ENABLE 1 input F2S_CTRL 1 input F2S_JTAG_ENABLE_CORE 1 input DFT_IN_FPGA_SCAN_EN 1 input DFT_IN_FPGA_ATPG_EN 1 input DFT_IN_FPGA_PLLBYPASS 1 input DFT_IN_FPGA_PLLBYPASS_SEL 1 input DFT_IN_FPGA_OSC1TESTEN 1 input DFT_IN_FPGA_MPUPERITESTEN 1 input DFT_IN_FPGA_MPUL2RAMTESTEN 1 input DFT_IN_FPGA_MPUTESTEN 1 input DFT_IN_FPGA_MPU_SCAN_MODE 1 input DFT_IN_FPGA_DBGATTESTEN 1 input DFT_IN_FPGA_DBGTESTEN 1 input DFT_IN_FPGA_DBGTRTESTEN 1 input DFT_IN_FPGA_DBGTMTESTEN 1 input DFT_IN_FPGA_L4MAINTESTEN 1 input DFT_IN_FPGA_L3MAINTESTEN 1 input DFT_IN_FPGA_L3MPTESTEN 1 input DFT_IN_FPGA_L3SPTESTEN 1 input DFT_IN_FPGA_CFGTESTEN 1 input DFT_IN_FPGA_L4MPTESTEN 1 input DFT_IN_FPGA_L4SPTESTEN 1 input DFT_IN_FPGA_USBMPTESTEN 1 input DFT_IN_FPGA_SPIMTESTEN 1 input DFT_IN_FPGA_DDRDQSTESTEN 1 input DFT_IN_FPGA_DDR2XDQSTESTEN 1 input DFT_IN_FPGA_DDRDQTESTEN 1 input DFT_IN_FPGA_EMAC0TESTEN 1 input DFT_IN_FPGA_EMAC1TESTEN 1 input DFT_IN_FPGA_CAN0TESTEN 1 input DFT_IN_FPGA_CAN1TESTEN 1 input DFT_IN_FPGA_GPIODBTESTEN 1 input DFT_IN_FPGA_SDMMCTESTEN 1 input DFT_IN_FPGA_NANDTESTEN 1 input DFT_IN_FPGA_NANDXTESTEN 1 input DFT_IN_FPGA_QSPITESTEN 1 input DFT_IN_FPGA_TEST_CLK 1 input DFT_IN_FPGA_TEST_CLKOFF 1 input DFT_IN_FPGA_TEST_CKEN 1 input DFT_IN_FPGA_PIPELINE_SE_ENABLE 1 input DFT_IN_HPS_TESTMODE_N 1 input DFT_IN_FPGA_BIST_SE 1 input DFT_IN_FPGA_BISTEN 1 input DFT_IN_FPGA_BIST_NRST 1 input DFT_IN_FPGA_BIST_PERI_SI_0 1 input DFT_IN_FPGA_BIST_PERI_SI_1 1 input DFT_IN_FPGA_BIST_PERI_SI_2 1 input DFT_IN_FPGA_BIST_CPU_SI 1 input DFT_IN_FPGA_BIST_L2_SI 1 input DFT_IN_FPGA_MEM_SE 1 input DFT_IN_FPGA_MEM_PERI_SI_0 1 input DFT_IN_FPGA_MEM_PERI_SI_1 1 input DFT_IN_FPGA_MEM_PERI_SI_2 1 input DFT_IN_FPGA_MEM_CPU_SI 1 input DFT_IN_FPGA_MEM_L2_SI 1 input DFT_IN_FPGA_MTESTEN 1 input DFT_IN_FPGA_ECCBYP 1 input DFT_IN_FPGA_VIOSCANIN 1 input DFT_IN_FPGA_VIOSCANEN 1 input DFT_IN_FPGA_OCTSCANIN 1 input DFT_IN_FPGA_OCTSCANEN 1 input DFT_IN_FPGA_OCTSCANCLK 1 input DFT_IN_FPGA_OCTENSERUSER 1 input DFT_IN_FPGA_OCTCLKENUSR 1 input DFT_IN_FPGA_OCTS2PLOAD 1 input DFT_IN_FPGA_OCTNCLRUSR 1 input DFT_IN_FPGA_OCTCLKUSR 1 input DFT_IN_FPGA_OCTSERDATA 1 input DFT_IN_FPGA_HIOSCANIN 2 input DFT_IN_FPGA_HIOSCANEN 1 input DFT_IN_FPGA_HIOSCLR 1 input DFT_IN_FPGA_HIOCLKIN0 1 input DFT_IN_FPGA_DQSUPDTEN 5 input DFT_IN_FPGA_PSTDQSENA 1 input DFT_IN_FPGA_IPSCIN 1 input DFT_IN_FPGA_IPSCUPDATE 1 input DFT_IN_FPGA_IPSCCLK 1 input DFT_IN_FPGA_IPSCENABLE 12 input DFT_IN_FPGA_DLLNRST 1 input DFT_IN_FPGA_DLLUPDWNEN 1 input DFT_IN_FPGA_DLLUPNDN 1 input DFT_IN_FPGA_FMBHNIOTRI 1 input DFT_IN_FPGA_FMNIOTRI 1 input DFT_IN_FPGA_FMPLNIOTRI 1 input DFT_IN_FPGA_FMCSREN 1 input DFT_IN_FPGA_PLL_CLKR 6 input DFT_IN_FPGA_PLL_CLKF 13 input DFT_IN_FPGA_PLL_CLKOD 9 input DFT_IN_FPGA_PLL_BWADJ 12 input DFT_IN_FPGA_PLL1_RESET 1 input DFT_IN_FPGA_PLL1_PWRDN 1 input DFT_IN_FPGA_PLL1_TEST 1 input DFT_IN_FPGA_PLL1_OUTRESET 1 input DFT_IN_FPGA_PLL1_OUTRESETALL 1 input DFT_IN_FPGA_PLL_FASTEN 1 input DFT_IN_FPGA_PLL_ENSAT 1 input DFT_IN_FPGA_PLL_ADVANCE 1 input DFT_IN_FPGA_PLL_STEP 1 input DFT_IN_FPGA_PLL2_RESET 1 input DFT_IN_FPGA_PLL2_PWRDN 1 input DFT_IN_FPGA_PLL2_TEST 1 input DFT_IN_FPGA_PLL2_OUTRESET 1 input DFT_IN_FPGA_PLL2_OUTRESETALL 1 input DFT_IN_FPGA_PLL3_RESET 1 input DFT_IN_FPGA_PLL3_PWRDN 1 input DFT_IN_FPGA_PLL3_TEST 1 input DFT_IN_FPGA_PLL3_OUTRESET 1 input DFT_IN_FPGA_PLL3_OUTRESETALL 1 input DFT_IN_FPGA_PLL1_CLK_SELECT 1 input DFT_IN_FPGA_PLL2_CLK_SELECT 1 input DFT_IN_FPGA_PLL3_CLK_SELECT 1 input DFT_IN_FPGA_PLL_TESTBUS_SEL 5 input DFT_IN_FPGA_PLL1_BG_RESET 1 input DFT_IN_FPGA_PLL1_BG_PWRDN 1 input DFT_IN_FPGA_PLL1_REG_RESET 1 input DFT_IN_FPGA_PLL1_REG_PWRDN 1 input DFT_IN_FPGA_PLL2_BG_RESET 1 input DFT_IN_FPGA_PLL2_BG_PWRDN 1 input DFT_IN_FPGA_PLL2_REG_RESET 1 input DFT_IN_FPGA_PLL2_REG_PWRDN 1 input DFT_IN_FPGA_PLL3_BG_RESET 1 input DFT_IN_FPGA_PLL3_BG_PWRDN 1 input DFT_IN_FPGA_PLL3_REG_RESET 1 input DFT_IN_FPGA_PLL3_REG_PWRDN 1 input DFT_IN_FPGA_PLL_REG_EXT_SEL 1 input DFT_IN_FPGA_PLL1_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL2_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL3_REG_TEST_SEL 1 input DFT_IN_FPGA_PLL_REG_TEST_REP 1 input DFT_IN_FPGA_PLL_REG_TEST_OUT 1 input DFT_IN_FPGA_PLL_REG_TEST_DRV 1 input DFT_IN_FPGA_PLLTEST_INPUT_EN 1 input DFT_IN_FPGA_VIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_HIOSCANCLK_TESTEN 1 input DFT_IN_FPGA_CTICLK_TESTEN 1 input DFT_IN_FPGA_TPIUTRACECLKIN_TESTEN 1 input DFT_IN_FPGA_AVSTWRCLK_TESTEN 4 input DFT_IN_FPGA_AVSTRDCLK_TESTEN 4 input DFT_IN_FPGA_AVSTCMDPORTCLK_TESTEN 6 input DFT_IN_FPGA_F2SAXICLK_TESTEN 1 input DFT_IN_FPGA_S2FAXICLK_TESTEN 1 input DFT_IN_FPGA_USBULPICLK_TESTEN 2 input DFT_IN_FPGA_F2SPCLKDBG_TESTEN 1 input DFT_IN_FPGA_LWH2FAXICLK_TESTEN 1 input DFT_IN_FPGA_SCANIN 390 input DFT_OUT_FPGA_BIST_PERI_SO_0 1 output DFT_OUT_FPGA_BIST_PERI_SO_1 1 output DFT_OUT_FPGA_BIST_PERI_SO_2 1 output DFT_OUT_FPGA_BIST_CPU_SO 1 output DFT_OUT_FPGA_BIST_L2_SO 1 output DFT_OUT_FPGA_MEM_PERI_SO_0 1 output DFT_OUT_FPGA_MEM_PERI_SO_1 1 output DFT_OUT_FPGA_MEM_PERI_SO_2 1 output DFT_OUT_FPGA_MEM_CPU_SO 1 output DFT_OUT_FPGA_MEM_L2_SO 1 output DFT_OUT_FPGA_VIOSCANOUT 1 output DFT_OUT_FPGA_OCTSERDATA 1 output DFT_OUT_FPGA_OCTCOMPOUT_RUP 1 output DFT_OUT_FPGA_OCTCOMPOUT_RDN 1 output DFT_OUT_FPGA_OCTCLKUSRDFT 1 output DFT_OUT_FPGA_OCTSCANOUT 1 output DFT_OUT_FPGA_HIOCDATA3IN 45 output DFT_OUT_FPGA_HIODQSUNGATING 5 output DFT_OUT_FPGA_HIODQSOUT 5 output DFT_OUT_FPGA_HIOOCTRT 5 output DFT_OUT_FPGA_HIOSCANOUT 2 output DFT_OUT_FPGA_PSTTRACKSAMPLE 5 output DFT_OUT_FPGA_PSTVFIFO 5 output DFT_OUT_FPGA_IPSCOUT 5 output DFT_OUT_FPGA_DLLSETTING 7 output DFT_OUT_FPGA_DLLUPDWNCORE 1 output DFT_OUT_FPGA_DLLLOCKED 1 output DFT_OUT_FPGA_PLL_TESTBUS_OUT 3 output DFT_OUT_FPGA_SCANOUT_2_3 2 output DFT_OUT_FPGA_SCANOUT_15_83 69 output DFT_OUT_FPGA_SCANOUT_100_126 27 output DFT_OUT_FPGA_SCANOUT_131_250 120 output DFT_OUT_FPGA_SCANOUT_254_264 11 output DFT_OUT_FPGA_SCANOUT_271_389 119 output} PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM {} PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR {} PLL_DR_CLK_FREQ 0.0 PLL_NIOS_CLK_MULT_PARAM 0 MEM_CLK_FREQ 400.0 MEM_BURST_LENGTH 8 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM {} PLL_DR_CLK_DIV_PARAM 0 CTL_ECC_AUTO_CORRECTION_ENABLED false desired_emac1_clk_hz 250000000 MEM_IF_DQSN_EN true CTL_TBP_NUM 4 MEM_LEVELING false desired_mpu_clk_mhz 800.0 CV_CPORT_TYPE_PORT_5 0 CV_CPORT_TYPE_PORT_4 0 CV_CPORT_TYPE_PORT_3 0 CV_CPORT_TYPE_PORT_2 0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR {2500 ps} CV_CPORT_TYPE_PORT_1 0 CV_CPORT_TYPE_PORT_0 0 PLL_DR_CLK_FREQ_SIM_STR_PARAM {} CV_ENUM_CPORT0_TYPE DISABLE F2SCLK_PERIPHCLK_FREQ 0 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_10 can1_clk_mhz 12.5 ENUM_ENABLE_ATPG DISABLED SPEED_GRADE_CACHE 7 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_4 5 S2FINTERRUPT_CTI_Enable false MSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_0 5 QVLD_EXTRA_FLOP_STAGES 5 main_pll_vco_auto_mhz 1850.0 PLL_HR_CLK_PHASE_PS 0 CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_MEM_IF_TWTR TWTR_4 JAVA_NAND_DATA {NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}}} CV_ENUM_CMD_PORT_IN_USE_3 FALSE I2C1_PinMuxing {HPS I/O Set 0} CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CMD_PORT_IN_USE_1 FALSE FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK 100 CV_ENUM_CMD_PORT_IN_USE_0 FALSE DELAY_PER_DQS_EN_DCHAIN_TAP 25 PLL_C2P_WRITE_CLK_FREQ_STR {} ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 HHP_HPS_SIMULATION false PLL_WRITE_CLK_DIV_PARAM 0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE {} PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 PLL_NIOS_CLK_MULT_CACHE 0 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_0 THRESHOLD_32 eosc1_clk_hz 25000000 ENUM_CLOCK_OFF_5 DISABLED PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE {} ENUM_CLOCK_OFF_4 DISABLED PLL_AFI_HALF_CLK_FREQ_SIM_STR {5000 ps} ENUM_INC_SYNC FIFO_SET_2 JAVA_SPIM1_DATA {SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}}} ENUM_CLOCK_OFF_3 DISABLED PLL_DR_CLK_DIV_CACHE 0 ENUM_CLOCK_OFF_2 DISABLED USB1_Mode SDR ENUM_CLOCK_OFF_1 DISABLED spi_m_clk_div 0 ENUM_CLOCK_OFF_0 DISABLED PLL_P2C_READ_CLK_PHASE_PS_SIM_STR {} MSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_4 5 REF_CLK_FREQ_MAX_PARAM 0.0 MSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_0 5 MEM_REGDIMM_ENABLED false TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 quartus_ini_hps_emif_pll false JAVA_I2C1_DATA {I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}}} TIMING_TQSH 0.4 dbg_base_clk_hz 25000000 PLL_DR_CLK_FREQ_SIM_STR_CACHE {} PHY_CSR_ENABLED false CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CTL_CS_WIDTH 1 CPORT_TYPE_PORT_5 0 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CPORT_TYPE_PORT_4 0 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CPORT_TYPE_PORT_3 0 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED PLL_ADDR_CMD_CLK_FREQ 400.0 CPORT_TYPE_PORT_2 0 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CPORT_TYPE_PORT_1 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CPORT_TYPE_PORT_0 0 ENUM_ENABLE_NO_DM DISABLED NUM_OF_PORTS 1 PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 RDIMM_INT 0 ENUM_CPORT0_RFIFO_MAP FIFO_0 I2C3_Mode N/A EXPORT_CSR_PORT false ENUM_PDN_EXIT_CYCLES SLOW_EXIT CTL_CSR_READ_ONLY 1 pin_muxing {{USB0 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} UART1 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B1T PIN_P17A0T PIN_P17B1T PIN_P18A0T} signals {CTS RTS RX TX} signal_parts {{UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}} {UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}}} mux_selects {1 1 2 2} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO11 GENERALIO12 GENERALIO15 GENERALIO16}}}} UART0 {signals_by_mode {{Flow Control} {RX TX CTS RTS} {No Flow Control} {RX TX}} pin_sets {{HPS I/O Set 2} {locations {PIN_P18B0T PIN_P18A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {2 2 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO17 GENERALIO18 GENERALIO9 GENERALIO10}} {HPS I/O Set 1} {locations {PIN_P17B0T PIN_P17A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {3 3 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO13 GENERALIO14 GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P16B0T PIN_P16A1T} signals {RX TX CTS RTS} signal_parts {{UART_RXD(0:0) {} {}} {{} UART_TXD(0:0) {}} {UART_CTS_N(0:0) {} {}} {{} UART_RTS_N(0:0) {}}} mux_selects {1 1 1 1} valid_modes {{Flow Control} {No Flow Control}} pins {GENERALIO1 GENERALIO2 GENERALIO9 GENERALIO10}}}} SDIO {signals_by_mode {{1-bit Data} {CMD CLK D0} {4-bit Data} {CMD CLK D0 D1 D2 D3} {8-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7 PWREN} {8-bit Data} {CMD CLK D0 D1 D2 D3 D4 D5 D6 D7} {1-bit Data with PWREN} {CMD CLK D0 PWREN} {4-bit Data with PWREN} {CMD CLK D0 D1 D2 D3 PWREN}} pin_sets {{HPS I/O Set 0} {locations {PIN_P25A0T PIN_P25B0T PIN_P25A1T PIN_P25B1T PIN_P26A0T PIN_P26B0T PIN_P26A1T PIN_P26B1T PIN_P27A0T PIN_P27B0T PIN_P27A1T PIN_P27B1T} signals {CMD PWREN D0 D1 D4 D5 D6 D7 HPS_GPIO44 CLK D2 D3} signal_parts {{SDMMC_CMD_I(0:0) SDMMC_CMD_O(0:0) SDMMC_CMD_OE(0:0)} {{} SDMMC_PWR_EN(0:0) {}} {SDMMC_DATA_I(0:0) SDMMC_DATA_O(0:0) SDMMC_DATA_OE(0:0)} {SDMMC_DATA_I(1:1) SDMMC_DATA_O(1:1) SDMMC_DATA_OE(1:1)} {SDMMC_DATA_I(4:4) SDMMC_DATA_O(4:4) SDMMC_DATA_OE(4:4)} {SDMMC_DATA_I(5:5) SDMMC_DATA_O(5:5) SDMMC_DATA_OE(5:5)} {SDMMC_DATA_I(6:6) SDMMC_DATA_O(6:6) SDMMC_DATA_OE(6:6)} {SDMMC_DATA_I(7:7) SDMMC_DATA_O(7:7) SDMMC_DATA_OE(7:7)} HPS_GPIO44 {{} SDMMC_CCLK(0:0) {}} {SDMMC_DATA_I(2:2) SDMMC_DATA_O(2:2) SDMMC_DATA_OE(2:2)} {SDMMC_DATA_I(3:3) SDMMC_DATA_O(3:3) SDMMC_DATA_OE(3:3)}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{1-bit Data} {4-bit Data} {8-bit Data with PWREN} {8-bit Data} {1-bit Data with PWREN} {4-bit Data with PWREN}} pins {FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11}}}} I2C3 {signals_by_mode {I2C {SDA SCL} {Used by EMAC1} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P20A1T PIN_P20B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC1}} mux_selects {1 1} pins {MIXED1IO6 MIXED1IO7}}}} I2C2 {signals_by_mode {I2C {SDA SCL} {Used by EMAC0} {SDA SCL}} pin_sets {{HPS I/O Set 0} {locations {PIN_P29A1T PIN_P29B1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} valid_modes {I2C {Used by EMAC0}} mux_selects {1 1} pins {EMACIO6 EMACIO7}}}} I2C1 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B0T PIN_P16A1T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {2 2} valid_modes I2C pins {GENERALIO9 GENERALIO10}} {HPS I/O Set 0} {locations {PIN_P14B1T PIN_P15A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO3 GENERALIO4}}}} I2C0 {signals_by_mode {I2C {SDA SCL}} pin_sets {{HPS I/O Set 1} {locations {PIN_P17B1T PIN_P18A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {3 3} valid_modes I2C pins {GENERALIO15 GENERALIO16}} {HPS I/O Set 0} {locations {PIN_P15B1T PIN_P16A0T} signals {SDA SCL} signal_parts {{I2C_DATA(0:0) {} I2C_DATA_OE(0:0)} {I2C_CLK(0:0) {} I2C_CLK_OE(0:0)}} mux_selects {1 1} valid_modes I2C pins {GENERALIO7 GENERALIO8}}}} TRACE {signals_by_mode {HPSx4 {CLK D0 D1 D2 D3} HPS {CLK D0 D1 D2 D3 D4 D5 D6 D7}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14A0T PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK D0 D1 D2 D3 D4 D5 D6 D7} signal_parts {{{} TPIU_TRACE_CLK(0:0) {}} {{} TPIU_TRACE_DATA(0:0) {}} {{} TPIU_TRACE_DATA(1:1) {}} {{} TPIU_TRACE_DATA(2:2) {}} {{} TPIU_TRACE_DATA(3:3) {}} {{} TPIU_TRACE_DATA(4:4) {}} {{} TPIU_TRACE_DATA(5:5) {}} {{} TPIU_TRACE_DATA(6:6) {}} {{} TPIU_TRACE_DATA(7:7) {}}} mux_selects {3 3 3 3 3 3 3 3 3} valid_modes {HPSx4 HPS} pins {GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} CAN1 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P16B1T PIN_P17A0T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO11 GENERALIO12}} {HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {1 1} valid_modes CAN pins {GENERALIO5 GENERALIO6}}}} CAN0 {signals_by_mode {CAN {RX TX}} pin_sets {{HPS I/O Set 1} {locations {PIN_P18B0T PIN_P18A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {3 3} valid_modes CAN pins {GENERALIO17 GENERALIO18}} {HPS I/O Set 0} {locations {PIN_P17B0T PIN_P17A1T} signals {RX TX} signal_parts {{CAN_RXD(0:0) {} {}} {{} CAN_TXD(0:0) {}}} mux_selects {2 2} valid_modes CAN pins {GENERALIO13 GENERALIO14}}}} QSPI {signals_by_mode {{2 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1} {1 SS} {CLK IO0 IO1 IO2 IO3 SS0} {4 SS} {CLK IO0 IO1 IO2 IO3 SS0 SS1 SS2 SS3}} pin_sets {{HPS I/O Set 1} {locations {PIN_P24B0T PIN_P19A0T PIN_P22B0T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS1 SS3 SS2 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(1:1) {}} {{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {3 1 1 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO21 MIXED1IO0 MIXED1IO13 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}} {HPS I/O Set 0} {locations {PIN_P19A0T PIN_P22B0T PIN_P22A1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T PIN_P23B1T PIN_P24A0T} signals {SS3 SS2 SS1 IO0 IO1 IO2 IO3 SS0 CLK} signal_parts {{{} QSPI_SS_N(3:3) {}} {{} QSPI_SS_N(2:2) {}} {{} QSPI_SS_N(1:1) {}} {QSPI_MI0(0:0) QSPI_MO0(0:0) QSPI_MO_EN_N(0:0)} {QSPI_MI1(0:0) QSPI_MO1(0:0) QSPI_MO_EN_N(1:1)} {QSPI_MI2(0:0) QSPI_MO2(0:0) QSPI_MO_EN_N(2:2)} {QSPI_MI3(0:0) QSPI_MO3(0:0) QSPI_MO_EN_N(3:3)} {{} QSPI_SS_N(0:0) {}} {{} QSPI_SCLK(0:0) {}}} mux_selects {1 1 2 3 3 3 3 3 3} valid_modes {{2 SS} {1 SS} {4 SS}} pins {MIXED1IO0 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20}}}} SPIM1 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P17A1T PIN_P17B1T PIN_P18A0T PIN_P18B0T PIN_P18A1T} signals {SS1 CLK MOSI MISO SS0} signal_parts {{{} SPI_MASTER_SS_1_N(0:0) {}} {{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}}} mux_selects {1 1 1 1 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18}}}} NAND {signals_by_mode {{ONFI 1.0} {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE}} pin_sets {{HPS I/O Set 0} {locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T PIN_P22A1T} signals {ALE CE CLE RE RB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WP WE} signal_parts {{{} NAND_ALE(0:0) {}} {{} NAND_CE_N(0:0) {}} {{} NAND_CLE(0:0) {}} {{} NAND_RE_N(0:0) {}} {NAND_RDY_BUSYN(0:0) {} {}} {NAND_ADQ_I(0:0) NAND_ADQ_O(0:0) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(1:1) NAND_ADQ_O(1:1) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(2:2) NAND_ADQ_O(2:2) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(3:3) NAND_ADQ_O(3:3) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(4:4) NAND_ADQ_O(4:4) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(5:5) NAND_ADQ_O(5:5) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(6:6) NAND_ADQ_O(6:6) NAND_ADQ_OE(0:0)} {NAND_ADQ_I(7:7) NAND_ADQ_O(7:7) NAND_ADQ_OE(0:0)} {{} NAND_WP_N(0:0) {}} {{} NAND_WE_N(0:0) {}}} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3 3} valid_modes {{ONFI 1.0}} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14}}}} SPIM0 {signals_by_mode {{Dual Slave Selects} {CLK MOSI MISO SS0 SS1} {Single Slave Select} {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P16B0T PIN_P16A1T PIN_P16B1T PIN_P17A0T PIN_P17B0T} signals {CLK MOSI MISO SS0 SS1} signal_parts {{{} SPI_MASTER_SCLK(0:0) {}} {{} SPI_MASTER_TXD(0:0) SPI_MASTER_SSI_OE_N(0:0)} {SPI_MASTER_RXD(0:0) {} {}} {{} SPI_MASTER_SS_0_N(0:0) {}} {{} SPI_MASTER_SS_1_N(0:0) {}}} mux_selects {3 3 3 3 1} valid_modes {{Dual Slave Selects} {Single Slave Select}} pins {GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13}}}} SPIS1 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P15B0T PIN_P15A1T PIN_P15B1T PIN_P16A0T} signals {CLK MOSI SS0 MISO} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {SPI_SLAVE_SS_N(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8}}}} SPIS0 {signals_by_mode {SPI {CLK MOSI MISO SS0}} pin_sets {{HPS I/O Set 0} {locations {PIN_P14B0T PIN_P14A1T PIN_P14B1T PIN_P15A0T} signals {CLK MOSI MISO SS0} signal_parts {{SPI_SLAVE_SCLK(0:0) {} {}} {SPI_SLAVE_RXD(0:0) {} {}} {{} SPI_SLAVE_TXD(0:0) SPI_SLAVE_SSI_OE_N(0:0)} {SPI_SLAVE_SS_N(0:0) {} {}}} mux_selects {2 2 2 2} valid_modes SPI pins {GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4}}}} EMAC1 {signals_by_mode {{RGMII with I2C3} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2 2 2} pins {MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C3}} locations {PIN_P19A0T PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P20B0T PIN_P20A1T PIN_P20B1T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22A0T PIN_P22B0T} linked_peripheral I2C3 linked_peripheral_mode {Used by EMAC1} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} EMAC0 {signals_by_mode {{RGMII with I2C2} {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3} RGMII {TX_CLK TX_CTL TXD0 TXD1 TXD2 TXD3 RX_CLK RX_CTL RXD0 RXD1 RXD2 RXD3 MDIO MDC}} pin_sets {{HPS I/O Set 0} {linked_peripheral_pin_set {HPS I/O Set 0} mux_selects {3 3 3 3 3 3 3 3 3 3 3 3 3 3} pins {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13} signals {TX_CLK TXD0 TXD1 TXD2 TXD3 RXD0 MDIO MDC RX_CTL TX_CTL RX_CLK RXD1 RXD2 RXD3} valid_modes {RGMII {RGMII with I2C2}} locations {PIN_P28A0T PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30B0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} linked_peripheral I2C2 linked_peripheral_mode {Used by EMAC0} signal_parts {{{} EMAC_CLK_TX(0:0) {}} {{} EMAC_PHY_TXD(0:0) {}} {{} EMAC_PHY_TXD(1:1) {}} {{} EMAC_PHY_TXD(2:2) {}} {{} EMAC_PHY_TXD(3:3) {}} {EMAC_PHY_RXD(0:0) {} {}} {EMAC_GMII_MDO_I(0:0) EMAC_GMII_MDO_O(0:0) EMAC_GMII_MDO_OE(0:0)} {{} EMAC_GMII_MDC(0:0) {}} {EMAC_PHY_RXDV(0:0) {} {}} {{} EMAC_PHY_TX_OE(0:0) {}} {EMAC_CLK_RX(0:0) {} {}} {EMAC_PHY_RXD(1:1) {} {}} {EMAC_PHY_RXD(2:2) {} {}} {EMAC_PHY_RXD(3:3) {} {}}}}}} USB1 {signals_by_mode {SDR {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} {SDR without external clock} {D0 D1 D2 D3 D4 D5 D6 D7 STP DIR NXT}} pin_sets {{HPS I/O Set 1} {locations {PIN_P19B0T PIN_P19A1T PIN_P19B1T PIN_P20A0T PIN_P21A0T PIN_P21B0T PIN_P21A1T PIN_P21B1T PIN_P22B1T PIN_P23A0T PIN_P23B0T PIN_P23A1T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {1 1 1 1 1 1 1 1 1 1 1 1} valid_modes {SDR {SDR without external clock}} pins {MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18}} {HPS I/O Set 0} {locations {PIN_P28B0T PIN_P28A1T PIN_P28B1T PIN_P29A0T PIN_P29B0T PIN_P29A1T PIN_P29B1T PIN_P30A0T PIN_P30A1T PIN_P30B1T PIN_P31A0T PIN_P31B0T} signals {D0 D1 D2 D3 D4 D5 D6 D7 CLK STP DIR NXT} signal_parts {{USB_ULPI_DATA_I(0:0) USB_ULPI_DATA_O(0:0) USB_ULPI_DATA_OE(0:0)} {USB_ULPI_DATA_I(1:1) USB_ULPI_DATA_O(1:1) USB_ULPI_DATA_OE(1:1)} {USB_ULPI_DATA_I(2:2) USB_ULPI_DATA_O(2:2) USB_ULPI_DATA_OE(2:2)} {USB_ULPI_DATA_I(3:3) USB_ULPI_DATA_O(3:3) USB_ULPI_DATA_OE(3:3)} {USB_ULPI_DATA_I(4:4) USB_ULPI_DATA_O(4:4) USB_ULPI_DATA_OE(4:4)} {USB_ULPI_DATA_I(5:5) USB_ULPI_DATA_O(5:5) USB_ULPI_DATA_OE(5:5)} {USB_ULPI_DATA_I(6:6) USB_ULPI_DATA_O(6:6) USB_ULPI_DATA_OE(6:6)} {USB_ULPI_DATA_I(7:7) USB_ULPI_DATA_O(7:7) USB_ULPI_DATA_OE(7:7)} {USB_ULPI_CLK(0:0) {} {}} {{} USB_ULPI_STP(0:0) {}} {USB_ULPI_DIR(0:0) {} {}} {USB_ULPI_NXT(0:0) {} {}}} mux_selects {2 2 2 2 2 2 2 2 2 2 2 2} valid_modes {SDR {SDR without external clock}} pins {EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO10 EMACIO11 EMACIO12 EMACIO13}}}}} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {EMACIO0 EMACIO1 EMACIO2 EMACIO3 EMACIO4 EMACIO5 EMACIO6 EMACIO7 EMACIO8 EMACIO9 EMACIO10 EMACIO11 EMACIO12 EMACIO13 MIXED1IO0 MIXED1IO1 MIXED1IO2 MIXED1IO3 MIXED1IO4 MIXED1IO5 MIXED1IO6 MIXED1IO7 MIXED1IO8 MIXED1IO9 MIXED1IO10 MIXED1IO11 MIXED1IO12 MIXED1IO13 MIXED1IO14 MIXED1IO15 MIXED1IO16 MIXED1IO17 MIXED1IO18 MIXED1IO19 MIXED1IO20 MIXED1IO21 FLASHIO0 FLASHIO1 FLASHIO2 FLASHIO3 FLASHIO4 FLASHIO5 FLASHIO6 FLASHIO7 FLASHIO8 FLASHIO9 FLASHIO10 FLASHIO11 GENERALIO0 GENERALIO1 GENERALIO2 GENERALIO3 GENERALIO4 GENERALIO5 GENERALIO6 GENERALIO7 GENERALIO8 GENERALIO9 GENERALIO10 GENERALIO11 GENERALIO12 GENERALIO13 GENERALIO14 GENERALIO15 GENERALIO16 GENERALIO17 GENERALIO18} {RGMII0_TX_CLK RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 RGMII0_RXD0 RGMII0_MDIO {RGMII0_MDC } RGMII0_RX_CTL RGMII0_TX_CTL RGMII0_RX_CLK RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 NAND_ALE NAND_CE NAND_CLE NAND_RE NAND_RB NAND_DQ0 NAND_DQ1 NAND_DQ2 NAND_DQ3 NAND_DQ4 NAND_DQ5 NAND_DQ6 NAND_DQ7 NAND_WP NAND_WE QSPI_IO0 QSPI_IO1 QSPI_IO2 QSPI_IO3 QSPI_SS0 QSPI_CLK QSPI_SS1 SDMMC_CMD SDMMC_PWREN SDMMC_D0 SDMMC_D1 SDMMC_D4 SDMMC_D5 SDMMC_D6 SDMMC_D7 HPS_GPIO44 SDMMC_CCLK_OUT SDMMC_D2 SDMMC_D3 TRACE_CLK TRACE_D0 TRACE_D1 TRACE_D2 TRACE_D3 TRACE_D4 TRACE_D5 TRACE_D6 TRACE_D7 SPIM0_CLK SPIM0_MOSI SPIM0_MISO SPIM0_SS0 UART0_RX UART0_TX I2C0_SDA I2C0_SCL CAN0_RX CAN0_TX} {DDRIO63_HPS DDRIO62_HPS DDRIO49_HPS DDRIO47_HPS DDRIO46_HPS DDRIO38_HPS DDRIO33_HPS DDRIO31_HPS DDRIO30_HPS DDRIO24_HPS DDRIO18_HPS DDRIO16_HPS DDRIO15_HPS DDRIO9_HPS}} periph_pll_n 1 periph_pll_m 79 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 DATA_RATE_RATIO 2 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_DWIDTH_0 DWIDTH_0 PLL_WRITE_CLK_DIV_CACHE 2 ENUM_CPORT3_WFIFO_MAP FIFO_0 CTL_RD_TO_RD_EXTRA_CLK 0 MEM_CLK_MAX_PS 1250.0 S2FCLK_USER1CLK_Enable true SDIO_Mode {4-bit Data} desired_qspi_clk_mhz 400.0 MEM_TRFC 104 PLL_HR_CLK_FREQ_STR {} PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 S2FINTERRUPT_L4TIMER_Enable false REF_CLK_FREQ_MAX_CACHE 500.0 DELAYED_CLOCK_PHASE_SETTING 2" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM" value="0" />
  <parameter name="CPORT_TYPE_PORT_5" value="0" />
  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED" value="2.0" />
  <parameter name="CPORT_TYPE_PORT_4" value="0" />
  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE" value="" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR" value="" />
  <parameter name="CV_MSB_RFIFO_PORT_1" value="5" />
  <parameter name="CV_MSB_RFIFO_PORT_0" value="5" />
  <parameter name="PLL_AFI_CLK_DIV" value="0" />
  <parameter name="ENUM_PORT5_WIDTH" value="PORT_64_BIT" />
  <parameter name="CV_MSB_RFIFO_PORT_5" value="5" />
  <parameter name="MEM_TFAW" value="0" />
  <parameter name="CV_MSB_RFIFO_PORT_4" value="5" />
  <parameter name="CV_MSB_RFIFO_PORT_3" value="5" />
  <parameter name="CV_ENUM_CPORT0_WFIFO_MAP" value="FIFO_0" />
  <parameter name="CV_MSB_RFIFO_PORT_2" value="5" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_dll_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_oct_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_inst_ROM.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_AC_ROM.hex"
       type="HEX"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sdram_io.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/alt_types.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/system.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/tclrpt.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/tclrpt.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_defines.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/sequencer_auto.pre.h"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/sequencer/emif.pre.xml"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_parameters.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_pin_map.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_report_timing_core.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_report_timing.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_timing.tcl"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.sdc"
       type="SDC"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.ppf"
       type="OTHER"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_altdqdqs.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_phy_csr.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset_sync.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_reset.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v"
       type="VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps_sdram_pll.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_hps_0_hps_io_border.sdc"
       type="SDC"
       attributes="" />
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/hps.pre.xml"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/hps/altera_interface_generator/altera_interface_generator_hw.tcl" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/guava-30.1-jre.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/failureaccess-1.0.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.entityinterfaces.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.infrastructure.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.jdbcsqlite.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.version.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.utilities.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-lang3-3.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-impl.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-api.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jaxb-core.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/commons-logging-1.1.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopclibrary.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.components.tclmodule.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.hdlwriter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.minieval2.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.generator.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcdocument.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/tools/intel/intelFPGA/21.1/quartus/sopc_builder/model/lib/jacl1.3.2a.jar" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="soc_system_hps_0_hps_io" as="border" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 2 starting:altera_interface_generator "submodules/soc_system_hps_0_hps_io_border"</message>
   <message level="Info" culprit="border"><![CDATA["<b>hps_io</b>" instantiated <b>altera_interface_generator</b> "<b>border</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="error_adapter:21.1:inBitsPerSymbol=34,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1"
   instancePathKey="soc_system:.:mm_interconnect_0:.:avalon_st_adapter:.:error_adapter_0"
   kind="error_adapter"
   version="21.1"
   name="soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0">
  <parameter name="inErrorWidth" value="0" />
  <parameter name="inUseReady" value="true" />
  <parameter name="inBitsPerSymbol" value="34" />
  <parameter name="inChannelWidth" value="0" />
  <parameter name="inSymbolsPerBeat" value="1" />
  <parameter name="inUseEmptyPort" value="NO" />
  <parameter name="outErrorWidth" value="1" />
  <parameter name="inMaxChannel" value="0" />
  <parameter name="inReadyLatency" value="0" />
  <parameter name="outErrorDescriptor" value="" />
  <parameter name="inUseEmpty" value="false" />
  <parameter name="inErrorDescriptor" value="" />
  <parameter name="inUsePackets" value="false" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="soc_system_mm_interconnect_0_avalon_st_adapter"
     as="error_adapter_0" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 1 starting:error_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0"</message>
   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="error_adapter:21.1:inBitsPerSymbol=18,inChannelWidth=0,inErrorDescriptor=,inErrorWidth=0,inMaxChannel=0,inReadyLatency=0,inSymbolsPerBeat=1,inUseEmpty=false,inUseEmptyPort=NO,inUsePackets=false,inUseReady=true,outErrorDescriptor=,outErrorWidth=1"
   instancePathKey="soc_system:.:mm_interconnect_0:.:avalon_st_adapter_001:.:error_adapter_0"
   kind="error_adapter"
   version="21.1"
   name="soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0">
  <parameter name="inErrorWidth" value="0" />
  <parameter name="inUseReady" value="true" />
  <parameter name="inBitsPerSymbol" value="18" />
  <parameter name="inChannelWidth" value="0" />
  <parameter name="inSymbolsPerBeat" value="1" />
  <parameter name="inUseEmptyPort" value="NO" />
  <parameter name="outErrorWidth" value="1" />
  <parameter name="inMaxChannel" value="0" />
  <parameter name="inReadyLatency" value="0" />
  <parameter name="outErrorDescriptor" value="" />
  <parameter name="inUseEmpty" value="false" />
  <parameter name="inErrorDescriptor" value="" />
  <parameter name="inUsePackets" value="false" />
  <generatedFiles>
   <file
       path="/homes/user/stud/spring25/rjh2173/test_final_4840/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv"
       type="SYSTEM_VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/tools/intel/intelFPGA/21.1/ip/altera/avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="soc_system_mm_interconnect_0_avalon_st_adapter_001"
     as="error_adapter_0" />
  <messages>
   <message level="Debug" culprit="soc_system">queue size: 0 starting:error_adapter "submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0"</message>
   <message level="Info" culprit="error_adapter_0"><![CDATA["<b>avalon_st_adapter_001</b>" instantiated <b>error_adapter</b> "<b>error_adapter_0</b>"]]></message>
  </messages>
 </entity>
</deploy>
