// soc_system_mm_interconnect_0.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 21.1 842

`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0 (
		input  wire [11:0] hps_0_h2f_lw_axi_master_awid,                                        //                                       hps_0_h2f_lw_axi_master.awid
		input  wire [20:0] hps_0_h2f_lw_axi_master_awaddr,                                      //                                                              .awaddr
		input  wire [3:0]  hps_0_h2f_lw_axi_master_awlen,                                       //                                                              .awlen
		input  wire [2:0]  hps_0_h2f_lw_axi_master_awsize,                                      //                                                              .awsize
		input  wire [1:0]  hps_0_h2f_lw_axi_master_awburst,                                     //                                                              .awburst
		input  wire [1:0]  hps_0_h2f_lw_axi_master_awlock,                                      //                                                              .awlock
		input  wire [3:0]  hps_0_h2f_lw_axi_master_awcache,                                     //                                                              .awcache
		input  wire [2:0]  hps_0_h2f_lw_axi_master_awprot,                                      //                                                              .awprot
		input  wire        hps_0_h2f_lw_axi_master_awvalid,                                     //                                                              .awvalid
		output wire        hps_0_h2f_lw_axi_master_awready,                                     //                                                              .awready
		input  wire [11:0] hps_0_h2f_lw_axi_master_wid,                                         //                                                              .wid
		input  wire [31:0] hps_0_h2f_lw_axi_master_wdata,                                       //                                                              .wdata
		input  wire [3:0]  hps_0_h2f_lw_axi_master_wstrb,                                       //                                                              .wstrb
		input  wire        hps_0_h2f_lw_axi_master_wlast,                                       //                                                              .wlast
		input  wire        hps_0_h2f_lw_axi_master_wvalid,                                      //                                                              .wvalid
		output wire        hps_0_h2f_lw_axi_master_wready,                                      //                                                              .wready
		output wire [11:0] hps_0_h2f_lw_axi_master_bid,                                         //                                                              .bid
		output wire [1:0]  hps_0_h2f_lw_axi_master_bresp,                                       //                                                              .bresp
		output wire        hps_0_h2f_lw_axi_master_bvalid,                                      //                                                              .bvalid
		input  wire        hps_0_h2f_lw_axi_master_bready,                                      //                                                              .bready
		input  wire [11:0] hps_0_h2f_lw_axi_master_arid,                                        //                                                              .arid
		input  wire [20:0] hps_0_h2f_lw_axi_master_araddr,                                      //                                                              .araddr
		input  wire [3:0]  hps_0_h2f_lw_axi_master_arlen,                                       //                                                              .arlen
		input  wire [2:0]  hps_0_h2f_lw_axi_master_arsize,                                      //                                                              .arsize
		input  wire [1:0]  hps_0_h2f_lw_axi_master_arburst,                                     //                                                              .arburst
		input  wire [1:0]  hps_0_h2f_lw_axi_master_arlock,                                      //                                                              .arlock
		input  wire [3:0]  hps_0_h2f_lw_axi_master_arcache,                                     //                                                              .arcache
		input  wire [2:0]  hps_0_h2f_lw_axi_master_arprot,                                      //                                                              .arprot
		input  wire        hps_0_h2f_lw_axi_master_arvalid,                                     //                                                              .arvalid
		output wire        hps_0_h2f_lw_axi_master_arready,                                     //                                                              .arready
		output wire [11:0] hps_0_h2f_lw_axi_master_rid,                                         //                                                              .rid
		output wire [31:0] hps_0_h2f_lw_axi_master_rdata,                                       //                                                              .rdata
		output wire [1:0]  hps_0_h2f_lw_axi_master_rresp,                                       //                                                              .rresp
		output wire        hps_0_h2f_lw_axi_master_rlast,                                       //                                                              .rlast
		output wire        hps_0_h2f_lw_axi_master_rvalid,                                      //                                                              .rvalid
		input  wire        hps_0_h2f_lw_axi_master_rready,                                      //                                                              .rready
		input  wire        clk_0_clk_clk,                                                       //                                                     clk_0_clk.clk
		input  wire        hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
		input  wire        vga_ball_0_reset_reset_bridge_in_reset_reset,                        //                        vga_ball_0_reset_reset_bridge_in_reset.reset
		output wire [2:0]  vga_ball_0_avalon_slave_0_address,                                   //                                     vga_ball_0_avalon_slave_0.address
		output wire        vga_ball_0_avalon_slave_0_write,                                     //                                                              .write
		output wire [7:0]  vga_ball_0_avalon_slave_0_writedata,                                 //                                                              .writedata
		output wire        vga_ball_0_avalon_slave_0_chipselect                                 //                                                              .chipselect
	);

	wire          rsp_mux_src_valid;                                             // rsp_mux:src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
	wire  [111:0] rsp_mux_src_data;                                              // rsp_mux:src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
	wire          rsp_mux_src_ready;                                             // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> rsp_mux:src_ready
	wire    [1:0] rsp_mux_src_channel;                                           // rsp_mux:src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
	wire          rsp_mux_src_startofpacket;                                     // rsp_mux:src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                       // rsp_mux:src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
	wire          rsp_mux_001_src_valid;                                         // rsp_mux_001:src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
	wire  [111:0] rsp_mux_001_src_data;                                          // rsp_mux_001:src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
	wire          rsp_mux_001_src_ready;                                         // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> rsp_mux_001:src_ready
	wire    [1:0] rsp_mux_001_src_channel;                                       // rsp_mux_001:src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
	wire          rsp_mux_001_src_startofpacket;                                 // rsp_mux_001:src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                   // rsp_mux_001:src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
	wire    [7:0] vga_ball_0_avalon_slave_0_agent_m0_readdata;                   // vga_ball_0_avalon_slave_0_translator:uav_readdata -> vga_ball_0_avalon_slave_0_agent:m0_readdata
	wire          vga_ball_0_avalon_slave_0_agent_m0_waitrequest;                // vga_ball_0_avalon_slave_0_translator:uav_waitrequest -> vga_ball_0_avalon_slave_0_agent:m0_waitrequest
	wire          vga_ball_0_avalon_slave_0_agent_m0_debugaccess;                // vga_ball_0_avalon_slave_0_agent:m0_debugaccess -> vga_ball_0_avalon_slave_0_translator:uav_debugaccess
	wire   [20:0] vga_ball_0_avalon_slave_0_agent_m0_address;                    // vga_ball_0_avalon_slave_0_agent:m0_address -> vga_ball_0_avalon_slave_0_translator:uav_address
	wire    [0:0] vga_ball_0_avalon_slave_0_agent_m0_byteenable;                 // vga_ball_0_avalon_slave_0_agent:m0_byteenable -> vga_ball_0_avalon_slave_0_translator:uav_byteenable
	wire          vga_ball_0_avalon_slave_0_agent_m0_read;                       // vga_ball_0_avalon_slave_0_agent:m0_read -> vga_ball_0_avalon_slave_0_translator:uav_read
	wire          vga_ball_0_avalon_slave_0_agent_m0_readdatavalid;              // vga_ball_0_avalon_slave_0_translator:uav_readdatavalid -> vga_ball_0_avalon_slave_0_agent:m0_readdatavalid
	wire          vga_ball_0_avalon_slave_0_agent_m0_lock;                       // vga_ball_0_avalon_slave_0_agent:m0_lock -> vga_ball_0_avalon_slave_0_translator:uav_lock
	wire    [7:0] vga_ball_0_avalon_slave_0_agent_m0_writedata;                  // vga_ball_0_avalon_slave_0_agent:m0_writedata -> vga_ball_0_avalon_slave_0_translator:uav_writedata
	wire          vga_ball_0_avalon_slave_0_agent_m0_write;                      // vga_ball_0_avalon_slave_0_agent:m0_write -> vga_ball_0_avalon_slave_0_translator:uav_write
	wire    [0:0] vga_ball_0_avalon_slave_0_agent_m0_burstcount;                 // vga_ball_0_avalon_slave_0_agent:m0_burstcount -> vga_ball_0_avalon_slave_0_translator:uav_burstcount
	wire          vga_ball_0_avalon_slave_0_agent_rf_source_valid;               // vga_ball_0_avalon_slave_0_agent:rf_source_valid -> vga_ball_0_avalon_slave_0_agent_rsp_fifo:in_valid
	wire   [85:0] vga_ball_0_avalon_slave_0_agent_rf_source_data;                // vga_ball_0_avalon_slave_0_agent:rf_source_data -> vga_ball_0_avalon_slave_0_agent_rsp_fifo:in_data
	wire          vga_ball_0_avalon_slave_0_agent_rf_source_ready;               // vga_ball_0_avalon_slave_0_agent_rsp_fifo:in_ready -> vga_ball_0_avalon_slave_0_agent:rf_source_ready
	wire          vga_ball_0_avalon_slave_0_agent_rf_source_startofpacket;       // vga_ball_0_avalon_slave_0_agent:rf_source_startofpacket -> vga_ball_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
	wire          vga_ball_0_avalon_slave_0_agent_rf_source_endofpacket;         // vga_ball_0_avalon_slave_0_agent:rf_source_endofpacket -> vga_ball_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
	wire          vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_valid;            // vga_ball_0_avalon_slave_0_agent_rsp_fifo:out_valid -> vga_ball_0_avalon_slave_0_agent:rf_sink_valid
	wire   [85:0] vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_data;             // vga_ball_0_avalon_slave_0_agent_rsp_fifo:out_data -> vga_ball_0_avalon_slave_0_agent:rf_sink_data
	wire          vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_ready;            // vga_ball_0_avalon_slave_0_agent:rf_sink_ready -> vga_ball_0_avalon_slave_0_agent_rsp_fifo:out_ready
	wire          vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket;    // vga_ball_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> vga_ball_0_avalon_slave_0_agent:rf_sink_startofpacket
	wire          vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket;      // vga_ball_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> vga_ball_0_avalon_slave_0_agent:rf_sink_endofpacket
	wire          vga_ball_0_avalon_slave_0_agent_rdata_fifo_src_valid;          // vga_ball_0_avalon_slave_0_agent:rdata_fifo_src_valid -> vga_ball_0_avalon_slave_0_agent_rdata_fifo:in_valid
	wire    [9:0] vga_ball_0_avalon_slave_0_agent_rdata_fifo_src_data;           // vga_ball_0_avalon_slave_0_agent:rdata_fifo_src_data -> vga_ball_0_avalon_slave_0_agent_rdata_fifo:in_data
	wire          vga_ball_0_avalon_slave_0_agent_rdata_fifo_src_ready;          // vga_ball_0_avalon_slave_0_agent_rdata_fifo:in_ready -> vga_ball_0_avalon_slave_0_agent:rdata_fifo_src_ready
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_valid;                  // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> router:sink_valid
	wire  [111:0] hps_0_h2f_lw_axi_master_agent_write_cp_data;                   // hps_0_h2f_lw_axi_master_agent:write_cp_data -> router:sink_data
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_ready;                  // router:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket;          // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket;            // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                              // router:src_valid -> cmd_demux:sink_valid
	wire  [111:0] router_src_data;                                               // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                              // cmd_demux:sink_ready -> router:src_ready
	wire    [1:0] router_src_channel;                                            // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                      // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                        // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_valid;                   // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> router_001:sink_valid
	wire  [111:0] hps_0_h2f_lw_axi_master_agent_read_cp_data;                    // hps_0_h2f_lw_axi_master_agent:read_cp_data -> router_001:sink_data
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_ready;                   // router_001:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket;           // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket;             // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                          // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [111:0] router_001_src_data;                                           // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                          // cmd_demux_001:sink_ready -> router_001:src_ready
	wire    [1:0] router_001_src_channel;                                        // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                  // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                    // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          vga_ball_0_avalon_slave_0_agent_rp_valid;                      // vga_ball_0_avalon_slave_0_agent:rp_valid -> router_002:sink_valid
	wire   [84:0] vga_ball_0_avalon_slave_0_agent_rp_data;                       // vga_ball_0_avalon_slave_0_agent:rp_data -> router_002:sink_data
	wire          vga_ball_0_avalon_slave_0_agent_rp_ready;                      // router_002:sink_ready -> vga_ball_0_avalon_slave_0_agent:rp_ready
	wire          vga_ball_0_avalon_slave_0_agent_rp_startofpacket;              // vga_ball_0_avalon_slave_0_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire          vga_ball_0_avalon_slave_0_agent_rp_endofpacket;                // vga_ball_0_avalon_slave_0_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire          vga_ball_0_avalon_slave_0_burst_adapter_source0_valid;         // vga_ball_0_avalon_slave_0_burst_adapter:source0_valid -> vga_ball_0_avalon_slave_0_agent:cp_valid
	wire   [84:0] vga_ball_0_avalon_slave_0_burst_adapter_source0_data;          // vga_ball_0_avalon_slave_0_burst_adapter:source0_data -> vga_ball_0_avalon_slave_0_agent:cp_data
	wire          vga_ball_0_avalon_slave_0_burst_adapter_source0_ready;         // vga_ball_0_avalon_slave_0_agent:cp_ready -> vga_ball_0_avalon_slave_0_burst_adapter:source0_ready
	wire    [1:0] vga_ball_0_avalon_slave_0_burst_adapter_source0_channel;       // vga_ball_0_avalon_slave_0_burst_adapter:source0_channel -> vga_ball_0_avalon_slave_0_agent:cp_channel
	wire          vga_ball_0_avalon_slave_0_burst_adapter_source0_startofpacket; // vga_ball_0_avalon_slave_0_burst_adapter:source0_startofpacket -> vga_ball_0_avalon_slave_0_agent:cp_startofpacket
	wire          vga_ball_0_avalon_slave_0_burst_adapter_source0_endofpacket;   // vga_ball_0_avalon_slave_0_burst_adapter:source0_endofpacket -> vga_ball_0_avalon_slave_0_agent:cp_endofpacket
	wire          cmd_demux_src0_valid;                                          // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [111:0] cmd_demux_src0_data;                                           // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                          // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [1:0] cmd_demux_src0_channel;                                        // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                  // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                    // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                      // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
	wire  [111:0] cmd_demux_001_src0_data;                                       // cmd_demux_001:src0_data -> cmd_mux:sink1_data
	wire          cmd_demux_001_src0_ready;                                      // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
	wire    [1:0] cmd_demux_001_src0_channel;                                    // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
	wire          cmd_demux_001_src0_startofpacket;                              // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
	wire          rsp_demux_src0_valid;                                          // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [111:0] rsp_demux_src0_data;                                           // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                          // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [1:0] rsp_demux_src0_channel;                                        // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                  // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                    // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_src1_valid;                                          // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
	wire  [111:0] rsp_demux_src1_data;                                           // rsp_demux:src1_data -> rsp_mux_001:sink0_data
	wire          rsp_demux_src1_ready;                                          // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
	wire    [1:0] rsp_demux_src1_channel;                                        // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
	wire          rsp_demux_src1_startofpacket;                                  // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          rsp_demux_src1_endofpacket;                                    // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          router_002_src_valid;                                          // router_002:src_valid -> vga_ball_0_avalon_slave_0_rsp_width_adapter:in_valid
	wire   [84:0] router_002_src_data;                                           // router_002:src_data -> vga_ball_0_avalon_slave_0_rsp_width_adapter:in_data
	wire          router_002_src_ready;                                          // vga_ball_0_avalon_slave_0_rsp_width_adapter:in_ready -> router_002:src_ready
	wire    [1:0] router_002_src_channel;                                        // router_002:src_channel -> vga_ball_0_avalon_slave_0_rsp_width_adapter:in_channel
	wire          router_002_src_startofpacket;                                  // router_002:src_startofpacket -> vga_ball_0_avalon_slave_0_rsp_width_adapter:in_startofpacket
	wire          router_002_src_endofpacket;                                    // router_002:src_endofpacket -> vga_ball_0_avalon_slave_0_rsp_width_adapter:in_endofpacket
	wire          vga_ball_0_avalon_slave_0_rsp_width_adapter_src_valid;         // vga_ball_0_avalon_slave_0_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
	wire  [111:0] vga_ball_0_avalon_slave_0_rsp_width_adapter_src_data;          // vga_ball_0_avalon_slave_0_rsp_width_adapter:out_data -> rsp_demux:sink_data
	wire          vga_ball_0_avalon_slave_0_rsp_width_adapter_src_ready;         // rsp_demux:sink_ready -> vga_ball_0_avalon_slave_0_rsp_width_adapter:out_ready
	wire    [1:0] vga_ball_0_avalon_slave_0_rsp_width_adapter_src_channel;       // vga_ball_0_avalon_slave_0_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
	wire          vga_ball_0_avalon_slave_0_rsp_width_adapter_src_startofpacket; // vga_ball_0_avalon_slave_0_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
	wire          vga_ball_0_avalon_slave_0_rsp_width_adapter_src_endofpacket;   // vga_ball_0_avalon_slave_0_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_mux_src_valid;                                             // cmd_mux:src_valid -> vga_ball_0_avalon_slave_0_cmd_width_adapter:in_valid
	wire  [111:0] cmd_mux_src_data;                                              // cmd_mux:src_data -> vga_ball_0_avalon_slave_0_cmd_width_adapter:in_data
	wire          cmd_mux_src_ready;                                             // vga_ball_0_avalon_slave_0_cmd_width_adapter:in_ready -> cmd_mux:src_ready
	wire    [1:0] cmd_mux_src_channel;                                           // cmd_mux:src_channel -> vga_ball_0_avalon_slave_0_cmd_width_adapter:in_channel
	wire          cmd_mux_src_startofpacket;                                     // cmd_mux:src_startofpacket -> vga_ball_0_avalon_slave_0_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                       // cmd_mux:src_endofpacket -> vga_ball_0_avalon_slave_0_cmd_width_adapter:in_endofpacket
	wire          vga_ball_0_avalon_slave_0_cmd_width_adapter_src_valid;         // vga_ball_0_avalon_slave_0_cmd_width_adapter:out_valid -> vga_ball_0_avalon_slave_0_burst_adapter:sink0_valid
	wire   [84:0] vga_ball_0_avalon_slave_0_cmd_width_adapter_src_data;          // vga_ball_0_avalon_slave_0_cmd_width_adapter:out_data -> vga_ball_0_avalon_slave_0_burst_adapter:sink0_data
	wire          vga_ball_0_avalon_slave_0_cmd_width_adapter_src_ready;         // vga_ball_0_avalon_slave_0_burst_adapter:sink0_ready -> vga_ball_0_avalon_slave_0_cmd_width_adapter:out_ready
	wire    [1:0] vga_ball_0_avalon_slave_0_cmd_width_adapter_src_channel;       // vga_ball_0_avalon_slave_0_cmd_width_adapter:out_channel -> vga_ball_0_avalon_slave_0_burst_adapter:sink0_channel
	wire          vga_ball_0_avalon_slave_0_cmd_width_adapter_src_startofpacket; // vga_ball_0_avalon_slave_0_cmd_width_adapter:out_startofpacket -> vga_ball_0_avalon_slave_0_burst_adapter:sink0_startofpacket
	wire          vga_ball_0_avalon_slave_0_cmd_width_adapter_src_endofpacket;   // vga_ball_0_avalon_slave_0_cmd_width_adapter:out_endofpacket -> vga_ball_0_avalon_slave_0_burst_adapter:sink0_endofpacket
	wire          vga_ball_0_avalon_slave_0_agent_rdata_fifo_out_valid;          // vga_ball_0_avalon_slave_0_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
	wire    [9:0] vga_ball_0_avalon_slave_0_agent_rdata_fifo_out_data;           // vga_ball_0_avalon_slave_0_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
	wire          vga_ball_0_avalon_slave_0_agent_rdata_fifo_out_ready;          // avalon_st_adapter:in_0_ready -> vga_ball_0_avalon_slave_0_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_out_0_valid;                                 // avalon_st_adapter:out_0_valid -> vga_ball_0_avalon_slave_0_agent:rdata_fifo_sink_valid
	wire    [9:0] avalon_st_adapter_out_0_data;                                  // avalon_st_adapter:out_0_data -> vga_ball_0_avalon_slave_0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                 // vga_ball_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                 // avalon_st_adapter:out_0_error -> vga_ball_0_avalon_slave_0_agent:rdata_fifo_sink_error

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (8),
		.UAV_DATA_W                     (8),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (1),
		.UAV_ADDRESS_W                  (21),
		.UAV_BURSTCOUNT_W               (1),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (1),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) vga_ball_0_avalon_slave_0_translator (
		.clk                    (clk_0_clk_clk),                                    //                      clk.clk
		.reset                  (vga_ball_0_reset_reset_bridge_in_reset_reset),     //                    reset.reset
		.uav_address            (vga_ball_0_avalon_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (vga_ball_0_avalon_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (vga_ball_0_avalon_slave_0_agent_m0_read),          //                         .read
		.uav_write              (vga_ball_0_avalon_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest        (vga_ball_0_avalon_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (vga_ball_0_avalon_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (vga_ball_0_avalon_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (vga_ball_0_avalon_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (vga_ball_0_avalon_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock               (vga_ball_0_avalon_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (vga_ball_0_avalon_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (vga_ball_0_avalon_slave_0_address),                //      avalon_anti_slave_0.address
		.av_write               (vga_ball_0_avalon_slave_0_write),                  //                         .write
		.av_writedata           (vga_ball_0_avalon_slave_0_writedata),              //                         .writedata
		.av_chipselect          (vga_ball_0_avalon_slave_0_chipselect),             //                         .chipselect
		.av_read                (),                                                 //              (terminated)
		.av_readdata            (8'b10101101),                                      //              (terminated)
		.av_begintransfer       (),                                                 //              (terminated)
		.av_beginbursttransfer  (),                                                 //              (terminated)
		.av_burstcount          (),                                                 //              (terminated)
		.av_byteenable          (),                                                 //              (terminated)
		.av_readdatavalid       (1'b0),                                             //              (terminated)
		.av_waitrequest         (1'b0),                                             //              (terminated)
		.av_writebyteenable     (),                                                 //              (terminated)
		.av_lock                (),                                                 //              (terminated)
		.av_clken               (),                                                 //              (terminated)
		.uav_clken              (1'b0),                                             //              (terminated)
		.av_debugaccess         (),                                                 //              (terminated)
		.av_outputenable        (),                                                 //              (terminated)
		.uav_response           (),                                                 //              (terminated)
		.av_response            (2'b00),                                            //              (terminated)
		.uav_writeresponsevalid (),                                                 //              (terminated)
		.av_writeresponsevalid  (1'b0)                                              //              (terminated)
	);

	altera_merlin_axi_master_ni #(
		.ID_WIDTH                  (12),
		.ADDR_WIDTH                (21),
		.RDATA_WIDTH               (32),
		.WDATA_WIDTH               (32),
		.ADDR_USER_WIDTH           (1),
		.DATA_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (4),
		.AXI_LOCK_WIDTH            (2),
		.AXI_VERSION               ("AXI3"),
		.WRITE_ISSUING_CAPABILITY  (8),
		.READ_ISSUING_CAPABILITY   (8),
		.PKT_BEGIN_BURST           (84),
		.PKT_CACHE_H               (106),
		.PKT_CACHE_L               (103),
		.PKT_ADDR_SIDEBAND_H       (82),
		.PKT_ADDR_SIDEBAND_L       (82),
		.PKT_PROTECTION_H          (102),
		.PKT_PROTECTION_L          (100),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_BURST_TYPE_H          (81),
		.PKT_BURST_TYPE_L          (80),
		.PKT_RESPONSE_STATUS_L     (107),
		.PKT_RESPONSE_STATUS_H     (108),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (70),
		.PKT_BYTE_CNT_H            (69),
		.PKT_BYTE_CNT_L            (63),
		.PKT_ADDR_H                (56),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_EXCLUSIVE       (62),
		.PKT_TRANS_LOCK            (61),
		.PKT_TRANS_COMPRESSED_READ (57),
		.PKT_TRANS_POSTED          (58),
		.PKT_TRANS_WRITE           (59),
		.PKT_TRANS_READ            (60),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (86),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (87),
		.PKT_DEST_ID_L             (87),
		.PKT_THREAD_ID_H           (99),
		.PKT_THREAD_ID_L           (88),
		.PKT_QOS_L                 (85),
		.PKT_QOS_H                 (85),
		.PKT_ORI_BURST_SIZE_L      (109),
		.PKT_ORI_BURST_SIZE_H      (111),
		.PKT_DATA_SIDEBAND_H       (83),
		.PKT_DATA_SIDEBAND_L       (83),
		.ST_DATA_W                 (112),
		.ST_CHANNEL_W              (2),
		.ID                        (0)
	) hps_0_h2f_lw_axi_master_agent (
		.aclk                   (clk_0_clk_clk),                                                        //              clk.clk
		.aresetn                (~hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //        clk_reset.reset_n
		.write_cp_valid         (hps_0_h2f_lw_axi_master_agent_write_cp_valid),                         //         write_cp.valid
		.write_cp_data          (hps_0_h2f_lw_axi_master_agent_write_cp_data),                          //                 .data
		.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket),                 //                 .startofpacket
		.write_cp_endofpacket   (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket),                   //                 .endofpacket
		.write_cp_ready         (hps_0_h2f_lw_axi_master_agent_write_cp_ready),                         //                 .ready
		.write_rp_valid         (rsp_mux_src_valid),                                                    //         write_rp.valid
		.write_rp_data          (rsp_mux_src_data),                                                     //                 .data
		.write_rp_channel       (rsp_mux_src_channel),                                                  //                 .channel
		.write_rp_startofpacket (rsp_mux_src_startofpacket),                                            //                 .startofpacket
		.write_rp_endofpacket   (rsp_mux_src_endofpacket),                                              //                 .endofpacket
		.write_rp_ready         (rsp_mux_src_ready),                                                    //                 .ready
		.read_cp_valid          (hps_0_h2f_lw_axi_master_agent_read_cp_valid),                          //          read_cp.valid
		.read_cp_data           (hps_0_h2f_lw_axi_master_agent_read_cp_data),                           //                 .data
		.read_cp_startofpacket  (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket),                  //                 .startofpacket
		.read_cp_endofpacket    (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket),                    //                 .endofpacket
		.read_cp_ready          (hps_0_h2f_lw_axi_master_agent_read_cp_ready),                          //                 .ready
		.read_rp_valid          (rsp_mux_001_src_valid),                                                //          read_rp.valid
		.read_rp_data           (rsp_mux_001_src_data),                                                 //                 .data
		.read_rp_channel        (rsp_mux_001_src_channel),                                              //                 .channel
		.read_rp_startofpacket  (rsp_mux_001_src_startofpacket),                                        //                 .startofpacket
		.read_rp_endofpacket    (rsp_mux_001_src_endofpacket),                                          //                 .endofpacket
		.read_rp_ready          (rsp_mux_001_src_ready),                                                //                 .ready
		.awid                   (hps_0_h2f_lw_axi_master_awid),                                         // altera_axi_slave.awid
		.awaddr                 (hps_0_h2f_lw_axi_master_awaddr),                                       //                 .awaddr
		.awlen                  (hps_0_h2f_lw_axi_master_awlen),                                        //                 .awlen
		.awsize                 (hps_0_h2f_lw_axi_master_awsize),                                       //                 .awsize
		.awburst                (hps_0_h2f_lw_axi_master_awburst),                                      //                 .awburst
		.awlock                 (hps_0_h2f_lw_axi_master_awlock),                                       //                 .awlock
		.awcache                (hps_0_h2f_lw_axi_master_awcache),                                      //                 .awcache
		.awprot                 (hps_0_h2f_lw_axi_master_awprot),                                       //                 .awprot
		.awvalid                (hps_0_h2f_lw_axi_master_awvalid),                                      //                 .awvalid
		.awready                (hps_0_h2f_lw_axi_master_awready),                                      //                 .awready
		.wid                    (hps_0_h2f_lw_axi_master_wid),                                          //                 .wid
		.wdata                  (hps_0_h2f_lw_axi_master_wdata),                                        //                 .wdata
		.wstrb                  (hps_0_h2f_lw_axi_master_wstrb),                                        //                 .wstrb
		.wlast                  (hps_0_h2f_lw_axi_master_wlast),                                        //                 .wlast
		.wvalid                 (hps_0_h2f_lw_axi_master_wvalid),                                       //                 .wvalid
		.wready                 (hps_0_h2f_lw_axi_master_wready),                                       //                 .wready
		.bid                    (hps_0_h2f_lw_axi_master_bid),                                          //                 .bid
		.bresp                  (hps_0_h2f_lw_axi_master_bresp),                                        //                 .bresp
		.bvalid                 (hps_0_h2f_lw_axi_master_bvalid),                                       //                 .bvalid
		.bready                 (hps_0_h2f_lw_axi_master_bready),                                       //                 .bready
		.arid                   (hps_0_h2f_lw_axi_master_arid),                                         //                 .arid
		.araddr                 (hps_0_h2f_lw_axi_master_araddr),                                       //                 .araddr
		.arlen                  (hps_0_h2f_lw_axi_master_arlen),                                        //                 .arlen
		.arsize                 (hps_0_h2f_lw_axi_master_arsize),                                       //                 .arsize
		.arburst                (hps_0_h2f_lw_axi_master_arburst),                                      //                 .arburst
		.arlock                 (hps_0_h2f_lw_axi_master_arlock),                                       //                 .arlock
		.arcache                (hps_0_h2f_lw_axi_master_arcache),                                      //                 .arcache
		.arprot                 (hps_0_h2f_lw_axi_master_arprot),                                       //                 .arprot
		.arvalid                (hps_0_h2f_lw_axi_master_arvalid),                                      //                 .arvalid
		.arready                (hps_0_h2f_lw_axi_master_arready),                                      //                 .arready
		.rid                    (hps_0_h2f_lw_axi_master_rid),                                          //                 .rid
		.rdata                  (hps_0_h2f_lw_axi_master_rdata),                                        //                 .rdata
		.rresp                  (hps_0_h2f_lw_axi_master_rresp),                                        //                 .rresp
		.rlast                  (hps_0_h2f_lw_axi_master_rlast),                                        //                 .rlast
		.rvalid                 (hps_0_h2f_lw_axi_master_rvalid),                                       //                 .rvalid
		.rready                 (hps_0_h2f_lw_axi_master_rready),                                       //                 .rready
		.awuser                 (1'b0),                                                                 //      (terminated)
		.aruser                 (1'b0),                                                                 //      (terminated)
		.awqos                  (4'b0000),                                                              //      (terminated)
		.arqos                  (4'b0000),                                                              //      (terminated)
		.awregion               (4'b0000),                                                              //      (terminated)
		.arregion               (4'b0000),                                                              //      (terminated)
		.wuser                  (1'b0),                                                                 //      (terminated)
		.ruser                  (),                                                                     //      (terminated)
		.buser                  ()                                                                      //      (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (84),
		.PKT_ORI_BURST_SIZE_L      (82),
		.PKT_RESPONSE_STATUS_H     (81),
		.PKT_RESPONSE_STATUS_L     (80),
		.PKT_BURST_SIZE_H          (52),
		.PKT_BURST_SIZE_L          (50),
		.PKT_TRANS_LOCK            (34),
		.PKT_BEGIN_BURST           (57),
		.PKT_PROTECTION_H          (75),
		.PKT_PROTECTION_L          (73),
		.PKT_BURSTWRAP_H           (49),
		.PKT_BURSTWRAP_L           (43),
		.PKT_BYTE_CNT_H            (42),
		.PKT_BYTE_CNT_L            (36),
		.PKT_ADDR_H                (29),
		.PKT_ADDR_L                (9),
		.PKT_TRANS_COMPRESSED_READ (30),
		.PKT_TRANS_POSTED          (31),
		.PKT_TRANS_WRITE           (32),
		.PKT_TRANS_READ            (33),
		.PKT_DATA_H                (7),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (8),
		.PKT_BYTEEN_L              (8),
		.PKT_SRC_ID_H              (59),
		.PKT_SRC_ID_L              (59),
		.PKT_DEST_ID_H             (60),
		.PKT_DEST_ID_L             (60),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (85),
		.AVS_BURSTCOUNT_W          (1),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) vga_ball_0_avalon_slave_0_agent (
		.clk                     (clk_0_clk_clk),                                                 //             clk.clk
		.reset                   (vga_ball_0_reset_reset_bridge_in_reset_reset),                  //       clk_reset.reset
		.m0_address              (vga_ball_0_avalon_slave_0_agent_m0_address),                    //              m0.address
		.m0_burstcount           (vga_ball_0_avalon_slave_0_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (vga_ball_0_avalon_slave_0_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (vga_ball_0_avalon_slave_0_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (vga_ball_0_avalon_slave_0_agent_m0_lock),                       //                .lock
		.m0_readdata             (vga_ball_0_avalon_slave_0_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (vga_ball_0_avalon_slave_0_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (vga_ball_0_avalon_slave_0_agent_m0_read),                       //                .read
		.m0_waitrequest          (vga_ball_0_avalon_slave_0_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (vga_ball_0_avalon_slave_0_agent_m0_writedata),                  //                .writedata
		.m0_write                (vga_ball_0_avalon_slave_0_agent_m0_write),                      //                .write
		.rp_endofpacket          (vga_ball_0_avalon_slave_0_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (vga_ball_0_avalon_slave_0_agent_rp_ready),                      //                .ready
		.rp_valid                (vga_ball_0_avalon_slave_0_agent_rp_valid),                      //                .valid
		.rp_data                 (vga_ball_0_avalon_slave_0_agent_rp_data),                       //                .data
		.rp_startofpacket        (vga_ball_0_avalon_slave_0_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (vga_ball_0_avalon_slave_0_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (vga_ball_0_avalon_slave_0_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (vga_ball_0_avalon_slave_0_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (vga_ball_0_avalon_slave_0_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (vga_ball_0_avalon_slave_0_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (vga_ball_0_avalon_slave_0_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (vga_ball_0_avalon_slave_0_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (vga_ball_0_avalon_slave_0_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (vga_ball_0_avalon_slave_0_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (vga_ball_0_avalon_slave_0_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (vga_ball_0_avalon_slave_0_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                 // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                 //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                  //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                 //                .error
		.rdata_fifo_src_ready    (vga_ball_0_avalon_slave_0_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (vga_ball_0_avalon_slave_0_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (vga_ball_0_avalon_slave_0_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                         //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                           //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (86),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) vga_ball_0_avalon_slave_0_agent_rsp_fifo (
		.clk               (clk_0_clk_clk),                                              //       clk.clk
		.reset             (vga_ball_0_reset_reset_bridge_in_reset_reset),               // clk_reset.reset
		.in_data           (vga_ball_0_avalon_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (vga_ball_0_avalon_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (vga_ball_0_avalon_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (vga_ball_0_avalon_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (vga_ball_0_avalon_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (vga_ball_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                      // (terminated)
		.csr_read          (1'b0),                                                       // (terminated)
		.csr_write         (1'b0),                                                       // (terminated)
		.csr_readdata      (),                                                           // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                       // (terminated)
		.almost_full_data  (),                                                           // (terminated)
		.almost_empty_data (),                                                           // (terminated)
		.in_empty          (1'b0),                                                       // (terminated)
		.out_empty         (),                                                           // (terminated)
		.in_error          (1'b0),                                                       // (terminated)
		.out_error         (),                                                           // (terminated)
		.in_channel        (1'b0),                                                       // (terminated)
		.out_channel       ()                                                            // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (10),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) vga_ball_0_avalon_slave_0_agent_rdata_fifo (
		.clk               (clk_0_clk_clk),                                        //       clk.clk
		.reset             (vga_ball_0_reset_reset_bridge_in_reset_reset),         // clk_reset.reset
		.in_data           (vga_ball_0_avalon_slave_0_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (vga_ball_0_avalon_slave_0_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (vga_ball_0_avalon_slave_0_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (vga_ball_0_avalon_slave_0_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (vga_ball_0_avalon_slave_0_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (vga_ball_0_avalon_slave_0_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                // (terminated)
		.csr_read          (1'b0),                                                 // (terminated)
		.csr_write         (1'b0),                                                 // (terminated)
		.csr_readdata      (),                                                     // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated)
		.almost_full_data  (),                                                     // (terminated)
		.almost_empty_data (),                                                     // (terminated)
		.in_startofpacket  (1'b0),                                                 // (terminated)
		.in_endofpacket    (1'b0),                                                 // (terminated)
		.out_startofpacket (),                                                     // (terminated)
		.out_endofpacket   (),                                                     // (terminated)
		.in_empty          (1'b0),                                                 // (terminated)
		.out_empty         (),                                                     // (terminated)
		.in_error          (1'b0),                                                 // (terminated)
		.out_error         (),                                                     // (terminated)
		.in_channel        (1'b0),                                                 // (terminated)
		.out_channel       ()                                                      // (terminated)
	);

	soc_system_mm_interconnect_0_router router (
		.sink_ready         (hps_0_h2f_lw_axi_master_agent_write_cp_ready),                        //      sink.ready
		.sink_valid         (hps_0_h2f_lw_axi_master_agent_write_cp_valid),                        //          .valid
		.sink_data          (hps_0_h2f_lw_axi_master_agent_write_cp_data),                         //          .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket),                //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket),                  //          .endofpacket
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                                    //       src.ready
		.src_valid          (router_src_valid),                                                    //          .valid
		.src_data           (router_src_data),                                                     //          .data
		.src_channel        (router_src_channel),                                                  //          .channel
		.src_startofpacket  (router_src_startofpacket),                                            //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                               //          .endofpacket
	);

	soc_system_mm_interconnect_0_router router_001 (
		.sink_ready         (hps_0_h2f_lw_axi_master_agent_read_cp_ready),                         //      sink.ready
		.sink_valid         (hps_0_h2f_lw_axi_master_agent_read_cp_valid),                         //          .valid
		.sink_data          (hps_0_h2f_lw_axi_master_agent_read_cp_data),                          //          .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket),                   //          .endofpacket
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                                                //       src.ready
		.src_valid          (router_001_src_valid),                                                //          .valid
		.src_data           (router_001_src_data),                                                 //          .data
		.src_channel        (router_001_src_channel),                                              //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                        //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                           //          .endofpacket
	);

	soc_system_mm_interconnect_0_router_002 router_002 (
		.sink_ready         (vga_ball_0_avalon_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (vga_ball_0_avalon_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (vga_ball_0_avalon_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (vga_ball_0_avalon_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (vga_ball_0_avalon_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_0_clk_clk),                                    //       clk.clk
		.reset              (vga_ball_0_reset_reset_bridge_in_reset_reset),     // clk_reset.reset
		.src_ready          (router_002_src_ready),                             //       src.ready
		.src_valid          (router_002_src_valid),                             //          .valid
		.src_data           (router_002_src_data),                              //          .data
		.src_channel        (router_002_src_channel),                           //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                     //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                        //          .endofpacket
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (29),
		.PKT_ADDR_L                (9),
		.PKT_BEGIN_BURST           (57),
		.PKT_BYTE_CNT_H            (42),
		.PKT_BYTE_CNT_L            (36),
		.PKT_BYTEEN_H              (8),
		.PKT_BYTEEN_L              (8),
		.PKT_BURST_SIZE_H          (52),
		.PKT_BURST_SIZE_L          (50),
		.PKT_BURST_TYPE_H          (54),
		.PKT_BURST_TYPE_L          (53),
		.PKT_BURSTWRAP_H           (49),
		.PKT_BURSTWRAP_L           (43),
		.PKT_TRANS_COMPRESSED_READ (30),
		.PKT_TRANS_WRITE           (32),
		.PKT_TRANS_READ            (33),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (85),
		.ST_CHANNEL_W              (2),
		.OUT_BYTE_CNT_H            (36),
		.OUT_BURSTWRAP_H           (49),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1")
	) vga_ball_0_avalon_slave_0_burst_adapter (
		.clk                   (clk_0_clk_clk),                                                 //       cr0.clk
		.reset                 (vga_ball_0_reset_reset_bridge_in_reset_reset),                  // cr0_reset.reset
		.sink0_valid           (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_valid),         //     sink0.valid
		.sink0_data            (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_data),          //          .data
		.sink0_channel         (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_channel),       //          .channel
		.sink0_startofpacket   (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.sink0_endofpacket     (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_endofpacket),   //          .endofpacket
		.sink0_ready           (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_ready),         //          .ready
		.source0_valid         (vga_ball_0_avalon_slave_0_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (vga_ball_0_avalon_slave_0_burst_adapter_source0_data),          //          .data
		.source0_channel       (vga_ball_0_avalon_slave_0_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (vga_ball_0_avalon_slave_0_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (vga_ball_0_avalon_slave_0_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (vga_ball_0_avalon_slave_0_burst_adapter_source0_ready)          //          .ready
	);

	soc_system_mm_interconnect_0_cmd_demux cmd_demux (
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                                                    //      sink.ready
		.sink_channel       (router_src_channel),                                                  //          .channel
		.sink_data          (router_src_data),                                                     //          .data
		.sink_startofpacket (router_src_startofpacket),                                            //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                                              //          .endofpacket
		.sink_valid         (router_src_valid),                                                    //          .valid
		.src0_ready         (cmd_demux_src0_ready),                                                //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                                //          .valid
		.src0_data          (cmd_demux_src0_data),                                                 //          .data
		.src0_channel       (cmd_demux_src0_channel),                                              //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                        //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                                           //          .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_demux cmd_demux_001 (
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                                                //      sink.ready
		.sink_channel       (router_001_src_channel),                                              //          .channel
		.sink_data          (router_001_src_data),                                                 //          .data
		.sink_startofpacket (router_001_src_startofpacket),                                        //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                                          //          .endofpacket
		.sink_valid         (router_001_src_valid),                                                //          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                                            //      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                                            //          .valid
		.src0_data          (cmd_demux_001_src0_data),                                             //          .data
		.src0_channel       (cmd_demux_001_src0_channel),                                          //          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),                                    //          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket)                                       //          .endofpacket
	);

	soc_system_mm_interconnect_0_cmd_mux cmd_mux (
		.clk                 (clk_0_clk_clk),                                //       clk.clk
		.reset               (vga_ball_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                            //       src.ready
		.src_valid           (cmd_mux_src_valid),                            //          .valid
		.src_data            (cmd_mux_src_data),                             //          .data
		.src_channel         (cmd_mux_src_channel),                          //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                    //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                      //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                         //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                         //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                       //          .channel
		.sink0_data          (cmd_demux_src0_data),                          //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                 //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket),                   //          .endofpacket
		.sink1_ready         (cmd_demux_001_src0_ready),                     //     sink1.ready
		.sink1_valid         (cmd_demux_001_src0_valid),                     //          .valid
		.sink1_channel       (cmd_demux_001_src0_channel),                   //          .channel
		.sink1_data          (cmd_demux_001_src0_data),                      //          .data
		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),             //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket)                //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_demux rsp_demux (
		.clk                (clk_0_clk_clk),                                                 //       clk.clk
		.reset              (vga_ball_0_reset_reset_bridge_in_reset_reset),                  // clk_reset.reset
		.sink_ready         (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_ready),         //      sink.ready
		.sink_channel       (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_channel),       //          .channel
		.sink_data          (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_data),          //          .data
		.sink_startofpacket (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.sink_endofpacket   (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_endofpacket),   //          .endofpacket
		.sink_valid         (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_valid),         //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                          //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                          //          .valid
		.src0_data          (rsp_demux_src0_data),                                           //          .data
		.src0_channel       (rsp_demux_src0_channel),                                        //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                  //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                                    //          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                                          //      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                                          //          .valid
		.src1_data          (rsp_demux_src1_data),                                           //          .data
		.src1_channel       (rsp_demux_src1_channel),                                        //          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                                  //          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket)                                     //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_mux rsp_mux (
		.clk                 (clk_0_clk_clk),                                                       //       clk.clk
		.reset               (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                   //       src.ready
		.src_valid           (rsp_mux_src_valid),                                                   //          .valid
		.src_data            (rsp_mux_src_data),                                                    //          .data
		.src_channel         (rsp_mux_src_channel),                                                 //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                           //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                             //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                                //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                                //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                                              //          .channel
		.sink0_data          (rsp_demux_src0_data),                                                 //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                                        //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket)                                           //          .endofpacket
	);

	soc_system_mm_interconnect_0_rsp_mux rsp_mux_001 (
		.clk                 (clk_0_clk_clk),                                                       //       clk.clk
		.reset               (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                                               //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                                               //          .valid
		.src_data            (rsp_mux_001_src_data),                                                //          .data
		.src_channel         (rsp_mux_001_src_channel),                                             //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                                       //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                                         //          .endofpacket
		.sink0_ready         (rsp_demux_src1_ready),                                                //     sink0.ready
		.sink0_valid         (rsp_demux_src1_valid),                                                //          .valid
		.sink0_channel       (rsp_demux_src1_channel),                                              //          .channel
		.sink0_data          (rsp_demux_src1_data),                                                 //          .data
		.sink0_startofpacket (rsp_demux_src1_startofpacket),                                        //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src1_endofpacket)                                           //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (29),
		.IN_PKT_ADDR_L                 (9),
		.IN_PKT_DATA_H                 (7),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (8),
		.IN_PKT_BYTEEN_L               (8),
		.IN_PKT_BYTE_CNT_H             (42),
		.IN_PKT_BYTE_CNT_L             (36),
		.IN_PKT_TRANS_COMPRESSED_READ  (30),
		.IN_PKT_TRANS_WRITE            (32),
		.IN_PKT_BURSTWRAP_H            (49),
		.IN_PKT_BURSTWRAP_L            (43),
		.IN_PKT_BURST_SIZE_H           (52),
		.IN_PKT_BURST_SIZE_L           (50),
		.IN_PKT_RESPONSE_STATUS_H      (81),
		.IN_PKT_RESPONSE_STATUS_L      (80),
		.IN_PKT_TRANS_EXCLUSIVE        (35),
		.IN_PKT_BURST_TYPE_H           (54),
		.IN_PKT_BURST_TYPE_L           (53),
		.IN_PKT_ORI_BURST_SIZE_L       (82),
		.IN_PKT_ORI_BURST_SIZE_H       (84),
		.IN_ST_DATA_W                  (85),
		.OUT_PKT_ADDR_H                (56),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (69),
		.OUT_PKT_BYTE_CNT_L            (63),
		.OUT_PKT_TRANS_COMPRESSED_READ (57),
		.OUT_PKT_BURST_SIZE_H          (79),
		.OUT_PKT_BURST_SIZE_L          (77),
		.OUT_PKT_RESPONSE_STATUS_H     (108),
		.OUT_PKT_RESPONSE_STATUS_L     (107),
		.OUT_PKT_TRANS_EXCLUSIVE       (62),
		.OUT_PKT_BURST_TYPE_H          (81),
		.OUT_PKT_BURST_TYPE_L          (80),
		.OUT_PKT_ORI_BURST_SIZE_L      (109),
		.OUT_PKT_ORI_BURST_SIZE_H      (111),
		.OUT_ST_DATA_W                 (112),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (1)
	) vga_ball_0_avalon_slave_0_rsp_width_adapter (
		.clk                  (clk_0_clk_clk),                                                 //       clk.clk
		.reset                (vga_ball_0_reset_reset_bridge_in_reset_reset),                  // clk_reset.reset
		.in_valid             (router_002_src_valid),                                          //      sink.valid
		.in_channel           (router_002_src_channel),                                        //          .channel
		.in_startofpacket     (router_002_src_startofpacket),                                  //          .startofpacket
		.in_endofpacket       (router_002_src_endofpacket),                                    //          .endofpacket
		.in_ready             (router_002_src_ready),                                          //          .ready
		.in_data              (router_002_src_data),                                           //          .data
		.out_endofpacket      (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_data),          //          .data
		.out_channel          (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_channel),       //          .channel
		.out_valid            (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_valid),         //          .valid
		.out_ready            (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (vga_ball_0_avalon_slave_0_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                         // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (56),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (69),
		.IN_PKT_BYTE_CNT_L             (63),
		.IN_PKT_TRANS_COMPRESSED_READ  (57),
		.IN_PKT_TRANS_WRITE            (59),
		.IN_PKT_BURSTWRAP_H            (76),
		.IN_PKT_BURSTWRAP_L            (70),
		.IN_PKT_BURST_SIZE_H           (79),
		.IN_PKT_BURST_SIZE_L           (77),
		.IN_PKT_RESPONSE_STATUS_H      (108),
		.IN_PKT_RESPONSE_STATUS_L      (107),
		.IN_PKT_TRANS_EXCLUSIVE        (62),
		.IN_PKT_BURST_TYPE_H           (81),
		.IN_PKT_BURST_TYPE_L           (80),
		.IN_PKT_ORI_BURST_SIZE_L       (109),
		.IN_PKT_ORI_BURST_SIZE_H       (111),
		.IN_ST_DATA_W                  (112),
		.OUT_PKT_ADDR_H                (29),
		.OUT_PKT_ADDR_L                (9),
		.OUT_PKT_DATA_H                (7),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (8),
		.OUT_PKT_BYTEEN_L              (8),
		.OUT_PKT_BYTE_CNT_H            (42),
		.OUT_PKT_BYTE_CNT_L            (36),
		.OUT_PKT_TRANS_COMPRESSED_READ (30),
		.OUT_PKT_BURST_SIZE_H          (52),
		.OUT_PKT_BURST_SIZE_L          (50),
		.OUT_PKT_RESPONSE_STATUS_H     (81),
		.OUT_PKT_RESPONSE_STATUS_L     (80),
		.OUT_PKT_TRANS_EXCLUSIVE       (35),
		.OUT_PKT_BURST_TYPE_H          (54),
		.OUT_PKT_BURST_TYPE_L          (53),
		.OUT_PKT_ORI_BURST_SIZE_L      (82),
		.OUT_PKT_ORI_BURST_SIZE_H      (84),
		.OUT_ST_DATA_W                 (85),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (1)
	) vga_ball_0_avalon_slave_0_cmd_width_adapter (
		.clk                  (clk_0_clk_clk),                                                 //       clk.clk
		.reset                (vga_ball_0_reset_reset_bridge_in_reset_reset),                  // clk_reset.reset
		.in_valid             (cmd_mux_src_valid),                                             //      sink.valid
		.in_channel           (cmd_mux_src_channel),                                           //          .channel
		.in_startofpacket     (cmd_mux_src_startofpacket),                                     //          .startofpacket
		.in_endofpacket       (cmd_mux_src_endofpacket),                                       //          .endofpacket
		.in_ready             (cmd_mux_src_ready),                                             //          .ready
		.in_data              (cmd_mux_src_data),                                              //          .data
		.out_endofpacket      (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_data),          //          .data
		.out_channel          (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_channel),       //          .channel
		.out_valid            (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_valid),         //          .valid
		.out_ready            (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (vga_ball_0_avalon_slave_0_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                         // (terminated)
	);

	soc_system_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (10),
		.inUsePackets    (0),
		.inDataWidth     (10),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (10),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (clk_0_clk_clk),                                        // in_clk_0.clk
		.in_rst_0_reset (vga_ball_0_reset_reset_bridge_in_reset_reset),         // in_rst_0.reset
		.in_0_data      (vga_ball_0_avalon_slave_0_agent_rdata_fifo_out_data),  //     in_0.data
		.in_0_valid     (vga_ball_0_avalon_slave_0_agent_rdata_fifo_out_valid), //         .valid
		.in_0_ready     (vga_ball_0_avalon_slave_0_agent_rdata_fifo_out_ready), //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                         //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                        //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                        //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                         //         .error
	);

endmodule
