# TCL File Generated by Component Editor 21.1
# Sun May 04 19:13:01 EDT 2025
# DO NOT MODIFY


# 
# vga_tiles "vga_tiles" v1.0
#  2025.05.04.19:13:01
# 
# 

# 
# request TCL package from ACDS 16.1
# 
package require -exact qsys 16.1


# 
# module vga_tiles
# 
set_module_property DESCRIPTION ""
set_module_property NAME vga_tiles
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME vga_tiles
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL vga_tiles
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file vga_tiles.sv SYSTEM_VERILOG PATH ../vga_tiles.sv TOP_LEVEL_FILE
add_fileset_file tiles.sv SYSTEM_VERILOG PATH ../tiles.sv
add_fileset_file vga_counters.sv SYSTEM_VERILOG PATH ../vga_counters.sv
add_fileset_file twoportbram.sv SYSTEM_VERILOG PATH ../twoportbram.sv


# 
# parameters
# 


# 
# module assignments
# 
set_module_assignment embeddedsw.dts.group vga
set_module_assignment embeddedsw.dts.name vga_tiles
set_module_assignment embeddedsw.dts.vendor csee4840


# 
# display items
# 


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1


# 
# connection point reset
# 
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset reset reset Input 1


# 
# connection point VGA
# 
add_interface VGA conduit end
set_interface_property VGA associatedClock vga_clock
set_interface_property VGA associatedReset vga_reset
set_interface_property VGA ENABLED true
set_interface_property VGA EXPORT_OF ""
set_interface_property VGA PORT_NAME_MAP ""
set_interface_property VGA CMSIS_SVD_VARIABLES ""
set_interface_property VGA SVD_ADDRESS_GROUP ""

add_interface_port VGA VGA_B b Output 8
add_interface_port VGA VGA_BLANK_n blank_n Output 1
add_interface_port VGA VGA_G g Output 8
add_interface_port VGA VGA_HS hs Output 1
add_interface_port VGA VGA_VS vs Output 1
add_interface_port VGA VGA_R r Output 8
add_interface_port VGA VGA_CLK clk Output 1


# 
# connection point avalon
# 
add_interface avalon avalon end
set_interface_property avalon addressUnits WORDS
set_interface_property avalon associatedClock clock
set_interface_property avalon associatedReset reset
set_interface_property avalon bitsPerSymbol 8
set_interface_property avalon burstOnBurstBoundariesOnly false
set_interface_property avalon burstcountUnits WORDS
set_interface_property avalon explicitAddressSpan 0
set_interface_property avalon holdTime 0
set_interface_property avalon linewrapBursts false
set_interface_property avalon maximumPendingReadTransactions 0
set_interface_property avalon maximumPendingWriteTransactions 0
set_interface_property avalon readLatency 0
set_interface_property avalon readWaitTime 1
set_interface_property avalon setupTime 0
set_interface_property avalon timingUnits Cycles
set_interface_property avalon writeWaitTime 0
set_interface_property avalon ENABLED true
set_interface_property avalon EXPORT_OF ""
set_interface_property avalon PORT_NAME_MAP ""
set_interface_property avalon CMSIS_SVD_VARIABLES ""
set_interface_property avalon SVD_ADDRESS_GROUP ""

add_interface_port avalon writedata writedata Input 8
add_interface_port avalon chipselect chipselect Input 1
add_interface_port avalon write write Input 1
add_interface_port avalon address address Input 15
add_interface_port avalon readdata readdata Output 8
set_interface_assignment avalon embeddedsw.configuration.isFlash 0
set_interface_assignment avalon embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon embeddedsw.configuration.isPrintableDevice 0


# 
# connection point vga_clock
# 
add_interface vga_clock clock end
set_interface_property vga_clock clockRate 0
set_interface_property vga_clock ENABLED true
set_interface_property vga_clock EXPORT_OF ""
set_interface_property vga_clock PORT_NAME_MAP ""
set_interface_property vga_clock CMSIS_SVD_VARIABLES ""
set_interface_property vga_clock SVD_ADDRESS_GROUP ""

add_interface_port vga_clock vga_clk_in clk Input 1


# 
# connection point vga_reset
# 
add_interface vga_reset reset end
set_interface_property vga_reset associatedClock vga_clock
set_interface_property vga_reset synchronousEdges DEASSERT
set_interface_property vga_reset ENABLED true
set_interface_property vga_reset EXPORT_OF ""
set_interface_property vga_reset PORT_NAME_MAP ""
set_interface_property vga_reset CMSIS_SVD_VARIABLES ""
set_interface_property vga_reset SVD_ADDRESS_GROUP ""

add_interface_port vga_reset VGA_RESET reset Input 1

